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Fixed video, kbd and buzzer

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This commit is contained in:
Adrian Scripca
2022-03-31 14:13:34 +03:00
parent 107dded913
commit 61ed88ce64
493 changed files with 633379 additions and 79570 deletions
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cpu/control/Timings.csv
+1172
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cpu/control/Timings.xlsm
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cpu/control/clk_delay.bdf
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cpu/control/clk_delay.bsf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 216 208)
(text "clk_delay" (rect 5 0 58 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 176 25 188)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 21 27 55 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M1" (rect 21 43 37 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T1" (rect 21 59 35 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 75 36 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "mwait" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "mwait" (rect 21 91 55 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "latch_wait" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "latch_wait" (rect 21 107 80 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "busrq" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "busrq" (rect 21 123 54 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 139 57 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "setM1" (rect 21 155 55 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 200 32)
(output)
(text "hold_clk_iorq" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "hold_clk_iorq" (rect 105 27 179 41)(font "Arial" (font_size 8)))
(line (pt 200 32)(pt 184 32))
)
(port
(pt 200 48)
(output)
(text "iorq_Tw" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "iorq_Tw" (rect 132 43 179 57)(font "Arial" (font_size 8)))
(line (pt 200 48)(pt 184 48))
)
(port
(pt 200 64)
(output)
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 95 59 179 73)(font "Arial" (font_size 8)))
(line (pt 200 64)(pt 184 64))
)
(port
(pt 200 80)
(output)
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 102 75 179 89)(font "Arial" (font_size 8)))
(line (pt 200 80)(pt 184 80))
)
(port
(pt 200 96)
(output)
(text "busack" (rect 0 0 41 14)(font "Arial" (font_size 8)))
(text "busack" (rect 138 91 179 105)(font "Arial" (font_size 8)))
(line (pt 200 96)(pt 184 96))
)
(port
(pt 200 112)
(output)
(text "hold_clk_busrq" (rect 0 0 86 14)(font "Arial" (font_size 8)))
(text "hold_clk_busrq" (rect 93 107 179 121)(font "Arial" (font_size 8)))
(line (pt 200 112)(pt 184 112))
)
(port
(pt 200 128)
(output)
(text "pin_control_oe" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "pin_control_oe" (rect 96 123 179 137)(font "Arial" (font_size 8)))
(line (pt 200 128)(pt 184 128))
)
(drawing
(rectangle (rect 16 16 184 176))
)
)
cpu/control/clk_delay.v
+159
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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:59:31 2016"
module clk_delay(
clk,
in_intr,
nreset,
T1,
latch_wait,
mwait,
M1,
busrq,
setM1,
hold_clk_iorq,
hold_clk_wait,
iorq_Tw,
busack,
pin_control_oe,
hold_clk_busrq,
nhold_clk_wait
);
input wire clk;
input wire in_intr;
input wire nreset;
input wire T1;
input wire latch_wait;
input wire mwait;
input wire M1;
input wire busrq;
input wire setM1;
output wire hold_clk_iorq;
output wire hold_clk_wait;
output wire iorq_Tw;
output wire busack;
output wire pin_control_oe;
output wire hold_clk_busrq;
output wire nhold_clk_wait;
reg hold_clk_busrq_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_1;
reg DFF_inst5;
reg SYNTHESIZED_WIRE_7;
reg SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
reg SYNTHESIZED_WIRE_9;
assign hold_clk_wait = SYNTHESIZED_WIRE_9;
assign iorq_Tw = DFF_inst5;
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_9 <= 0;
end
else
if (SYNTHESIZED_WIRE_1)
begin
SYNTHESIZED_WIRE_9 <= mwait;
end
end
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_8 <= 0;
end
else
begin
SYNTHESIZED_WIRE_8 <= busrq;
end
end
assign hold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7;
assign busack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED;
assign pin_control_oe = SYNTHESIZED_WIRE_3 & nreset;
assign SYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1;
assign SYNTHESIZED_WIRE_3 = ~hold_clk_busrq_ALTERA_SYNTHESIZED;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_7 <= 0;
end
else
begin
SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
hold_clk_busrq_ALTERA_SYNTHESIZED <= 0;
end
else
if (SYNTHESIZED_WIRE_5)
begin
hold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFF_inst5 <= 0;
end
else
begin
DFF_inst5 <= SYNTHESIZED_WIRE_7;
end
end
assign SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
assign SYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;
assign nhold_clk_wait = ~SYNTHESIZED_WIRE_9;
assign SYNTHESIZED_WIRE_6 = ~clk;
assign hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
endmodule
cpu/control/decode_state.bdf
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cpu/control/decode_state.bsf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 240 304)
(text "decode_state" (rect 5 0 82 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 272 25 284)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "ctl_state_iy_set" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "ctl_state_iy_set" (rect 21 27 110 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "ctl_state_ixiy_clr" (rect 0 0 95 14)(font "Arial" (font_size 8)))
(text "ctl_state_ixiy_clr" (rect 21 43 116 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "ctl_state_ixiy_we" (rect 0 0 100 14)(font "Arial" (font_size 8)))
(text "ctl_state_ixiy_we" (rect 21 59 121 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "ctl_state_halt_set" (rect 0 0 100 14)(font "Arial" (font_size 8)))
(text "ctl_state_halt_set" (rect 21 75 121 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 21 91 55 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "in_nmi" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "in_nmi" (rect 21 107 56 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "ctl_state_tbl_cb_set" (rect 0 0 114 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_cb_set" (rect 21 123 135 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "ctl_state_tbl_we" (rect 0 0 94 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_we" (rect 21 139 115 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 21 155 105 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "ctl_state_tbl_ed_set" (rect 0 0 114 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_ed_set" (rect 21 171 135 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "address_is_1" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "address_is_1" (rect 21 187 98 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 0 208)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 203 36 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208))
)
(port
(pt 0 224)
(input)
(text "ctl_repeat_we" (rect 0 0 82 14)(font "Arial" (font_size 8)))
(text "ctl_repeat_we" (rect 21 219 103 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224))
)
(port
(pt 0 240)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 235 57 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240))
)
(port
(pt 0 256)
(input)
(text "ctl_state_alu" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "ctl_state_alu" (rect 21 251 92 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256))
)
(port
(pt 224 32)
(output)
(text "use_ix" (rect 0 0 37 14)(font "Arial" (font_size 8)))
(text "use_ix" (rect 166 27 203 41)(font "Arial" (font_size 8)))
(line (pt 224 32)(pt 208 32))
)
(port
(pt 224 48)
(output)
(text "use_ixiy" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "use_ixiy" (rect 156 43 203 57)(font "Arial" (font_size 8)))
(line (pt 224 48)(pt 208 48))
)
(port
(pt 224 64)
(output)
(text "in_halt" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "in_halt" (rect 167 59 203 73)(font "Arial" (font_size 8)))
(line (pt 224 64)(pt 208 64))
)
(port
(pt 224 80)
(output)
(text "table_cb" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "table_cb" (rect 155 75 203 89)(font "Arial" (font_size 8)))
(line (pt 224 80)(pt 208 80))
)
(port
(pt 224 96)
(output)
(text "table_xx" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "table_xx" (rect 155 91 203 105)(font "Arial" (font_size 8)))
(line (pt 224 96)(pt 208 96))
)
(port
(pt 224 112)
(output)
(text "table_ed" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "table_ed" (rect 155 107 203 121)(font "Arial" (font_size 8)))
(line (pt 224 112)(pt 208 112))
)
(port
(pt 224 128)
(output)
(text "repeat_en" (rect 0 0 57 14)(font "Arial" (font_size 8)))
(text "repeat_en" (rect 146 123 203 137)(font "Arial" (font_size 8)))
(line (pt 224 128)(pt 208 128))
)
(port
(pt 224 144)
(output)
(text "in_alu" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "in_alu" (rect 170 139 203 153)(font "Arial" (font_size 8)))
(line (pt 224 144)(pt 208 144))
)
(drawing
(rectangle (rect 16 16 208 272))
)
)
cpu/control/decode_state.v
+182
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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:55:35 2016"
module decode_state(
ctl_state_iy_set,
ctl_state_ixiy_clr,
ctl_state_ixiy_we,
ctl_state_halt_set,
ctl_state_tbl_ed_set,
ctl_state_tbl_cb_set,
ctl_state_alu,
clk,
address_is_1,
ctl_repeat_we,
in_intr,
in_nmi,
nreset,
ctl_state_tbl_we,
nhold_clk_wait,
in_halt,
table_cb,
table_ed,
table_xx,
use_ix,
use_ixiy,
in_alu,
repeat_en
);
input wire ctl_state_iy_set;
input wire ctl_state_ixiy_clr;
input wire ctl_state_ixiy_we;
input wire ctl_state_halt_set;
input wire ctl_state_tbl_ed_set;
input wire ctl_state_tbl_cb_set;
input wire ctl_state_alu;
input wire clk;
input wire address_is_1;
input wire ctl_repeat_we;
input wire in_intr;
input wire in_nmi;
input wire nreset;
input wire ctl_state_tbl_we;
input wire nhold_clk_wait;
output reg in_halt;
output wire table_cb;
output wire table_ed;
output wire table_xx;
output wire use_ix;
output wire use_ixiy;
output wire in_alu;
output wire repeat_en;
reg DFFE_instNonRep;
reg DFFE_instIY1;
reg DFFE_inst4;
reg DFFE_instED;
reg DFFE_instCB;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_3;
assign in_alu = ctl_state_alu;
assign table_cb = DFFE_instCB;
assign table_ed = DFFE_instED;
assign use_ix = DFFE_inst4;
assign repeat_en = ~DFFE_instNonRep;
assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
assign table_xx = ~(DFFE_instED | DFFE_instCB);
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_inst4 <= 0;
end
else
if (ctl_state_ixiy_we)
begin
DFFE_inst4 <= SYNTHESIZED_WIRE_0;
end
end
assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_we & nhold_clk_wait;
assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instCB <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
begin
DFFE_instCB <= ctl_state_tbl_cb_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instED <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
begin
DFFE_instED <= ctl_state_tbl_ed_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
in_halt <= 0;
end
else
begin
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instIY1 <= 0;
end
else
if (ctl_state_ixiy_we)
begin
DFFE_instIY1 <= ctl_state_iy_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instNonRep <= 0;
end
else
if (ctl_repeat_we)
begin
DFFE_instNonRep <= address_is_1;
end
end
endmodule
cpu/control/exec_matrix.vh
+3882
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cpu/control/exec_matrix_compiled.vh
+5812
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cpu/control/exec_module.vh
+127
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// Automatically generated by genref.py
// Module: control/decode_state.v
output reg ctl_state_iy_set,
output reg ctl_state_ixiy_clr,
output reg ctl_state_ixiy_we,
output reg ctl_state_halt_set,
output reg ctl_state_tbl_ed_set,
output reg ctl_state_tbl_cb_set,
output reg ctl_state_alu,
output reg ctl_repeat_we,
output reg ctl_state_tbl_we,
// Module: control/interrupts.v
output reg ctl_iff1_iff2,
output reg ctl_iffx_we,
output reg ctl_iffx_bit,
output reg ctl_im_we,
output reg ctl_no_ints,
// Module: control/ir.v
output reg ctl_ir_we,
// Module: control/memory_ifc.v
output reg ctl_mRead,
output reg ctl_mWrite,
output reg ctl_iorw,
// Module: alu/alu_control.v
output reg ctl_shift_en,
output reg ctl_daa_oe,
output reg ctl_alu_op_low,
output reg ctl_cond_short,
output reg ctl_alu_core_hf,
output reg ctl_eval_cond,
output reg ctl_66_oe,
output reg [1:0] ctl_pf_sel,
// Module: alu/alu_select.v
output reg ctl_alu_oe,
output reg ctl_alu_shift_oe,
output reg ctl_alu_op2_oe,
output reg ctl_alu_res_oe,
output reg ctl_alu_op1_oe,
output reg ctl_alu_bs_oe,
output reg ctl_alu_op1_sel_bus,
output reg ctl_alu_op1_sel_low,
output reg ctl_alu_op1_sel_zero,
output reg ctl_alu_op2_sel_zero,
output reg ctl_alu_op2_sel_bus,
output reg ctl_alu_op2_sel_lq,
output reg ctl_alu_sel_op2_neg,
output reg ctl_alu_sel_op2_high,
output reg ctl_alu_core_R,
output reg ctl_alu_core_V,
output reg ctl_alu_core_S,
// Module: alu/alu_flags.v
output reg ctl_flags_oe,
output reg ctl_flags_bus,
output reg ctl_flags_alu,
output reg ctl_flags_nf_set,
output reg ctl_flags_cf_set,
output reg ctl_flags_cf_cpl,
output reg ctl_flags_cf_we,
output reg ctl_flags_sz_we,
output reg ctl_flags_xy_we,
output reg ctl_flags_hf_we,
output reg ctl_flags_pf_we,
output reg ctl_flags_nf_we,
output reg ctl_flags_cf2_we,
output reg ctl_flags_hf_cpl,
output reg ctl_flags_use_cf2,
output reg ctl_flags_hf2_we,
output reg ctl_flags_nf_clr,
output reg ctl_alu_zero_16bit,
output reg ctl_flags_cf2_sel_shift,
output reg ctl_flags_cf2_sel_daa,
// Module: registers/reg_file.v
output reg ctl_sw_4u,
output reg ctl_reg_in_hi,
output reg ctl_reg_in_lo,
output reg ctl_reg_out_lo,
output reg ctl_reg_out_hi,
// Module: registers/reg_control.v
output reg ctl_reg_exx,
output reg ctl_reg_ex_af,
output reg ctl_reg_ex_de_hl,
output reg ctl_reg_use_sp,
output reg ctl_reg_sel_pc,
output reg ctl_reg_sel_ir,
output reg ctl_reg_sel_wz,
output reg ctl_reg_gp_we,
output reg ctl_reg_not_pc,
output reg ctl_reg_sys_we_lo,
output reg ctl_reg_sys_we_hi,
output reg ctl_reg_sys_we,
output reg ctl_sw_4d,
output reg [1:0] ctl_reg_gp_hilo,
output reg [1:0] ctl_reg_gp_sel,
output reg [1:0] ctl_reg_sys_hilo,
// Module: bus/address_latch.v
output reg ctl_inc_cy,
output reg ctl_inc_dec,
output reg ctl_al_we,
output reg ctl_inc_limit6,
output reg ctl_bus_inc_oe,
output reg ctl_apin_mux,
output reg ctl_apin_mux2,
// Module: bus/bus_control.v
output reg ctl_bus_ff_oe,
output reg ctl_bus_zero_oe,
// Module: bus/bus_switch.v
output reg ctl_sw_1u,
output reg ctl_sw_1d,
output reg ctl_sw_2u,
output reg ctl_sw_2d,
output reg ctl_sw_mask543_en,
// Module: bus/data_pins.v
output reg ctl_bus_db_we,
output reg ctl_bus_db_oe,
cpu/control/exec_zero.vh
+127
View File
@@ -0,0 +1,127 @@
// Automatically generated by genref.py
// Module: control/decode_state.v
ctl_state_iy_set = 0;
ctl_state_ixiy_clr = 0;
ctl_state_ixiy_we = 0;
ctl_state_halt_set = 0;
ctl_state_tbl_ed_set = 0;
ctl_state_tbl_cb_set = 0;
ctl_state_alu = 0;
ctl_repeat_we = 0;
ctl_state_tbl_we = 0;
// Module: control/interrupts.v
ctl_iff1_iff2 = 0;
ctl_iffx_we = 0;
ctl_iffx_bit = 0;
ctl_im_we = 0;
ctl_no_ints = 0;
// Module: control/ir.v
ctl_ir_we = 0;
// Module: control/memory_ifc.v
ctl_mRead = 0;
ctl_mWrite = 0;
ctl_iorw = 0;
// Module: alu/alu_control.v
ctl_shift_en = 0;
ctl_daa_oe = 0;
ctl_alu_op_low = 0;
ctl_cond_short = 0;
ctl_alu_core_hf = 0;
ctl_eval_cond = 0;
ctl_66_oe = 0;
ctl_pf_sel = 0;
// Module: alu/alu_select.v
ctl_alu_oe = 0;
ctl_alu_shift_oe = 0;
ctl_alu_op2_oe = 0;
ctl_alu_res_oe = 0;
ctl_alu_op1_oe = 0;
ctl_alu_bs_oe = 0;
ctl_alu_op1_sel_bus = 0;
ctl_alu_op1_sel_low = 0;
ctl_alu_op1_sel_zero = 0;
ctl_alu_op2_sel_zero = 0;
ctl_alu_op2_sel_bus = 0;
ctl_alu_op2_sel_lq = 0;
ctl_alu_sel_op2_neg = 0;
ctl_alu_sel_op2_high = 0;
ctl_alu_core_R = 0;
ctl_alu_core_V = 0;
ctl_alu_core_S = 0;
// Module: alu/alu_flags.v
ctl_flags_oe = 0;
ctl_flags_bus = 0;
ctl_flags_alu = 0;
ctl_flags_nf_set = 0;
ctl_flags_cf_set = 0;
ctl_flags_cf_cpl = 0;
ctl_flags_cf_we = 0;
ctl_flags_sz_we = 0;
ctl_flags_xy_we = 0;
ctl_flags_hf_we = 0;
ctl_flags_pf_we = 0;
ctl_flags_nf_we = 0;
ctl_flags_cf2_we = 0;
ctl_flags_hf_cpl = 0;
ctl_flags_use_cf2 = 0;
ctl_flags_hf2_we = 0;
ctl_flags_nf_clr = 0;
ctl_alu_zero_16bit = 0;
ctl_flags_cf2_sel_shift = 0;
ctl_flags_cf2_sel_daa = 0;
// Module: registers/reg_file.v
ctl_sw_4u = 0;
ctl_reg_in_hi = 0;
ctl_reg_in_lo = 0;
ctl_reg_out_lo = 0;
ctl_reg_out_hi = 0;
// Module: registers/reg_control.v
ctl_reg_exx = 0;
ctl_reg_ex_af = 0;
ctl_reg_ex_de_hl = 0;
ctl_reg_use_sp = 0;
ctl_reg_sel_pc = 0;
ctl_reg_sel_ir = 0;
ctl_reg_sel_wz = 0;
ctl_reg_gp_we = 0;
ctl_reg_not_pc = 0;
ctl_reg_sys_we_lo = 0;
ctl_reg_sys_we_hi = 0;
ctl_reg_sys_we = 0;
ctl_sw_4d = 0;
ctl_reg_gp_hilo = 0;
ctl_reg_gp_sel = 0;
ctl_reg_sys_hilo = 0;
// Module: bus/address_latch.v
ctl_inc_cy = 0;
ctl_inc_dec = 0;
ctl_al_we = 0;
ctl_inc_limit6 = 0;
ctl_bus_inc_oe = 0;
ctl_apin_mux = 0;
ctl_apin_mux2 = 0;
// Module: bus/bus_control.v
ctl_bus_ff_oe = 0;
ctl_bus_zero_oe = 0;
// Module: bus/bus_switch.v
ctl_sw_1u = 0;
ctl_sw_1d = 0;
ctl_sw_2u = 0;
ctl_sw_2d = 0;
ctl_sw_mask543_en = 0;
// Module: bus/data_pins.v
ctl_bus_db_we = 0;
ctl_bus_db_oe = 0;
cpu/control/execute.bsf
+946
View File
@@ -0,0 +1,946 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "ctl_alu_core_R" (rect 173 667 235 679)(font "Arial" ))
(line (pt 256 672)(pt 240 672)(line_width 1))
)
(port
(pt 256 688)
(output)
(text "ctl_alu_core_V" (rect 0 0 62 12)(font "Arial" ))
(text "ctl_alu_core_V" (rect 173 683 235 695)(font "Arial" ))
(line (pt 256 688)(pt 240 688)(line_width 1))
)
(port
(pt 256 704)
(output)
(text "ctl_alu_core_S" (rect 0 0 60 12)(font "Arial" ))
(text "ctl_alu_core_S" (rect 175 699 235 711)(font "Arial" ))
(line (pt 256 704)(pt 240 704)(line_width 1))
)
(port
(pt 256 720)
(output)
(text "ctl_flags_oe" (rect 0 0 48 12)(font "Arial" ))
(text "ctl_flags_oe" (rect 187 715 235 727)(font "Arial" ))
(line (pt 256 720)(pt 240 720)(line_width 1))
)
(port
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(output)
(text "ctl_flags_bus" (rect 0 0 53 12)(font "Arial" ))
(text "ctl_flags_bus" (rect 182 731 235 743)(font "Arial" ))
(line (pt 256 736)(pt 240 736)(line_width 1))
)
(port
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(output)
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(text "ctl_flags_alu" (rect 186 747 235 759)(font "Arial" ))
(line (pt 256 752)(pt 240 752)(line_width 1))
)
(port
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(output)
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(text "ctl_flags_nf_set" (rect 171 763 235 775)(font "Arial" ))
(line (pt 256 768)(pt 240 768)(line_width 1))
)
(port
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(text "ctl_flags_cf_set" (rect 171 779 235 791)(font "Arial" ))
(line (pt 256 784)(pt 240 784)(line_width 1))
)
(port
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(output)
(text "ctl_flags_cf_cpl" (rect 0 0 63 12)(font "Arial" ))
(text "ctl_flags_cf_cpl" (rect 172 795 235 807)(font "Arial" ))
(line (pt 256 800)(pt 240 800)(line_width 1))
)
(port
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(output)
(text "ctl_flags_cf_we" (rect 0 0 63 12)(font "Arial" ))
(text "ctl_flags_cf_we" (rect 172 811 235 823)(font "Arial" ))
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(port
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(port
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(text "ctl_flags_xy_we" (rect 169 843 235 855)(font "Arial" ))
(line (pt 256 848)(pt 240 848)(line_width 1))
)
(port
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(output)
(text "ctl_flags_hf_we" (rect 0 0 63 12)(font "Arial" ))
(text "ctl_flags_hf_we" (rect 172 859 235 871)(font "Arial" ))
(line (pt 256 864)(pt 240 864)(line_width 1))
)
(port
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(port
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(text "ctl_flags_nf_we" (rect 172 891 235 903)(font "Arial" ))
(line (pt 256 896)(pt 240 896)(line_width 1))
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(port
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(text "ctl_flags_cf2_we" (rect 167 907 235 919)(font "Arial" ))
(line (pt 256 912)(pt 240 912)(line_width 1))
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(port
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(text "ctl_flags_hf_cpl" (rect 0 0 63 12)(font "Arial" ))
(text "ctl_flags_hf_cpl" (rect 172 923 235 935)(font "Arial" ))
(line (pt 256 928)(pt 240 928)(line_width 1))
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(port
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(text "ctl_flags_use_cf2" (rect 164 939 235 951)(font "Arial" ))
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(line (pt 256 976)(pt 240 976)(line_width 1))
)
(port
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(output)
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(text "ctl_alu_zero_16bit" (rect 166 987 235 999)(font "Arial" ))
(line (pt 256 992)(pt 240 992)(line_width 1))
)
(port
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(text "ctl_flags_cf2_sel_shift" (rect 0 0 90 12)(font "Arial" ))
(text "ctl_flags_cf2_sel_shift" (rect 145 1003 235 1015)(font "Arial" ))
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(text "ctl_flags_cf2_sel_daa" (rect 147 1019 235 1031)(font "Arial" ))
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)
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(text "ctl_sw_4u" (rect 194 1035 235 1047)(font "Arial" ))
(line (pt 256 1040)(pt 240 1040)(line_width 1))
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(port
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(line (pt 256 1168)(pt 240 1168)(line_width 1))
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(port
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(text "ctl_reg_sel_pc" (rect 0 0 59 12)(font "Arial" ))
(text "ctl_reg_sel_pc" (rect 176 1179 235 1191)(font "Arial" ))
(line (pt 256 1184)(pt 240 1184)(line_width 1))
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(text "ctl_reg_sel_ir" (rect 181 1195 235 1207)(font "Arial" ))
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)
(port
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(text "ctl_reg_sel_wz" (rect 0 0 59 12)(font "Arial" ))
(text "ctl_reg_sel_wz" (rect 176 1211 235 1223)(font "Arial" ))
(line (pt 256 1216)(pt 240 1216)(line_width 1))
)
(port
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(text "ctl_reg_gp_we" (rect 176 1227 235 1239)(font "Arial" ))
(line (pt 256 1232)(pt 240 1232)(line_width 1))
)
(port
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(text "ctl_reg_not_pc" (rect 0 0 60 12)(font "Arial" ))
(text "ctl_reg_not_pc" (rect 175 1243 235 1255)(font "Arial" ))
(line (pt 256 1248)(pt 240 1248)(line_width 1))
)
(port
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(text "ctl_reg_sys_we_lo" (rect 0 0 76 12)(font "Arial" ))
(text "ctl_reg_sys_we_lo" (rect 159 1259 235 1271)(font "Arial" ))
(line (pt 256 1264)(pt 240 1264)(line_width 1))
)
(port
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(text "ctl_reg_sys_we_hi" (rect 159 1275 235 1287)(font "Arial" ))
(line (pt 256 1280)(pt 240 1280)(line_width 1))
)
(port
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(text "ctl_reg_sys_we" (rect 171 1291 235 1303)(font "Arial" ))
(line (pt 256 1296)(pt 240 1296)(line_width 1))
)
(port
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(text "ctl_sw_4d" (rect 0 0 41 12)(font "Arial" ))
(text "ctl_sw_4d" (rect 194 1307 235 1319)(font "Arial" ))
(line (pt 256 1312)(pt 240 1312)(line_width 1))
)
(port
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(text "ctl_reg_gp_hilo[1..0]" (rect 0 0 79 12)(font "Arial" ))
(text "ctl_reg_gp_hilo[1..0]" (rect 156 1323 235 1335)(font "Arial" ))
(line (pt 256 1328)(pt 240 1328)(line_width 3))
)
(port
(pt 256 1344)
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(text "ctl_reg_gp_sel[1..0]" (rect 158 1339 235 1351)(font "Arial" ))
(line (pt 256 1344)(pt 240 1344)(line_width 3))
)
(port
(pt 256 1360)
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(text "ctl_reg_sys_hilo[1..0]" (rect 0 0 84 12)(font "Arial" ))
(text "ctl_reg_sys_hilo[1..0]" (rect 151 1355 235 1367)(font "Arial" ))
(line (pt 256 1360)(pt 240 1360)(line_width 3))
)
(port
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(text "ctl_inc_cy" (rect 0 0 41 12)(font "Arial" ))
(text "ctl_inc_cy" (rect 194 1371 235 1383)(font "Arial" ))
(line (pt 256 1376)(pt 240 1376)(line_width 1))
)
(port
(pt 256 1392)
(output)
(text "ctl_inc_dec" (rect 0 0 44 12)(font "Arial" ))
(text "ctl_inc_dec" (rect 191 1387 235 1399)(font "Arial" ))
(line (pt 256 1392)(pt 240 1392)(line_width 1))
)
(port
(pt 256 1408)
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(text "ctl_al_we" (rect 0 0 36 12)(font "Arial" ))
(text "ctl_al_we" (rect 199 1403 235 1415)(font "Arial" ))
(line (pt 256 1408)(pt 240 1408)(line_width 1))
)
(port
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(text "ctl_inc_limit6" (rect 186 1419 235 1431)(font "Arial" ))
(line (pt 256 1424)(pt 240 1424)(line_width 1))
)
(port
(pt 256 1440)
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(text "ctl_bus_inc_oe" (rect 0 0 60 12)(font "Arial" ))
(text "ctl_bus_inc_oe" (rect 175 1435 235 1447)(font "Arial" ))
(line (pt 256 1440)(pt 240 1440)(line_width 1))
)
(port
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(text "ctl_apin_mux" (rect 0 0 53 12)(font "Arial" ))
(text "ctl_apin_mux" (rect 182 1451 235 1463)(font "Arial" ))
(line (pt 256 1456)(pt 240 1456)(line_width 1))
)
(port
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(output)
(text "ctl_apin_mux2" (rect 0 0 57 12)(font "Arial" ))
(text "ctl_apin_mux2" (rect 178 1467 235 1479)(font "Arial" ))
(line (pt 256 1472)(pt 240 1472)(line_width 1))
)
(port
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(output)
(text "ctl_bus_ff_oe" (rect 0 0 56 12)(font "Arial" ))
(text "ctl_bus_ff_oe" (rect 179 1483 235 1495)(font "Arial" ))
(line (pt 256 1488)(pt 240 1488)(line_width 1))
)
(port
(pt 256 1504)
(output)
(text "ctl_bus_zero_oe" (rect 0 0 66 12)(font "Arial" ))
(text "ctl_bus_zero_oe" (rect 169 1499 235 1511)(font "Arial" ))
(line (pt 256 1504)(pt 240 1504)(line_width 1))
)
(port
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(output)
(text "ctl_sw_1u" (rect 0 0 38 12)(font "Arial" ))
(text "ctl_sw_1u" (rect 197 1515 235 1527)(font "Arial" ))
(line (pt 256 1520)(pt 240 1520)(line_width 1))
)
(port
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(output)
(text "ctl_sw_1d" (rect 0 0 38 12)(font "Arial" ))
(text "ctl_sw_1d" (rect 197 1531 235 1543)(font "Arial" ))
(line (pt 256 1536)(pt 240 1536)(line_width 1))
)
(port
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(output)
(text "ctl_sw_2u" (rect 0 0 40 12)(font "Arial" ))
(text "ctl_sw_2u" (rect 195 1547 235 1559)(font "Arial" ))
(line (pt 256 1552)(pt 240 1552)(line_width 1))
)
(port
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(output)
(text "ctl_sw_2d" (rect 0 0 40 12)(font "Arial" ))
(text "ctl_sw_2d" (rect 195 1563 235 1575)(font "Arial" ))
(line (pt 256 1568)(pt 240 1568)(line_width 1))
)
(port
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(output)
(text "ctl_sw_mask543_en" (rect 0 0 83 12)(font "Arial" ))
(text "ctl_sw_mask543_en" (rect 152 1579 235 1591)(font "Arial" ))
(line (pt 256 1584)(pt 240 1584)(line_width 1))
)
(port
(pt 256 1600)
(output)
(text "ctl_bus_db_we" (rect 0 0 60 12)(font "Arial" ))
(text "ctl_bus_db_we" (rect 175 1595 235 1607)(font "Arial" ))
(line (pt 256 1600)(pt 240 1600)(line_width 1))
)
(port
(pt 256 1616)
(output)
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(text "ctl_bus_db_oe" (rect 176 1611 235 1623)(font "Arial" ))
(line (pt 256 1616)(pt 240 1616)(line_width 1))
)
(port
(pt 256 1632)
(output)
(text "nextM" (rect 0 0 24 12)(font "Arial" ))
(text "nextM" (rect 211 1627 235 1639)(font "Arial" ))
(line (pt 256 1632)(pt 240 1632)(line_width 1))
)
(port
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(output)
(text "setM1" (rect 0 0 23 12)(font "Arial" ))
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(line (pt 256 1648)(pt 240 1648)(line_width 1))
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(port
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(text "fFetch" (rect 210 1659 235 1671)(font "Arial" ))
(line (pt 256 1664)(pt 240 1664)(line_width 1))
)
(port
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(output)
(text "fMRead" (rect 0 0 34 12)(font "Arial" ))
(text "fMRead" (rect 201 1675 235 1687)(font "Arial" ))
(line (pt 256 1680)(pt 240 1680)(line_width 1))
)
(port
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(output)
(text "fMWrite" (rect 0 0 34 12)(font "Arial" ))
(text "fMWrite" (rect 201 1691 235 1703)(font "Arial" ))
(line (pt 256 1696)(pt 240 1696)(line_width 1))
)
(port
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(output)
(text "fIORead" (rect 0 0 35 12)(font "Arial" ))
(text "fIORead" (rect 200 1707 235 1719)(font "Arial" ))
(line (pt 256 1712)(pt 240 1712)(line_width 1))
)
(port
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(output)
(text "fIOWrite" (rect 0 0 35 12)(font "Arial" ))
(text "fIOWrite" (rect 200 1723 235 1735)(font "Arial" ))
(line (pt 256 1728)(pt 240 1728)(line_width 1))
)
(drawing
(rectangle (rect 16 16 240 1760)(line_width 1))
)
)
cpu/control/execute.v
+158
View File
@@ -0,0 +1,158 @@
//=============================================================================
// This module implements the instruction execute state logic.
//
// Copyright (C) 2014-2016 Goran Devic
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//=============================================================================
// Using a compiled format will include files generated by "gencompile.py" script
// These files are a processed version of "exec_matrix_compiled.vh"
// You would define this on Xilinx and undefine (comment out) on Altera
`define USE_COMPILED_FORMAT
module execute
(
//----------------------------------------------------------
// Control signals generated by the instruction execution
//----------------------------------------------------------
`include "exec_module.vh"
output reg nextM, // Last M cycle of any instruction
output reg setM1, // Last T clock of any instruction
output reg fFetch, // Function: opcode fetch cycle ("M1")
output reg fMRead, // Function: memory read cycle
output reg fMWrite, // Function: memory write cycle
output reg fIORead, // Function: IO Read cycle
output reg fIOWrite, // Function: IO Write cycle
//----------------------------------------------------------
// Inputs from the instruction decode PLA
//----------------------------------------------------------
input wire [104:0] pla, // Statically decoded instructions
//----------------------------------------------------------
// Inputs from various blocks
//----------------------------------------------------------
input wire in_intr, // Servicing maskable interrupt
input wire in_nmi, // Servicing non-maskable interrupt
input wire in_halt, // Currently in HALT mode
input wire im1, // Interrupt Mode 1
input wire im2, // Interrupt Mode 2
input wire use_ixiy, // Special decode signal
input wire flags_cond_true, // Flags condition is true
input wire repeat_en, // Enable repeat of a block instruction
input wire flags_zf, // ZF to test a condition
input wire flags_nf, // NF to test for subtraction
input wire flags_sf, // SF to test for 8-bit sign of a value
input wire flags_cf, // CF to set HF for CCF
//----------------------------------------------------------
// Machine and clock cycles
//----------------------------------------------------------
input wire M1, // Machine cycle #1
input wire M2, // Machine cycle #2
input wire M3, // Machine cycle #3
input wire M4, // Machine cycle #4
input wire M5, // Machine cycle #5
input wire T1, // T-cycle #1
input wire T2, // T-cycle #2
input wire T3, // T-cycle #3
input wire T4, // T-cycle #4
input wire T5, // T-cycle #5
input wire T6 // T-cycle #6
);
// Detects unknown instructions by signalling the known ones
reg validPLA; // Valid PLA asserts this reg
// Activates a state machine to compute WZ=IX+d; takes 5T cycles
reg ixy_d; // Compute WX=IX+d
// Signals the setting of IX/IY prefix flags; inhibits clearing them
reg setIXIY; // Set IX/IY flag at the next T cycle
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
reg nonRep; // Non-repeating block instruction
// Suspends incrementing PC through address latch unless in HALT or interrupt mode
reg pc_inc_hold; // Normally 0 unless in one of those modes
//--------------------------------------------------------------
// Define various shortcuts to field naming
//--------------------------------------------------------------
`define GP_REG_BC 2'h0
`define GP_REG_DE 2'h1
`define GP_REG_HL 2'h2
`define GP_REG_AF 2'h3
`define PFSEL_P 2'h0
`define PFSEL_V 2'h1
`define PFSEL_IFF2 2'h2
`define PFSEL_REP 2'h3
//--------------------------------------------------------------
// Make available different bits and sections of the opcode byte
//--------------------------------------------------------------
wire op0 = pla[99];
wire op1 = pla[100];
wire op2 = pla[101];
wire op3 = pla[102];
wire op4 = pla[103];
wire op5 = pla[104];
wire [1:0] op21 = { pla[101], pla[100] };
wire [1:0] op54 = { pla[104], pla[103] };
//--------------------------------------------------------------
// 8-bit register selections needs to swizzle mux for A and F
//--------------------------------------------------------------
wire rsel0 = op0 ^ (op1 & op2);
wire rsel3 = op3 ^ (op4 & op5);
`ifdef USE_COMPILED_FORMAT
`include "temp_wires.vh" // Define all temp wires used with compiled equations
`endif
always @(*) // always_comb
begin
//-----------------------------------------------------------------------------
// Default assignment of all control outputs to 0 to prevent generating latches
//-----------------------------------------------------------------------------
`include "exec_zero.vh" // Initial assignment to all ctl wires to zero
// Reset internal control regs
validPLA = 0; // Will be set by every *valid* PLA entry
nextM = 0; // Will be set to advance to the next M cycle
setM1 = 0; // Will be set on a last M/T cycle of an instruction
// Reset global machine cycle functions
fFetch = M1; // Fetch is aliased to M1
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
ixy_d = 0;
setIXIY = 0;
nonRep = 0;
pc_inc_hold = 0;
//-------------------------------------------------------------------------
// State-based signal assignment; code generated from Timings spreadsheet
//-------------------------------------------------------------------------
`ifdef USE_COMPILED_FORMAT
`include "exec_matrix_compiled.vh" // Compiled execution equations
`else
`include "exec_matrix.vh" // Execution statements in the original nested-if format
`endif
// Needed by data bus 0 override logic, make only one bus writer active at any time
ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);
end
endmodule
cpu/control/gencompile.py
+146
View File
@@ -0,0 +1,146 @@
#!/usr/bin/env python3
#
# This script reads 'exec_matrix.vh' file and compiles it into an alternate format
# that can be used with Xilinx toolchain.
#
# Xilinx synthesis tool is effectively not capable of processing that file.
# Altera Quartus has no problems compiling it.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#-------------------------------------------------------------------------------
import os
import io
import copy
import tokenize
from io import BytesIO
from tokenize import NAME, INDENT, DEDENT, ENCODING
# Input file to process
fname = "exec_matrix.vh"
# Output file to contain compiled version of the input
oname = "exec_matrix_compiled.vh"
# Output file to contain a list of temporary wires used by the compiled Verilog file
tname = "temp_wires.vh"
# Define a list of control signals that are 2-bits wide
ctls_wide = ['ctl_reg_gp_sel', 'ctl_reg_gp_hilo', 'ctl_reg_sys_hilo', 'ctl_pf_sel']
# Help recognizing control signal names
def is_ctl(name):
return name.startswith('ctl_') or name=='validPLA' or name=='nextM' or name=='setM1' \
or name=='fFetch' or name=='fMRead' or name=='fMWrite' or name=='fIORead' or name=='fIOWrite' \
or name=='ixy_d' or name=='setIXIY' or name=='nonRep' or name=='pc_inc_hold'
def str2tok(s):
t = io.BytesIO(bytes(s.encode()))
return list(tokenize.tokenize(t.readline))[1:-1]
def tok2str(tokens):
line = [ tokens[n][m].string for n in range(len(tokens)) for m in range(len(tokens[n])) ]
return ''.join(line)
def get_rval(tokens, i):
assert (tokens[i+1].string=='=' or tokens[i+1].string=='|=')
paren = list(str2tok('()'))
rval = paren[:1]
while (tokens[i+2].string!=';'):
rval.append(tokens[i+2])
i += 1
rval.extend(paren[1:2])
return [rval]
def decomment(s):
i = s.find('//') # Remove trailing comments from a line
if i>=0:
return s[:i]
i = s.find('/*') # Remove comments within a line
j = s.find('*/')
if i>=0 and j>=0:
return decomment(s[:i] + s[j+2:])
return s
#--------------------------------------------------------------------------------
# Generate a sequential-or form for all control wires
#--------------------------------------------------------------------------------
def sequential_or(f, t, tokens):
incond = False # Inside an "if" condition state
cond = [] # Condition nested lists
ccond = [] # Currently scanned condition list
ctls = {} # Dictionary of control wires and their equations
ccwires = [] # List of wires at the current condition list level
i = 0 # Current index into the tokens list
while i < len(tokens):
tok = tokens[i]
(toknum, tokval, _, _, _) = tok
if incond and not (toknum==NAME and tokval=='begin'):
if toknum != DEDENT and toknum != INDENT:
ccond.append(tok)
if toknum==NAME:
if tokval=='if':
incond = True
if tokval=='begin': # Push a condition list
incond = False
cond.append(copy.deepcopy(ccond))
ccond.clear()
ccwires.clear()
if tokval=='end': # Pop a condition list
cond.pop()
if is_ctl(tokval) and not incond:
rval = get_rval(tokens, i)
linesub = tok2str(cond)
rhs = tok2str(rval)
line = "{0} = {0} | ".format(tokval)
if tokval in ccwires: # Check for duplicate assignments
hint = [ cond[n][m].string for n in range(len(cond)) for m in range(len(cond[n])) ]
print ("WARNING: {0}: Multiple assignment of {1}".format(''.join(hint), tokval))
ccwires.append(tokval) # Track this wire as assigned at this condition level
if tokval in ctls_wide:
tr = linesub.translate(str.maketrans(dict.fromkeys('~','n'))) # Make temporary name
tmpname = "{0}_{1}_{2}".format(tokval, tr.translate(str.maketrans(dict.fromkeys('[]()&',None))), len(ccwires))
t.write("reg {0};\n".format(tmpname))
line = "{0} = {1};\n".format(tmpname, linesub) + line
line += "({{{0},{0}}}){1}".format(tmpname, rhs)
else:
line += linesub + rhs
line = line.replace(')(', ')&(')
line = line.replace('&&', '&')
line = line.replace('(1)&', '')
line = line.replace('&(1)', '')
i += len(rval[0])
f.write ('{0};\n'.format(line))
i += 1
#--------------------------------------------------------------------------------
tokens = []
# Input file which we are processing
with open(fname) as f:
lines = f.readlines()
for line in lines:
src = decomment(line)
src = bytes(src.encode())
src = io.BytesIO(src)
toklist = list(tokenize.tokenize(src.readline))
tokens.extend(toklist)
with open(oname, 'w') as f:
with open(tname, 'w') as t:
f.write("// Automatically generated by gencompile.py\n\n")
t.write("// Automatically generated by gencompile.py\n\n")
sequential_or(f, t, tokens)
# Touch a file that includes 'exec_matrix_compiled.vh' to ensure it will recompile correctly
os.utime("execute.v", None)
cpu/control/genmatrix.py
+189
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#!/usr/bin/env python3
#
# This script reads A-Z80 instruction timing data from a spreadsheet text file
# 'Timings.csv' (which is a TAB-delimited text file exported from 'Timings.xlsm')
# and generates a Verilog include file defining the control block execution matrix.
# Token keywords in the timing spreadsheet are substituted using a list of keys
# defined in 'timing_macros.i'.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2014,2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#-------------------------------------------------------------------------------
import string
import sys
import csv
import os
# Input file (exported from 'Timings.xlsm'):
fname = "Timings.csv"
# Input file containing macro substitution keys
kname = "timing_macros.i"
# Set this to 1 if you want abbreviated matrix (no-action lines removed)
abbr = 1
# Set this to 0 if you want to strip all comments from the resulting file
comment = 1
# Set this to 1 if you want debug $display() printout on each PLA line
debug = 0
# Print this string in front of every line that starts with "ctl_". This helps
# formatting the output to be more readable.
ctl_prefix = "\n"+" "*19
# Read in the content of the macro substitution file
macros = []
with open(kname, 'r') as f:
for line in f:
if len(line.strip())>0 and line[0]!='/':
# Wrap up non-starting //-style comments into /* ... */ so the
# line can be concatenated while preserving comments
i = line.find("//")
if i>0:
if comment==1:
macros.append( line.rstrip().replace("//", "/*", 1) + " */" )
else:
macros.append( line.rstrip()[0:i] )
else:
macros.append(line.rstrip())
# List of errors / keys and macros that did not match. We stash them as we go
# and then print at the end so it is easier to find them
errors = []
# Returns a substitution string given the section name (key) and the macro token
# This is done by simply traversing macro substitution list of lines, finding a
# section that starts with a :key and copying the substitution lines verbatim.
def getSubst(key, token):
subst = []
multiline = False
validset = False
if key=="Comments": # Special case: ignore "Comments" column!
return ""
for l in macros:
if multiline==True:
# Multiline copies lines until a char at [0] is not a space
if len(l.strip())==0 or l[0]!=' ':
return '\n' + "\n".join(subst).rstrip()
else:
subst.append(l.rstrip())
lx = l.split(' ') # Split the string and then ignore (duplicate)
lx = list(filter(None, lx)) # spaces in the list left by the split()
if l.startswith(":"): # Find and recognize a matching set (key) section
if validset: # Error if there is a new section going from the macthing one
break # meaning we did not find our macro in there
if l[1:]==key:
validset = True
elif validset and lx[0]==token:
if len(lx)==1:
return ""
if lx[1]=='\\': # Multi-line macro state starts with '\' character
multiline = True
continue
lx.pop(0)
s = " ".join(lx)
return ' ' + s.strip()
err = "{0} not in {1}".format(token, key)
if err not in errors:
errors.append(err)
return " --- {0} ?? {1} --- ".format(token, key)
# Read the content of a file and using the csv reader and remove any quotes from the input fields
content = [] # Content of the spreadsheet timing file
with open(fname, 'r') as csvFile:
reader = csv.reader(csvFile, delimiter='\t', quotechar='"')
for row in reader:
content.append('\t'.join(row))
# The first line is special: it contains names of sets for our macro substitutions
tkeys = {} # Spreadsheet table column keys
tokens = content.pop(0).split('\t')
for col in range(len(tokens)):
if len(tokens[col])==0:
continue
tkeys[col] = tokens[col]
# Process each line separately (stateless processor)
imatrix = [] # Verilog execution matrix code
for line in content:
col = line.split('\t') # Split the string into a list of columns
col_clean = list(filter(None, col)) # Removed all empty fields (between the separators)
if len(col_clean)==0: # Ignore completely empty lines
continue
if col_clean[0].startswith('//') and comment==1:
imatrix.append(col_clean[0]) # Optionally print comment lines
if col_clean[0].startswith("#end"): # Print the end of a condition
imatrix.append("end\n")
if col_clean[0].startswith('#if'): # Print the start of a condition
s = col_clean[0]
tag = s.find(":")
condition = s[4:tag]
imatrix.append("if ({0}) begin".format(condition.strip()))
if debug and len(s[tag:])>1: # Print only in debug and there is something to print
imatrix.append(" $display(\"{0}\");".format(s[4:]))
# We recognize 2 kinds of timing statements based on the starting characters:
# "#0".. common timings using M and T cycles (M being optional)
# "#always" timing that does not depend on M and T cycles (ex. ALU operations)
if col_clean[0].startswith('#0') or col_clean[0].startswith('#always'):
# M and T states are hard-coded in the table at the index 1 and 2
if col_clean[0].startswith('#0'):
if col[1]=='?': # M is optional, use '?' to skip it
state = " if (T{0}) begin".format(col[2])
else:
state = " if (M{0} & T{1}) begin".format(col[1], col[2])
else:
state = " begin"
# Loop over all other columns and perform verbatim substitution
action = ""
for i in range(3,len(col)):
# There may be multiple tokens separated by commas
tokList = col[i].strip().split(',')
tokList = list(filter(None, tokList)) # Filter out empty lines
for token in tokList:
token = token.strip()
if i in tkeys and len(token)>0:
macro = getSubst(tkeys[i], token)
if macro.strip().startswith("ctl_"):
action += ctl_prefix
action += macro
if state.find("ERROR")>=0:
print ("{0} {1}".format(state, action))
break
# Complete and write out a line
if abbr and len(action)==0:
continue
imatrix.append("{0}{1} end".format(state, action))
# Create a file containing the logic matrix code
with open('exec_matrix.vh', 'w') as file:
if comment==1:
file.write("// Automatically generated by genmatrix.py\n\n")
# If there were errors, print them first (and output to the console)
if len(errors)>0:
for error in errors:
print (error)
file.write(error + "\n")
file.write("-" * 80 + "\n")
for item in imatrix:
file.write("{}\n".format(item))
# Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly
os.utime("execute.v", None)
cpu/control/genref.py
+61
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@@ -0,0 +1,61 @@
#!/usr/bin/env python3
#
# This script reads and parses selected Verilog and SystemVerilog modules
# and generates a set of Verilog include files for the control block.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2014 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#-------------------------------------------------------------------------------
import glob
import os
with open('../top-level-files.txt') as f:
files = f.read().splitlines()
# Create 2 files that should be included by the execution engine:
# 1. A file listing all control signals
# 2. A file containing statements initializing control signals to zero
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
file1.write("// Automatically generated by genref.py\n")
file0.write("// Automatically generated by genref.py\n")
# Read and parse each file from the list of input files
for infile in files:
wires = []
if not os.path.isfile('../' + infile):
continue
with open('../' + infile, "r") as f:
for line in f:
info = line.split()
# input wire register case
if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"):
wires.append(info[2].strip(';,'))
# input wire bus case (ex. "[1:0]")
if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
wires.append(info[2] + " " + info[3].strip(';,'))
if len(wires)>0:
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
print ("MODULE:", infile)
file0.write("\n// Module: " + infile + "\n")
file1.write("\n// Module: " + infile + "\n")
for wire in wires:
print (" ", wire)
file1.write("output reg " + wire + ",\n")
if "[" in wire:
file0.write(wire.split()[1] + " = 0;\n")
else:
file0.write(wire + " = 0;\n")
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
os.utime("execute.v", None)
cpu/control/interrupts.bdf
+1885
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File diff suppressed because it is too large Load Diff
cpu/control/interrupts.bsf
+141
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@@ -0,0 +1,141 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 64 64 216 288)
(text "interrupts" (rect 5 0 59 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "ctl_iff1_iff2" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "ctl_iff1_iff2" (rect 21 27 85 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "ctl_iffx_we" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "ctl_iffx_we" (rect 21 43 85 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "ctl_iffx_bit" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "ctl_iffx_bit" (rect 21 59 80 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "nmi" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "nmi" (rect 21 75 39 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "intr" (rect 0 0 17 14)(font "Arial" (font_size 8)))
(text "intr" (rect 21 91 38 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "setM1" (rect 21 107 55 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "ctl_no_ints" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "ctl_no_ints" (rect 21 123 82 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "db[1..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "db[1..0]" (rect 21 139 63 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 155 36 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "ctl_im_we" (rect 0 0 57 14)(font "Arial" (font_size 8)))
(text "ctl_im_we" (rect 21 171 78 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 187 57 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 152 32)
(output)
(text "iff2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "iff2" (rect 113 27 131 41)(font "Arial" (font_size 8)))
(line (pt 152 32)(pt 136 32))
)
(port
(pt 152 48)
(output)
(text "in_nmi" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "in_nmi" (rect 96 43 131 57)(font "Arial" (font_size 8)))
(line (pt 152 48)(pt 136 48))
)
(port
(pt 152 64)
(output)
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 97 59 131 73)(font "Arial" (font_size 8)))
(line (pt 152 64)(pt 136 64))
)
(port
(pt 152 80)
(output)
(text "im1" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im1" (rect 113 75 131 89)(font "Arial" (font_size 8)))
(line (pt 152 80)(pt 136 80))
)
(port
(pt 152 96)
(output)
(text "im2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im2" (rect 113 91 131 105)(font "Arial" (font_size 8)))
(line (pt 152 96)(pt 136 96))
)
(drawing
(rectangle (rect 16 16 136 208))
)
)
cpu/control/interrupts.v
+248
View File
@@ -0,0 +1,248 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 13 19:23:03 2016"
module interrupts(
ctl_iff1_iff2,
nmi,
setM1,
intr,
ctl_iffx_we,
ctl_iffx_bit,
ctl_im_we,
clk,
ctl_no_ints,
nreset,
db,
iff2,
im1,
im2,
in_nmi,
in_intr
);
input wire ctl_iff1_iff2;
input wire nmi;
input wire setM1;
input wire intr;
input wire ctl_iffx_we;
input wire ctl_iffx_bit;
input wire ctl_im_we;
input wire clk;
input wire ctl_no_ints;
input wire nreset;
input wire [1:0] db;
output wire iff2;
output reg im1;
output reg im2;
output wire in_nmi;
output wire in_intr;
reg iff1;
wire in_intr_ALTERA_SYNTHESIZED;
reg in_nmi_ALTERA_SYNTHESIZED;
reg int_armed;
reg nmi_armed;
wire test1;
wire SYNTHESIZED_WIRE_0;
reg DFFE_instIFF2;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
reg DFFE_inst44;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
assign iff2 = DFFE_instIFF2;
assign SYNTHESIZED_WIRE_10 = 1;
assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;
assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_4 = ~db[0];
assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_20 = db[1] & db[0];
assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;
assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_13 = iff1 & intr;
assign test1 = setM1 & SYNTHESIZED_WIRE_8;
always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)
begin
if (!SYNTHESIZED_WIRE_9)
begin
nmi_armed <= 0;
end
else
begin
nmi_armed <= SYNTHESIZED_WIRE_10;
end
end
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
in_nmi_ALTERA_SYNTHESIZED <= 0;
end
else
if (test1)
begin
in_nmi_ALTERA_SYNTHESIZED <= nmi_armed;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_inst44 <= 0;
end
else
if (test1)
begin
DFFE_inst44 <= int_armed;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_12)
begin
if (!SYNTHESIZED_WIRE_12)
begin
int_armed <= 0;
end
else
begin
int_armed <= SYNTHESIZED_WIRE_13;
end
end
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;
assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints;
always@(posedge clk or negedge SYNTHESIZED_WIRE_15)
begin
if (!SYNTHESIZED_WIRE_15)
begin
iff1 <= 0;
end
else
if (SYNTHESIZED_WIRE_17)
begin
iff1 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_21)
begin
if (!SYNTHESIZED_WIRE_21)
begin
DFFE_instIFF2 <= 0;
end
else
if (ctl_iffx_we)
begin
DFFE_instIFF2 <= ctl_iffx_bit;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im1 <= 0;
end
else
if (ctl_im_we)
begin
im1 <= SYNTHESIZED_WIRE_19;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im2 <= 0;
end
else
if (ctl_im_we)
begin
im2 <= SYNTHESIZED_WIRE_20;
end
end
assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED;
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED;
assign in_intr = in_intr_ALTERA_SYNTHESIZED;
endmodule
cpu/control/interrupts.v.bak
+246
View File
@@ -0,0 +1,246 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 13 19:23:03 2016"
module interrupts(
ctl_iff1_iff2,
nmi,
setM1,
intr,
ctl_iffx_we,
ctl_iffx_bit,
ctl_im_we,
clk,
ctl_no_ints,
nreset,
db,
iff2,
im1,
im2,
in_nmi,
in_intr
);
input wire ctl_iff1_iff2;
input wire nmi;
input wire setM1;
input wire intr;
input wire ctl_iffx_we;
input wire ctl_iffx_bit;
input wire ctl_im_we;
input wire clk;
input wire ctl_no_ints;
input wire nreset;
input wire [1:0] db;
output wire iff2;
output reg im1;
output reg im2;
output wire in_nmi;
output wire in_intr;
reg iff1;
wire in_intr_ALTERA_SYNTHESIZED;
reg in_nmi_ALTERA_SYNTHESIZED;
reg int_armed;
reg nmi_armed;
wire test1;
wire SYNTHESIZED_WIRE_0;
reg DFFE_instIFF2;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
reg DFFE_inst44;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
assign iff2 = DFFE_instIFF2;
assign SYNTHESIZED_WIRE_10 = 1;
assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;
assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_4 = ~db[0];
assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_20 = db[1] & db[0];
assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;
assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_13 = iff1 & intr;
assign test1 = setM1 & SYNTHESIZED_WIRE_8;
always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)
begin
if (!SYNTHESIZED_WIRE_9)
begin
nmi_armed <= 0;
end
else
begin
nmi_armed <= SYNTHESIZED_WIRE_10;
end
end
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
in_nmi_ALTERA_SYNTHESIZED <= 0;
end
else
if (test1)
begin
in_nmi_ALTERA_SYNTHESIZED <= nmi_armed;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_inst44 <= 0;
end
else
if (test1)
begin
DFFE_inst44 <= int_armed;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_12)
begin
if (!SYNTHESIZED_WIRE_12)
begin
int_armed <= 0;
end
else
begin
int_armed <= SYNTHESIZED_WIRE_13;
end
end
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;
assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints;
always@(posedge clk or negedge SYNTHESIZED_WIRE_15)
begin
if (!SYNTHESIZED_WIRE_15)
begin
iff1 <= 0;
end
else
if (SYNTHESIZED_WIRE_17)
begin
iff1 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_21)
begin
if (!SYNTHESIZED_WIRE_21)
begin
DFFE_instIFF2 <= 0;
end
else
if (ctl_iffx_we)
begin
DFFE_instIFF2 <= ctl_iffx_bit;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im1 <= 0;
end
else
if (ctl_im_we)
begin
im1 <= SYNTHESIZED_WIRE_19;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im2 <= 0;
end
else
if (ctl_im_we)
begin
im2 <= SYNTHESIZED_WIRE_20;
end
end
assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED;
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED;
assign in_intr = in_intr_ALTERA_SYNTHESIZED;
endmodule
cpu/control/ir.bdf
+260
View File
@@ -0,0 +1,260 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 40 96 216 112)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ctl_ir_we" (rect 9 0 51 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 48 216 64)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "db[7..0]" (rect 9 0 46 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
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(rect 40 64 216 80)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "clk" (rect 9 0 23 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 152 216 168)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nreset" (rect 9 0 39 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 112 216 128)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nhold_clk_wait" (rect 9 0 79 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 504 48 680 64)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "opcode[7..0]" (rect 90 0 151 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 392 32 456 112)
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "ir" (rect 3 68 8 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 296 88 360 136)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 37 26 49)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(connector
(pt 216 56)
(pt 392 56)
(bus)
)
(connector
(pt 216 72)
(pt 392 72)
)
(connector
(pt 456 56)
(pt 504 56)
(bus)
)
(connector
(pt 424 160)
(pt 216 160)
)
(connector
(pt 424 112)
(pt 424 160)
)
(connector
(pt 392 88)
(pt 376 88)
)
(connector
(pt 376 88)
(pt 376 112)
)
(connector
(pt 376 112)
(pt 360 112)
)
(connector
(pt 216 104)
(pt 296 104)
)
(connector
(pt 216 120)
(pt 296 120)
)
(text "8 latches implement the opcode Instruction Register" (rect 328 216 619 230)(font "Arial" (font_size 8)))
(title_block
(rect 40 216 297 268)
(name "title-custom-small")
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "ir" (rect 43 2 52 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014, 2016" (rect 56 3 161 17)(font "Arial" (font_size 8)))(border))
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(drawing
)
)
cpu/control/ir.bsf
+71
View File
@@ -0,0 +1,71 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 224 144)
(text "ir" (rect 5 0 12 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "db[7..0]" (rect 21 27 63 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "ctl_ir_we" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "ctl_ir_we" (rect 21 59 74 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 21 75 105 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 91 57 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 208 32)
(output)
(text "opcode[7..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "opcode[7..0]" (rect 117 27 187 41)(font "Arial" (font_size 8)))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 112))
)
)
cpu/control/ir.v
+58
View File
@@ -0,0 +1,58 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:56:46 2016"
module ir(
ctl_ir_we,
clk,
nreset,
nhold_clk_wait,
db,
opcode
);
input wire ctl_ir_we;
input wire clk;
input wire nreset;
input wire nhold_clk_wait;
input wire [7:0] db;
output reg [7:0] opcode;
wire SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
opcode[7:0] <= 8'b00000000;
end
else
if (SYNTHESIZED_WIRE_0)
begin
opcode[7:0] <= db[7:0];
end
end
endmodule
cpu/control/memory_ifc.bdf
+3677
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File diff suppressed because it is too large Load Diff
cpu/control/memory_ifc.bsf
+176
View File
@@ -0,0 +1,176 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 224 272)
(text "memory_ifc" (rect 5 0 71 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 240 25 252)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "nM1_int" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "nM1_int" (rect 21 27 64 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 59 57 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "setM1" (rect 21 75 55 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "timings_en" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "timings_en" (rect 21 91 81 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 21 107 55 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "ctl_mRead" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "ctl_mRead" (rect 21 123 80 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "ctl_mWrite" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "ctl_mWrite" (rect 21 139 80 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "ctl_iorw" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "ctl_iorw" (rect 21 155 67 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "fIORead" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "fIORead" (rect 21 171 67 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "fIOWrite" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "fIOWrite" (rect 21 187 67 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 0 208)
(input)
(text "iorq_Tw" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "iorq_Tw" (rect 21 203 68 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208))
)
(port
(pt 0 224)
(input)
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 21 219 105 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224))
)
(port
(pt 208 32)
(output)
(text "nRFSH_out" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "nRFSH_out" (rect 124 27 187 41)(font "Arial" (font_size 8)))
(line (pt 208 32)(pt 192 32))
)
(port
(pt 208 48)
(output)
(text "nM1_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nM1_out" (rect 139 43 187 57)(font "Arial" (font_size 8)))
(line (pt 208 48)(pt 192 48))
)
(port
(pt 208 64)
(output)
(text "nMREQ_out" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "nMREQ_out" (rect 121 59 187 73)(font "Arial" (font_size 8)))
(line (pt 208 64)(pt 192 64))
)
(port
(pt 208 80)
(output)
(text "wait_m1" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "wait_m1" (rect 139 75 187 89)(font "Arial" (font_size 8)))
(line (pt 208 80)(pt 192 80))
)
(port
(pt 208 96)
(output)
(text "nRD_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nRD_out" (rect 139 91 187 105)(font "Arial" (font_size 8)))
(line (pt 208 96)(pt 192 96))
)
(port
(pt 208 112)
(output)
(text "nWR_out" (rect 0 0 51 14)(font "Arial" (font_size 8)))
(text "nWR_out" (rect 136 107 187 121)(font "Arial" (font_size 8)))
(line (pt 208 112)(pt 192 112))
)
(port
(pt 208 128)
(output)
(text "nIORQ_out" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "nIORQ_out" (rect 126 123 187 137)(font "Arial" (font_size 8)))
(line (pt 208 128)(pt 192 128))
)
(port
(pt 208 144)
(output)
(text "latch_wait" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "latch_wait" (rect 128 139 187 153)(font "Arial" (font_size 8)))
(line (pt 208 144)(pt 192 144))
)
(drawing
(rectangle (rect 16 16 192 240))
)
)
cpu/control/memory_ifc.v
+430
View File
@@ -0,0 +1,430 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Dec 09 19:14:29 2018"
module memory_ifc(
clk,
nM1_int,
ctl_mRead,
ctl_mWrite,
in_intr,
nreset,
fIORead,
fIOWrite,
setM1,
ctl_iorw,
timings_en,
iorq_Tw,
nhold_clk_wait,
nM1_out,
nRFSH_out,
nMREQ_out,
nRD_out,
nWR_out,
nIORQ_out,
latch_wait,
wait_m1
);
input wire clk;
input wire nM1_int;
input wire ctl_mRead;
input wire ctl_mWrite;
input wire in_intr;
input wire nreset;
input wire fIORead;
input wire fIOWrite;
input wire setM1;
input wire ctl_iorw;
input wire timings_en;
input wire iorq_Tw;
input wire nhold_clk_wait;
output wire nM1_out;
output wire nRFSH_out;
output wire nMREQ_out;
output wire nRD_out;
output wire nWR_out;
output wire nIORQ_out;
output wire latch_wait;
output wire wait_m1;
wire intr_iorq;
wire ioRead;
wire iorq;
wire ioWrite;
wire m1_mreq;
wire mrd_mreq;
wire mwr_mreq;
reg mwr_wr;
wire nMEMRQ_int;
wire nq2;
reg q1;
reg q2;
wire wait_io;
reg wait_iorq;
reg wait_iorqinta;
reg wait_m_ALTERA_SYNTHESIZED1;
reg wait_mrd;
reg wait_mwr;
wire SYNTHESIZED_WIRE_0;
reg DFFE_m1_ff3;
wire SYNTHESIZED_WIRE_1;
reg DFFE_iorq_ff4;
reg SYNTHESIZED_WIRE_15;
reg DFFE_mrd_ff3;
reg DFFE_intr_ff3;
wire SYNTHESIZED_WIRE_2;
reg SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
reg DFFE_iorq_ff1;
reg DFFE_m1_ff1;
reg DFFE_mrd_ff1;
reg DFFE_mwr_ff1;
reg DFFE_mreq_ff2;
assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
assign ioRead = iorq & fIORead;
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
assign iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
assign ioWrite = iorq & fIOWrite;
assign latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
assign nWR_out = ~(ioWrite | mwr_wr);
assign mwr_mreq = mwr_wr | wait_mwr;
assign nIORQ_out = ~(intr_iorq | iorq);
assign wait_io = wait_iorqinta | wait_iorq;
assign intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_iorqinta <= 0;
end
else
begin
wait_iorqinta <= iorq_Tw;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_intr_ff3 <= 0;
end
else
if (nhold_clk_wait)
begin
DFFE_intr_ff3 <= wait_iorqinta;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_iorq_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_iorq_ff1 <= ctl_iorw;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_15 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_iorq <= 0;
end
else
if (timings_en)
begin
wait_iorq <= SYNTHESIZED_WIRE_15;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_iorq_ff4 <= 0;
end
else
if (timings_en)
begin
DFFE_iorq_ff4 <= wait_iorq;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_16 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_16 <= nM1_int;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_m1_ff1 <= 1;
end
else
if (timings_en)
begin
DFFE_m1_ff1 <= setM1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_m_ALTERA_SYNTHESIZED1 <= 0;
end
else
if (timings_en)
begin
wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_m1_ff3 <= 0;
end
else
if (timings_en)
begin
DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_mrd_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_mrd_ff1 <= ctl_mRead;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_mrd <= 0;
end
else
if (timings_en)
begin
wait_mrd <= DFFE_mrd_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_mrd_ff3 <= 0;
end
else
if (timings_en)
begin
DFFE_mrd_ff3 <= wait_mrd;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_17 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_mreq_ff2 <= 0;
end
else
if (timings_en)
begin
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_mwr_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_mwr_ff1 <= ctl_mWrite;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_mwr <= 0;
end
else
if (timings_en)
begin
wait_mwr <= DFFE_mwr_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
mwr_wr <= 0;
end
else
if (timings_en)
begin
mwr_wr <= wait_mwr;
end
end
assign SYNTHESIZED_WIRE_18 = ~clk;
assign nq2 = ~q2;
assign SYNTHESIZED_WIRE_2 = ~nreset;
assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
q1 <= 0;
end
else
if (timings_en)
begin
q1 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
q2 <= 0;
end
else
if (timings_en)
begin
q2 <= q1;
end
end
assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
endmodule
cpu/control/pin_control.bdf
+1087
View File
File diff suppressed because it is too large Load Diff
cpu/control/pin_control.bsf
+113
View File
@@ -0,0 +1,113 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 208 208)
(text "pin_control" (rect 5 0 67 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 176 25 188)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T1" (rect 21 27 35 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T2" (rect 21 43 35 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "T3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T3" (rect 21 59 35 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "T4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T4" (rect 21 75 35 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "fFetch" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "fFetch" (rect 21 91 57 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "fMRead" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "fMRead" (rect 21 107 64 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "fMWrite" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "fMWrite" (rect 21 123 64 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "fIORead" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "fIORead" (rect 21 139 67 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "fIOWrite" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "fIOWrite" (rect 21 155 67 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 192 32)
(output)
(text "bus_ab_pin_we" (rect 0 0 92 14)(font "Arial" (font_size 8)))
(text "bus_ab_pin_we" (rect 79 27 171 41)(font "Arial" (font_size 8)))
(line (pt 192 32)(pt 176 32))
)
(port
(pt 192 48)
(output)
(text "bus_db_pin_oe" (rect 0 0 87 14)(font "Arial" (font_size 8)))
(text "bus_db_pin_oe" (rect 84 43 171 57)(font "Arial" (font_size 8)))
(line (pt 192 48)(pt 176 48))
)
(port
(pt 192 64)
(output)
(text "bus_db_pin_re" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "bus_db_pin_re" (rect 87 59 171 73)(font "Arial" (font_size 8)))
(line (pt 192 64)(pt 176 64))
)
(drawing
(rectangle (rect 16 16 176 176))
)
)
cpu/control/pin_control.v
+89
View File
@@ -0,0 +1,89 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 21:18:37 2014"
module pin_control(
fFetch,
fMRead,
fMWrite,
fIORead,
fIOWrite,
T1,
T2,
T3,
T4,
bus_ab_pin_we,
bus_db_pin_oe,
bus_db_pin_re
);
input wire fFetch;
input wire fMRead;
input wire fMWrite;
input wire fIORead;
input wire fIOWrite;
input wire T1;
input wire T2;
input wire T3;
input wire T4;
output wire bus_ab_pin_we;
output wire bus_db_pin_oe;
output wire bus_db_pin_re;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite;
assign SYNTHESIZED_WIRE_7 = T3 | T2;
assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_3 = T3 & fIORead;
assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6;
assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4;
assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite;
assign SYNTHESIZED_WIRE_4 = T2 & fFetch;
assign SYNTHESIZED_WIRE_2 = T2 & fMRead;
assign SYNTHESIZED_WIRE_6 = T3 & fFetch;
assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9;
endmodule
cpu/control/pla_decode.bsf
+50
View File
@@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 208 96)
(text "pla_decode" (rect 5 0 49 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "opcode[7..0]" (rect 0 0 48 12)(font "Arial" ))
(text "opcode[7..0]" (rect 21 27 69 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "prefix[6..0]" (rect 0 0 42 12)(font "Arial" ))
(text "prefix[6..0]" (rect 21 43 63 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 192 32)
(output)
(text "pla[104..0]" (rect 0 0 40 12)(font "Arial" ))
(text "pla[104..0]" (rect 131 27 171 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 64)(line_width 1))
)
)
cpu/control/pla_decode.v
+121
View File
@@ -0,0 +1,121 @@
//=====================================================================================
// This file is automatically generated by the z80_pla_checker tool. Do not edit!
//=====================================================================================
module pla_decode
(
input wire [6:0] prefix,
input wire [7:0] opcode,
output wire [104:0] pla
);
assign pla[ 0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldx/cpx/inx/outx brk
assign pla[ 1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0; // exx
assign pla[ 2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0; // ex de,hl
assign pla[ 3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0; // IX/IY prefix
assign pla[ 5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0; // ld sp,hl
assign pla[ 6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0; // jp hl
assign pla[ 7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0; // ld rr,nn
assign pla[ 8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld (rr),a/a,(rr)
assign pla[ 9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0; // inc/dec rr
assign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0; // ex (sp),hl
assign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld direction
assign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0; // rrd/rld
assign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0; // push rr
assign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0; // ld r,n
assign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0; // outx/otxr
assign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/inxr
assign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0; // push/pop
assign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0; // call nn
assign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0; // rlca/rla/rrca/rra
assign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0; // djnz e
assign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0; // in/out r,(c)
assign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a
assign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0; // jp nn
assign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0; // ld hl,(nn)/(nn),hl
assign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld rr,(nn)/(nn),rr
assign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld direction
assign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0; // out (c),r
assign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0; // ret
assign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a/a,(n)
assign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0; // ld (nn),a/a,(nn)
assign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0; // ex af,af'
assign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0; // ld (ix+d),n
assign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0; // call cc,nn
assign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0; // jp cc,nn
assign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0; // CB prefix
assign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0; // ret cc
assign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0; // reti/retn
assign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0; // jr e
assign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0; // jr ss,e
assign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0; // CB prefix with IX/IY
assign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0; // ld (hl),n
assign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0; // ED prefix
assign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cp (hl)
assign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0; // inc/dec (hl)
assign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0; // Every CB op (hl)
assign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0; // rst p
assign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0; // ld i,a/r,a
assign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0; // ld r,(hl)
assign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0; // ld (hl),r
assign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0; // ld r,r'
assign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,imm
assign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,r
assign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0; // inc/dec r
assign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0; // adc/sbc hl,rr
assign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0; // add hl,rr
assign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0; // rlc r
assign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0; // bit b,r
assign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0; // res b,r
assign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0; // set b,r
assign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0; // dec r
assign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0; // 111 (CP)
assign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0; // daa
assign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0; // 010 (SUB)
assign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0; // 011 (SBC)
assign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0; // 001 (ADC)
assign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0; // cpl
assign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0; // neg
assign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0; // ld a,i/a,r
assign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0; // 000 (ADD)
assign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0; // 100 (AND)
assign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0; // 110 (OR)
assign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0; // 101 (XOR)
assign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0; // ccf
assign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/outx/inxr/otxr
assign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0; // scf
assign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0; // halt
assign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0; // im n
assign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0; // di/ei
assign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0; // opcode[0]
assign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0; // opcode[1]
assign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0; // opcode[2]
assign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0; // opcode[3]
assign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0; // opcode[4]
assign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0; // opcode[5]
// Entries not used by our timing matrix
assign pla[ 67] = 1'b0; // in
assign pla[ 62] = 1'b0; // For all CB opcodes
assign pla[ 54] = 1'b0; // Every CB with IX/IY
assign pla[ 22] = 1'b0; // CB prefix w/o IX/IY
assign pla[ 14] = 1'b0; // dec rr
assign pla[ 4] = 1'b0; // ld x,a/a,x
// Duplicate entries
assign pla[ 18] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 19] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 32] = 1'b0; // ld i,a/a,i/r,a/a,r
assign pla[ 36] = 1'b0; // ld(rr),a/a,(rr)
assign pla[ 41] = 1'b0; // IX/IY
assign pla[ 60] = 1'b0; // rrd/rld
assign pla[ 63] = 1'b0; // ld r,*
assign pla[ 71] = 1'b0; // rlca/rla/rrca/rra
assign pla[ 87] = 1'b0; // ld a,i / ld a,r
assign pla[ 90] = 1'b0; // djnz *
assign pla[ 93] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 94] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 98] = 1'b0; // out (*),a/in a,(*)
endmodule
cpu/control/resets.bdf
+1114
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cpu/control/resets.bsf
+85
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@@ -0,0 +1,85 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 192 176)
(text "resets" (rect 5 0 41 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 144 25 156)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "fpga_reset" (rect 0 0 62 14)(font "Arial" (font_size 8)))
(text "fpga_reset" (rect 21 27 83 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "reset_in" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "reset_in" (rect 21 43 67 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M1" (rect 21 59 37 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T2" (rect 21 75 35 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 21 107 105 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 176 32)
(output)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 119 27 155 41)(font "Arial" (font_size 8)))
(line (pt 176 32)(pt 160 32))
)
(port
(pt 176 48)
(output)
(text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8)))
(text "clrpc" (rect 127 43 155 57)(font "Arial" (font_size 8)))
(line (pt 176 48)(pt 160 48))
)
(drawing
(rectangle (rect 16 16 160 144))
)
)
cpu/control/resets.v
+144
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@@ -0,0 +1,144 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:57:54 2016"
module resets(
reset_in,
clk,
M1,
T2,
fpga_reset,
nhold_clk_wait,
clrpc,
nreset
);
input wire reset_in;
input wire clk;
input wire M1;
input wire T2;
input wire fpga_reset;
input wire nhold_clk_wait;
output wire clrpc;
output wire nreset;
reg clrpc_int;
wire nclk;
reg x1;
wire x2;
wire x3;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_1;
reg SYNTHESIZED_WIRE_9;
reg DFFE_intr_ff3;
reg SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_6;
assign nreset = SYNTHESIZED_WIRE_6;
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
begin
if (!SYNTHESIZED_WIRE_8)
begin
x1 <= 1;
end
else
begin
x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
end
end
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_1 = ~reset_in;
assign x2 = x1 & SYNTHESIZED_WIRE_11;
assign SYNTHESIZED_WIRE_11 = M1 & T2;
assign x3 = x1 & SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
assign nclk = ~clk;
assign SYNTHESIZED_WIRE_8 = ~fpga_reset;
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
DFFE_intr_ff3 <= SYNTHESIZED_WIRE_9;
end
end
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
end
end
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
begin
if (!SYNTHESIZED_WIRE_8)
begin
SYNTHESIZED_WIRE_12 <= 1;
end
else
begin
SYNTHESIZED_WIRE_12 <= x3;
end
end
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
begin
if (!SYNTHESIZED_WIRE_6)
begin
clrpc_int <= 0;
end
else
begin
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
end
end
endmodule
cpu/control/sequencer.bdf
+2320
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cpu/control/sequencer.bsf
+162
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@@ -0,0 +1,162 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 216 272)
(text "sequencer" (rect 5 0 66 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 240 25 252)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "setM1" (rect 21 27 55 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 59 57 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "nextM" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "nextM" (rect 21 75 55 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "hold_clk_iorq" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "hold_clk_iorq" (rect 21 91 95 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 107 98 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "hold_clk_busrq" (rect 0 0 86 14)(font "Arial" (font_size 8)))
(text "hold_clk_busrq" (rect 21 123 107 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 200 32)
(output)
(text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M1" (rect 163 27 179 41)(font "Arial" (font_size 8)))
(line (pt 200 32)(pt 184 32))
)
(port
(pt 200 48)
(output)
(text "M2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M2" (rect 163 43 179 57)(font "Arial" (font_size 8)))
(line (pt 200 48)(pt 184 48))
)
(port
(pt 200 64)
(output)
(text "M3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M3" (rect 163 59 179 73)(font "Arial" (font_size 8)))
(line (pt 200 64)(pt 184 64))
)
(port
(pt 200 80)
(output)
(text "M4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M4" (rect 163 75 179 89)(font "Arial" (font_size 8)))
(line (pt 200 80)(pt 184 80))
)
(port
(pt 200 96)
(output)
(text "M5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M5" (rect 163 91 179 105)(font "Arial" (font_size 8)))
(line (pt 200 96)(pt 184 96))
)
(port
(pt 200 128)
(output)
(text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T1" (rect 165 123 179 137)(font "Arial" (font_size 8)))
(line (pt 200 128)(pt 184 128))
)
(port
(pt 200 144)
(output)
(text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T2" (rect 165 139 179 153)(font "Arial" (font_size 8)))
(line (pt 200 144)(pt 184 144))
)
(port
(pt 200 160)
(output)
(text "T3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T3" (rect 165 155 179 169)(font "Arial" (font_size 8)))
(line (pt 200 160)(pt 184 160))
)
(port
(pt 200 176)
(output)
(text "T4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T4" (rect 165 171 179 185)(font "Arial" (font_size 8)))
(line (pt 200 176)(pt 184 176))
)
(port
(pt 200 192)
(output)
(text "T5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T5" (rect 165 187 179 201)(font "Arial" (font_size 8)))
(line (pt 200 192)(pt 184 192))
)
(port
(pt 200 208)
(output)
(text "T6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "T6" (rect 165 203 179 217)(font "Arial" (font_size 8)))
(line (pt 200 208)(pt 184 208))
)
(port
(pt 200 224)
(output)
(text "timings_en" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "timings_en" (rect 119 219 179 233)(font "Arial" (font_size 8)))
(line (pt 200 224)(pt 184 224))
)
(drawing
(rectangle (rect 16 16 184 240))
)
)
cpu/control/sequencer.v
+279
View File
@@ -0,0 +1,279 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 13 17:56:57 2016"
module sequencer(
clk,
nextM,
setM1,
nreset,
hold_clk_iorq,
hold_clk_wait,
hold_clk_busrq,
M1,
M2,
M3,
M4,
M5,
T1,
T2,
T3,
T4,
T5,
T6,
timings_en
);
input wire clk;
input wire nextM;
input wire setM1;
input wire nreset;
input wire hold_clk_iorq;
input wire hold_clk_wait;
input wire hold_clk_busrq;
output wire M1;
output wire M2;
output wire M3;
output wire M4;
output reg M5;
output wire T1;
output wire T2;
output wire T3;
output wire T4;
output wire T5;
output reg T6;
output wire timings_en;
wire ena_M;
wire ena_T;
reg DFFE_M4_ff;
wire SYNTHESIZED_WIRE_18;
reg DFFE_T1_ff;
wire SYNTHESIZED_WIRE_19;
reg DFFE_T2_ff;
reg DFFE_T3_ff;
reg DFFE_T4_ff;
reg DFFE_T5_ff;
reg DFFE_M1_ff;
reg DFFE_M2_ff;
reg DFFE_M3_ff;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
assign M1 = DFFE_M1_ff;
assign M2 = DFFE_M2_ff;
assign M3 = DFFE_M3_ff;
assign M4 = DFFE_M4_ff;
assign T1 = DFFE_T1_ff;
assign T2 = DFFE_T2_ff;
assign T3 = DFFE_T3_ff;
assign T4 = DFFE_T4_ff;
assign T5 = DFFE_T5_ff;
assign ena_M = nextM | setM1;
assign SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;
assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M1_ff <= 1;
end
else
if (ena_M)
begin
DFFE_M1_ff <= setM1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M2_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M2_ff <= SYNTHESIZED_WIRE_9;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M3_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M3_ff <= SYNTHESIZED_WIRE_10;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M4_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M4_ff <= SYNTHESIZED_WIRE_11;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
M5 <= 0;
end
else
if (ena_M)
begin
M5 <= SYNTHESIZED_WIRE_12;
end
end
assign SYNTHESIZED_WIRE_19 = ~ena_M;
assign SYNTHESIZED_WIRE_18 = ~setM1;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T1_ff <= 1;
end
else
if (ena_T)
begin
DFFE_T1_ff <= ena_M;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T2_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T2_ff <= SYNTHESIZED_WIRE_13;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T3_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T3_ff <= SYNTHESIZED_WIRE_14;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T4_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T4_ff <= SYNTHESIZED_WIRE_15;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T5_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T5_ff <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
T6 <= 0;
end
else
if (ena_T)
begin
T6 <= SYNTHESIZED_WIRE_17;
end
end
assign timings_en = ena_T;
endmodule
cpu/control/simulation/modelsim/r
+1
View File
@@ -0,0 +1 @@
restart -f ; run -all
cpu/control/simulation/modelsim/test_control.mpf
+524
View File
@@ -0,0 +1,524 @@
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 0 ns
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 4
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
DelayFileOpen = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 8
Project_File_0 = $ROOT/cpu/control/interrupts.v
Project_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_1 = $ROOT/cpu/control/pin_control.v
Project_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_2 = $ROOT/cpu/control/resets.v
Project_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_3 = $ROOT/cpu/control/sequencer.v
Project_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_4 = $ROOT/cpu/control/test_interrupts.sv
Project_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_5 = $ROOT/cpu/control/test_pin_control.sv
Project_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_6 = $ROOT/cpu/control/test_reset.sv
Project_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_7 = $ROOT/cpu/control/test_sequencer.sv
Project_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_Sim_Count = 4
Project_Sim_0 = Test pin control
Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
Project_Sim_1 = Test interrupts
Project_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder interrupts +pulse_e {} additional_dus work.test_interrupts -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
Project_Sim_2 = Test reset
Project_Sim_P_2 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder reset +pulse_e {} additional_dus work.test_reset -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
Project_Sim_3 = Test sequencer
Project_Sim_P_3 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder sequencer +pulse_e {} additional_dus work.test_sequencer -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
Project_Folder_Count = 4
Project_Folder_0 = interrupts
Project_Folder_P_0 = folder {Top Level}
Project_Folder_1 = pin control
Project_Folder_P_1 = folder {Top Level}
Project_Folder_2 = reset
Project_Folder_P_2 = folder {Top Level}
Project_Folder_3 = sequencer
Project_Folder_P_3 = folder {Top Level}
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 1
cpu/control/simulation/modelsim/wave_interrupts.do
+38
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@@ -0,0 +1,38 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /test_interrupts/clk
add wave -noupdate /test_interrupts/nreset
add wave -noupdate /test_interrupts/ctl_iff1_iff2_sig
add wave -noupdate /test_interrupts/nmi_sig
add wave -noupdate /test_interrupts/setM1_sig
add wave -noupdate /test_interrupts/intr_sig
add wave -noupdate /test_interrupts/ctl_iffx_we_sig
add wave -noupdate /test_interrupts/ctl_iffx_bit_sig
add wave -noupdate /test_interrupts/ctl_im_we_sig
add wave -noupdate /test_interrupts/db_sig
add wave -noupdate /test_interrupts/ctl_no_ints_sig
add wave -noupdate -divider STATE
add wave -noupdate -color Aquamarine /test_interrupts/iff1_sig
add wave -noupdate -color Aquamarine /test_interrupts/iff2_sig
add wave -noupdate -color Pink /test_interrupts/im1_sig
add wave -noupdate -color Pink /test_interrupts/im2_sig
add wave -noupdate /test_interrupts/in_nmi_sig
add wave -noupdate /test_interrupts/in_intr_sig
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1800 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 202
configure wave -valuecolwidth 66
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 1
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ns} {25800 ns}
cpu/control/simulation/modelsim/wave_pin_control.do
+33
View File
@@ -0,0 +1,33 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /test_pin_control/fFetch_sig
add wave -noupdate /test_pin_control/fMRead_sig
add wave -noupdate /test_pin_control/fMWrite_sig
add wave -noupdate /test_pin_control/fIORead_sig
add wave -noupdate /test_pin_control/fIOWrite_sig
add wave -noupdate /test_pin_control/T1_sig
add wave -noupdate /test_pin_control/T2_sig
add wave -noupdate /test_pin_control/T3_sig
add wave -noupdate /test_pin_control/T4_sig
add wave -noupdate -divider STATE
add wave -noupdate -color Pink /test_pin_control/bus_ab_pin_we_sig
add wave -noupdate -color Pink /test_pin_control/bus_db_pin_oe_sig
add wave -noupdate -color Pink /test_pin_control/bus_db_pin_re_sig
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1400 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 240
configure wave -valuecolwidth 54
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 1
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {4600 ns}
cpu/control/simulation/modelsim/wave_reset.do
+31
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@@ -0,0 +1,31 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /test_reset/clk
add wave -noupdate /test_reset/reset_in
add wave -noupdate /test_reset/fpga_reset
add wave -noupdate /test_reset/M1
add wave -noupdate /test_reset/T2
add wave -noupdate -color Gold /test_reset/clrpc
add wave -noupdate /test_reset/reset_block/nhold_clk_wait
add wave -noupdate /test_reset/nreset
add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x1
add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x2
add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x3
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2800 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 112
configure wave -valuecolwidth 73
configure wave -justifyvalue right
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 1
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {13700 ns}
cpu/control/simulation/modelsim/wave_sequencer.do
+40
View File
@@ -0,0 +1,40 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /test_sequencer/clk
add wave -noupdate /test_sequencer/nreset
add wave -noupdate /test_sequencer/nextM_sig
add wave -noupdate /test_sequencer/setM1_sig
add wave -noupdate /test_sequencer/hold_clk_iorq_sig
add wave -noupdate /test_sequencer/hold_clk_wait_sig
add wave -noupdate /test_sequencer/hold_clk_busrq_sig
add wave -noupdate -divider M-STATE
add wave -noupdate -color Aquamarine /test_sequencer/M1_sig
add wave -noupdate -color Aquamarine /test_sequencer/M2_sig
add wave -noupdate -color Aquamarine /test_sequencer/M3_sig
add wave -noupdate -color Aquamarine /test_sequencer/M4_sig
add wave -noupdate -color Aquamarine /test_sequencer/M5_sig
add wave -noupdate -divider T-STATE
add wave -noupdate -color Pink /test_sequencer/T1_sig
add wave -noupdate -color Pink /test_sequencer/T2_sig
add wave -noupdate -color Pink /test_sequencer/T3_sig
add wave -noupdate -color Pink /test_sequencer/T4_sig
add wave -noupdate -color Pink /test_sequencer/T5_sig
add wave -noupdate -color Pink /test_sequencer/T6_sig
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {6800 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 226
configure wave -valuecolwidth 78
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 1
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {25 us}
cpu/control/temp_wires.vh
+694
View File
@@ -0,0 +1,694 @@
// Automatically generated by gencompile.py
reg ctl_reg_gp_sel_pla17npla50M1T1_2;
reg ctl_reg_gp_hilo_pla17npla50M1T1_3;
reg ctl_reg_sys_hilo_pla17npla50M2T1_3;
reg ctl_reg_sys_hilo_pla17npla50M2T2_4;
reg ctl_reg_gp_sel_pla61npla58npla59M1T1_2;
reg ctl_reg_gp_hilo_pla61npla58npla59M1T1_3;
reg ctl_reg_gp_sel_pla61npla58npla59M1T4_3;
reg ctl_reg_gp_hilo_pla61npla58npla59M1T4_4;
reg ctl_reg_gp_sel_use_ixiypla58M1T1_2;
reg ctl_reg_gp_hilo_use_ixiypla58M1T1_3;
reg ctl_reg_sys_hilo_use_ixiypla58M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla58M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla58M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla58M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla59M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla59M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla59M1T4_4;
reg ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5;
reg ctl_reg_gp_sel_nuse_ixiypla59M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla59M4T1_3;
reg ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4;
reg ctl_reg_sys_hilo_pla40M2T1_3;
reg ctl_reg_sys_hilo_pla40M2T2_4;
reg ctl_reg_sys_hilo_pla40M3T1_3;
reg ctl_reg_sys_hilo_pla40M3T2_4;
reg ctl_reg_sys_hilo_pla50npla40M2T1_3;
reg ctl_reg_sys_hilo_pla50npla40M2T2_4;
reg ctl_reg_gp_sel_pla50npla40M3T1_2;
reg ctl_reg_gp_hilo_pla50npla40M3T1_3;
reg ctl_reg_gp_sel_pla8pla13M1T4_4;
reg ctl_reg_gp_hilo_pla8pla13M1T4_5;
reg ctl_reg_gp_sel_pla8pla13M2T1_2;
reg ctl_reg_gp_hilo_pla8pla13M2T1_3;
reg ctl_reg_sys_hilo_pla8pla13M2T2_4;
reg ctl_reg_gp_sel_pla8npla13M1T1_2;
reg ctl_reg_gp_hilo_pla8npla13M1T1_3;
reg ctl_reg_gp_sel_pla8npla13M2T1_2;
reg ctl_reg_gp_hilo_pla8npla13M2T1_3;
reg ctl_reg_sys_hilo_pla8npla13M2T2_4;
reg ctl_reg_sys_hilo_pla38pla13M2T1_3;
reg ctl_reg_sys_hilo_pla38pla13M2T2_4;
reg ctl_reg_sys_hilo_pla38pla13M2T3_6;
reg ctl_reg_sys_hilo_pla38pla13M3T1_3;
reg ctl_reg_sys_hilo_pla38pla13M3T2_4;
reg ctl_reg_sys_hilo_pla38pla13M3T3_5;
reg ctl_reg_sys_hilo_pla38pla13M3T3_10;
reg ctl_reg_gp_sel_pla38pla13M4T1_3;
reg ctl_reg_gp_hilo_pla38pla13M4T1_4;
reg ctl_reg_sys_hilo_pla38pla13M4T2_4;
reg ctl_reg_gp_sel_pla38npla13M1T1_2;
reg ctl_reg_gp_hilo_pla38npla13M1T1_3;
reg ctl_reg_sys_hilo_pla38npla13M2T1_3;
reg ctl_reg_sys_hilo_pla38npla13M2T2_4;
reg ctl_reg_sys_hilo_pla38npla13M2T3_6;
reg ctl_reg_sys_hilo_pla38npla13M3T1_3;
reg ctl_reg_sys_hilo_pla38npla13M3T2_4;
reg ctl_reg_sys_hilo_pla38npla13M3T3_6;
reg ctl_reg_sys_hilo_pla38npla13M4T1_3;
reg ctl_reg_sys_hilo_pla38npla13M4T2_4;
reg ctl_reg_gp_sel_pla83M1T1_2;
reg ctl_reg_gp_hilo_pla83M1T1_3;
reg ctl_pf_sel_pla83M1T1_19;
reg ctl_reg_gp_sel_pla83M1T2_2;
reg ctl_reg_gp_hilo_pla83M1T2_3;
reg ctl_reg_gp_sel_pla83M1T3_1;
reg ctl_reg_gp_hilo_pla83M1T3_2;
reg ctl_reg_sys_hilo_pla83M1T4_3;
reg ctl_reg_gp_sel_pla57M1T3_1;
reg ctl_reg_gp_hilo_pla57M1T3_2;
reg ctl_reg_sys_hilo_pla57M1T4_4;
reg ctl_reg_gp_sel_pla7M1T1_2;
reg ctl_reg_gp_hilo_pla7M1T1_3;
reg ctl_reg_sys_hilo_pla7M2T1_3;
reg ctl_reg_sys_hilo_pla7M2T2_4;
reg ctl_reg_sys_hilo_pla7M3T1_3;
reg ctl_reg_gp_sel_pla7M3T1_6;
reg ctl_reg_gp_hilo_pla7M3T1_7;
reg ctl_reg_sys_hilo_pla7M3T2_4;
reg ctl_reg_sys_hilo_pla30pla13M2T1_3;
reg ctl_reg_sys_hilo_pla30pla13M2T2_4;
reg ctl_reg_sys_hilo_pla30pla13M2T3_6;
reg ctl_reg_sys_hilo_pla30pla13M3T1_3;
reg ctl_reg_sys_hilo_pla30pla13M3T2_4;
reg ctl_reg_sys_hilo_pla30pla13M3T3_5;
reg ctl_reg_sys_hilo_pla30pla13M3T3_10;
reg ctl_reg_gp_sel_pla30pla13M4T1_3;
reg ctl_reg_gp_hilo_pla30pla13M4T1_4;
reg ctl_reg_sys_hilo_pla30pla13M4T2_4;
reg ctl_reg_sys_hilo_pla30pla13M4T3_5;
reg ctl_reg_gp_sel_pla30pla13M5T1_3;
reg ctl_reg_gp_hilo_pla30pla13M5T1_4;
reg ctl_reg_sys_hilo_pla30pla13M5T2_4;
reg ctl_reg_sys_hilo_pla30npla13M2T1_3;
reg ctl_reg_sys_hilo_pla30npla13M2T2_4;
reg ctl_reg_sys_hilo_pla30npla13M2T3_6;
reg ctl_reg_sys_hilo_pla30npla13M3T1_3;
reg ctl_reg_sys_hilo_pla30npla13M3T2_4;
reg ctl_reg_sys_hilo_pla30npla13M3T3_6;
reg ctl_reg_sys_hilo_pla30npla13M4T1_3;
reg ctl_reg_sys_hilo_pla30npla13M4T2_4;
reg ctl_reg_gp_sel_pla30npla13M4T3_5;
reg ctl_reg_gp_hilo_pla30npla13M4T3_6;
reg ctl_reg_sys_hilo_pla30npla13M5T1_3;
reg ctl_reg_sys_hilo_pla30npla13M5T2_4;
reg ctl_reg_gp_sel_pla30npla13M5T3_4;
reg ctl_reg_gp_hilo_pla30npla13M5T3_5;
reg ctl_reg_sys_hilo_pla31pla33M2T1_3;
reg ctl_reg_sys_hilo_pla31pla33M2T2_4;
reg ctl_reg_sys_hilo_pla31pla33M2T3_6;
reg ctl_reg_sys_hilo_pla31pla33M3T1_3;
reg ctl_reg_sys_hilo_pla31pla33M3T2_4;
reg ctl_reg_sys_hilo_pla31pla33M3T3_5;
reg ctl_reg_sys_hilo_pla31pla33M3T3_10;
reg ctl_reg_gp_sel_pla31pla33M4T1_3;
reg ctl_reg_gp_hilo_pla31pla33M4T1_4;
reg ctl_reg_sys_hilo_pla31pla33M4T2_4;
reg ctl_reg_sys_hilo_pla31pla33M4T3_5;
reg ctl_reg_gp_sel_pla31pla33M5T1_3;
reg ctl_reg_gp_hilo_pla31pla33M5T1_4;
reg ctl_reg_sys_hilo_pla31pla33M5T2_4;
reg ctl_reg_sys_hilo_pla31npla33M2T1_3;
reg ctl_reg_sys_hilo_pla31npla33M2T2_4;
reg ctl_reg_sys_hilo_pla31npla33M2T3_6;
reg ctl_reg_sys_hilo_pla31npla33M3T1_3;
reg ctl_reg_sys_hilo_pla31npla33M3T2_4;
reg ctl_reg_sys_hilo_pla31npla33M3T3_6;
reg ctl_reg_sys_hilo_pla31npla33M4T1_3;
reg ctl_reg_sys_hilo_pla31npla33M4T2_4;
reg ctl_reg_gp_sel_pla31npla33M4T3_5;
reg ctl_reg_gp_hilo_pla31npla33M4T3_6;
reg ctl_reg_sys_hilo_pla31npla33M5T1_3;
reg ctl_reg_sys_hilo_pla31npla33M5T2_4;
reg ctl_reg_gp_sel_pla31npla33M5T3_4;
reg ctl_reg_gp_hilo_pla31npla33M5T3_5;
reg ctl_reg_gp_sel_pla5M1T4_2;
reg ctl_reg_gp_hilo_pla5M1T4_3;
reg ctl_reg_gp_sel_pla5M1T5_2;
reg ctl_reg_gp_hilo_pla5M1T5_3;
reg ctl_reg_gp_sel_pla23pla16M1T5_4;
reg ctl_reg_gp_hilo_pla23pla16M1T5_5;
reg ctl_reg_gp_sel_pla23pla16M2T1_5;
reg ctl_reg_gp_hilo_pla23pla16M2T1_6;
reg ctl_reg_gp_sel_pla23pla16M2T2_3;
reg ctl_reg_gp_hilo_pla23pla16M2T2_4;
reg ctl_reg_gp_sel_pla23pla16M2T3_5;
reg ctl_reg_gp_hilo_pla23pla16M2T3_6;
reg ctl_reg_gp_sel_pla23pla16M3T1_5;
reg ctl_reg_gp_hilo_pla23pla16M3T1_6;
reg ctl_reg_gp_sel_pla23pla16M3T2_3;
reg ctl_reg_gp_hilo_pla23pla16M3T2_4;
reg ctl_reg_gp_sel_pla23npla16M2T1_3;
reg ctl_reg_gp_hilo_pla23npla16M2T1_4;
reg ctl_reg_gp_sel_pla23npla16M2T2_3;
reg ctl_reg_gp_hilo_pla23npla16M2T2_4;
reg ctl_reg_gp_sel_pla23npla16M2T3_5;
reg ctl_reg_gp_hilo_pla23npla16M2T3_6;
reg ctl_reg_gp_sel_pla23npla16M3T1_3;
reg ctl_reg_gp_hilo_pla23npla16M3T1_4;
reg ctl_reg_gp_sel_pla23npla16M3T2_3;
reg ctl_reg_gp_hilo_pla23npla16M3T2_4;
reg ctl_reg_gp_sel_pla23npla16M3T3_4;
reg ctl_reg_gp_hilo_pla23npla16M3T3_5;
reg ctl_reg_gp_sel_pla10M2T1_3;
reg ctl_reg_gp_hilo_pla10M2T1_4;
reg ctl_reg_gp_sel_pla10M2T2_3;
reg ctl_reg_gp_hilo_pla10M2T2_4;
reg ctl_reg_sys_hilo_pla10M2T3_6;
reg ctl_reg_gp_sel_pla10M3T1_3;
reg ctl_reg_gp_hilo_pla10M3T1_4;
reg ctl_reg_gp_sel_pla10M3T2_3;
reg ctl_reg_gp_hilo_pla10M3T2_4;
reg ctl_reg_sys_hilo_pla10M3T3_4;
reg ctl_reg_gp_sel_pla10M3T4_4;
reg ctl_reg_gp_hilo_pla10M3T4_5;
reg ctl_reg_gp_sel_pla10M4T1_5;
reg ctl_reg_gp_hilo_pla10M4T1_6;
reg ctl_reg_gp_sel_pla10M4T2_3;
reg ctl_reg_gp_hilo_pla10M4T2_4;
reg ctl_reg_gp_sel_pla10M4T3_5;
reg ctl_reg_gp_hilo_pla10M4T3_6;
reg ctl_reg_gp_sel_pla10M5T1_5;
reg ctl_reg_gp_hilo_pla10M5T1_6;
reg ctl_reg_gp_sel_pla10M5T2_3;
reg ctl_reg_gp_hilo_pla10M5T2_4;
reg ctl_reg_sys_hilo_pla10M5T3_3;
reg ctl_reg_gp_sel_pla10M5T4_2;
reg ctl_reg_gp_hilo_pla10M5T4_3;
reg ctl_pf_sel_pla12M1T1_12;
reg ctl_reg_gp_sel_pla12M1T2_2;
reg ctl_reg_gp_hilo_pla12M1T2_3;
reg ctl_reg_gp_sel_pla12M1T3_1;
reg ctl_reg_gp_hilo_pla12M1T3_2;
reg ctl_reg_gp_sel_pla12M2T1_2;
reg ctl_reg_gp_hilo_pla12M2T1_3;
reg ctl_reg_gp_sel_pla12M2T2_3;
reg ctl_reg_gp_hilo_pla12M2T2_4;
reg ctl_reg_gp_sel_pla12M3T1_2;
reg ctl_reg_gp_hilo_pla12M3T1_3;
reg ctl_reg_gp_sel_pla12M3T2_3;
reg ctl_reg_gp_hilo_pla12M3T2_4;
reg ctl_reg_gp_sel_pla12M3T3_2;
reg ctl_reg_gp_hilo_pla12M3T3_3;
reg ctl_reg_gp_sel_pla12M3T4_2;
reg ctl_reg_gp_hilo_pla12M3T4_3;
reg ctl_reg_sys_hilo_pla12M4T1_2;
reg ctl_reg_sys_hilo_pla12M4T2_3;
reg ctl_reg_sys_hilo_pla12M4T3_2;
reg ctl_reg_sys_hilo_pla12M4T4_3;
reg ctl_pf_sel_pla11M1T1_11;
reg ctl_reg_gp_sel_pla11M1T2_2;
reg ctl_reg_gp_hilo_pla11M1T2_3;
reg ctl_reg_gp_sel_pla11M1T3_1;
reg ctl_reg_gp_hilo_pla11M1T3_2;
reg ctl_reg_gp_sel_pla11M2T1_2;
reg ctl_reg_gp_hilo_pla11M2T1_3;
reg ctl_reg_gp_sel_pla11M2T2_3;
reg ctl_reg_gp_hilo_pla11M2T2_4;
reg ctl_reg_gp_sel_pla11M3T3_1;
reg ctl_reg_gp_hilo_pla11M3T3_2;
reg ctl_reg_gp_sel_pla11M3T4_2;
reg ctl_reg_gp_hilo_pla11M3T4_3;
reg ctl_reg_sys_hilo_pla11M4T1_2;
reg ctl_reg_sys_hilo_pla11M4T2_3;
reg ctl_reg_sys_hilo_pla11M4T3_2;
reg ctl_reg_sys_hilo_pla11M4T4_3;
reg ctl_reg_gp_sel_pla65npla52M1T2_2;
reg ctl_reg_gp_hilo_pla65npla52M1T2_3;
reg ctl_reg_gp_sel_pla65npla52M1T3_1;
reg ctl_reg_gp_hilo_pla65npla52M1T3_2;
reg ctl_reg_gp_sel_pla65npla52M1T4_3;
reg ctl_reg_gp_hilo_pla65npla52M1T4_4;
reg ctl_reg_gp_sel_pla64M1T2_2;
reg ctl_reg_gp_hilo_pla64M1T2_3;
reg ctl_reg_gp_sel_pla64M1T3_1;
reg ctl_reg_gp_hilo_pla64M1T3_2;
reg ctl_reg_gp_sel_pla64M1T4_4;
reg ctl_reg_gp_hilo_pla64M1T4_5;
reg ctl_reg_sys_hilo_pla64M2T1_3;
reg ctl_reg_sys_hilo_pla64M2T2_4;
reg ctl_reg_gp_sel_use_ixiypla52M1T3_1;
reg ctl_reg_gp_hilo_use_ixiypla52M1T3_2;
reg ctl_reg_sys_hilo_use_ixiypla52M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla52M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla52M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla52M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla52M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla52M4T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3;
reg ctl_reg_gp_sel_pla66npla53M1T1_2;
reg ctl_reg_gp_hilo_pla66npla53M1T1_3;
reg ctl_pf_sel_pla66npla53M1T1_15;
reg ctl_reg_gp_sel_pla66npla53M1T2_2;
reg ctl_reg_gp_hilo_pla66npla53M1T2_3;
reg ctl_reg_gp_sel_pla66npla53M1T3_1;
reg ctl_reg_gp_hilo_pla66npla53M1T3_2;
reg ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1;
reg ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2;
reg ctl_reg_gp_sel_use_ixiypla53M1T3_1;
reg ctl_reg_gp_hilo_use_ixiypla53M1T3_2;
reg ctl_reg_sys_hilo_use_ixiypla53M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla53M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla53M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla53M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla53M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3;
reg ctl_pf_sel_nuse_ixiypla53M2T4_14;
reg ctl_pf_sel_nuse_ixiypla53M4T4_14;
reg ctl_reg_gp_sel_pla69M1T2_2;
reg ctl_reg_gp_hilo_pla69M1T2_3;
reg ctl_reg_gp_sel_pla69M1T3_1;
reg ctl_reg_gp_hilo_pla69M1T3_2;
reg ctl_reg_gp_sel_pla69M1T4_3;
reg ctl_reg_gp_hilo_pla69M1T4_4;
reg ctl_reg_gp_sel_pla69M2T1_1;
reg ctl_reg_gp_hilo_pla69M2T1_2;
reg ctl_reg_sys_hilo_pla69M2T2_3;
reg ctl_reg_gp_sel_pla69M2T3_1;
reg ctl_reg_gp_hilo_pla69M2T3_2;
reg ctl_reg_gp_sel_pla69M2T4_2;
reg ctl_reg_gp_hilo_pla69M2T4_3;
reg ctl_reg_sys_hilo_pla69M3T1_2;
reg ctl_reg_sys_hilo_pla69M3T1_7;
reg ctl_reg_gp_sel_pla69M3T2_2;
reg ctl_reg_gp_hilo_pla69M3T2_3;
reg ctl_reg_gp_sel_op3pla68M1T2_2;
reg ctl_reg_gp_hilo_op3pla68M1T2_3;
reg ctl_reg_gp_sel_op3pla68M1T3_1;
reg ctl_reg_gp_hilo_op3pla68M1T3_2;
reg ctl_reg_gp_sel_op3pla68M1T4_3;
reg ctl_reg_gp_hilo_op3pla68M1T4_4;
reg ctl_reg_gp_sel_op3pla68M2T1_1;
reg ctl_reg_gp_hilo_op3pla68M2T1_2;
reg ctl_reg_sys_hilo_op3pla68M2T2_3;
reg ctl_reg_gp_sel_op3pla68M2T3_1;
reg ctl_reg_gp_hilo_op3pla68M2T3_2;
reg ctl_reg_gp_sel_op3pla68M2T4_2;
reg ctl_reg_gp_hilo_op3pla68M2T4_3;
reg ctl_reg_sys_hilo_op3pla68M3T1_2;
reg ctl_reg_sys_hilo_op3pla68M3T1_7;
reg ctl_pf_sel_op3pla68M3T1_18;
reg ctl_reg_gp_sel_op3pla68M3T2_2;
reg ctl_reg_gp_hilo_op3pla68M3T2_3;
reg ctl_reg_gp_sel_nop3pla68M1T2_2;
reg ctl_reg_gp_hilo_nop3pla68M1T2_3;
reg ctl_reg_gp_sel_nop3pla68M1T3_1;
reg ctl_reg_gp_hilo_nop3pla68M1T3_2;
reg ctl_reg_gp_sel_nop3pla68M1T4_3;
reg ctl_reg_gp_hilo_nop3pla68M1T4_4;
reg ctl_reg_gp_sel_nop3pla68M2T1_1;
reg ctl_reg_gp_hilo_nop3pla68M2T1_2;
reg ctl_reg_sys_hilo_nop3pla68M2T2_3;
reg ctl_reg_gp_sel_nop3pla68M2T3_1;
reg ctl_reg_gp_hilo_nop3pla68M2T3_2;
reg ctl_reg_gp_sel_nop3pla68M2T4_2;
reg ctl_reg_gp_hilo_nop3pla68M2T4_3;
reg ctl_reg_sys_hilo_nop3pla68M3T1_2;
reg ctl_reg_sys_hilo_nop3pla68M3T1_7;
reg ctl_pf_sel_nop3pla68M3T1_20;
reg ctl_reg_gp_sel_nop3pla68M3T2_2;
reg ctl_reg_gp_hilo_nop3pla68M3T2_3;
reg ctl_reg_gp_sel_pla9M1T4_2;
reg ctl_reg_gp_hilo_pla9M1T4_3;
reg ctl_reg_gp_sel_pla9M1T5_2;
reg ctl_reg_gp_hilo_pla9M1T5_3;
reg ctl_reg_gp_sel_pla77M1T1_2;
reg ctl_reg_gp_hilo_pla77M1T1_3;
reg ctl_pf_sel_pla77M1T1_14;
reg ctl_reg_gp_sel_pla77M1T2_2;
reg ctl_reg_gp_hilo_pla77M1T2_3;
reg ctl_reg_gp_sel_pla77M1T3_1;
reg ctl_reg_gp_hilo_pla77M1T3_2;
reg ctl_reg_gp_sel_pla81M1T1_2;
reg ctl_reg_gp_hilo_pla81M1T1_3;
reg ctl_reg_gp_sel_pla81M1T2_2;
reg ctl_reg_gp_hilo_pla81M1T2_3;
reg ctl_reg_gp_sel_pla81M1T3_1;
reg ctl_reg_gp_hilo_pla81M1T3_2;
reg ctl_reg_gp_sel_pla82M1T1_2;
reg ctl_reg_gp_hilo_pla82M1T1_3;
reg ctl_pf_sel_pla82M1T1_16;
reg ctl_reg_gp_sel_pla82M1T2_2;
reg ctl_reg_gp_hilo_pla82M1T2_3;
reg ctl_reg_gp_sel_pla82M1T3_1;
reg ctl_reg_gp_hilo_pla82M1T3_2;
reg ctl_reg_gp_sel_pla89M1T2_2;
reg ctl_reg_gp_hilo_pla89M1T2_3;
reg ctl_reg_gp_sel_pla89M1T3_1;
reg ctl_reg_gp_hilo_pla89M1T3_2;
reg ctl_reg_gp_sel_pla92M1T2_2;
reg ctl_reg_gp_hilo_pla92M1T2_3;
reg ctl_reg_gp_sel_pla92M1T3_1;
reg ctl_reg_gp_hilo_pla92M1T3_2;
reg ctl_reg_gp_sel_pla25M1T1_2;
reg ctl_reg_gp_hilo_pla25M1T1_3;
reg ctl_reg_gp_sel_pla25M1T2_2;
reg ctl_reg_gp_hilo_pla25M1T2_3;
reg ctl_reg_gp_sel_pla25M1T3_1;
reg ctl_reg_gp_hilo_pla25M1T3_2;
reg ctl_reg_gp_sel_pla25M1T4_3;
reg ctl_reg_gp_hilo_pla25M1T4_4;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3;
reg ctl_pf_sel_nuse_ixiypla70npla55M1T1_20;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3;
reg ctl_pf_sel_nuse_ixiypla70npla55M5T1_19;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3;
reg ctl_pf_sel_nuse_ixiypla70pla55M3T1_19;
reg ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3;
reg ctl_pf_sel_nuse_ixiypla70pla55M5T1_19;
reg ctl_reg_gp_sel_pla15op3M1T1_2;
reg ctl_reg_gp_hilo_pla15op3M1T1_3;
reg ctl_pf_sel_pla15op3M1T1_18;
reg ctl_reg_gp_sel_pla15op3M1T2_2;
reg ctl_reg_gp_hilo_pla15op3M1T2_3;
reg ctl_reg_gp_sel_pla15op3M1T3_1;
reg ctl_reg_gp_hilo_pla15op3M1T3_2;
reg ctl_reg_gp_sel_pla15op3M2T1_2;
reg ctl_reg_gp_hilo_pla15op3M2T1_3;
reg ctl_reg_sys_hilo_pla15op3M2T2_4;
reg ctl_reg_gp_sel_pla15nop3M1T1_2;
reg ctl_reg_gp_hilo_pla15nop3M1T1_3;
reg ctl_pf_sel_pla15nop3M1T1_18;
reg ctl_reg_gp_sel_pla15nop3M1T2_2;
reg ctl_reg_gp_hilo_pla15nop3M1T2_3;
reg ctl_reg_gp_sel_pla15nop3M1T3_1;
reg ctl_reg_gp_hilo_pla15nop3M1T3_2;
reg ctl_reg_gp_sel_pla15nop3M2T1_2;
reg ctl_reg_gp_hilo_pla15nop3M2T1_3;
reg ctl_reg_sys_hilo_pla15nop3M2T2_4;
reg ctl_reg_gp_sel_pla15nop3M3T3_1;
reg ctl_reg_gp_hilo_pla15nop3M3T3_2;
reg ctl_pf_sel_nuse_ixiypla72npla55M1T1_10;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4;
reg ctl_pf_sel_nuse_ixiypla72pla55M1T1_10;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3;
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3;
reg ctl_reg_gp_sel_pla37npla28M1T1_2;
reg ctl_reg_gp_hilo_pla37npla28M1T1_3;
reg ctl_reg_sys_hilo_pla37npla28M2T1_3;
reg ctl_reg_sys_hilo_pla37npla28M2T2_4;
reg ctl_reg_gp_sel_pla37npla28M3T1_2;
reg ctl_reg_gp_hilo_pla37npla28M3T1_3;
reg ctl_reg_gp_sel_pla27npla34M1T1_2;
reg ctl_reg_gp_hilo_pla27npla34M1T1_3;
reg ctl_pf_sel_pla27npla34M1T1_20;
reg ctl_reg_gp_sel_pla27npla34M1T2_2;
reg ctl_reg_gp_hilo_pla27npla34M1T2_3;
reg ctl_reg_gp_sel_pla27npla34M1T3_1;
reg ctl_reg_gp_hilo_pla27npla34M1T3_2;
reg ctl_reg_gp_sel_pla27npla34M2T1_2;
reg ctl_reg_gp_hilo_pla27npla34M2T1_3;
reg ctl_reg_sys_hilo_pla37pla28M2T1_3;
reg ctl_reg_sys_hilo_pla37pla28M2T2_4;
reg ctl_reg_gp_sel_pla37pla28M2T3_4;
reg ctl_reg_gp_hilo_pla37pla28M2T3_5;
reg ctl_reg_gp_sel_pla37pla28M3T1_3;
reg ctl_reg_gp_hilo_pla37pla28M3T1_4;
reg ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1;
reg ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2;
reg ctl_reg_gp_sel_pla27pla34M2T1_2;
reg ctl_reg_gp_hilo_pla27pla34M2T1_3;
reg ctl_pf_sel_pla91pla21M1T1_8;
reg ctl_reg_gp_sel_pla91pla21M1T2_2;
reg ctl_reg_gp_hilo_pla91pla21M1T2_3;
reg ctl_reg_gp_sel_pla91pla21M1T3_1;
reg ctl_reg_gp_hilo_pla91pla21M1T3_2;
reg ctl_reg_gp_sel_pla91pla21M2T1_2;
reg ctl_reg_gp_hilo_pla91pla21M2T1_3;
reg ctl_reg_gp_sel_pla91pla21M2T2_2;
reg ctl_reg_gp_hilo_pla91pla21M2T2_3;
reg ctl_reg_gp_sel_pla91pla21M2T3_3;
reg ctl_reg_gp_hilo_pla91pla21M2T3_4;
reg ctl_reg_gp_sel_pla91pla21M3T1_2;
reg ctl_reg_gp_hilo_pla91pla21M3T1_3;
reg ctl_reg_gp_sel_pla91pla21M3T2_3;
reg ctl_reg_gp_hilo_pla91pla21M3T2_4;
reg ctl_reg_sys_hilo_pla91pla21M4T1_2;
reg ctl_reg_sys_hilo_pla91pla21M4T2_3;
reg ctl_reg_sys_hilo_pla91pla21M4T3_2;
reg ctl_reg_sys_hilo_pla91pla21M4T4_3;
reg ctl_pf_sel_pla91pla20M1T1_9;
reg ctl_reg_gp_sel_pla91pla20M1T2_2;
reg ctl_reg_gp_hilo_pla91pla20M1T2_3;
reg ctl_reg_gp_sel_pla91pla20M1T3_1;
reg ctl_reg_gp_hilo_pla91pla20M1T3_2;
reg ctl_reg_gp_sel_pla91pla20M1T4_2;
reg ctl_reg_gp_hilo_pla91pla20M1T4_3;
reg ctl_reg_gp_sel_pla91pla20M1T5_4;
reg ctl_reg_gp_hilo_pla91pla20M1T5_5;
reg ctl_reg_gp_sel_pla91pla20M2T1_2;
reg ctl_reg_gp_hilo_pla91pla20M2T1_3;
reg ctl_reg_gp_sel_pla91pla20M2T2_3;
reg ctl_reg_gp_hilo_pla91pla20M2T2_4;
reg ctl_reg_gp_sel_pla91pla20M2T3_4;
reg ctl_reg_gp_hilo_pla91pla20M2T3_5;
reg ctl_reg_gp_sel_pla91pla20M3T1_2;
reg ctl_reg_gp_hilo_pla91pla20M3T1_3;
reg ctl_reg_sys_hilo_pla91pla20M4T1_2;
reg ctl_reg_sys_hilo_pla91pla20M4T2_3;
reg ctl_reg_sys_hilo_pla91pla20M4T3_2;
reg ctl_reg_sys_hilo_pla91pla20M4T4_3;
reg ctl_reg_sys_hilo_pla29M2T1_3;
reg ctl_reg_sys_hilo_pla29M2T2_4;
reg ctl_reg_sys_hilo_pla29M2T3_6;
reg ctl_reg_sys_hilo_pla29M3T1_3;
reg ctl_reg_sys_hilo_pla29M3T2_4;
reg ctl_reg_sys_hilo_pla29M3T3_4;
reg ctl_reg_sys_hilo_pla29M3T3_9;
reg ctl_reg_gp_sel_pla43M1T3_1;
reg ctl_reg_gp_hilo_pla43M1T3_2;
reg ctl_reg_sys_hilo_pla43M2T1_3;
reg ctl_reg_sys_hilo_pla43M2T2_4;
reg ctl_reg_sys_hilo_pla43M2T3_6;
reg ctl_reg_sys_hilo_pla43M3T1_3;
reg ctl_reg_sys_hilo_pla43M3T2_4;
reg ctl_reg_sys_hilo_pla43M3T3_5;
reg ctl_reg_sys_hilo_pla43M3T3_10;
reg ctl_reg_gp_sel_pla47M1T3_1;
reg ctl_reg_gp_hilo_pla47M1T3_2;
reg ctl_reg_sys_hilo_pla47M2T1_3;
reg ctl_reg_sys_hilo_pla47M2T2_4;
reg ctl_reg_sys_hilo_pla47M3T2_2;
reg ctl_reg_sys_hilo_pla47M3T3_3;
reg ctl_reg_sys_hilo_pla47M3T4_2;
reg ctl_reg_sys_hilo_pla47M3T5_3;
reg ctl_reg_sys_hilo_pla47M3T5_8;
reg ctl_reg_gp_sel_pla48M1T3_1;
reg ctl_reg_gp_hilo_pla48M1T3_2;
reg ctl_reg_sys_hilo_pla48M2T1_3;
reg ctl_reg_sys_hilo_pla48M2T2_4;
reg ctl_reg_sys_hilo_pla48M3T2_2;
reg ctl_reg_sys_hilo_pla48M3T3_3;
reg ctl_reg_sys_hilo_pla48M3T4_2;
reg ctl_reg_sys_hilo_pla48M3T5_3;
reg ctl_reg_sys_hilo_pla48M3T5_8;
reg ctl_reg_gp_sel_pla6M1T4_3;
reg ctl_reg_gp_hilo_pla6M1T4_4;
reg ctl_reg_gp_sel_pla26M1T3_1;
reg ctl_reg_gp_hilo_pla26M1T3_2;
reg ctl_reg_gp_sel_pla26M1T4_2;
reg ctl_reg_gp_hilo_pla26M1T4_3;
reg ctl_reg_gp_sel_pla26M1T5_4;
reg ctl_reg_gp_hilo_pla26M1T5_5;
reg ctl_reg_sys_hilo_pla26M2T1_3;
reg ctl_reg_sys_hilo_pla26M2T2_4;
reg ctl_reg_sys_hilo_pla26M3T2_2;
reg ctl_reg_sys_hilo_pla26M3T3_3;
reg ctl_reg_sys_hilo_pla26M3T4_2;
reg ctl_reg_sys_hilo_pla26M3T5_3;
reg ctl_reg_sys_hilo_pla26M3T5_8;
reg ctl_reg_sys_hilo_pla24M2T1_3;
reg ctl_reg_sys_hilo_pla24M2T2_4;
reg ctl_reg_sys_hilo_pla24M2T3_6;
reg ctl_reg_sys_hilo_pla24M3T1_3;
reg ctl_reg_sys_hilo_pla24M3T2_4;
reg ctl_reg_sys_hilo_pla24M3T3_4;
reg ctl_reg_gp_sel_pla24M3T4_4;
reg ctl_reg_gp_hilo_pla24M3T4_5;
reg ctl_reg_sys_hilo_pla24M4T1_6;
reg ctl_reg_gp_sel_pla24M4T2_3;
reg ctl_reg_gp_hilo_pla24M4T2_4;
reg ctl_reg_gp_sel_pla24M4T3_5;
reg ctl_reg_gp_hilo_pla24M4T3_6;
reg ctl_reg_sys_hilo_pla24M5T1_6;
reg ctl_reg_gp_sel_pla24M5T2_3;
reg ctl_reg_gp_hilo_pla24M5T2_4;
reg ctl_reg_sys_hilo_pla24M5T3_4;
reg ctl_reg_gp_sel_pla42M1T3_1;
reg ctl_reg_gp_hilo_pla42M1T3_2;
reg ctl_reg_sys_hilo_pla42M2T1_3;
reg ctl_reg_sys_hilo_pla42M2T2_4;
reg ctl_reg_sys_hilo_pla42M2T3_6;
reg ctl_reg_sys_hilo_pla42M3T1_3;
reg ctl_reg_sys_hilo_pla42M3T2_4;
reg ctl_reg_sys_hilo_pla42M3T3_6;
reg ctl_reg_gp_sel_pla42M3T4_4;
reg ctl_reg_gp_hilo_pla42M3T4_5;
reg ctl_reg_sys_hilo_pla42M4T1_6;
reg ctl_reg_gp_sel_pla42M4T2_3;
reg ctl_reg_gp_hilo_pla42M4T2_4;
reg ctl_reg_gp_sel_pla42M4T3_5;
reg ctl_reg_gp_hilo_pla42M4T3_6;
reg ctl_reg_sys_hilo_pla42M5T1_6;
reg ctl_reg_gp_sel_pla42M5T2_3;
reg ctl_reg_gp_hilo_pla42M5T2_4;
reg ctl_reg_sys_hilo_pla42M5T3_4;
reg ctl_reg_gp_sel_pla35M2T1_3;
reg ctl_reg_gp_hilo_pla35M2T1_4;
reg ctl_reg_gp_sel_pla35M2T2_3;
reg ctl_reg_gp_hilo_pla35M2T2_4;
reg ctl_reg_sys_hilo_pla35M2T3_6;
reg ctl_reg_gp_sel_pla35M3T1_3;
reg ctl_reg_gp_hilo_pla35M3T1_4;
reg ctl_reg_gp_sel_pla35M3T2_3;
reg ctl_reg_gp_hilo_pla35M3T2_4;
reg ctl_reg_sys_hilo_pla35M3T3_4;
reg ctl_reg_sys_hilo_pla35M3T3_9;
reg ctl_reg_gp_sel_pla45M1T3_1;
reg ctl_reg_gp_hilo_pla45M1T3_2;
reg ctl_reg_gp_sel_pla45M2T1_3;
reg ctl_reg_gp_hilo_pla45M2T1_4;
reg ctl_reg_gp_sel_pla45M2T2_3;
reg ctl_reg_gp_hilo_pla45M2T2_4;
reg ctl_reg_sys_hilo_pla45M2T3_6;
reg ctl_reg_gp_sel_pla45M3T1_3;
reg ctl_reg_gp_hilo_pla45M3T1_4;
reg ctl_reg_gp_sel_pla45M3T2_3;
reg ctl_reg_gp_hilo_pla45M3T2_4;
reg ctl_reg_sys_hilo_pla45M3T3_4;
reg ctl_reg_sys_hilo_pla45M3T3_9;
reg ctl_reg_gp_sel_pla46M2T1_3;
reg ctl_reg_gp_hilo_pla46M2T1_4;
reg ctl_reg_gp_sel_pla46M2T2_3;
reg ctl_reg_gp_hilo_pla46M2T2_4;
reg ctl_reg_sys_hilo_pla46M2T3_6;
reg ctl_reg_gp_sel_pla46M3T1_3;
reg ctl_reg_gp_hilo_pla46M3T1_4;
reg ctl_reg_gp_sel_pla46M3T2_3;
reg ctl_reg_gp_hilo_pla46M3T2_4;
reg ctl_reg_sys_hilo_pla46M3T3_4;
reg ctl_reg_sys_hilo_pla46M3T3_9;
reg ctl_reg_sys_hilo_pla56M1T3_3;
reg ctl_reg_gp_sel_pla56M1T5_4;
reg ctl_reg_gp_hilo_pla56M1T5_5;
reg ctl_reg_sys_hilo_pla56M2T1_6;
reg ctl_reg_gp_sel_pla56M2T2_3;
reg ctl_reg_gp_hilo_pla56M2T2_4;
reg ctl_reg_gp_sel_pla56M2T3_5;
reg ctl_reg_gp_hilo_pla56M2T3_6;
reg ctl_reg_sys_hilo_pla56M3T1_6;
reg ctl_reg_gp_sel_pla56M3T2_3;
reg ctl_reg_gp_hilo_pla56M3T2_4;
reg ctl_reg_sys_hilo_pla56M3T3_6;
reg ctl_reg_sys_hilo_pla56M4T1_3;
reg ctl_reg_sys_hilo_pla56M4T3_6;
reg ctl_reg_sys_hilo_pla56M5T1_3;
reg ctl_reg_sys_hilo_pla56M5T3_4;
reg ctl_reg_sys_hilo_pla56M5T3_9;
reg ctl_reg_gp_sel_pla49M1T3_1;
reg ctl_reg_gp_hilo_pla49M1T3_2;
reg ctl_reg_sys_hilo_pla49M2T1_3;
reg ctl_reg_sys_hilo_pla49M2T2_4;
reg ctl_reg_sys_hilo_pla49M3T1_3;
reg ctl_reg_sys_hilo_pla49M3T2_4;
reg ctl_pf_sel_pla76M1T1_2;
reg ctl_reg_gp_sel_pla78M1T1_2;
reg ctl_reg_gp_hilo_pla78M1T1_3;
reg ctl_pf_sel_pla78M1T1_8;
reg ctl_reg_gp_sel_pla79M1T1_2;
reg ctl_reg_gp_hilo_pla79M1T1_3;
reg ctl_pf_sel_pla79M1T1_8;
reg ctl_reg_gp_sel_pla80M1T1_2;
reg ctl_reg_gp_hilo_pla80M1T1_3;
reg ctl_pf_sel_pla80M1T1_8;
reg ctl_reg_gp_sel_pla84M1T1_2;
reg ctl_reg_gp_hilo_pla84M1T1_3;
reg ctl_pf_sel_pla84M1T1_8;
reg ctl_reg_gp_sel_pla85M1T1_2;
reg ctl_reg_gp_hilo_pla85M1T1_3;
reg ctl_pf_sel_pla85M1T1_8;
reg ctl_reg_gp_sel_pla86M1T1_2;
reg ctl_reg_gp_hilo_pla86M1T1_3;
reg ctl_pf_sel_pla86M1T1_8;
reg ctl_reg_gp_sel_pla88M1T1_2;
reg ctl_reg_gp_hilo_pla88M1T1_3;
reg ctl_pf_sel_pla88M1T1_8;
reg ctl_reg_gp_sel_ixy_dT2_1;
reg ctl_reg_gp_hilo_ixy_dT2_2;
reg ctl_reg_sys_hilo_ixy_dT3_3;
reg ctl_reg_gp_sel_ixy_dT4_1;
reg ctl_reg_gp_hilo_ixy_dT4_2;
reg ctl_reg_sys_hilo_ixy_dT5_2;
reg ctl_reg_sys_hilo_ixy_dT5_7;
reg ctl_reg_sys_hilo_1M1T1_3;
reg ctl_reg_sys_hilo_1M1T2_2;
reg ctl_reg_sys_hilo_1M1T3_3;
reg ctl_reg_sys_hilo_setM1_2;
cpu/control/test_control.qpf
+30
View File
@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 09:22:29 October 13, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "09:22:29 October 13, 2014"
# Revisions
PROJECT_REVISION = "test_control"
cpu/control/test_control.qsf
+74
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@@ -0,0 +1,74 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 09:22:29 October 13, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# test_control_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY execute
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:22:29 OCTOBER 13, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name VERILOG_FILE pla_decode.v
set_global_assignment -name VERILOG_FILE execute.v
set_global_assignment -name BDF_FILE sequencer.bdf
set_global_assignment -name BDF_FILE resets.bdf
set_global_assignment -name BDF_FILE memory_ifc.bdf
set_global_assignment -name BDF_FILE ir.bdf
set_global_assignment -name BDF_FILE interrupts.bdf
set_global_assignment -name BDF_FILE decode_state.bdf
set_global_assignment -name BDF_FILE clk_delay.bdf
set_global_assignment -name BDF_FILE pin_control.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
cpu/control/test_decode.sv
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//==============================================================
// Test PLA decode and combinatorial static execute
//==============================================================
`timescale 100 ns/ 100 ns
module test_decode;
reg [7:0] ir_sig;
reg [4:0] prefix_sig;
wire [107:0] pla_sig;
// ----------------- TEST -------------------
initial begin
integer opcode;
// Test every opcode in the first table
//================================================
// Regular instructions with no prefix
//================================================
$display("START IXY0:XX");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b10100;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
//================================================
// Regular instructions with IX/IY prefix
//================================================
$display("START IXY1:XX");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
//================================================
// CD instructions with no prefix
//================================================
$display("START IXY0:CB");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b10010;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
//================================================
// CB instructions with IX/IY prefix
//================================================
$display("START IXY1:CB");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b01010;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
//================================================
// ED instructions with no prefix
//================================================
$display("START IXY0:ED");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b10001;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01100;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
//================================================
// ED instructions with IX/IY prefix
//================================================
$display("START IXY1:ED");
opcode = 0;
while(opcode<256) begin
#1 $display("OPCODE: 0x%2H", opcode);
prefix_sig[4:0] = 5'b01001;
ir_sig[7:0] = opcode;
#1 // Reset the IR into NOP so we get the trigger signal again
prefix_sig[4:0] = 5'b01001;
ir_sig[7:0] = 0;
opcode++;
end
#1 $display("END");
end
//--------------------------------------------------------------
// Instantiate decode blocks
//--------------------------------------------------------------
pla_decode pla_decode_inst
(
.prefix(prefix_sig) , // input [6:0] prefix_sig
.opcode(ir_sig) , // input [7:0] opcode
.pla(pla_sig) // output [104:0] pla_sig
);
execute execute_inst
(
.pla(pla_sig) , // input [107:0] pla_sig
.M1(M1_sig) , // input M1_sig
.M2(M2_sig) , // input M2_sig
.M3(M3_sig) , // input M3_sig
.M4(M4_sig) , // input M4_sig
.M5(M5_sig) , // input M5_sig
.T1(T1_sig) , // input T1_sig
.T2(T2_sig) , // input T2_sig
.T3(T3_sig) , // input T3_sig
.T4(T4_sig) , // input T4_sig
.T5(T5_sig) , // input T5_sig
.T6(T6_sig) , // input T6_sig
.nextM(nextM_sig) , // output nextM_sig
.setM1(setM1_sig) , // output setM1_sig
.setM1ss(setM1ss_sig) , // output setM1ss_sig
.setM1cc(setM1cc_sig) , // output setM1cc_sig
.setM1bz(setM1bz_sig) , // output setM1bz_sig
.fFetch(fFetch_sig) , // output fFetch_sig
.fMRead(fMRead_sig) , // output fMRead_sig
.fMWrite(fMWrite_sig) , // output fMWrite_sig
.fIORead(fIORead_sig) , // output fIORead_sig
.fIOWrite(fIOWrite_sig) , // output fIOWrite_sig
.FIntr(FIntr_sig) , // output FIntr_sig
.ctl_bus_sw1(ctl_bus_sw1_sig) , // output ctl_bus_sw1_sig
.ctl_bus_sw2(ctl_bus_sw2_sig) , // output ctl_bus_sw2_sig
.ctl_bus_sw4(ctl_bus_sw4_sig) , // output ctl_bus_sw4_sig
.ctl_al_we(ctl_al_we_sig) , // output ctl_al_we_sig
.ctl_inc_dec(ctl_inc_dec_sig) , // output ctl_inc_dec_sig
.ctl_inc_limit6(ctl_inc_limit6_sig) , // output ctl_inc_limit6_sig
.ctl_inc_cy(ctl_inc_cy_sig) , // output ctl_inc_cy_sig
.ctl_ab_mux_inc(ctl_ab_mux_inc_sig) , // output ctl_ab_mux_inc_sig
.explode(explode_sig) // output explode_sig
);
endmodule
cpu/control/test_interrupts.sv
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//==============================================================
// Test interrupts unit
//==============================================================
`timescale 100 ns/ 100 ns
module test_interrupts;
// ----------------- CLOCKS AND RESET -----------------
// Define one full T-clock cycle delay
`define T #2
bit clk = 1;
initial repeat (20) #1 clk = ~clk;
logic nreset = 0;
// ----------------- CONTROL ----------------
logic ctl_iff1_iff2_sig=0;
logic ctl_iffx_we_sig=0;
logic ctl_iffx_bit_sig=0;
logic nmi_sig=0;
logic setM1_sig=0;
logic intr_sig=0;
logic ctl_im_we_sig=0;
logic [1:0] db_sig=0;
logic clk_sig=0;
logic ctl_no_ints_sig=0;
// ----------------- STATES ----------------
wire iff1_sig;
assign iff1_sig = interrupts_inst.iff1;
wire iff2_sig;
wire im1_sig;
wire im2_sig;
wire in_nmi_sig;
wire in_intr_sig;
// ----------------- TEST -------------------
initial begin
// Init / reset
`T nreset = 1;
// Test interrupt modes
db_sig = 2'b10; // IM1
ctl_im_we_sig = 1;
`T assert(im1_sig==1 && im2_sig==0);
db_sig = 2'b11; // IM2
`T assert(im1_sig==0 && im2_sig==1);
db_sig = 2'b00; // IM0
`T assert(im1_sig==0 && im2_sig==0);
// Test IFF state flags
assert(iff1_sig==0 && iff2_sig==0);
ctl_iff1_iff2_sig = 1;
ctl_iffx_we_sig = 1;
ctl_iffx_bit_sig = 1;
`T assert(iff1_sig==0 && iff2_sig==1);
`T assert(iff1_sig==1 && iff2_sig==1);
ctl_iff1_iff2_sig = 0;
ctl_iffx_we_sig = 0;
ctl_iffx_bit_sig = 0;
// Simulate NMI triggering
nmi_sig = 1;
`T setM1_sig = 1;
`T assert(iff1_sig==0 && iff2_sig==1);
`T $display("End of test");
end
//--------------------------------------------------------------
// Instantiate interrupts
//--------------------------------------------------------------
interrupts interrupts_inst
(
.ctl_iff1_iff2(ctl_iff1_iff2_sig) , // input ctl_iff1_iff2_sig
.nmi(nmi_sig) , // input nmi_sig
.setM1(setM1_sig) , // input setM1_sig
.intr(intr_sig) , // input intr_sig
.ctl_iffx_we(ctl_iffx_we_sig) , // input ctl_iffx_we_sig
.ctl_iffx_bit(ctl_iffx_bit_sig) , // input ctl_iffx_bit_sig
.ctl_im_we(ctl_im_we_sig) , // input ctl_im_we_sig
.db(db_sig) , // input [1:0] db_sig
.clk(clk) , // input clk
.ctl_no_ints(ctl_no_ints_sig) , // input ctl_no_ints_sig
.nreset(nreset) , // input nreset
.iff2(iff2_sig) , // output iff2_sig
.im1(im1_sig) , // output im1_sig
.im2(im2_sig) , // output im2_sig
.in_nmi(in_nmi_sig) , // output in_nmi_sig
.in_intr(in_intr_sig) // output in_intr_sig
);
endmodule
cpu/control/test_pin_control.sv
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//==============================================================
// Test pin control unit
//==============================================================
`timescale 100 ns/ 100 ns
module test_pin_control;
// ----------------- CONTROL ----------------
logic fFetch_sig=0;
logic fMRead_sig=0;
logic fMWrite_sig=0;
logic fIORead_sig=0;
logic fIOWrite_sig=0;
logic T1_sig=0;
logic T2_sig=0;
logic T3_sig=0;
logic T4_sig=0;
// ----------------- STATES ----------------
wire bus_ab_pin_we_sig;
wire bus_db_pin_oe_sig;
wire bus_db_pin_re_sig;
// ----------------- TEST -------------------
initial begin
// Initial condition
#1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// Activate formula for each signal
fFetch_sig = 1;
T1_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
T1_sig = 0;
T3_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
fFetch_sig = 0;
T1_sig = 0;
T3_sig = 0;
#1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// Read phase
fMRead_sig = 1;
#1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
T1_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// Write phase
fMRead_sig = 0;
fMWrite_sig = 1;
fIORead_sig = 0;
fIOWrite_sig = 0;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// IO Read phase
fMRead_sig = 0;
fMWrite_sig = 0;
fIORead_sig = 1;
fIOWrite_sig = 0;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// IO Write phase
fMRead_sig = 0;
fMWrite_sig = 0;
fIORead_sig = 0;
fIOWrite_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
fIOWrite_sig = 0;
#1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
// Test bus pin control
T2_sig = 1;
fMWrite_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==1 && bus_db_pin_re_sig==0);
fMWrite_sig = 0;
fIORead_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);
T3_sig = 1;
#1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==1);
#1 $display("End of test");
end
//--------------------------------------------------------------
// Instantiate pin control
//--------------------------------------------------------------
pin_control pin_control_inst
(
.fFetch(fFetch_sig) , // input fFetch_sig
.fMRead(fMRead_sig) , // input fMRead_sig
.fMWrite(fMWrite_sig) , // input fMWrite_sig
.fIORead(fIORead_sig) , // input fIORead_sig
.fIOWrite(fIOWrite_sig) , // input fIOWrite_sig
.T1(T1_sig) , // input T1_sig
.T2(T2_sig) , // input T2_sig
.T3(T3_sig) , // input T3_sig
.T4(T4_sig) , // input T4_sig
.bus_ab_pin_we(bus_ab_pin_we_sig) , // output bus_ab_pin_we_sig
.bus_db_pin_oe(bus_db_pin_oe_sig) , // output bus_db_pin_oe_sig
.bus_db_pin_re(bus_db_pin_re_sig) // output bus_db_pin_re_sig
);
endmodule
cpu/control/test_reset.sv
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//==============================================================
// Test reset circuit
//==============================================================
`timescale 100 ns/ 100 ns
module test_reset;
// ----------------- CLOCKS AND RESET -----------------
`define T #2
bit clk = 1;
initial repeat (40) #1 clk = ~clk;
// Specific to FPGA, some modules in the schematic need to be pre-initialized
reg fpga_reset = 1;
always_latch
if (clk) fpga_reset <= 0;
//----------------------------------------------------------
// Input reset from the pin; state from the sequencer
//----------------------------------------------------------
logic reset_in = 0;
logic M1 = 0;
logic T2 = 0;
wire clrpc; // Load 0 to PC
wire nhold_clk_wait; // Hold clrpc
wire nreset; // Internal inverted reset signal
assign nhold_clk_wait = 1; // Will not test this case
// ----------------- TEST -------------------
initial begin
// Test normal reset sequence - 3 clocks long
`T reset_in = 1;
`T `T `T reset_in = 0;
`T assert(nreset==0);
// Out of the reset for several more cycles
// Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
`T assert(nreset==1 && clrpc==1);
`T assert(nreset==1 && clrpc==1);
`T assert(nreset==1 && clrpc==0);
`T assert(nreset==1 && clrpc==0);
`T assert(nreset==1 && clrpc==0);
// Test special reset sequence: a reset pin is briefly
// asserted at M1/T1 and CLRPC should hold until the next
// M1/T2
`T reset_in = 1; M1=1;
`T reset_in = 0; M1=1; T2=1;
`T M1=1; T2=0;
`T `T
`T assert(nreset==1 && clrpc==1);
`T M1=1; T2=1;
`T M1=1; T2=0;
`T assert(nreset==1 && clrpc==0);
`T $display("End of test");
end
//--------------------------------------------------------------
// Instantiate DUT
//--------------------------------------------------------------
resets reset_block ( .* );
endmodule
cpu/control/test_sequencer.sv
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//==============================================================
// Test sequencer
//==============================================================
`timescale 100 ns/ 100 ns
module test_sequencer;
// ----------------- CLOCKS AND RESET -----------------
// Define one full T-clock cycle delay
`define T #2
bit clk = 1;
initial repeat (100) #1 clk = ~clk;
logic nreset = 0;
// ----------------- CONTROL ----------------
logic nextM_sig;
logic setM1_sig;
logic hold_clk_iorq_sig=0;
logic hold_clk_wait_sig=0;
logic hold_clk_busrq_sig=0;
wire T6_sig;
wire M5_sig;
assign nextM_sig = T6_sig; // Restart when reaching T6
assign setM1_sig = M5_sig & T6_sig; // Restart when reaching M5/T6
// ----------------- TEST -------------------
initial begin
// Init / reset
`T nreset = 1;
repeat (100) @(posedge clk); nreset <= 1;
// This test does not use assert() -- we just check visually
`T $display("End of test");
end
//--------------------------------------------------------------
// Instantiate sequencer
//--------------------------------------------------------------
sequencer sequencer_inst
(
.clk(clk) , // input clk
.nextM(nextM_sig) , // input nextM_sig
.setM1(setM1_sig) , // input setM1_sig
.nreset(nreset) , // input nreset
.hold_clk_iorq(hold_clk_iorq_sig) , // input hold_clk_iorq_sig
.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
.hold_clk_busrq(hold_clk_busrq_sig),// input hold_clk_busrq_sig
.M1(M1_sig) , // output M1_sig
.M2(M2_sig) , // output M2_sig
.M3(M3_sig) , // output M3_sig
.M4(M4_sig) , // output M4_sig
.M5(M5_sig) , // output M5_sig
.T1(T1_sig) , // output T1_sig
.T2(T2_sig) , // output T2_sig
.T3(T3_sig) , // output T3_sig
.T4(T4_sig) , // output T4_sig
.T5(T5_sig) , // output T5_sig
.T6(T6_sig) , // output T6_sig
.timings_en(timings_en_sig) // output timings_en_sig
);
endmodule
cpu/control/timing_macros.i
+372
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//=========================================================================================
// This file contains substitute strings for macro expansions. Macros are defined in an
// Excel timing spreadsheet 'Timings.xlsm' and exported to a .csv file which is then read
// and processed by genmatrix.py script to generate exec_matrix.vh include file.
//
// Macro format:
//
// * Each key is prefixed by ':' and corresponds to a spreadsheet *column* name.
// * A key may contain several different macros, one per line.
// * A macro may span multiple lines; use the '\' character to continue on the next line.
// * Multi-line macros end when a line does not start with a space character.
// //-style comments are wrapped within /* ... */ if they don't start a line.
//=========================================================================================
//-----------------------------------------------------------------------------------------
// CPU machine state
//-----------------------------------------------------------------------------------------
:Function
//Fetch is M1
fMFetch
fMRead fMRead=1;
fMWrite fMWrite=1;
fIORead fIORead=1;
fIOWrite fIOWrite=1;
//-----------------------------------------------------------------------------------------
// Basic timing control
//-----------------------------------------------------------------------------------------
:valid
Y validPLA=1;
:nextM
Y nextM=1;
mr nextM=1; ctl_mRead=1;
mw nextM=1; ctl_mWrite=1;
ior nextM=1; ctl_iorw=1;
iow nextM=1; ctl_iorw=1;
CC nextM=~flags_cond_true;
INT nextM=1; ctl_mRead=in_intr & im2; // RST38 interrupt extension
:setM1
Y setM1=1;
SS setM1=~flags_cond_true;
CC setM1=~flags_cond_true;
ZF setM1=flags_zf; // Used in DJNZ
BR setM1=nonRep | ~repeat_en;
BRZ setM1=nonRep | ~repeat_en | flags_zf;
BZ setM1=nonRep | flags_zf;
INT setM1=~(in_intr & im2); // RST38 interrupt extension
//-----------------------------------------------------------------------------------------
// Register file, address (downstream) endpoint
//-----------------------------------------------------------------------------------------
:A:reg rd
// General purpose registers
A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; // Read 8-bit general purpose A register, enable SW4 downstream
r16 ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit general purpose register, enable SW4 downstream
BC ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit BC, enable SW4 downstream
DE ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit DE, enable SW4 downstream
HL ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit HL, enable SW4 downstream
SP ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;// Read 16-bit SP, enable SW4 downstream
// System registers
WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; // Select 16-bit WZ
IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR
I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register
PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC
// Conditional assertions of WZ, HL instead of PC
WZ? ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;
// Alternate format:
// if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)
// ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
// end
:A:reg wr
// General purpose registers
r16 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit general purpose register, enable SW4 upstream
BC ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream
DE ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream
HL ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit HL, enable SW4 upstream
SP ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; // Write 16-bit SP, enable SW4 upstream
// System registers
WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream
IR ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR
// PC will not be incremented if we are in HALT, INTR or NMI state
PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer
> ctl_sw_4u=1;
//-----------------------------------------------------------------------------------------
// Controls the address latch incrementer, the address latch and the address pin mux
//-----------------------------------------------------------------------------------------
:inc/dec
+ ctl_inc_cy=~pc_inc_hold; // Increment
- ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; // Decrement
op3 ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise
:A:latch
W ctl_al_we=1; // Write a value from the register bus to the address latch
R ctl_bus_inc_oe=1; // Output enable incrementer to the register bus
P ctl_apin_mux=1; // Apin sourced from incrementer
RL ctl_bus_inc_oe=1; ctl_apin_mux2=1; // Apin sourced from AL
//-----------------------------------------------------------------------------------------
// Register file, data (upstream) endpoint
//-----------------------------------------------------------------------------------------
:D:reg rd
//----- General purpose registers -----
A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
AF ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
B ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
H ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
L ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
r8 ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]
r8' \ // r8 addressing does not allow reading F register (indices of A and F are also swapped) (ex. in OUT (c),r)
if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end // Trying to read flags? Put 0 on the bus instead.
if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end // Read 8-bit GP register
rh ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Read 8-bit GP register high byte
rl ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Read 8-bit GP register low byte
//----- System registers -----
WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
Z ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z
I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)
PCh ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
PCl ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
:D:reg wr
? // Which register to be written is decided elsewhere
//----- General purpose registers -----
A ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
F ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
B ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; // Write 8-bit GP register
r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]
rh ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte
rl ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte
//----- System registers -----
I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)
WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Selecting only W
W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Conditionally selecting only W
Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; // Selecting only Z
//-----------------------------------------------------------------------------------------
// Controls the register file gate connecting it with the ALU and data bus
//-----------------------------------------------------------------------------------------
:Reg gate
< ctl_reg_in_hi=1; ctl_reg_in_lo=1; // From the ALU side into the register file
<l ctl_reg_in_lo=1; // From the ALU side into the register file low byte only
<h ctl_reg_in_hi=1; // From the ALU side into the register file high byte only
> ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the FLAGT and ALU
// Enables a register gate (high/low) corresponding to the selected 8-bit register
>r8 ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; // Enable register gate based on the rsel0
>r8' ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; // Enable register gate based on the rsel3
>l ctl_reg_out_lo=1; // From the register file onto the db1 (sw2 + FLAGT + sw1)
>h ctl_reg_out_hi=1; // From the register file onto the db2 (sw2 + ALU)
//-----------------------------------------------------------------------------------------
// Switches on the data bus for each direction (upstream, downstream)
//-----------------------------------------------------------------------------------------
:SW2
d ctl_sw_2d=1;
u ctl_sw_2u=1;
- // Controlled by register gate
:SW1
< ctl_sw_1d=1;
> ctl_sw_1u=1;
//-----------------------------------------------------------------------------------------
// Data bus latches and pads control
//-----------------------------------------------------------------------------------------
:DB pads
R ctl_bus_db_oe=1; // Read DB pads to internal data bus
W ctl_bus_db_we=1; // Write DB pads with internal data bus value
00 ctl_bus_zero_oe=1; // Force 0x00 on the data bus
FF ctl_bus_ff_oe=1; // Force 0xFF on the data bus
//-----------------------------------------------------------------------------------------
// ALU
//-----------------------------------------------------------------------------------------
:ALU
// Controls the master ALU output enable and the ALU input, only one can be active at a time
// >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load
< ctl_alu_oe=1; // Enable ALU onto the data bus
>s0 ctl_alu_shift_oe=~ctl_alu_bs_oe; // Shifter unit without shift-enable
>s1 ctl_alu_shift_oe=1; ctl_shift_en=1; // Shifter unit AND shift enable!
>bs ctl_alu_bs_oe=1; // Bit-selector unit
:ALU bus
// Controls the writer to the internal ALU bus
op1 ctl_alu_op1_oe=1; // OP1 latch
op2 ctl_alu_op2_oe=1; // OP2 latch
res ctl_alu_res_oe=1; // Result latch
:op2 latch
// Controls a MUX to select the input to the OP2 latch
bus ctl_alu_op2_sel_bus=1; // Internal bus
lq ctl_alu_op2_sel_lq=1; // Cross-bus wire (see schematic)
0 ctl_alu_op2_sel_zero=1; // Zero
:op1 latch
// Controls a MUX to select the input to the OP1 latch
bus ctl_alu_op1_sel_bus=1; // Internal bus
low ctl_alu_op1_sel_low=1; // Write low nibble with a high nibble
0 ctl_alu_op1_sel_zero=1; // Zero
:operation
// Defines the ALU core compute operation
// The listing is also showing their alternate formats (using if/then)
//-----------------------------------------------------------------------------------------
CP ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SUB ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SBC ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_cpl=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SBCh ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (~ctl_alu_op_low) begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
ADC ctl_alu_core_hf|=~ctl_alu_op_low;
// if (~ctl_alu_op_low) begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
ADD ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
AND ctl_alu_core_S=1; ctl_flags_cf_set=1;
OR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
XOR ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
NAND ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;
NOR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1;
//-----------------------------------------------------------------------------------------
PLA ctl_state_alu=1; // Assert the ALU PLA modifier to determine operation
:nibble
// ALU compute phase: working on low nibble or high nibble
L ctl_alu_op_low=1; // Activate ALU operation on low nibble
H ctl_alu_sel_op2_high=1; // Activate ALU operation on high nibble
//-----------------------------------------------------------------------------------------
// FLAGT
//-----------------------------------------------------------------------------------------
:FLAGT
< ctl_flags_oe=1; // Enable FLAGT onto the data bus
> ctl_flags_bus=1; // Load FLAGT from the data bus
alu ctl_flags_alu=1; // Load FLAGT from the ALU
// Write enables for various flag bits and segments
:SZ
* ctl_flags_sz_we=1;
:XY
* ctl_flags_xy_we=1;
?
:HF
* ctl_flags_hf_we=1;
W2 ctl_flags_hf2_we=1; // Write HF2 flag (DAA only)
:PF
* ctl_flags_pf_we=1;
P ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
V ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
iff2 ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
REP ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
?
:NF
* ctl_flags_nf_we=1; // Previous NF, to be used when loading FLAGT
0 ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1 ctl_flags_nf_we=1; ctl_flags_nf_set=1;
S ctl_flags_nf_we=1; // Sign bit, to be used with FLAGT source set to "alu"
?
:CF
* ctl_flags_cf_we=1;
0 ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // Clear CF going into the ALU core
1 ctl_flags_cf_set=1; // Set CF going into the ALU core
^ ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; // CCF
:CF2
R ctl_flags_use_cf2=1;
W ctl_flags_cf2_we=1;
W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1;
W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
//------------------------------------------------------------------------------------------
// Macros for some special cases; also simplifies control logic for a number of instructions
//------------------------------------------------------------------------------------------
:Special
USE_SP ctl_reg_use_sp=1; // For 16-bit loads: use SP instead of AF
// A few more specific states and instructions:
Ex_DE_HL ctl_reg_ex_de_hl=1; // EX DE,HL
Ex_AF_AF' ctl_reg_ex_af=1; // EX AF,AF'
EXX ctl_reg_exx=1; // EXX
HALT ctl_state_halt_set=1; // Enter HALT state
DI_EI ctl_iffx_bit=op3; ctl_iffx_we=1; // DI/EI
IM ctl_im_we=1; // IM n ('n' is read by opcode[4:3])
WZ=IX+d ixy_d=1; // Compute WZ=IX+d
IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag if not explicitly set
CB ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; // CB-table prefix
ED ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; // ED-table prefix
CLR_CB_ED ctl_state_tbl_we=1; // Clear CB/ED prefix if not explicitly set
// If the NF is set, complement HF and CF on the way out to the bus
// This is used to correctly set those flags after subtraction operations
?NF_HF_CF ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf;
?NF_HF ctl_flags_hf_cpl=flags_nf;
?~CF_HF ctl_flags_hf_cpl=~flags_cf; // Used for CCF
?SF_NEG ctl_alu_sel_op2_neg=flags_sf;
NEG_OP2 ctl_alu_sel_op2_neg=1;
?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf;
// M1 opcode read cycle and the refresh register increment cycle
// Write opcode into the instruction register through internal db0 bus:
OpcodeToIR ctl_ir_we=1;
// At the common instruction load M1/T3, override opcode byte when servicing interrupts:
// 1. We are in HALT mode: push NOP (0x00) instead
// 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead
// 3. We are in NMI mode: push RST38 (0xFF) instead
OverrideIR ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi;
// RST instruction uses opcode[5:3] to specify a vector and this macro passes those 3 bits through
MASK_543 ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);
// Based on the in_nmi state:
// 1. Disable SW1 so the opcode will not get onto db1 bus
// 2. Generate 0x66 on the db1 bus which will be used as the target vector address
// 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi)
RST_NMI ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;
// Based on the in_intr state:
// 1. IM1 mode, force 0xFF on the db0 bus
// 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr)
RST_INT ctl_bus_ff_oe=in_intr & im1;
RETN ctl_iff1_iff2=1; // RETN copies IFF2 into IFF1
NO_INTS ctl_no_ints=1; // Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD)
EvalCond ctl_eval_cond=1; // Evaluate flags condition based on the opcode[5:3]
CondShort ctl_cond_short=1; // M1/T3 only: force a short flags condition (SS)
Limit6 ctl_inc_limit6=1; // Limit the incrementer to 6 bits
DAA ctl_daa_oe=1; // Write DAA correction factor to the bus
ZERO_16BIT ctl_alu_zero_16bit=1; // 16-bit arithmetic operation uses ZF calculated over 2 bytes
NonRep nonRep=1; // Non-repeating block instruction
WriteBC=1 ctl_repeat_we=1; // Update repeating flag latch with BC=1 status
NOT_PC! ctl_reg_not_pc=1; // For M1/T1 load from a register other than PC