94 lines
2.9 KiB
Systemverilog
94 lines
2.9 KiB
Systemverilog
//==============================================================
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// Test interrupts unit
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//==============================================================
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`timescale 100 ns/ 100 ns
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module test_interrupts;
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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`define T #2
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bit clk = 1;
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initial repeat (20) #1 clk = ~clk;
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logic nreset = 0;
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// ----------------- CONTROL ----------------
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logic ctl_iff1_iff2_sig=0;
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logic ctl_iffx_we_sig=0;
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logic ctl_iffx_bit_sig=0;
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logic nmi_sig=0;
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logic setM1_sig=0;
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logic intr_sig=0;
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logic ctl_im_we_sig=0;
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logic [1:0] db_sig=0;
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logic clk_sig=0;
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logic ctl_no_ints_sig=0;
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// ----------------- STATES ----------------
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wire iff1_sig;
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assign iff1_sig = interrupts_inst.iff1;
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wire iff2_sig;
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wire im1_sig;
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wire im2_sig;
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wire in_nmi_sig;
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wire in_intr_sig;
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// ----------------- TEST -------------------
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initial begin
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// Init / reset
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`T nreset = 1;
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// Test interrupt modes
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db_sig = 2'b10; // IM1
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ctl_im_we_sig = 1;
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`T assert(im1_sig==1 && im2_sig==0);
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db_sig = 2'b11; // IM2
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`T assert(im1_sig==0 && im2_sig==1);
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db_sig = 2'b00; // IM0
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`T assert(im1_sig==0 && im2_sig==0);
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// Test IFF state flags
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assert(iff1_sig==0 && iff2_sig==0);
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ctl_iff1_iff2_sig = 1;
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ctl_iffx_we_sig = 1;
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ctl_iffx_bit_sig = 1;
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`T assert(iff1_sig==0 && iff2_sig==1);
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`T assert(iff1_sig==1 && iff2_sig==1);
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ctl_iff1_iff2_sig = 0;
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ctl_iffx_we_sig = 0;
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ctl_iffx_bit_sig = 0;
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// Simulate NMI triggering
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nmi_sig = 1;
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`T setM1_sig = 1;
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`T assert(iff1_sig==0 && iff2_sig==1);
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`T $display("End of test");
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end
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//--------------------------------------------------------------
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// Instantiate interrupts
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//--------------------------------------------------------------
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interrupts interrupts_inst
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(
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.ctl_iff1_iff2(ctl_iff1_iff2_sig) , // input ctl_iff1_iff2_sig
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.nmi(nmi_sig) , // input nmi_sig
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.setM1(setM1_sig) , // input setM1_sig
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.intr(intr_sig) , // input intr_sig
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.ctl_iffx_we(ctl_iffx_we_sig) , // input ctl_iffx_we_sig
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.ctl_iffx_bit(ctl_iffx_bit_sig) , // input ctl_iffx_bit_sig
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.ctl_im_we(ctl_im_we_sig) , // input ctl_im_we_sig
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.db(db_sig) , // input [1:0] db_sig
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.clk(clk) , // input clk
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.ctl_no_ints(ctl_no_ints_sig) , // input ctl_no_ints_sig
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.nreset(nreset) , // input nreset
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.iff2(iff2_sig) , // output iff2_sig
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.im1(im1_sig) , // output im1_sig
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.im2(im2_sig) , // output im2_sig
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.in_nmi(in_nmi_sig) , // output in_nmi_sig
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.in_intr(in_intr_sig) // output in_intr_sig
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);
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endmodule
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