Fixed video, kbd and buzzer
This commit is contained in:
+4176
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+309
@@ -0,0 +1,309 @@
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/*
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||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
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||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 272 464)
|
||||
(text "alu" (rect 5 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 432 25 444)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "alu_oe" (rect 0 0 37 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_oe" (rect 21 27 58 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
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||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
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||||
(text "alu_shift_in" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_in" (rect 21 43 85 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
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||||
(text "alu_shift_left" (rect 0 0 73 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_left" (rect 21 59 94 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "alu_shift_right" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_right" (rect 21 75 101 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "alu_core_R" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_R" (rect 21 91 85 105)(font "Arial" (font_size 8)))
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||||
(line (pt 0 96)(pt 16 96))
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||||
)
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||||
(port
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||||
(pt 0 112)
|
||||
(input)
|
||||
(text "alu_core_V" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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||||
(text "alu_core_V" (rect 21 107 87 121)(font "Arial" (font_size 8)))
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||||
(line (pt 0 112)(pt 16 112))
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||||
)
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||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "alu_core_S" (rect 0 0 64 14)(font "Arial" (font_size 8)))
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||||
(text "alu_core_S" (rect 21 123 85 137)(font "Arial" (font_size 8)))
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||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "alu_bs_oe" (rect 0 0 59 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_bs_oe" (rect 21 139 80 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "alu_parity_in" (rect 0 0 71 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_parity_in" (rect 21 155 92 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "alu_shift_oe" (rect 0 0 69 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_oe" (rect 21 171 90 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176))
|
||||
)
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||||
(port
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||||
(pt 0 192)
|
||||
(input)
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||||
(text "alu_core_cf_in" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_cf_in" (rect 21 187 105 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192))
|
||||
)
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||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "alu_op2_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_oe" (rect 21 203 87 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208))
|
||||
)
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||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "alu_op1_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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||||
(text "alu_op1_oe" (rect 21 219 87 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224))
|
||||
)
|
||||
(port
|
||||
(pt 0 240)
|
||||
(input)
|
||||
(text "alu_res_oe" (rect 0 0 63 14)(font "Arial" (font_size 8)))
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||||
(text "alu_res_oe" (rect 21 235 84 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 240)(pt 16 240))
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||||
)
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||||
(port
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||||
(pt 0 256)
|
||||
(input)
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||||
(text "alu_op1_sel_low" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op1_sel_low" (rect 21 251 117 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 256)(pt 16 256))
|
||||
)
|
||||
(port
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||||
(pt 0 272)
|
||||
(input)
|
||||
(text "alu_op1_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
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||||
(text "alu_op1_sel_zero" (rect 21 267 122 281)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 272)(pt 16 272))
|
||||
)
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||||
(port
|
||||
(pt 0 288)
|
||||
(input)
|
||||
(text "alu_op1_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
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||||
(text "alu_op1_sel_bus" (rect 21 283 117 297)(font "Arial" (font_size 8)))
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||||
(line (pt 0 288)(pt 16 288))
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||||
)
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||||
(port
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||||
(pt 0 304)
|
||||
(input)
|
||||
(text "alu_op2_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_zero" (rect 21 299 122 313)(font "Arial" (font_size 8)))
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||||
(line (pt 0 304)(pt 16 304))
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||||
)
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||||
(port
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||||
(pt 0 320)
|
||||
(input)
|
||||
(text "alu_op2_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_bus" (rect 21 315 117 329)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 320)(pt 16 320))
|
||||
)
|
||||
(port
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||||
(pt 0 336)
|
||||
(input)
|
||||
(text "alu_op2_sel_lq" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_lq" (rect 21 331 105 345)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 336)(pt 16 336))
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||||
)
|
||||
(port
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||||
(pt 0 352)
|
||||
(input)
|
||||
(text "alu_op_low" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op_low" (rect 21 347 87 361)(font "Arial" (font_size 8)))
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||||
(line (pt 0 352)(pt 16 352))
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||||
)
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||||
(port
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||||
(pt 0 368)
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||||
(input)
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||||
(text "alu_sel_op2_neg" (rect 0 0 96 14)(font "Arial" (font_size 8)))
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||||
(text "alu_sel_op2_neg" (rect 21 363 117 377)(font "Arial" (font_size 8)))
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||||
(line (pt 0 368)(pt 16 368))
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||||
)
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||||
(port
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||||
(pt 0 384)
|
||||
(input)
|
||||
(text "alu_sel_op2_high" (rect 0 0 99 14)(font "Arial" (font_size 8)))
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||||
(text "alu_sel_op2_high" (rect 21 379 120 393)(font "Arial" (font_size 8)))
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||||
(line (pt 0 384)(pt 16 384))
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||||
)
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||||
(port
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||||
(pt 0 400)
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||||
(input)
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||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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||||
(text "clk" (rect 21 395 36 409)(font "Arial" (font_size 8)))
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||||
(line (pt 0 400)(pt 16 400))
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||||
)
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||||
(port
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||||
(pt 0 416)
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||||
(input)
|
||||
(text "bsel[2..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
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||||
(text "bsel[2..0]" (rect 21 411 72 425)(font "Arial" (font_size 8)))
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||||
(line (pt 0 416)(pt 16 416)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 256 32)
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||||
(output)
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||||
(text "alu_zero" (rect 0 0 49 14)(font "Arial" (font_size 8)))
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||||
(text "alu_zero" (rect 186 27 235 41)(font "Arial" (font_size 8)))
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||||
(line (pt 256 32)(pt 240 32))
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||||
)
|
||||
(port
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||||
(pt 256 48)
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||||
(output)
|
||||
(text "alu_parity_out" (rect 0 0 80 14)(font "Arial" (font_size 8)))
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||||
(text "alu_parity_out" (rect 155 43 235 57)(font "Arial" (font_size 8)))
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||||
(line (pt 256 48)(pt 240 48))
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||||
)
|
||||
(port
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||||
(pt 256 64)
|
||||
(output)
|
||||
(text "alu_high_eq_9" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_high_eq_9" (rect 153 59 235 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 64)(pt 240 64))
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||||
)
|
||||
(port
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||||
(pt 256 80)
|
||||
(output)
|
||||
(text "alu_high_gt_9" (rect 0 0 79 14)(font "Arial" (font_size 8)))
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||||
(text "alu_high_gt_9" (rect 156 75 235 89)(font "Arial" (font_size 8)))
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||||
(line (pt 256 80)(pt 240 80))
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||||
)
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||||
(port
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||||
(pt 256 96)
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||||
(output)
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||||
(text "alu_low_gt_9" (rect 0 0 76 14)(font "Arial" (font_size 8)))
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||||
(text "alu_low_gt_9" (rect 159 91 235 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 96)(pt 240 96))
|
||||
)
|
||||
(port
|
||||
(pt 256 112)
|
||||
(output)
|
||||
(text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_db0" (rect 159 107 235 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 112)(pt 240 112))
|
||||
)
|
||||
(port
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||||
(pt 256 128)
|
||||
(output)
|
||||
(text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_db7" (rect 159 123 235 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 128)(pt 240 128))
|
||||
)
|
||||
(port
|
||||
(pt 256 144)
|
||||
(output)
|
||||
(text "alu_core_cf_out" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_cf_out" (rect 142 139 235 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 144)(pt 240 144))
|
||||
)
|
||||
(port
|
||||
(pt 256 160)
|
||||
(output)
|
||||
(text "alu_sf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_sf_out" (rect 175 155 235 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 160)(pt 240 160))
|
||||
)
|
||||
(port
|
||||
(pt 256 176)
|
||||
(output)
|
||||
(text "alu_yf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_yf_out" (rect 175 171 235 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 176)(pt 240 176))
|
||||
)
|
||||
(port
|
||||
(pt 256 192)
|
||||
(output)
|
||||
(text "alu_xf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_xf_out" (rect 175 187 235 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 192)(pt 240 192))
|
||||
)
|
||||
(port
|
||||
(pt 256 208)
|
||||
(output)
|
||||
(text "alu_vf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_vf_out" (rect 175 203 235 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 208)(pt 240 208))
|
||||
)
|
||||
(port
|
||||
(pt 256 224)
|
||||
(output)
|
||||
(text "test_db_low[3..0]" (rect 0 0 99 14)(font "Arial" (font_size 8)))
|
||||
(text "test_db_low[3..0]" (rect 136 219 235 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 224)(pt 240 224)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 256)
|
||||
(output)
|
||||
(text "test_db_high[3..0]" (rect 0 0 101 14)(font "Arial" (font_size 8)))
|
||||
(text "test_db_high[3..0]" (rect 134 251 235 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 256)(pt 240 256)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 240)
|
||||
(bidir)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 193 235 235 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 240)(pt 240 240)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 240 432))
|
||||
)
|
||||
)
|
||||
+384
@@ -0,0 +1,384 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Nov 07 19:44:45 2014"
|
||||
|
||||
module alu(
|
||||
alu_core_R,
|
||||
alu_core_V,
|
||||
alu_core_S,
|
||||
alu_bs_oe,
|
||||
alu_parity_in,
|
||||
alu_oe,
|
||||
alu_shift_oe,
|
||||
alu_core_cf_in,
|
||||
alu_op2_oe,
|
||||
alu_op1_oe,
|
||||
alu_res_oe,
|
||||
alu_op1_sel_low,
|
||||
alu_op1_sel_zero,
|
||||
alu_op1_sel_bus,
|
||||
alu_op2_sel_zero,
|
||||
alu_op2_sel_bus,
|
||||
alu_op2_sel_lq,
|
||||
alu_op_low,
|
||||
alu_shift_in,
|
||||
alu_sel_op2_neg,
|
||||
alu_sel_op2_high,
|
||||
alu_shift_left,
|
||||
alu_shift_right,
|
||||
clk,
|
||||
bsel,
|
||||
alu_zero,
|
||||
alu_parity_out,
|
||||
alu_high_eq_9,
|
||||
alu_high_gt_9,
|
||||
alu_low_gt_9,
|
||||
alu_shift_db0,
|
||||
alu_shift_db7,
|
||||
alu_core_cf_out,
|
||||
alu_sf_out,
|
||||
alu_yf_out,
|
||||
alu_xf_out,
|
||||
alu_vf_out,
|
||||
db,
|
||||
test_db_high,
|
||||
test_db_low
|
||||
);
|
||||
|
||||
|
||||
input wire alu_core_R;
|
||||
input wire alu_core_V;
|
||||
input wire alu_core_S;
|
||||
input wire alu_bs_oe;
|
||||
input wire alu_parity_in;
|
||||
input wire alu_oe;
|
||||
input wire alu_shift_oe;
|
||||
input wire alu_core_cf_in;
|
||||
input wire alu_op2_oe;
|
||||
input wire alu_op1_oe;
|
||||
input wire alu_res_oe;
|
||||
input wire alu_op1_sel_low;
|
||||
input wire alu_op1_sel_zero;
|
||||
input wire alu_op1_sel_bus;
|
||||
input wire alu_op2_sel_zero;
|
||||
input wire alu_op2_sel_bus;
|
||||
input wire alu_op2_sel_lq;
|
||||
input wire alu_op_low;
|
||||
input wire alu_shift_in;
|
||||
input wire alu_sel_op2_neg;
|
||||
input wire alu_sel_op2_high;
|
||||
input wire alu_shift_left;
|
||||
input wire alu_shift_right;
|
||||
input wire clk;
|
||||
input wire [2:0] bsel;
|
||||
output wire alu_zero;
|
||||
output wire alu_parity_out;
|
||||
output wire alu_high_eq_9;
|
||||
output wire alu_high_gt_9;
|
||||
output wire alu_low_gt_9;
|
||||
output wire alu_shift_db0;
|
||||
output wire alu_shift_db7;
|
||||
output wire alu_core_cf_out;
|
||||
output wire alu_sf_out;
|
||||
output wire alu_yf_out;
|
||||
output wire alu_xf_out;
|
||||
output wire alu_vf_out;
|
||||
inout wire [7:0] db;
|
||||
output wire [3:0] test_db_high;
|
||||
output wire [3:0] test_db_low;
|
||||
|
||||
wire [3:0] alu_op1;
|
||||
wire [3:0] alu_op2;
|
||||
wire [3:0] db_high;
|
||||
wire [3:0] db_low;
|
||||
reg [3:0] op1_high;
|
||||
reg [3:0] op1_low;
|
||||
reg [3:0] op2_high;
|
||||
reg [3:0] op2_low;
|
||||
wire [3:0] result_hi;
|
||||
reg [3:0] result_lo;
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire [3:0] SYNTHESIZED_WIRE_1;
|
||||
wire [3:0] SYNTHESIZED_WIRE_2;
|
||||
wire [3:0] SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire [3:0] SYNTHESIZED_WIRE_5;
|
||||
wire [3:0] SYNTHESIZED_WIRE_7;
|
||||
wire [3:0] SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire [3:0] SYNTHESIZED_WIRE_10;
|
||||
wire [3:0] SYNTHESIZED_WIRE_11;
|
||||
wire [3:0] SYNTHESIZED_WIRE_12;
|
||||
wire [3:0] SYNTHESIZED_WIRE_13;
|
||||
wire [3:0] SYNTHESIZED_WIRE_14;
|
||||
wire [3:0] SYNTHESIZED_WIRE_15;
|
||||
wire [3:0] SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire [3:0] SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire [3:0] SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire [3:0] SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire [3:0] SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire [3:0] SYNTHESIZED_WIRE_33;
|
||||
wire [3:0] SYNTHESIZED_WIRE_34;
|
||||
|
||||
|
||||
|
||||
|
||||
assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz;
|
||||
assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz;
|
||||
assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz;
|
||||
assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz;
|
||||
assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz;
|
||||
assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz;
|
||||
assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz;
|
||||
|
||||
|
||||
alu_core b2v_core(
|
||||
.cy_in(alu_core_cf_in),
|
||||
.S(alu_core_S),
|
||||
.V(alu_core_V),
|
||||
.R(alu_core_R),
|
||||
.op1(alu_op1),
|
||||
.op2(alu_op2),
|
||||
.cy_out(alu_core_cf_out),
|
||||
.vf_out(alu_vf_out),
|
||||
.result(result_hi));
|
||||
|
||||
assign db[3] = alu_oe ? db_low[3] : 1'bz;
|
||||
assign db[2] = alu_oe ? db_low[2] : 1'bz;
|
||||
assign db[1] = alu_oe ? db_low[1] : 1'bz;
|
||||
assign db[0] = alu_oe ? db_low[0] : 1'bz;
|
||||
|
||||
assign db[7] = alu_oe ? db_high[3] : 1'bz;
|
||||
assign db[6] = alu_oe ? db_high[2] : 1'bz;
|
||||
assign db[5] = alu_oe ? db_high[1] : 1'bz;
|
||||
assign db[4] = alu_oe ? db_high[0] : 1'bz;
|
||||
|
||||
|
||||
alu_bit_select b2v_input_bit_select(
|
||||
.bsel(bsel),
|
||||
.bs_out_high(SYNTHESIZED_WIRE_1),
|
||||
.bs_out_low(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
alu_shifter_core b2v_input_shift(
|
||||
.shift_in(alu_shift_in),
|
||||
.shift_left(alu_shift_left),
|
||||
.shift_right(alu_shift_right),
|
||||
.db(db),
|
||||
.shift_db0(alu_shift_db0),
|
||||
.shift_db7(alu_shift_db7),
|
||||
.out_high(SYNTHESIZED_WIRE_34),
|
||||
.out_low(SYNTHESIZED_WIRE_33));
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (alu_op_low)
|
||||
begin
|
||||
result_lo[3:0] <= result_hi[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = ~alu_op_low;
|
||||
|
||||
assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz;
|
||||
assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz;
|
||||
assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz;
|
||||
assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz;
|
||||
assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz;
|
||||
assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz;
|
||||
assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~op2_low;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~op2_high;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9};
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high;
|
||||
|
||||
assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz;
|
||||
assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz;
|
||||
assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz;
|
||||
assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz;
|
||||
assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz;
|
||||
assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz;
|
||||
assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low};
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high;
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_20)
|
||||
begin
|
||||
op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_23)
|
||||
begin
|
||||
op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_37)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_26)
|
||||
begin
|
||||
op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_37)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz;
|
||||
assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz;
|
||||
assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz;
|
||||
assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz;
|
||||
assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz;
|
||||
assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz;
|
||||
assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = ~clk;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = ~clk;
|
||||
|
||||
|
||||
alu_mux_2z b2v_op1_latch_mux_high(
|
||||
.sel_a(alu_op1_sel_bus),
|
||||
.sel_zero(alu_op1_sel_zero),
|
||||
.a(db_high),
|
||||
.ena(SYNTHESIZED_WIRE_20),
|
||||
.Q(SYNTHESIZED_WIRE_18));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op1_latch_mux_low(
|
||||
.sel_a(alu_op1_sel_bus),
|
||||
.sel_b(alu_op1_sel_low),
|
||||
.sel_zero(alu_op1_sel_zero),
|
||||
.a(db_low),
|
||||
.b(db_high),
|
||||
.ena(SYNTHESIZED_WIRE_23),
|
||||
.Q(SYNTHESIZED_WIRE_21));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op2_latch_mux_high(
|
||||
.sel_a(alu_op2_sel_bus),
|
||||
.sel_b(alu_op2_sel_lq),
|
||||
.sel_zero(alu_op2_sel_zero),
|
||||
.a(db_high),
|
||||
.b(db_low),
|
||||
.ena(SYNTHESIZED_WIRE_26),
|
||||
.Q(SYNTHESIZED_WIRE_24));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op2_latch_mux_low(
|
||||
.sel_a(alu_op2_sel_bus),
|
||||
.sel_b(alu_op2_sel_lq),
|
||||
.sel_zero(alu_op2_sel_zero),
|
||||
.a(db_low),
|
||||
.b(alu_op1),
|
||||
.ena(SYNTHESIZED_WIRE_29),
|
||||
.Q(SYNTHESIZED_WIRE_27));
|
||||
|
||||
assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3];
|
||||
|
||||
|
||||
alu_prep_daa b2v_prep_daa(
|
||||
.high(op1_high),
|
||||
.low(op1_low),
|
||||
.low_gt_9(alu_low_gt_9),
|
||||
.high_gt_9(alu_high_gt_9),
|
||||
.high_eq_9(alu_high_eq_9));
|
||||
|
||||
assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz;
|
||||
assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz;
|
||||
assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz;
|
||||
assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz;
|
||||
assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz;
|
||||
assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz;
|
||||
assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz;
|
||||
|
||||
assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]);
|
||||
|
||||
assign alu_sf_out = db_high[3];
|
||||
assign alu_yf_out = db_high[1];
|
||||
assign alu_xf_out = db_low[3];
|
||||
assign test_db_high = db_high;
|
||||
assign test_db_low = db_low;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,848 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 32 200 48)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "bsel[2..0]" (rect 9 0 55 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 712 136 888 152)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "bs_out_low[3..0]" (rect 90 0 170 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 720 328 896 344)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "bs_out_high[3..0]" (rect 90 0 174 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 448 120 512 168)
|
||||
(text "AND3" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "and0" (rect 3 37 26 49)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 16 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 24)(pt 16 24))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
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||||
)
|
||||
(connector
|
||||
(pt 416 472)
|
||||
(pt 448 472)
|
||||
)
|
||||
(connector
|
||||
(pt 384 480)
|
||||
(pt 448 480)
|
||||
)
|
||||
(connector
|
||||
(pt 352 488)
|
||||
(pt 448 488)
|
||||
)
|
||||
(connector
|
||||
(pt 256 56)
|
||||
(pt 272 56)
|
||||
)
|
||||
(connector
|
||||
(pt 256 96)
|
||||
(pt 272 96)
|
||||
)
|
||||
(connector
|
||||
(pt 256 136)
|
||||
(pt 272 136)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_low[3..0]" (rect 647 128 727 140)(font "Arial" ))
|
||||
(pt 632 144)
|
||||
(pt 712 144)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_high[3..0]" (rect 644 320 728 332)(font "Arial" ))
|
||||
(pt 632 336)
|
||||
(pt 720 336)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_low[0]" (rect 562 128 629 140)(font "Arial" ))
|
||||
(pt 512 144)
|
||||
(pt 632 144)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_low[1]" (rect 564 176 631 188)(font "Arial" ))
|
||||
(pt 512 192)
|
||||
(pt 632 192)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_low[2]" (rect 563 224 630 236)(font "Arial" ))
|
||||
(pt 512 240)
|
||||
(pt 632 240)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_low[3]" (rect 563 272 630 284)(font "Arial" ))
|
||||
(pt 512 288)
|
||||
(pt 632 288)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_high[0]" (rect 563 320 634 332)(font "Arial" ))
|
||||
(pt 512 336)
|
||||
(pt 632 336)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_high[1]" (rect 563 368 634 380)(font "Arial" ))
|
||||
(pt 512 384)
|
||||
(pt 632 384)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_high[2]" (rect 564 416 635 428)(font "Arial" ))
|
||||
(pt 512 432)
|
||||
(pt 632 432)
|
||||
)
|
||||
(connector
|
||||
(text "bs_out_high[3]" (rect 563 464 634 476)(font "Arial" ))
|
||||
(pt 512 480)
|
||||
(pt 632 480)
|
||||
)
|
||||
(connector
|
||||
(pt 320 56)
|
||||
(pt 400 56)
|
||||
)
|
||||
(connector
|
||||
(pt 320 96)
|
||||
(pt 368 96)
|
||||
)
|
||||
(connector
|
||||
(pt 320 136)
|
||||
(pt 336 136)
|
||||
)
|
||||
(connector
|
||||
(pt 400 56)
|
||||
(pt 400 136)
|
||||
)
|
||||
(connector
|
||||
(pt 400 136)
|
||||
(pt 400 232)
|
||||
)
|
||||
(connector
|
||||
(pt 400 232)
|
||||
(pt 400 328)
|
||||
)
|
||||
(connector
|
||||
(pt 400 328)
|
||||
(pt 400 424)
|
||||
)
|
||||
(connector
|
||||
(pt 368 96)
|
||||
(pt 368 144)
|
||||
)
|
||||
(connector
|
||||
(pt 368 144)
|
||||
(pt 368 192)
|
||||
)
|
||||
(connector
|
||||
(pt 368 192)
|
||||
(pt 368 336)
|
||||
)
|
||||
(connector
|
||||
(pt 368 336)
|
||||
(pt 368 384)
|
||||
)
|
||||
(connector
|
||||
(pt 336 136)
|
||||
(pt 336 152)
|
||||
)
|
||||
(connector
|
||||
(pt 336 152)
|
||||
(pt 336 200)
|
||||
)
|
||||
(connector
|
||||
(pt 336 200)
|
||||
(pt 336 248)
|
||||
)
|
||||
(connector
|
||||
(pt 336 248)
|
||||
(pt 336 296)
|
||||
)
|
||||
(connector
|
||||
(pt 352 120)
|
||||
(pt 352 344)
|
||||
)
|
||||
(connector
|
||||
(pt 352 344)
|
||||
(pt 352 392)
|
||||
)
|
||||
(connector
|
||||
(pt 352 392)
|
||||
(pt 352 440)
|
||||
)
|
||||
(connector
|
||||
(pt 352 440)
|
||||
(pt 352 488)
|
||||
)
|
||||
(connector
|
||||
(pt 416 40)
|
||||
(pt 416 184)
|
||||
)
|
||||
(connector
|
||||
(pt 416 184)
|
||||
(pt 416 280)
|
||||
)
|
||||
(connector
|
||||
(pt 416 280)
|
||||
(pt 416 376)
|
||||
)
|
||||
(connector
|
||||
(pt 416 376)
|
||||
(pt 416 472)
|
||||
)
|
||||
(connector
|
||||
(pt 384 80)
|
||||
(pt 384 240)
|
||||
)
|
||||
(connector
|
||||
(pt 384 240)
|
||||
(pt 384 288)
|
||||
)
|
||||
(connector
|
||||
(pt 384 288)
|
||||
(pt 384 432)
|
||||
)
|
||||
(connector
|
||||
(pt 384 432)
|
||||
(pt 384 480)
|
||||
)
|
||||
(connector
|
||||
(text "bsel[0]" (rect 222 24 255 36)(font "Arial" ))
|
||||
(pt 216 40)
|
||||
(pt 256 40)
|
||||
)
|
||||
(connector
|
||||
(pt 256 40)
|
||||
(pt 416 40)
|
||||
)
|
||||
(connector
|
||||
(pt 216 40)
|
||||
(pt 216 80)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 80)
|
||||
(pt 216 120)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "bsel[1]" (rect 221 64 254 76)(font "Arial" ))
|
||||
(pt 216 80)
|
||||
(pt 256 80)
|
||||
)
|
||||
(connector
|
||||
(pt 256 80)
|
||||
(pt 384 80)
|
||||
)
|
||||
(connector
|
||||
(text "bsel[2]" (rect 220 104 253 116)(font "Arial" ))
|
||||
(pt 216 120)
|
||||
(pt 256 120)
|
||||
)
|
||||
(connector
|
||||
(pt 256 120)
|
||||
(pt 352 120)
|
||||
)
|
||||
(connector
|
||||
(pt 632 144)
|
||||
(pt 632 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 632 192)
|
||||
(pt 632 240)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 632 240)
|
||||
(pt 632 288)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 632 336)
|
||||
(pt 632 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 632 384)
|
||||
(pt 632 432)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 632 432)
|
||||
(pt 632 480)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 200 40)
|
||||
(pt 216 40)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 400 136))
|
||||
(junction (pt 400 232))
|
||||
(junction (pt 400 328))
|
||||
(junction (pt 368 144))
|
||||
(junction (pt 368 192))
|
||||
(junction (pt 368 336))
|
||||
(junction (pt 336 152))
|
||||
(junction (pt 336 200))
|
||||
(junction (pt 336 248))
|
||||
(junction (pt 352 344))
|
||||
(junction (pt 352 392))
|
||||
(junction (pt 352 440))
|
||||
(junction (pt 416 184))
|
||||
(junction (pt 416 280))
|
||||
(junction (pt 416 376))
|
||||
(junction (pt 384 240))
|
||||
(junction (pt 384 288))
|
||||
(junction (pt 384 432))
|
||||
(junction (pt 256 40))
|
||||
(junction (pt 216 40))
|
||||
(junction (pt 256 80))
|
||||
(junction (pt 216 80))
|
||||
(junction (pt 256 120))
|
||||
(junction (pt 632 144))
|
||||
(junction (pt 632 192))
|
||||
(junction (pt 632 240))
|
||||
(junction (pt 632 336))
|
||||
(junction (pt 632 384))
|
||||
(junction (pt 632 432))
|
||||
(title_block
|
||||
(rect 24 536 281 588)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_bit_select" (rect 43 2 137 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 216 112)
|
||||
(text "alu_bit_select" (rect 5 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 80 25 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "bsel[2..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
|
||||
(text "bsel[2..0]" (rect 21 27 72 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 200 32)
|
||||
(output)
|
||||
(text "bs_out_low[3..0]" (rect 0 0 95 14)(font "Arial" (font_size 8)))
|
||||
(text "bs_out_low[3..0]" (rect 84 27 179 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 200 32)(pt 184 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 200 48)
|
||||
(output)
|
||||
(text "bs_out_high[3..0]" (rect 0 0 97 14)(font "Arial" (font_size 8)))
|
||||
(text "bs_out_high[3..0]" (rect 82 43 179 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 200 48)(pt 184 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 184 80))
|
||||
)
|
||||
(fill (color 217 255 255))
|
||||
)
|
||||
@@ -0,0 +1,64 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:21:31 2014"
|
||||
|
||||
module alu_bit_select(
|
||||
bsel,
|
||||
bs_out_high,
|
||||
bs_out_low
|
||||
);
|
||||
|
||||
|
||||
input wire [2:0] bsel;
|
||||
output wire [3:0] bs_out_high;
|
||||
output wire [3:0] bs_out_low;
|
||||
|
||||
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
|
||||
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
|
||||
|
||||
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = ~bsel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = ~bsel[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = ~bsel[2];
|
||||
|
||||
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
|
||||
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,288 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 248 496)
|
||||
(text "alu_control" (rect 5 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 464 25 476)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_db7" (rect 21 27 97 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_db0" (rect 21 43 97 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "ctl_shift_en" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_shift_en" (rect 21 59 87 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "op543[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "op543[2..0]" (rect 21 75 84 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "flags_cf_latch" (rect 0 0 81 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_cf_latch" (rect 21 91 102 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "ctl_cond_short" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_cond_short" (rect 21 107 105 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "flags_zf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_zf" (rect 21 123 68 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "flags_cf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_cf" (rect 21 139 68 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "flags_pf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_pf" (rect 21 155 68 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "flags_sf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_sf" (rect 21 171 68 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "ctl_eval_cond" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_eval_cond" (rect 21 187 100 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "ctl_daa_oe" (rect 0 0 62 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_daa_oe" (rect 21 203 83 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "ctl_66_oe" (rect 0 0 55 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_66_oe" (rect 21 219 76 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224))
|
||||
)
|
||||
(port
|
||||
(pt 0 240)
|
||||
(input)
|
||||
(text "alu_low_gt_9" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_low_gt_9" (rect 21 235 97 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 240)(pt 16 240))
|
||||
)
|
||||
(port
|
||||
(pt 0 256)
|
||||
(input)
|
||||
(text "flags_hf2" (rect 0 0 54 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_hf2" (rect 21 251 75 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 256)(pt 16 256))
|
||||
)
|
||||
(port
|
||||
(pt 0 272)
|
||||
(input)
|
||||
(text "alu_high_eq_9" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_high_eq_9" (rect 21 267 103 281)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 272)(pt 16 272))
|
||||
)
|
||||
(port
|
||||
(pt 0 288)
|
||||
(input)
|
||||
(text "alu_high_gt_9" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_high_gt_9" (rect 21 283 100 297)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 288)(pt 16 288))
|
||||
)
|
||||
(port
|
||||
(pt 0 304)
|
||||
(input)
|
||||
(text "alu_parity_out" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_parity_out" (rect 21 299 101 313)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 304)(pt 16 304))
|
||||
)
|
||||
(port
|
||||
(pt 0 320)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||
(text "clk" (rect 21 315 36 329)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 320)(pt 16 320))
|
||||
)
|
||||
(port
|
||||
(pt 0 336)
|
||||
(input)
|
||||
(text "ctl_alu_op_low" (rect 0 0 86 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op_low" (rect 21 331 107 345)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 336)(pt 16 336))
|
||||
)
|
||||
(port
|
||||
(pt 0 352)
|
||||
(input)
|
||||
(text "ctl_pf_sel[1..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_pf_sel[1..0]" (rect 21 347 104 361)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 352)(pt 16 352)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 368)
|
||||
(input)
|
||||
(text "alu_vf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_vf_out" (rect 21 363 81 377)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 368)(pt 16 368))
|
||||
)
|
||||
(port
|
||||
(pt 0 384)
|
||||
(input)
|
||||
(text "iff2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
|
||||
(text "iff2" (rect 21 379 39 393)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 384)(pt 16 384))
|
||||
)
|
||||
(port
|
||||
(pt 0 400)
|
||||
(input)
|
||||
(text "repeat_en" (rect 0 0 57 14)(font "Arial" (font_size 8)))
|
||||
(text "repeat_en" (rect 21 395 78 409)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 400)(pt 16 400))
|
||||
)
|
||||
(port
|
||||
(pt 0 416)
|
||||
(input)
|
||||
(text "ctl_alu_core_hf" (rect 0 0 88 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_core_hf" (rect 21 411 109 425)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 416)(pt 16 416))
|
||||
)
|
||||
(port
|
||||
(pt 0 432)
|
||||
(input)
|
||||
(text "flags_hf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_hf" (rect 21 427 68 441)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 432)(pt 16 432))
|
||||
)
|
||||
(port
|
||||
(pt 232 32)
|
||||
(output)
|
||||
(text "shift_cf_out" (rect 0 0 68 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_cf_out" (rect 143 27 211 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 32)(pt 216 32))
|
||||
)
|
||||
(port
|
||||
(pt 232 48)
|
||||
(output)
|
||||
(text "alu_shift_left" (rect 0 0 73 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_left" (rect 138 43 211 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 48)(pt 216 48))
|
||||
)
|
||||
(port
|
||||
(pt 232 64)
|
||||
(output)
|
||||
(text "alu_shift_right" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_right" (rect 131 59 211 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 64)(pt 216 64))
|
||||
)
|
||||
(port
|
||||
(pt 232 80)
|
||||
(output)
|
||||
(text "alu_shift_in" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_in" (rect 147 75 211 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 80)(pt 216 80))
|
||||
)
|
||||
(port
|
||||
(pt 232 96)
|
||||
(output)
|
||||
(text "flags_cond_true" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_cond_true" (rect 118 91 211 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 96)(pt 216 96))
|
||||
)
|
||||
(port
|
||||
(pt 232 112)
|
||||
(output)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 169 107 211 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 112)(pt 216 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 128)
|
||||
(output)
|
||||
(text "daa_cf_out" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "daa_cf_out" (rect 147 123 211 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 128)(pt 216 128))
|
||||
)
|
||||
(port
|
||||
(pt 232 144)
|
||||
(output)
|
||||
(text "alu_parity_in" (rect 0 0 71 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_parity_in" (rect 140 139 211 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 144)(pt 216 144))
|
||||
)
|
||||
(port
|
||||
(pt 232 160)
|
||||
(output)
|
||||
(text "alu_op_low" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op_low" (rect 145 155 211 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 160)(pt 216 160))
|
||||
)
|
||||
(port
|
||||
(pt 232 176)
|
||||
(output)
|
||||
(text "pf_sel" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "pf_sel" (rect 176 171 211 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 176)(pt 216 176))
|
||||
)
|
||||
(port
|
||||
(pt 232 192)
|
||||
(output)
|
||||
(text "alu_core_cf_in" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_cf_in" (rect 127 187 211 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 192)(pt 216 192))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 216 464))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,250 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Tue Oct 21 20:41:52 2014"
|
||||
|
||||
module alu_control(
|
||||
alu_shift_db0,
|
||||
alu_shift_db7,
|
||||
ctl_shift_en,
|
||||
alu_low_gt_9,
|
||||
alu_high_gt_9,
|
||||
alu_high_eq_9,
|
||||
ctl_daa_oe,
|
||||
ctl_alu_op_low,
|
||||
alu_parity_out,
|
||||
flags_cf,
|
||||
flags_zf,
|
||||
flags_pf,
|
||||
flags_sf,
|
||||
ctl_cond_short,
|
||||
alu_vf_out,
|
||||
iff2,
|
||||
ctl_alu_core_hf,
|
||||
ctl_eval_cond,
|
||||
repeat_en,
|
||||
flags_cf_latch,
|
||||
flags_hf2,
|
||||
flags_hf,
|
||||
ctl_66_oe,
|
||||
clk,
|
||||
ctl_pf_sel,
|
||||
op543,
|
||||
alu_shift_in,
|
||||
alu_shift_right,
|
||||
alu_shift_left,
|
||||
shift_cf_out,
|
||||
alu_parity_in,
|
||||
flags_cond_true,
|
||||
daa_cf_out,
|
||||
pf_sel,
|
||||
alu_op_low,
|
||||
alu_core_cf_in,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire alu_shift_db0;
|
||||
input wire alu_shift_db7;
|
||||
input wire ctl_shift_en;
|
||||
input wire alu_low_gt_9;
|
||||
input wire alu_high_gt_9;
|
||||
input wire alu_high_eq_9;
|
||||
input wire ctl_daa_oe;
|
||||
input wire ctl_alu_op_low;
|
||||
input wire alu_parity_out;
|
||||
input wire flags_cf;
|
||||
input wire flags_zf;
|
||||
input wire flags_pf;
|
||||
input wire flags_sf;
|
||||
input wire ctl_cond_short;
|
||||
input wire alu_vf_out;
|
||||
input wire iff2;
|
||||
input wire ctl_alu_core_hf;
|
||||
input wire ctl_eval_cond;
|
||||
input wire repeat_en;
|
||||
input wire flags_cf_latch;
|
||||
input wire flags_hf2;
|
||||
input wire flags_hf;
|
||||
input wire ctl_66_oe;
|
||||
input wire clk;
|
||||
input wire [1:0] ctl_pf_sel;
|
||||
input wire [2:0] op543;
|
||||
output wire alu_shift_in;
|
||||
output wire alu_shift_right;
|
||||
output wire alu_shift_left;
|
||||
output wire shift_cf_out;
|
||||
output wire alu_parity_in;
|
||||
output reg flags_cond_true;
|
||||
output wire daa_cf_out;
|
||||
output wire pf_sel;
|
||||
output wire alu_op_low;
|
||||
output wire alu_core_cf_in;
|
||||
output wire [7:0] db;
|
||||
|
||||
wire condition;
|
||||
wire [7:0] out;
|
||||
wire [1:0] sel;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
reg DFFE_latch_pf_tmp;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign alu_op_low = ctl_alu_op_low;
|
||||
assign daa_cf_out = SYNTHESIZED_WIRE_21;
|
||||
assign SYNTHESIZED_WIRE_22 = 0;
|
||||
assign SYNTHESIZED_WIRE_18 = 1;
|
||||
|
||||
|
||||
|
||||
assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1;
|
||||
|
||||
|
||||
|
||||
assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz;
|
||||
assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz;
|
||||
assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz;
|
||||
assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz;
|
||||
assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz;
|
||||
assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz;
|
||||
assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz;
|
||||
assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz;
|
||||
|
||||
assign alu_shift_right = ctl_shift_en & op543[0];
|
||||
|
||||
assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe;
|
||||
|
||||
assign sel[0] = op543[1];
|
||||
|
||||
|
||||
assign out[1] = SYNTHESIZED_WIRE_20;
|
||||
|
||||
|
||||
assign out[2] = SYNTHESIZED_WIRE_20;
|
||||
|
||||
|
||||
assign out[5] = SYNTHESIZED_WIRE_21;
|
||||
|
||||
|
||||
assign out[6] = SYNTHESIZED_WIRE_21;
|
||||
|
||||
|
||||
assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~op543[0];
|
||||
|
||||
assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11;
|
||||
|
||||
assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf;
|
||||
|
||||
assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf;
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_eval_cond)
|
||||
begin
|
||||
flags_cond_true <= condition;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_cond_mux(
|
||||
.in0(flags_zf),
|
||||
.in1(flags_cf),
|
||||
.in2(flags_pf),
|
||||
.in3(flags_sf),
|
||||
.sel(sel),
|
||||
.out(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_pf_sel(
|
||||
.in0(alu_parity_out),
|
||||
.in1(alu_vf_out),
|
||||
.in2(iff2),
|
||||
.in3(repeat_en),
|
||||
.sel(ctl_pf_sel),
|
||||
.out(pf_sel));
|
||||
|
||||
|
||||
alu_mux_8 b2v_inst_shift_mux(
|
||||
.in0(alu_shift_db7),
|
||||
.in1(alu_shift_db0),
|
||||
.in2(flags_cf_latch),
|
||||
.in3(flags_cf_latch),
|
||||
.in4(SYNTHESIZED_WIRE_22),
|
||||
.in5(alu_shift_db7),
|
||||
.in6(SYNTHESIZED_WIRE_18),
|
||||
.in7(SYNTHESIZED_WIRE_22),
|
||||
.sel(op543),
|
||||
.out(alu_shift_in));
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_alu_op_low)
|
||||
begin
|
||||
DFFE_latch_pf_tmp <= alu_parity_out;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = ~op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short;
|
||||
|
||||
|
||||
assign out[3] = 0;
|
||||
assign out[7] = 0;
|
||||
assign out[0] = 0;
|
||||
assign out[4] = 0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,870 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
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||||
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|
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@@ -0,0 +1,92 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
(line (pt 160 32)(pt 144 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 48)
|
||||
(output)
|
||||
(text "cy_out" (rect 0 0 38 14)(font "Arial" (font_size 8)))
|
||||
(text "cy_out" (rect 101 43 139 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 48)(pt 144 48))
|
||||
)
|
||||
(port
|
||||
(pt 160 64)
|
||||
(output)
|
||||
(text "vf_out" (rect 0 0 36 14)(font "Arial" (font_size 8)))
|
||||
(text "vf_out" (rect 103 59 139 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 64)(pt 144 64))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 144 144))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,100 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:17:04 2014"
|
||||
|
||||
module alu_core(
|
||||
cy_in,
|
||||
S,
|
||||
V,
|
||||
R,
|
||||
op1,
|
||||
op2,
|
||||
cy_out,
|
||||
vf_out,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire cy_in;
|
||||
input wire S;
|
||||
input wire V;
|
||||
input wire R;
|
||||
input wire [3:0] op1;
|
||||
input wire [3:0] op2;
|
||||
output wire cy_out;
|
||||
output wire vf_out;
|
||||
output wire [3:0] result;
|
||||
|
||||
wire [3:0] result_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign cy_out = SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_0(
|
||||
.cy_in(cy_in),
|
||||
.op1(op1[0]),
|
||||
.op2(op2[0]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[0]),
|
||||
.cy_out(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_1(
|
||||
.cy_in(SYNTHESIZED_WIRE_0),
|
||||
.op1(op1[1]),
|
||||
.op2(op2[1]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[1]),
|
||||
.cy_out(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_2(
|
||||
.cy_in(SYNTHESIZED_WIRE_1),
|
||||
.op1(op1[2]),
|
||||
.op2(op2[2]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[2]),
|
||||
.cy_out(SYNTHESIZED_WIRE_5));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_3(
|
||||
.cy_in(SYNTHESIZED_WIRE_5),
|
||||
.op1(op1[3]),
|
||||
.op2(op2[3]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[3]),
|
||||
.cy_out(SYNTHESIZED_WIRE_3));
|
||||
|
||||
assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign result = result_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,302 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 280 560)
|
||||
(text "alu_flags" (rect 5 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 528 25 540)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "ctl_flags_oe" (rect 0 0 69 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_oe" (rect 21 27 90 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "ctl_flags_bus" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_bus" (rect 21 43 97 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "ctl_flags_alu" (rect 0 0 71 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_alu" (rect 21 59 92 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "alu_sf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_sf_out" (rect 21 75 81 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ctl_flags_sz_we" (rect 0 0 95 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_sz_we" (rect 21 91 116 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "alu_zero" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_zero" (rect 21 107 70 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "ctl_alu_zero_16bit" (rect 0 0 103 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_zero_16bit" (rect 21 123 124 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "alu_yf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_yf_out" (rect 21 139 81 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "ctl_flags_xy_we" (rect 0 0 95 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_xy_we" (rect 21 155 116 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "ctl_flags_hf_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_hf_we" (rect 21 171 114 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "ctl_flags_hf_cpl" (rect 0 0 90 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_hf_cpl" (rect 21 187 111 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "ctl_flags_hf2_we" (rect 0 0 100 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_hf2_we" (rect 21 203 121 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "alu_xf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_xf_out" (rect 21 219 81 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224))
|
||||
)
|
||||
(port
|
||||
(pt 0 240)
|
||||
(input)
|
||||
(text "pf_sel" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "pf_sel" (rect 21 235 56 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 240)(pt 16 240))
|
||||
)
|
||||
(port
|
||||
(pt 0 256)
|
||||
(input)
|
||||
(text "ctl_flags_pf_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_pf_we" (rect 21 251 114 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 256)(pt 16 256))
|
||||
)
|
||||
(port
|
||||
(pt 0 272)
|
||||
(input)
|
||||
(text "ctl_flags_nf_set" (rect 0 0 92 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_nf_set" (rect 21 267 113 281)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 272)(pt 16 272))
|
||||
)
|
||||
(port
|
||||
(pt 0 288)
|
||||
(input)
|
||||
(text "ctl_flags_nf_clr" (rect 0 0 88 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_nf_clr" (rect 21 283 109 297)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 288)(pt 16 288))
|
||||
)
|
||||
(port
|
||||
(pt 0 304)
|
||||
(input)
|
||||
(text "ctl_flags_nf_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_nf_we" (rect 21 299 114 313)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 304)(pt 16 304))
|
||||
)
|
||||
(port
|
||||
(pt 0 320)
|
||||
(input)
|
||||
(text "alu_core_cf_out" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_cf_out" (rect 21 315 114 329)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 320)(pt 16 320))
|
||||
)
|
||||
(port
|
||||
(pt 0 336)
|
||||
(input)
|
||||
(text "ctl_flags_cf_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf_we" (rect 21 331 114 345)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 336)(pt 16 336))
|
||||
)
|
||||
(port
|
||||
(pt 0 352)
|
||||
(input)
|
||||
(text "ctl_flags_cf2_we" (rect 0 0 100 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf2_we" (rect 21 347 121 361)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 352)(pt 16 352))
|
||||
)
|
||||
(port
|
||||
(pt 0 368)
|
||||
(input)
|
||||
(text "ctl_flags_cf2_sel_shift" (rect 0 0 129 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf2_sel_shift" (rect 21 363 150 377)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 368)(pt 16 368))
|
||||
)
|
||||
(port
|
||||
(pt 0 384)
|
||||
(input)
|
||||
(text "ctl_flags_cf2_sel_daa" (rect 0 0 126 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf2_sel_daa" (rect 21 379 147 393)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 384)(pt 16 384))
|
||||
)
|
||||
(port
|
||||
(pt 0 400)
|
||||
(input)
|
||||
(text "shift_cf_out" (rect 0 0 68 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_cf_out" (rect 21 395 89 409)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 400)(pt 16 400))
|
||||
)
|
||||
(port
|
||||
(pt 0 416)
|
||||
(input)
|
||||
(text "daa_cf_out" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "daa_cf_out" (rect 21 411 85 425)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 416)(pt 16 416))
|
||||
)
|
||||
(port
|
||||
(pt 0 432)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||
(text "clk" (rect 21 427 36 441)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 432)(pt 16 432))
|
||||
)
|
||||
(port
|
||||
(pt 0 448)
|
||||
(input)
|
||||
(text "ctl_flags_use_cf2" (rect 0 0 102 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_use_cf2" (rect 21 443 123 457)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 448)(pt 16 448))
|
||||
)
|
||||
(port
|
||||
(pt 0 464)
|
||||
(input)
|
||||
(text "ctl_flags_cf_set" (rect 0 0 92 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf_set" (rect 21 459 113 473)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 464)(pt 16 464))
|
||||
)
|
||||
(port
|
||||
(pt 0 480)
|
||||
(input)
|
||||
(text "ctl_flags_cf_cpl" (rect 0 0 90 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_flags_cf_cpl" (rect 21 475 111 489)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 480)(pt 16 480))
|
||||
)
|
||||
(port
|
||||
(pt 0 496)
|
||||
(input)
|
||||
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "nhold_clk_wait" (rect 21 491 105 505)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 496)(pt 16 496))
|
||||
)
|
||||
(port
|
||||
(pt 264 48)
|
||||
(output)
|
||||
(text "flags_sf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_sf" (rect 196 43 243 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 48)(pt 248 48))
|
||||
)
|
||||
(port
|
||||
(pt 264 64)
|
||||
(output)
|
||||
(text "flags_zf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_zf" (rect 196 59 243 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 64)(pt 248 64))
|
||||
)
|
||||
(port
|
||||
(pt 264 80)
|
||||
(output)
|
||||
(text "flags_hf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_hf" (rect 196 75 243 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 80)(pt 248 80))
|
||||
)
|
||||
(port
|
||||
(pt 264 96)
|
||||
(output)
|
||||
(text "flags_hf2" (rect 0 0 54 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_hf2" (rect 189 91 243 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 96)(pt 248 96))
|
||||
)
|
||||
(port
|
||||
(pt 264 112)
|
||||
(output)
|
||||
(text "flags_pf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_pf" (rect 196 107 243 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 112)(pt 248 112))
|
||||
)
|
||||
(port
|
||||
(pt 264 128)
|
||||
(output)
|
||||
(text "flags_nf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_nf" (rect 196 123 243 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 128)(pt 248 128))
|
||||
)
|
||||
(port
|
||||
(pt 264 144)
|
||||
(output)
|
||||
(text "flags_cf_latch" (rect 0 0 81 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_cf_latch" (rect 162 139 243 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 144)(pt 248 144))
|
||||
)
|
||||
(port
|
||||
(pt 264 160)
|
||||
(output)
|
||||
(text "flags_cf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "flags_cf" (rect 196 155 243 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 160)(pt 248 160))
|
||||
)
|
||||
(port
|
||||
(pt 264 32)
|
||||
(bidir)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 201 27 243 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 264 32)(pt 248 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 248 528))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,358 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 09:01:30 2016"
|
||||
|
||||
module alu_flags(
|
||||
ctl_flags_oe,
|
||||
ctl_flags_bus,
|
||||
ctl_flags_alu,
|
||||
alu_sf_out,
|
||||
alu_yf_out,
|
||||
alu_xf_out,
|
||||
ctl_flags_nf_set,
|
||||
alu_zero,
|
||||
shift_cf_out,
|
||||
alu_core_cf_out,
|
||||
daa_cf_out,
|
||||
ctl_flags_cf_set,
|
||||
ctl_flags_cf_cpl,
|
||||
pf_sel,
|
||||
ctl_flags_cf_we,
|
||||
ctl_flags_sz_we,
|
||||
ctl_flags_xy_we,
|
||||
ctl_flags_hf_we,
|
||||
ctl_flags_pf_we,
|
||||
ctl_flags_nf_we,
|
||||
ctl_flags_cf2_we,
|
||||
ctl_flags_hf_cpl,
|
||||
ctl_flags_use_cf2,
|
||||
ctl_flags_hf2_we,
|
||||
ctl_flags_nf_clr,
|
||||
ctl_alu_zero_16bit,
|
||||
clk,
|
||||
ctl_flags_cf2_sel_shift,
|
||||
ctl_flags_cf2_sel_daa,
|
||||
nhold_clk_wait,
|
||||
flags_sf,
|
||||
flags_zf,
|
||||
flags_hf,
|
||||
flags_pf,
|
||||
flags_cf,
|
||||
flags_nf,
|
||||
flags_cf_latch,
|
||||
flags_hf2,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_flags_oe;
|
||||
input wire ctl_flags_bus;
|
||||
input wire ctl_flags_alu;
|
||||
input wire alu_sf_out;
|
||||
input wire alu_yf_out;
|
||||
input wire alu_xf_out;
|
||||
input wire ctl_flags_nf_set;
|
||||
input wire alu_zero;
|
||||
input wire shift_cf_out;
|
||||
input wire alu_core_cf_out;
|
||||
input wire daa_cf_out;
|
||||
input wire ctl_flags_cf_set;
|
||||
input wire ctl_flags_cf_cpl;
|
||||
input wire pf_sel;
|
||||
input wire ctl_flags_cf_we;
|
||||
input wire ctl_flags_sz_we;
|
||||
input wire ctl_flags_xy_we;
|
||||
input wire ctl_flags_hf_we;
|
||||
input wire ctl_flags_pf_we;
|
||||
input wire ctl_flags_nf_we;
|
||||
input wire ctl_flags_cf2_we;
|
||||
input wire ctl_flags_hf_cpl;
|
||||
input wire ctl_flags_use_cf2;
|
||||
input wire ctl_flags_hf2_we;
|
||||
input wire ctl_flags_nf_clr;
|
||||
input wire ctl_alu_zero_16bit;
|
||||
input wire clk;
|
||||
input wire ctl_flags_cf2_sel_shift;
|
||||
input wire ctl_flags_cf2_sel_daa;
|
||||
input wire nhold_clk_wait;
|
||||
output wire flags_sf;
|
||||
output wire flags_zf;
|
||||
output wire flags_hf;
|
||||
output wire flags_pf;
|
||||
output wire flags_cf;
|
||||
output wire flags_nf;
|
||||
output wire flags_cf_latch;
|
||||
output reg flags_hf2;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg flags_xf;
|
||||
reg flags_yf;
|
||||
wire [1:0] sel;
|
||||
reg DFFE_inst_latch_hf;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
reg SYNTHESIZED_WIRE_39;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
reg DFFE_inst_latch_sf;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
reg DFFE_inst_latch_pf;
|
||||
reg DFFE_inst_latch_nf;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_33;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
reg DFFE_inst_latch_cf;
|
||||
reg DFFE_inst_latch_cf2;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
|
||||
assign flags_sf = DFFE_inst_latch_sf;
|
||||
assign flags_zf = SYNTHESIZED_WIRE_39;
|
||||
assign flags_hf = SYNTHESIZED_WIRE_23;
|
||||
assign flags_pf = DFFE_inst_latch_pf;
|
||||
assign flags_cf = SYNTHESIZED_WIRE_24;
|
||||
assign flags_nf = DFFE_inst_latch_nf;
|
||||
assign flags_cf_latch = DFFE_inst_latch_cf;
|
||||
assign SYNTHESIZED_WIRE_38 = 0;
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
|
||||
|
||||
assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
|
||||
|
||||
assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
|
||||
|
||||
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
|
||||
|
||||
assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
|
||||
|
||||
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
|
||||
|
||||
assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
|
||||
|
||||
assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
|
||||
|
||||
assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
|
||||
|
||||
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_27)
|
||||
begin
|
||||
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_hf_we)
|
||||
begin
|
||||
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_hf2_we)
|
||||
begin
|
||||
flags_hf2 <= SYNTHESIZED_WIRE_40;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_nf_we)
|
||||
begin
|
||||
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_pf_we)
|
||||
begin
|
||||
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_sz_we)
|
||||
begin
|
||||
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_xy_we)
|
||||
begin
|
||||
flags_xf <= SYNTHESIZED_WIRE_35;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_xy_we)
|
||||
begin
|
||||
flags_yf <= SYNTHESIZED_WIRE_36;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_sz_we)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
alu_mux_2 b2v_inst_mux_cf(
|
||||
.in0(DFFE_inst_latch_cf),
|
||||
.in1(DFFE_inst_latch_cf2),
|
||||
.sel1(ctl_flags_use_cf2),
|
||||
.out(SYNTHESIZED_WIRE_25));
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_mux_cf2(
|
||||
.in0(alu_core_cf_out),
|
||||
.in1(shift_cf_out),
|
||||
.in2(daa_cf_out),
|
||||
.in3(SYNTHESIZED_WIRE_38),
|
||||
.sel(sel),
|
||||
.out(SYNTHESIZED_WIRE_28));
|
||||
|
||||
assign sel[0] = ctl_flags_cf2_sel_shift;
|
||||
assign sel[1] = ctl_flags_cf2_sel_daa;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 104 208 120)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "sel1" (rect 9 0 29 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 88 208 104)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in1" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 40 208 56)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in0" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 480 72 656 88)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "out" (rect 90 0 105 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 248 48 296 80)
|
||||
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(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
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@@ -0,0 +1,57 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
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|
||||
(port
|
||||
(pt 0 32)
|
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(input)
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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(pt 0 64)
|
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|
||||
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|
||||
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|
||||
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|
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)
|
||||
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|
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|
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|
||||
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|
||||
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|
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|
||||
@@ -0,0 +1,48 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:10:35 2014"
|
||||
|
||||
module alu_mux_2(
|
||||
sel1,
|
||||
in1,
|
||||
in0,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire sel1;
|
||||
input wire in1;
|
||||
input wire in0;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = in1 & sel1;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~sel1;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,299 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 32 200 48)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
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|
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|
||||
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||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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(name "title-custom-small")
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(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
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(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_2z" (rect 43 2 124 17)(font "Arial" (font_size 9)(bold)))(border))
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@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
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(symbol
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|
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|
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|
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|
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|
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|
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(line (pt 144 32)(pt 128 32)(line_width 3))
|
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)
|
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|
||||
(pt 144 48)
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(output)
|
||||
(text "ena" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "ena" (rect 102 43 123 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 144 48)(pt 128 48))
|
||||
)
|
||||
(drawing
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||||
(rectangle (rect 16 16 128 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,49 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Oct 31 21:18:33 2014"
|
||||
|
||||
module alu_mux_2z(
|
||||
sel_a,
|
||||
sel_zero,
|
||||
a,
|
||||
ena,
|
||||
Q
|
||||
);
|
||||
|
||||
|
||||
input wire sel_a;
|
||||
input wire sel_zero;
|
||||
input wire [3:0] a;
|
||||
output wire ena;
|
||||
output wire [3:0] Q;
|
||||
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a};
|
||||
|
||||
assign ena = sel_a | sel_zero;
|
||||
|
||||
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,445 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 160 200 176)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "sel_zero" (rect 9 0 49 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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)
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|
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(pt 384 168)
|
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(pt 416 168)
|
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)
|
||||
(junction (pt 280 56))
|
||||
(junction (pt 264 120))
|
||||
(junction (pt 384 168))
|
||||
(title_block
|
||||
(rect 24 272 281 324)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_3z" (rect 43 2 124 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
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(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border))
|
||||
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|
||||
(drawing
|
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)
|
||||
)
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 160 144)
|
||||
(text "alu_mux_3z" (rect 5 0 73 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "a[3..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "a[3..0]" (rect 21 27 56 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "sel_a" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "sel_a" (rect 21 43 51 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
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|
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|
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|
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|
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(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "sel_b" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "sel_b" (rect 21 75 51 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "sel_zero" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "sel_zero" (rect 21 91 70 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 144 32)
|
||||
(output)
|
||||
(text "Q[3..0]" (rect 0 0 37 14)(font "Arial" (font_size 8)))
|
||||
(text "Q[3..0]" (rect 86 27 123 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 144 32)(pt 128 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 144 48)
|
||||
(output)
|
||||
(text "ena" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "ena" (rect 102 43 123 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 144 48)(pt 128 48))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 128 112))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,59 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Oct 31 21:08:42 2014"
|
||||
|
||||
module alu_mux_3z(
|
||||
sel_zero,
|
||||
sel_a,
|
||||
sel_b,
|
||||
a,
|
||||
b,
|
||||
ena,
|
||||
Q
|
||||
);
|
||||
|
||||
|
||||
input wire sel_zero;
|
||||
input wire sel_a;
|
||||
input wire sel_b;
|
||||
input wire [3:0] a;
|
||||
input wire [3:0] b;
|
||||
output wire ena;
|
||||
output wire [3:0] Q;
|
||||
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire [3:0] SYNTHESIZED_WIRE_2;
|
||||
wire [3:0] SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a};
|
||||
|
||||
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign ena = sel_a | sel_b | sel_zero;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b};
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,556 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 192 208 208)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in0" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 240 208 256)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in1" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
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|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
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|
||||
(rect 32 288 208 304)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in2" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
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|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
(line (pt 92 12)(pt 92 4))
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(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 21, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_4" (rect 43 2 117 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 128 144)
|
||||
(text "alu_mux_4" (rect 5 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "sel[1..0]" (rect 21 27 65 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "in0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in0" (rect 21 43 37 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "in1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in1" (rect 21 59 37 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "in2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in2" (rect 21 75 37 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "in3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in3" (rect 21 91 37 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 112 32)
|
||||
(output)
|
||||
(text "out" (rect 0 0 17 14)(font "Arial" (font_size 8)))
|
||||
(text "out" (rect 74 27 91 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 112 32)(pt 96 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 96 112))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,61 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:05:38 2014"
|
||||
|
||||
module alu_mux_4(
|
||||
in0,
|
||||
in1,
|
||||
in2,
|
||||
in3,
|
||||
sel,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire in0;
|
||||
input wire in1;
|
||||
input wire in2;
|
||||
input wire in3;
|
||||
input wire [1:0] sel;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = ~sel[1];
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 128 208)
|
||||
(text "alu_mux_8" (rect 5 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 176 25 188)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "sel[2..0]" (rect 21 27 65 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "in0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in0" (rect 21 43 37 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "in1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in1" (rect 21 59 37 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "in2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in2" (rect 21 75 37 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "in3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in3" (rect 21 91 37 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "in4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in4" (rect 21 107 37 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "in5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in5" (rect 21 123 37 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "in6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in6" (rect 21 139 37 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "in7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "in7" (rect 21 155 37 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160))
|
||||
)
|
||||
(port
|
||||
(pt 112 32)
|
||||
(output)
|
||||
(text "out" (rect 0 0 17 14)(font "Arial" (font_size 8)))
|
||||
(text "out" (rect 74 27 91 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 112 32)(pt 96 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 96 176))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,84 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:04:13 2014"
|
||||
|
||||
module alu_mux_8(
|
||||
in0,
|
||||
in1,
|
||||
in2,
|
||||
in3,
|
||||
in4,
|
||||
in5,
|
||||
in6,
|
||||
in7,
|
||||
sel,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire in0;
|
||||
input wire in1;
|
||||
input wire in2;
|
||||
input wire in3;
|
||||
input wire in4;
|
||||
input wire in5;
|
||||
input wire in6;
|
||||
input wire in7;
|
||||
input wire [2:0] sel;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = ~sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ~sel[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = ~sel[2];
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,624 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 48 200 64)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "low[3..0]" (rect 9 0 50 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 192 200 208)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "high[3..0]" (rect 9 0 55 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 552 80 728 96)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "low_gt_9" (rect 90 0 132 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 552 304 728 320)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "high_eq_9" (rect 90 0 139 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 552 224 728 240)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "high_gt_9" (rect 90 0 137 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
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(pt 224 200)
|
||||
(pt 200 200)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 224 72))
|
||||
(junction (pt 360 56))
|
||||
(junction (pt 224 56))
|
||||
(junction (pt 360 248))
|
||||
(junction (pt 360 200))
|
||||
(junction (pt 336 216))
|
||||
(junction (pt 224 200))
|
||||
(junction (pt 224 216))
|
||||
(junction (pt 312 264))
|
||||
(junction (pt 224 264))
|
||||
(text "A" (rect 272 40 281 54)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 272 56 280 70)(font "Arial" (font_size 8)))
|
||||
(text "C" (rect 272 104 280 118)(font "Arial" (font_size 8)))
|
||||
(text "A" (rect 272 184 281 198)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 272 200 280 214)(font "Arial" (font_size 8)))
|
||||
(text "C" (rect 272 248 280 262)(font "Arial" (font_size 8)))
|
||||
(text "D" (rect 272 288 280 302)(font "Arial" (font_size 8)))
|
||||
(text "n>9 : A * B + A * C" (rect 560 152 668 166)(font "Arial" (font_size 8)))
|
||||
(text "n==9 : A * /B * /C * D" (rect 560 280 682 294)(font "Arial" (font_size 8)))
|
||||
(title_block
|
||||
(rect 32 400 289 452)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_prep_daa" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 184 112)
|
||||
(text "alu_prep_daa" (rect 5 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 80 25 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "low[3..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "low[3..0]" (rect 21 27 70 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "high[3..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
|
||||
(text "high[3..0]" (rect 21 43 72 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "low_gt_9" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "low_gt_9" (rect 94 27 147 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32))
|
||||
)
|
||||
(port
|
||||
(pt 168 48)
|
||||
(output)
|
||||
(text "high_gt_9" (rect 0 0 55 14)(font "Arial" (font_size 8)))
|
||||
(text "high_gt_9" (rect 92 43 147 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 168 48)(pt 152 48))
|
||||
)
|
||||
(port
|
||||
(pt 168 64)
|
||||
(output)
|
||||
(text "high_eq_9" (rect 0 0 59 14)(font "Arial" (font_size 8)))
|
||||
(text "high_eq_9" (rect 88 59 147 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 168 64)(pt 152 64))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,63 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:01:36 2014"
|
||||
|
||||
module alu_prep_daa(
|
||||
high,
|
||||
low,
|
||||
low_gt_9,
|
||||
high_eq_9,
|
||||
high_gt_9
|
||||
);
|
||||
|
||||
|
||||
input wire [3:0] high;
|
||||
input wire [3:0] low;
|
||||
output wire low_gt_9;
|
||||
output wire high_eq_9;
|
||||
output wire high_gt_9;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~high[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = low[3] & low[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = high[3] & high[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = low[3] & low[1];
|
||||
|
||||
assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = high[3] & high[1];
|
||||
|
||||
assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~high[1];
|
||||
|
||||
assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,653 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 40 216 56)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_oe" (rect 9 0 58 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 80 216 96)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_shift_oe" (rect 9 0 86 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
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|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 104 216 120)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op2_oe" (rect 9 0 82 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 4)(pt 121 8))
|
||||
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|
||||
)
|
||||
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|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 128 216 144)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_res_oe" (rect 9 0 79 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 152 216 168)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op1_oe" (rect 9 0 82 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 176 216 192)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_bs_oe" (rect 9 0 76 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 232 216 248)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op1_sel_bus" (rect 9 0 108 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 256 216 272)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op1_sel_low" (rect 9 0 105 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 280 216 296)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op1_sel_zero" (rect 9 0 110 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 328 216 344)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op2_sel_zero" (rect 9 0 110 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
)
|
||||
(pin
|
||||
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|
||||
(rect 40 352 216 368)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op2_sel_bus" (rect 9 0 108 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 376 216 392)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_op2_sel_lq" (rect 9 0 98 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 400 216 416)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_sel_op2_neg" (rect 9 0 108 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 424 216 440)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_sel_op2_high" (rect 9 0 110 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 472 216 488)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_alu_core_R" (rect 9 0 82 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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(name "title-custom-small")
|
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|
||||
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|
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|
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|
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|
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|
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|
||||
@@ -0,0 +1,267 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
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||||
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||||
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|
||||
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|
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||||
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||||
(pt 0 80)
|
||||
(input)
|
||||
(text "ctl_alu_res_oe" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_res_oe" (rect 21 75 104 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ctl_alu_op1_oe" (rect 0 0 86 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op1_oe" (rect 21 91 107 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "ctl_alu_bs_oe" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_bs_oe" (rect 21 107 100 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "ctl_alu_op1_sel_bus" (rect 0 0 116 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op1_sel_bus" (rect 21 123 137 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "ctl_alu_op1_sel_low" (rect 0 0 116 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op1_sel_low" (rect 21 139 137 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "ctl_alu_op1_sel_zero" (rect 0 0 121 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op1_sel_zero" (rect 21 155 142 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "ctl_alu_op2_sel_zero" (rect 0 0 121 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op2_sel_zero" (rect 21 171 142 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "ctl_alu_op2_sel_bus" (rect 0 0 116 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op2_sel_bus" (rect 21 187 137 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "ctl_alu_op2_sel_lq" (rect 0 0 105 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_op2_sel_lq" (rect 21 203 126 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "ctl_alu_sel_op2_neg" (rect 0 0 116 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_sel_op2_neg" (rect 21 219 137 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224))
|
||||
)
|
||||
(port
|
||||
(pt 0 240)
|
||||
(input)
|
||||
(text "ctl_alu_sel_op2_high" (rect 0 0 119 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_sel_op2_high" (rect 21 235 140 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 240)(pt 16 240))
|
||||
)
|
||||
(port
|
||||
(pt 0 256)
|
||||
(input)
|
||||
(text "ctl_alu_core_R" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_core_R" (rect 21 251 105 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 256)(pt 16 256))
|
||||
)
|
||||
(port
|
||||
(pt 0 272)
|
||||
(input)
|
||||
(text "ctl_alu_core_V" (rect 0 0 86 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_core_V" (rect 21 267 107 281)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 272)(pt 16 272))
|
||||
)
|
||||
(port
|
||||
(pt 0 288)
|
||||
(input)
|
||||
(text "ctl_alu_core_S" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_alu_core_S" (rect 21 283 105 297)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 288)(pt 16 288))
|
||||
)
|
||||
(port
|
||||
(pt 280 32)
|
||||
(output)
|
||||
(text "alu_oe" (rect 0 0 37 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_oe" (rect 222 27 259 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 32)(pt 264 32))
|
||||
)
|
||||
(port
|
||||
(pt 280 48)
|
||||
(output)
|
||||
(text "alu_shift_oe" (rect 0 0 69 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_shift_oe" (rect 190 43 259 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 48)(pt 264 48))
|
||||
)
|
||||
(port
|
||||
(pt 280 64)
|
||||
(output)
|
||||
(text "alu_op2_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_oe" (rect 193 59 259 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 64)(pt 264 64))
|
||||
)
|
||||
(port
|
||||
(pt 280 80)
|
||||
(output)
|
||||
(text "alu_res_oe" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_res_oe" (rect 196 75 259 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 80)(pt 264 80))
|
||||
)
|
||||
(port
|
||||
(pt 280 96)
|
||||
(output)
|
||||
(text "alu_op1_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op1_oe" (rect 193 91 259 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 96)(pt 264 96))
|
||||
)
|
||||
(port
|
||||
(pt 280 112)
|
||||
(output)
|
||||
(text "alu_bs_oe" (rect 0 0 59 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_bs_oe" (rect 200 107 259 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 112)(pt 264 112))
|
||||
)
|
||||
(port
|
||||
(pt 280 128)
|
||||
(output)
|
||||
(text "alu_op1_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op1_sel_bus" (rect 163 123 259 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 128)(pt 264 128))
|
||||
)
|
||||
(port
|
||||
(pt 280 144)
|
||||
(output)
|
||||
(text "alu_op1_sel_low" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op1_sel_low" (rect 163 139 259 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 144)(pt 264 144))
|
||||
)
|
||||
(port
|
||||
(pt 280 160)
|
||||
(output)
|
||||
(text "alu_op1_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op1_sel_zero" (rect 158 155 259 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 160)(pt 264 160))
|
||||
)
|
||||
(port
|
||||
(pt 280 176)
|
||||
(output)
|
||||
(text "alu_op2_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_zero" (rect 158 171 259 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 176)(pt 264 176))
|
||||
)
|
||||
(port
|
||||
(pt 280 192)
|
||||
(output)
|
||||
(text "alu_op2_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_bus" (rect 163 187 259 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 192)(pt 264 192))
|
||||
)
|
||||
(port
|
||||
(pt 280 208)
|
||||
(output)
|
||||
(text "alu_op2_sel_lq" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_op2_sel_lq" (rect 175 203 259 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 208)(pt 264 208))
|
||||
)
|
||||
(port
|
||||
(pt 280 224)
|
||||
(output)
|
||||
(text "alu_sel_op2_neg" (rect 0 0 96 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_sel_op2_neg" (rect 163 219 259 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 224)(pt 264 224))
|
||||
)
|
||||
(port
|
||||
(pt 280 240)
|
||||
(output)
|
||||
(text "alu_sel_op2_high" (rect 0 0 99 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_sel_op2_high" (rect 160 235 259 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 240)(pt 264 240))
|
||||
)
|
||||
(port
|
||||
(pt 280 256)
|
||||
(output)
|
||||
(text "alu_core_R" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_R" (rect 195 251 259 265)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 256)(pt 264 256))
|
||||
)
|
||||
(port
|
||||
(pt 280 272)
|
||||
(output)
|
||||
(text "alu_core_V" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_V" (rect 193 267 259 281)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 272)(pt 264 272))
|
||||
)
|
||||
(port
|
||||
(pt 280 288)
|
||||
(output)
|
||||
(text "alu_core_S" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "alu_core_S" (rect 195 283 259 297)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 288)(pt 264 288))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 264 304))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,114 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:59:39 2014"
|
||||
|
||||
module alu_select(
|
||||
ctl_alu_oe,
|
||||
ctl_alu_shift_oe,
|
||||
ctl_alu_op2_oe,
|
||||
ctl_alu_res_oe,
|
||||
ctl_alu_op1_oe,
|
||||
ctl_alu_bs_oe,
|
||||
ctl_alu_op1_sel_bus,
|
||||
ctl_alu_op1_sel_low,
|
||||
ctl_alu_op1_sel_zero,
|
||||
ctl_alu_op2_sel_zero,
|
||||
ctl_alu_op2_sel_bus,
|
||||
ctl_alu_op2_sel_lq,
|
||||
ctl_alu_sel_op2_neg,
|
||||
ctl_alu_sel_op2_high,
|
||||
ctl_alu_core_R,
|
||||
ctl_alu_core_V,
|
||||
ctl_alu_core_S,
|
||||
alu_oe,
|
||||
alu_shift_oe,
|
||||
alu_op2_oe,
|
||||
alu_res_oe,
|
||||
alu_op1_oe,
|
||||
alu_bs_oe,
|
||||
alu_op1_sel_bus,
|
||||
alu_op1_sel_low,
|
||||
alu_op1_sel_zero,
|
||||
alu_op2_sel_zero,
|
||||
alu_op2_sel_bus,
|
||||
alu_op2_sel_lq,
|
||||
alu_sel_op2_neg,
|
||||
alu_sel_op2_high,
|
||||
alu_core_R,
|
||||
alu_core_V,
|
||||
alu_core_S
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_alu_oe;
|
||||
input wire ctl_alu_shift_oe;
|
||||
input wire ctl_alu_op2_oe;
|
||||
input wire ctl_alu_res_oe;
|
||||
input wire ctl_alu_op1_oe;
|
||||
input wire ctl_alu_bs_oe;
|
||||
input wire ctl_alu_op1_sel_bus;
|
||||
input wire ctl_alu_op1_sel_low;
|
||||
input wire ctl_alu_op1_sel_zero;
|
||||
input wire ctl_alu_op2_sel_zero;
|
||||
input wire ctl_alu_op2_sel_bus;
|
||||
input wire ctl_alu_op2_sel_lq;
|
||||
input wire ctl_alu_sel_op2_neg;
|
||||
input wire ctl_alu_sel_op2_high;
|
||||
input wire ctl_alu_core_R;
|
||||
input wire ctl_alu_core_V;
|
||||
input wire ctl_alu_core_S;
|
||||
output wire alu_oe;
|
||||
output wire alu_shift_oe;
|
||||
output wire alu_op2_oe;
|
||||
output wire alu_res_oe;
|
||||
output wire alu_op1_oe;
|
||||
output wire alu_bs_oe;
|
||||
output wire alu_op1_sel_bus;
|
||||
output wire alu_op1_sel_low;
|
||||
output wire alu_op1_sel_zero;
|
||||
output wire alu_op2_sel_zero;
|
||||
output wire alu_op2_sel_bus;
|
||||
output wire alu_op2_sel_lq;
|
||||
output wire alu_sel_op2_neg;
|
||||
output wire alu_sel_op2_high;
|
||||
output wire alu_core_R;
|
||||
output wire alu_core_V;
|
||||
output wire alu_core_S;
|
||||
|
||||
|
||||
assign alu_oe = ctl_alu_oe;
|
||||
assign alu_shift_oe = ctl_alu_shift_oe;
|
||||
assign alu_op2_oe = ctl_alu_op2_oe;
|
||||
assign alu_res_oe = ctl_alu_res_oe;
|
||||
assign alu_op1_oe = ctl_alu_op1_oe;
|
||||
assign alu_bs_oe = ctl_alu_bs_oe;
|
||||
assign alu_op1_sel_bus = ctl_alu_op1_sel_bus;
|
||||
assign alu_op1_sel_low = ctl_alu_op1_sel_low;
|
||||
assign alu_op1_sel_zero = ctl_alu_op1_sel_zero;
|
||||
assign alu_op2_sel_zero = ctl_alu_op2_sel_zero;
|
||||
assign alu_op2_sel_bus = ctl_alu_op2_sel_bus;
|
||||
assign alu_op2_sel_lq = ctl_alu_op2_sel_lq;
|
||||
assign alu_sel_op2_neg = ctl_alu_sel_op2_neg;
|
||||
assign alu_sel_op2_high = ctl_alu_sel_op2_high;
|
||||
assign alu_core_R = ctl_alu_core_R;
|
||||
assign alu_core_V = ctl_alu_core_V;
|
||||
assign alu_core_S = ctl_alu_core_S;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 200 144)
|
||||
(text "alu_shifter_core" (rect 5 0 98 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 21 27 63 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "shift_in" (rect 0 0 41 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_in" (rect 21 43 62 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "shift_left" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_left" (rect 21 59 70 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "shift_right" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_right" (rect 21 75 77 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "shift_db0" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_db0" (rect 110 27 163 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 184 32)(pt 168 32))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(output)
|
||||
(text "shift_db7" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "shift_db7" (rect 110 43 163 57)(font "Arial" (font_size 8)))
|
||||
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(text "out_low[3..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
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(text "out_low[3..0]" (rect 89 59 163 73)(font "Arial" (font_size 8)))
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|
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)
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(pt 184 80)
|
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(output)
|
||||
(text "out_high[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
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(text "out_high[3..0]" (rect 87 75 163 89)(font "Arial" (font_size 8)))
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(rectangle (rect 16 16 168 112))
|
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)
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(fill (color 217 255 255))
|
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)
|
||||
@@ -0,0 +1,142 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:55:31 2014"
|
||||
|
||||
module alu_shifter_core(
|
||||
shift_in,
|
||||
shift_right,
|
||||
shift_left,
|
||||
db,
|
||||
shift_db0,
|
||||
shift_db7,
|
||||
out_high,
|
||||
out_low
|
||||
);
|
||||
|
||||
|
||||
input wire shift_in;
|
||||
input wire shift_right;
|
||||
input wire shift_left;
|
||||
input wire [7:0] db;
|
||||
output wire shift_db0;
|
||||
output wire shift_db7;
|
||||
output wire [3:0] out_high;
|
||||
output wire [3:0] out_low;
|
||||
|
||||
wire [3:0] out_high_ALTERA_SYNTHESIZED;
|
||||
wire [3:0] out_low_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign shift_db0 = db[0];
|
||||
assign shift_db7 = db[7];
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = shift_in & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = db[1] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = db[0] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = db[2] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = db[1] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = db[3] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = db[2] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = db[4] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = db[3] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = db[5] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = db[4] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_25 = db[6] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_27 = db[5] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_28 = db[7] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = db[6] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = shift_in & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = ~(shift_right | shift_left);
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign out_high = out_high_ALTERA_SYNTHESIZED;
|
||||
assign out_low = out_low_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,756 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
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(pin
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||||
(rect 24 72 200 88)
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(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_slice" (rect 43 2 103 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 136 176)
|
||||
(text "alu_slice" (rect 5 0 54 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 144 25 156)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "cy_in" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "cy_in" (rect 21 27 51 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "op1" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "op1" (rect 21 43 42 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "op2" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "op2" (rect 21 59 42 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "S" (rect 0 0 8 14)(font "Arial" (font_size 8)))
|
||||
(text "S" (rect 21 75 29 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "V" (rect 0 0 9 14)(font "Arial" (font_size 8)))
|
||||
(text "V" (rect 21 91 30 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "R" (rect 0 0 8 14)(font "Arial" (font_size 8)))
|
||||
(text "R" (rect 21 107 29 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 120 32)
|
||||
(output)
|
||||
(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||
(text "result" (rect 68 27 99 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 120 32)(pt 104 32))
|
||||
)
|
||||
(port
|
||||
(pt 120 48)
|
||||
(output)
|
||||
(text "cy_out" (rect 0 0 38 14)(font "Arial" (font_size 8)))
|
||||
(text "cy_out" (rect 61 43 99 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 120 48)(pt 104 48))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 104 144))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,76 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:51:12 2014"
|
||||
|
||||
module alu_slice(
|
||||
op2,
|
||||
op1,
|
||||
cy_in,
|
||||
R,
|
||||
S,
|
||||
V,
|
||||
cy_out,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire op2;
|
||||
input wire op1;
|
||||
input wire cy_in;
|
||||
input wire R;
|
||||
input wire S;
|
||||
input wire V;
|
||||
output wire cy_out;
|
||||
output wire result;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = op2 | cy_in | op1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = cy_in & op2 & op1;
|
||||
|
||||
assign result = ~SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4);
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = op2 | op1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = op1 & op2;
|
||||
|
||||
assign cy_out = ~(R | SYNTHESIZED_WIRE_10);
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S);
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1 @@
|
||||
restart -f ; run -all
|
||||
@@ -0,0 +1,539 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||
max = $MODEL_TECH/../altera/vhdl/max
|
||||
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
||||
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
||||
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
||||
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
||||
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
||||
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
||||
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
||||
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
||||
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
||||
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
||||
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
||||
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
||||
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
||||
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
max_ver = $MODEL_TECH/../altera/verilog/max
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
||||
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
||||
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
||||
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
||||
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
||||
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
||||
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
||||
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
||||
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
||||
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
||||
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
||||
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
||||
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
||||
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
||||
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
||||
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 0 ns
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 14
|
||||
Project_File_0 = $ROOT/cpu/alu/alu.v
|
||||
Project_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
|
||||
Project_File_P_1 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_2 = $ROOT/cpu/alu/alu_core.v
|
||||
Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_3 = $ROOT/cpu/alu/alu_mux_2z.v
|
||||
Project_File_P_3 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_4 = $ROOT/cpu/alu/alu_mux_3z.v
|
||||
Project_File_P_4 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_5 = $ROOT/cpu/alu/alu_prep_daa.v
|
||||
Project_File_P_5 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_6 = $ROOT/cpu/alu/alu_shifter_core.v
|
||||
Project_File_P_6 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_7 = $ROOT/cpu/alu/alu_slice.v
|
||||
Project_File_P_7 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_8 = $ROOT/cpu/alu/test_alu.sv
|
||||
Project_File_P_8 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 1 vlog_enable0In 0 vlog_hazard 1 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_9 = $ROOT/cpu/alu/test_core.sv
|
||||
Project_File_P_9 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_10 = $ROOT/cpu/alu/test_mux_3z.sv
|
||||
Project_File_P_10 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_11 = $ROOT/cpu/alu/test_prep_daa.sv
|
||||
Project_File_P_11 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_12 = $ROOT/cpu/alu/test_shifter_core.sv
|
||||
Project_File_P_12 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_13 = $ROOT/cpu/alu/test_slice.sv
|
||||
Project_File_P_13 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_Sim_Count = 6
|
||||
Project_Sim_0 = Test slice
|
||||
Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_slice -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_1 = Test core
|
||||
Project_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_2 = Test prep daa
|
||||
Project_Sim_P_2 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_prep_daa -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0
|
||||
Project_Sim_3 = Test ALU
|
||||
Project_Sim_P_3 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {ALU Complete} +pulse_e {} additional_dus work.test_alu -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_4 = Test shifter core
|
||||
Project_Sim_P_4 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder shifter +pulse_e {} additional_dus work.test_shifter_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_5 = Test mux 3z
|
||||
Project_Sim_P_5 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_mux_3z -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0
|
||||
Project_Folder_Count = 4
|
||||
Project_Folder_0 = misc
|
||||
Project_Folder_P_0 = folder {Top Level}
|
||||
Project_Folder_1 = shifter
|
||||
Project_Folder_P_1 = folder {Top Level}
|
||||
Project_Folder_2 = alu
|
||||
Project_Folder_P_2 = folder {Top Level}
|
||||
Project_Folder_3 = ALU Complete
|
||||
Project_Folder_P_3 = folder {Top Level}
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 1
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 10
|
||||
Project_Minor_Version = 1
|
||||
@@ -0,0 +1,74 @@
|
||||
onerror {resume}
|
||||
quietly virtual signal -install /test_alu { (context /test_alu )&{test_db_low ,test_db_high }} test_bus
|
||||
quietly virtual signal -install /test_alu { (context /test_alu )&{test_db_high ,test_db_low }} test_bus001
|
||||
quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op1_high, /test_alu/alu_inst/op1_low }} OP1
|
||||
quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op2_high, /test_alu/alu_inst/op2_low }} OP2
|
||||
quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/result_hi, /test_alu/alu_inst/result_lo }} RESULT
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db_w[7]} -radix hexadecimal} {{/test_alu/db_w[6]} -radix hexadecimal} {{/test_alu/db_w[5]} -radix hexadecimal} {{/test_alu/db_w[4]} -radix hexadecimal} {{/test_alu/db_w[3]} -radix hexadecimal} {{/test_alu/db_w[2]} -radix hexadecimal} {{/test_alu/db_w[1]} -radix hexadecimal} {{/test_alu/db_w[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db_w[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db_w
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db[7]} -radix hexadecimal} {{/test_alu/db[6]} -radix hexadecimal} {{/test_alu/db[5]} -radix hexadecimal} {{/test_alu/db[4]} -radix hexadecimal} {{/test_alu/db[3]} -radix hexadecimal} {{/test_alu/db[2]} -radix hexadecimal} {{/test_alu/db[1]} -radix hexadecimal} {{/test_alu/db[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db
|
||||
add wave -noupdate -color {Medium Orchid} -itemcolor Gold -label test_bus -radix hexadecimal -childformat {{{/test_alu/test_bus001[7]} -radix hexadecimal} {{/test_alu/test_bus001[6]} -radix hexadecimal} {{/test_alu/test_bus001[5]} -radix hexadecimal} {{/test_alu/test_bus001[4]} -radix hexadecimal} {{/test_alu/test_bus001[3]} -radix hexadecimal} {{/test_alu/test_bus001[2]} -radix hexadecimal} {{/test_alu/test_bus001[1]} -radix hexadecimal} {{/test_alu/test_bus001[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/test_db_high[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal}} /test_alu/test_bus001
|
||||
add wave -noupdate /test_alu/clk
|
||||
add wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op1
|
||||
add wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op2
|
||||
add wave -noupdate -expand -group Registers -radix hexadecimal -childformat {{(7) -radix hexadecimal} {(6) -radix hexadecimal} {(5) -radix hexadecimal} {(4) -radix hexadecimal} {(3) -radix hexadecimal} {(2) -radix hexadecimal} {(1) -radix hexadecimal} {(0) -radix hexadecimal}} -subitemconfig {{/test_alu/alu_inst/op1_high[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[0]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[0]} {-radix hexadecimal}} /test_alu/alu_inst/OP1
|
||||
add wave -noupdate -expand -group Registers -radix hexadecimal /test_alu/alu_inst/OP2
|
||||
add wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_hi
|
||||
add wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_lo
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_oe
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_op1_oe
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_op2_oe
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_res_oe
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_shift_oe
|
||||
add wave -noupdate -expand -group {Bus control} /test_alu/alu_bs_oe
|
||||
add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db0
|
||||
add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db7
|
||||
add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_in
|
||||
add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_right
|
||||
add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_left
|
||||
add wave -noupdate /test_alu/bsel
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_bus
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_low
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_zero
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_bus
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_lq
|
||||
add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_zero
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_R
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_S
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_V
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_neg
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_high
|
||||
add wave -noupdate -expand -group {ALU core} /test_alu/alu_op_low
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_core_cf_in
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_core_cf_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_parity_in
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_parity_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_zero
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_vf_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_sf_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_xf_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_yf_out
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_low_gt_9
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_high_gt_9
|
||||
add wave -noupdate -expand -group Flags /test_alu/alu_high_eq_9
|
||||
add wave -noupdate /test_alu/cf
|
||||
add wave -noupdate /test_alu/pf
|
||||
add wave -noupdate /test_alu/hf
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1800 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 180
|
||||
configure wave -valuecolwidth 58
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {4800 ns}
|
||||
@@ -0,0 +1,29 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -radix hexadecimal /test_core/op1_sig
|
||||
add wave -noupdate -radix hexadecimal /test_core/op2_sig
|
||||
add wave -noupdate /test_core/cy_in_sig
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_core/result_sig
|
||||
add wave -noupdate -color Gold -format Literal -itemcolor Gold /test_core/cy_out_sig
|
||||
add wave -noupdate -color Gray75 -itemcolor Gray75 /test_core/vf_out_sig
|
||||
add wave -noupdate /test_core/R_sig
|
||||
add wave -noupdate /test_core/S_sig
|
||||
add wave -noupdate /test_core/V_sig
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2000 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 140
|
||||
configure wave -valuecolwidth 53
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {4400 ns}
|
||||
@@ -0,0 +1,27 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -radix hexadecimal /test_mux_3z/a_sig
|
||||
add wave -noupdate -radix hexadecimal /test_mux_3z/b_sig
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_mux_3z/Q_sig
|
||||
add wave -noupdate /test_mux_3z/sel_a_sig
|
||||
add wave -noupdate /test_mux_3z/sel_b_sig
|
||||
add wave -noupdate /test_mux_3z/sel_zero_sig
|
||||
add wave -noupdate /test_mux_3z/ena_out_sig
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {600 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 118
|
||||
configure wave -valuecolwidth 59
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {3800 ns}
|
||||
@@ -0,0 +1,25 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/low_sig
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/high_sig
|
||||
add wave -noupdate /test_prep_daa/low_gt_9_sig
|
||||
add wave -noupdate /test_prep_daa/high_gt_9_sig
|
||||
add wave -noupdate /test_prep_daa/high_eq_9_sig
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1400 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 138
|
||||
configure wave -valuecolwidth 60
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {4100 ns}
|
||||
@@ -0,0 +1,30 @@
|
||||
onerror {resume}
|
||||
quietly virtual signal -install /test_shifter_core { (context /test_shifter_core )&{out_high ,out_low }} db_out
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -radix binary -childformat {{{/test_shifter_core/db[7]} -radix binary} {{/test_shifter_core/db[6]} -radix binary} {{/test_shifter_core/db[5]} -radix binary} {{/test_shifter_core/db[4]} -radix binary} {{/test_shifter_core/db[3]} -radix binary} {{/test_shifter_core/db[2]} -radix binary} {{/test_shifter_core/db[1]} -radix binary} {{/test_shifter_core/db[0]} -radix binary}} -subitemconfig {{/test_shifter_core/db[7]} {-height 15 -radix binary} {/test_shifter_core/db[6]} {-height 15 -radix binary} {/test_shifter_core/db[5]} {-height 15 -radix binary} {/test_shifter_core/db[4]} {-height 15 -radix binary} {/test_shifter_core/db[3]} {-height 15 -radix binary} {/test_shifter_core/db[2]} {-height 15 -radix binary} {/test_shifter_core/db[1]} {-height 15 -radix binary} {/test_shifter_core/db[0]} {-height 15 -radix binary}} /test_shifter_core/db
|
||||
add wave -noupdate -color Gold -itemcolor Gold /test_shifter_core/db_out
|
||||
add wave -noupdate -color {Medium Aquamarine} -itemcolor {Medium Aquamarine} /test_shifter_core/shift_db0
|
||||
add wave -noupdate -color Cyan -itemcolor Cyan /test_shifter_core/shift_db7
|
||||
add wave -noupdate /test_shifter_core/shift_in
|
||||
add wave -noupdate /test_shifter_core/shift_left
|
||||
add wave -noupdate /test_shifter_core/shift_right
|
||||
add wave -noupdate /test_shifter_core/out_high
|
||||
add wave -noupdate /test_shifter_core/out_low
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {5100 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 143
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {9500 ns}
|
||||
@@ -0,0 +1,31 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -radix hexadecimal /test_slice/op1_sig
|
||||
add wave -noupdate -radix hexadecimal /test_slice/op2_sig
|
||||
add wave -noupdate /test_slice/cy_in_sig
|
||||
add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_slice/result_sig
|
||||
add wave -noupdate -color Gold -format Literal -itemcolor Gold /test_slice/cy_out_sig
|
||||
add wave -noupdate /test_slice/R_sig
|
||||
add wave -noupdate /test_slice/S_sig
|
||||
add wave -noupdate /test_slice/V_sig
|
||||
add wave -noupdate /test_slice/cy_out_D_sig
|
||||
add wave -noupdate /test_slice/cy_out_C_sig
|
||||
add wave -noupdate /test_slice/cy_out_B_sig
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2000 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 132
|
||||
configure wave -valuecolwidth 57
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {4100 ns}
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:01:54 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "09:01:54 October 13, 2014"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "test_alu"
|
||||
@@ -0,0 +1,66 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:01:54 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# test_alu_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C20F484C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY alu_control
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:01:54 OCTOBER 13, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name BDF_FILE alu_slice.bdf
|
||||
set_global_assignment -name BDF_FILE alu_shifter_core.bdf
|
||||
set_global_assignment -name BDF_FILE alu_select.bdf
|
||||
set_global_assignment -name BDF_FILE alu_prep_daa.bdf
|
||||
set_global_assignment -name BDF_FILE alu_mux_8.bdf
|
||||
set_global_assignment -name BDF_FILE alu_mux_4.bdf
|
||||
set_global_assignment -name BDF_FILE alu_mux_3z.bdf
|
||||
set_global_assignment -name BDF_FILE alu_mux_2z.bdf
|
||||
set_global_assignment -name BDF_FILE alu_mux_2.bdf
|
||||
set_global_assignment -name BDF_FILE alu_flags.bdf
|
||||
set_global_assignment -name BDF_FILE alu_core.bdf
|
||||
set_global_assignment -name BDF_FILE alu_control.bdf
|
||||
set_global_assignment -name BDF_FILE alu_bit_select.bdf
|
||||
set_global_assignment -name BDF_FILE alu.bdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,229 @@
|
||||
//==============================================================
|
||||
// Test complete ALU block
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_alu;
|
||||
|
||||
// ----------------- CLOCKS AND RESET -----------------
|
||||
// Define one full T-clock cycle delay
|
||||
`define T #2
|
||||
bit clk = 1;
|
||||
initial repeat (24) #1 clk = ~clk;
|
||||
|
||||
// ------------------------ BUS LOGIC ------------------------
|
||||
// Bus control
|
||||
logic alu_oe; // ALU unit output enable to the outside bus
|
||||
|
||||
// Write to the ALU internal data buses
|
||||
logic alu_op1_oe; // Enable writing by the OP1 latch
|
||||
logic alu_op2_oe; // Enable writing by the OP2 latch
|
||||
logic alu_res_oe; // Enable writing by the ALU result latch
|
||||
logic alu_shift_oe; // Enable writing by the input shifter
|
||||
logic alu_bs_oe; // Enable writing by the input bit selector
|
||||
// Our own test internal mux to select ALU bus writers
|
||||
logic [2:0] bus_sel; // Select internal bus writer:
|
||||
|
||||
typedef enum logic[2:0] {
|
||||
BUS_HIGHZ, BUS_OP1, BUS_OP2, BUS_RES, BUS_SHIFT, BUS_BS
|
||||
} bus_t;
|
||||
|
||||
// Mux to select only one block to drive internal ALU bus
|
||||
always_comb
|
||||
begin
|
||||
alu_op1_oe = 0;
|
||||
alu_op2_oe = 0;
|
||||
alu_res_oe = 0;
|
||||
alu_shift_oe = 0;
|
||||
alu_bs_oe = 0;
|
||||
case (bus_sel)
|
||||
BUS_OP1 : alu_op1_oe = 1;
|
||||
BUS_OP2 : alu_op2_oe = 1;
|
||||
BUS_RES : alu_res_oe = 1;
|
||||
BUS_SHIFT : alu_shift_oe = 1;
|
||||
BUS_BS : alu_bs_oe = 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ------------------------ INPUT ------------------------
|
||||
// Input shifter control wires and output from the shifter
|
||||
logic alu_shift_in; // Carry-in into the shifter
|
||||
logic alu_shift_right; // Shift right
|
||||
logic alu_shift_left; // Shift left
|
||||
wire alu_shift_db0; // Output db[0] from the shifter for the shift logic
|
||||
wire alu_shift_db7; // Output db[7] from the shifter for the shift logic
|
||||
|
||||
// Input bit selector control wires
|
||||
logic [2:0] bsel; // Selects a bit to generate
|
||||
|
||||
// Operator latch 1 mux select
|
||||
logic alu_op1_sel_bus; // OP1 is read from the internal bus
|
||||
logic alu_op1_sel_low; // OP1 is read from the low nibble
|
||||
logic alu_op1_sel_zero; // OP1 is loaded with zero
|
||||
|
||||
// Operator 2 latch mux select
|
||||
logic alu_op2_sel_bus; // OP2 is read from the internal bus
|
||||
logic alu_op2_sel_lq; // OP2 is read from the L-Q gates (see schematic)
|
||||
logic alu_op2_sel_zero; // OP2 is loaded with zero
|
||||
|
||||
// ALU operator mux select
|
||||
logic alu_sel_op2_neg; // Selects complemented OP2
|
||||
logic alu_sel_op2_high; // Selects high OP2 nibble as opposed to low
|
||||
|
||||
// ALU Core operations
|
||||
logic alu_core_cf_in; // Carry input into the ALU core
|
||||
logic alu_core_R; // Operation control "R"
|
||||
logic alu_core_S; // Operation control "S"
|
||||
logic alu_core_V; // Operation control "V"
|
||||
logic alu_op_low; // Signal to compute and store the low nibble (see schematic)
|
||||
wire alu_core_cf_out; // Output carry bit from the ALU core
|
||||
wire alu_vf_out; // Output overflow flag from the ALU
|
||||
|
||||
// Zero-detect, parity calculation, flag preparation and DAA-preparation logic
|
||||
logic alu_parity_in; // Input parity bit from a previous nibble
|
||||
wire alu_parity_out; // Output parity on the result and a previous nibble
|
||||
wire alu_zero; // Output signal that the result is zero
|
||||
wire alu_sf_out; // Output signal containing the result sign bit
|
||||
wire alu_yf_out; // Output signal containing the result[5] bit which is YF
|
||||
wire alu_xf_out; // Output signal containing the result[3] bit which is XF
|
||||
wire alu_low_gt_9; // Output signal that the low nibble result > 9
|
||||
wire alu_high_gt_9; // Output signal that the high nibble result > 9
|
||||
wire alu_high_eq_9; // Output signal that the high nibble result == 9
|
||||
|
||||
// ------------------------ BUSSES ------------------------
|
||||
// Bidirectional data bus, interface to the outside world
|
||||
logic [7:0] db_w; // Drive it using this bus
|
||||
wire [7:0] db; // Read it using this bus
|
||||
|
||||
wire [3:0] test_db_low; // Test point to probe internal low nibble bus
|
||||
wire [3:0] test_db_high; // Test point to probe internal high nibble bus
|
||||
|
||||
// ------------------------ FLAGS ------------------------
|
||||
reg cf; // Carry flag
|
||||
reg pf; // Parity flag
|
||||
reg hf; // Half-carry flag
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
initial begin
|
||||
// Init / reset
|
||||
db_w = 8'h00;
|
||||
bus_sel = BUS_HIGHZ;
|
||||
|
||||
alu_shift_in = 0;
|
||||
alu_shift_right = 0;
|
||||
alu_shift_left = 0;
|
||||
|
||||
bsel = 2'h0;
|
||||
|
||||
alu_op1_sel_bus = 0;
|
||||
alu_op1_sel_low = 0;
|
||||
alu_op1_sel_zero = 0;
|
||||
|
||||
alu_op2_sel_bus = 0;
|
||||
alu_op2_sel_lq = 0;
|
||||
alu_op2_sel_zero = 0;
|
||||
|
||||
alu_sel_op2_neg = 0;
|
||||
alu_sel_op2_high = 0;
|
||||
|
||||
alu_parity_in = 0;
|
||||
alu_core_cf_in = 0;
|
||||
alu_core_R = 0;
|
||||
alu_core_S = 0;
|
||||
alu_core_V = 0;
|
||||
alu_op_low = 0;
|
||||
|
||||
cf = 0;
|
||||
hf = 0;
|
||||
pf = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test loading to internal bus from the input shifter through the OP1 latch
|
||||
`T db_w = 8'h24; // High: 0010 Low: 0100
|
||||
bus_sel = BUS_SHIFT;
|
||||
alu_shift_right = 1; // Enable shift and shift *right*
|
||||
alu_shift_in = 1; // shift in <- 1
|
||||
alu_op1_sel_bus = 1; // Write into the OP1 latch
|
||||
|
||||
`T db_w = 'z;
|
||||
alu_op1_sel_bus = 0;
|
||||
alu_shift_in = 0;
|
||||
bus_sel = BUS_OP1; // Read back OP1 latch
|
||||
alu_shift_right = 0;
|
||||
// Expected output on the external ALU bus : 1001 0010, 0x92
|
||||
`T assert(db==8'h92);
|
||||
// Reset
|
||||
bus_sel = BUS_HIGHZ;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test loading to internal bus from the input bit selector through the OP2 latch
|
||||
`T db_w = 'z; // Not using external bus to load, but the bit-select
|
||||
bsel = 2'h3; // Bit 3: 0000 1000
|
||||
bus_sel = BUS_BS;
|
||||
alu_op2_sel_bus = 1; // Write into the OP2 latch
|
||||
|
||||
`T db_w = 'z;
|
||||
alu_op2_sel_bus = 0;
|
||||
alu_shift_in = 0;
|
||||
bus_sel = BUS_OP2;
|
||||
bsel = 2'h0;
|
||||
// Expected output on the external ALU bus : 0000 1000, 0x08
|
||||
`T assert(db==8'h08);
|
||||
// Reset
|
||||
`T bus_sel = BUS_HIGHZ;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test the full adding function, ADD
|
||||
`T db_w = 8'h8C; // Operand 1: 8C
|
||||
bus_sel = BUS_SHIFT; // Shifter writes to internal bus
|
||||
alu_op1_sel_bus = 1; // Write into the OP1 latch
|
||||
|
||||
`T db_w = 8'h68; // Operand 1: 68
|
||||
alu_op_low = 1; // Perform the low nibble calculation
|
||||
alu_op1_sel_bus = 0;
|
||||
bus_sel = BUS_SHIFT; // Shifter writes to internal bus
|
||||
alu_op2_sel_bus = 1; // Write into the OP2 latch
|
||||
// Do a low nibble addition in this cycle
|
||||
alu_sel_op2_high = 0; // ALU select low OP nibble
|
||||
alu_parity_in = 0; // Reset parity of the nibble
|
||||
alu_core_cf_in = 0; // CF in 0
|
||||
alu_core_R = 0;
|
||||
alu_core_S = 0;
|
||||
alu_core_V = 0;
|
||||
hf = alu_core_cf_out; // Load the HF with the half-carry out
|
||||
pf = alu_parity_out; // Load the PF with the parity of the nibble result
|
||||
|
||||
`T db_w = 'z;
|
||||
alu_op_low = 0; // Perform the high nibble calculation
|
||||
alu_op2_sel_bus = 0;
|
||||
alu_sel_op2_high = 1; // ALU select high OP2 nibble
|
||||
alu_core_cf_in = 0;
|
||||
alu_core_cf_in = hf; // Carry in the half-carry
|
||||
alu_parity_in = pf; // Parity in the parity of the low result nibble
|
||||
bus_sel = BUS_RES; // ALU result latch writes to the bus
|
||||
// Expected output on the external ALU bus : 8C + 68 = F4
|
||||
`T assert(db==8'hF4);
|
||||
// Reset
|
||||
bus_sel = BUS_HIGHZ;
|
||||
|
||||
`T $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// External bus logic
|
||||
assign db = db_w; // Drive 3-state bidirectional bus
|
||||
always_comb // Output internal ALU bus only when our
|
||||
begin // test is not driving it
|
||||
if (db_w==='z)
|
||||
alu_oe = 1;
|
||||
else
|
||||
alu_oe = 0;
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate ALU block and assign identical nets and variables
|
||||
//--------------------------------------------------------------
|
||||
|
||||
alu alu_inst( .* );
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,135 @@
|
||||
//==============================================================
|
||||
// Test ALU core
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_core;
|
||||
|
||||
// ----------------- INPUT -----------------
|
||||
reg [3:0] op1_sig; // Operand 1
|
||||
reg [3:0] op2_sig; // Operand 2
|
||||
reg cy_in_sig; // Carry in (to slice D)
|
||||
reg R_sig; // Operation control "R"
|
||||
reg S_sig; // Operation control "S"
|
||||
reg V_sig; // Operation control "V"
|
||||
|
||||
// ----------------- OUTPUT -----------------
|
||||
wire cy_out_sig; // Carry out (from slice A)
|
||||
wire vf_out_sig; // Overflow out
|
||||
wire [3:0] result_sig; // Result bits
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK(arg) \
|
||||
assert(result_sig==arg);
|
||||
|
||||
initial begin
|
||||
//------------------------------------------------------------
|
||||
// Test ADD/ADC: R=0 S=0 V=0 Cin for ADC operation
|
||||
R_sig = 0;
|
||||
S_sig = 0;
|
||||
V_sig = 0;
|
||||
op1_sig = 4'h0; // 0 + 0 + 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'h0);
|
||||
cy_in_sig = 1; // 0 + 0 + 1 = 1
|
||||
#1 `CHECK(4'h1);
|
||||
op1_sig = 4'h2; // 2 + 8 + 0 = A
|
||||
op2_sig = 4'h8;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'hA);
|
||||
cy_in_sig = 1; // 2 + 8 + 1 = B
|
||||
#1 `CHECK(4'hB);
|
||||
op1_sig = 4'hB; // B + 4 + 0 = F
|
||||
op2_sig = 4'h4;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'hF);
|
||||
cy_in_sig = 1; // B + 4 + 1 = 0 + CY
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'hD; // D + 6 + 0 = 3 + CY
|
||||
op2_sig = 4'h6;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'h3);
|
||||
cy_in_sig = 1; // D + 6 + 1 = 4 + CY
|
||||
#1 `CHECK(4'h4);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test XOR: R=1 S=0 V=0 Cin=0
|
||||
#1
|
||||
R_sig = 1;
|
||||
S_sig = 0;
|
||||
V_sig = 0;
|
||||
cy_in_sig = 0;
|
||||
op1_sig = 4'h0; // 0 ^ 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 ^ C = F
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'hF);
|
||||
op1_sig = 4'h6; // 6 ^ 3 = 5
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h5);
|
||||
op1_sig = 4'hF; // F ^ F = 0
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'h0);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test AND: R=0 S=1 V=0 Cin=1
|
||||
#1
|
||||
R_sig = 0;
|
||||
S_sig = 1;
|
||||
V_sig = 0;
|
||||
cy_in_sig = 1;
|
||||
op1_sig = 4'h0; // 0 & 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 & C = 0
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h6; // 6 & 3 = 2
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h2);
|
||||
op1_sig = 4'hF; // F & F = F
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'hF);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test OR: R=1 S=1 V=1 Cin=0
|
||||
#1
|
||||
R_sig = 1;
|
||||
S_sig = 1;
|
||||
V_sig = 1;
|
||||
cy_in_sig = 0;
|
||||
op1_sig = 4'h0; // 0 | 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 | C = F
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'hF);
|
||||
op1_sig = 4'h6; // 6 | 3 = 7
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h7);
|
||||
op1_sig = 4'hF; // F | F = F
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'hf);
|
||||
|
||||
#1 $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate ALU core block
|
||||
//--------------------------------------------------------------
|
||||
alu_core alu_core_inst
|
||||
(
|
||||
.cy_in(cy_in_sig) , // input cy_in_sig
|
||||
.op1(op1_sig[3:0]) , // input [3:0] op1_sig
|
||||
.op2(op2_sig[3:0]) , // input [3:0] op2_sig
|
||||
.S(S_sig) , // input S_sig
|
||||
.V(V_sig) , // input V_sig
|
||||
.R(R_sig) , // input R_sig
|
||||
.cy_out(cy_out_sig) , // output cy_out_sig
|
||||
.vf_out(vf_out_sig) , // output vf_out_sig
|
||||
.result(result_sig[3:0]) // output [3:0] result_sig
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,73 @@
|
||||
//==============================================================
|
||||
// Test ALU op1 MUX which is a bit more complicated
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_mux_3z;
|
||||
|
||||
// ----------------- INPUT -----------------
|
||||
reg sel_a_sig;
|
||||
reg sel_b_sig;
|
||||
reg sel_zero_sig;
|
||||
reg [3:0] a_sig;
|
||||
reg [3:0] b_sig;
|
||||
|
||||
// ----------------- OUTPUT -----------------
|
||||
wire [3:0] Q_sig; // Output of a mux
|
||||
wire ena_out_sig; // Write enable to the latch
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK(arg) \
|
||||
assert(Q_sig==arg);
|
||||
|
||||
initial begin
|
||||
sel_a_sig = 0;
|
||||
sel_b_sig = 0;
|
||||
sel_zero_sig = 0;
|
||||
a_sig = 4'hA;
|
||||
b_sig = 4'h5;
|
||||
#1 `CHECK(0);
|
||||
|
||||
sel_zero_sig = 0;
|
||||
sel_a_sig = 0;
|
||||
sel_b_sig = 0;
|
||||
#1 `CHECK(0);
|
||||
|
||||
sel_zero_sig = 1;
|
||||
sel_a_sig = 0;
|
||||
sel_b_sig = 0;
|
||||
#1 `CHECK(0);
|
||||
|
||||
sel_zero_sig = 0;
|
||||
sel_a_sig = 1;
|
||||
sel_b_sig = 0;
|
||||
#1 `CHECK(a_sig);
|
||||
|
||||
sel_zero_sig = 0;
|
||||
sel_a_sig = 0;
|
||||
sel_b_sig = 1;
|
||||
#1 `CHECK(b_sig);
|
||||
|
||||
sel_zero_sig = 1;
|
||||
sel_a_sig = 1;
|
||||
sel_b_sig = 1;
|
||||
#1 `CHECK(0);
|
||||
|
||||
#1 $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate a mux
|
||||
//--------------------------------------------------------------
|
||||
alu_mux_3z alu_mux_3z_inst
|
||||
(
|
||||
.sel_zero(sel_zero_sig) , // input sel_zero_sig
|
||||
.sel_a(sel_a_sig) , // input sel_a_sig
|
||||
.b(b_sig) , // input [3:0] b_sig
|
||||
.sel_b(sel_b_sig) , // input sel_b_sig
|
||||
.a(a_sig) , // input [3:0] a_sig
|
||||
.Q(Q_sig) , // output [3:0] Q_sig
|
||||
.ena(ena_out_sig) // output ena_out_sig
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
//==============================================================
|
||||
// Test ALU state preparation for DAA instruction
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_prep_daa;
|
||||
|
||||
// ----------------- INPUT -----------------
|
||||
reg [3:0] low_sig; // Input data bus A (independent)
|
||||
reg [3:0] high_sig; // Input data bus B (independent)
|
||||
|
||||
// ----------------- OUTPUT -----------------
|
||||
wire low_gt_9_sig; // low bus > 9
|
||||
wire high_gt_9_sig; // high bus > 9
|
||||
wire high_eq_9_sig; // high bus == 9
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK \
|
||||
assert(low_gt_9_sig==low_sig>9 && high_gt_9_sig==high_sig>9 && high_eq_9_sig==(high_sig==9));
|
||||
|
||||
initial begin
|
||||
low_sig = 4'h0;
|
||||
high_sig = 4'h0;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h1;
|
||||
high_sig = 4'h1;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h2;
|
||||
high_sig = 4'h2;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h3;
|
||||
high_sig = 4'h3;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h4;
|
||||
high_sig = 4'h4;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h5;
|
||||
high_sig = 4'h5;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h6;
|
||||
high_sig = 4'h6;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h7;
|
||||
high_sig = 4'h7;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h8;
|
||||
high_sig = 4'h8;
|
||||
#1 `CHECK
|
||||
low_sig = 4'h9;
|
||||
high_sig = 4'h9;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hA;
|
||||
high_sig = 4'hA;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hB;
|
||||
high_sig = 4'hB;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hC;
|
||||
high_sig = 4'hC;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hD;
|
||||
high_sig = 4'hD;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hE;
|
||||
high_sig = 4'hE;
|
||||
#1 `CHECK
|
||||
low_sig = 4'hF;
|
||||
high_sig = 4'hF;
|
||||
#1 `CHECK
|
||||
|
||||
#1 $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate prep-DAA block
|
||||
//--------------------------------------------------------------
|
||||
alu_prep_daa alu_prep_daa_inst
|
||||
(
|
||||
.low(low_sig) , // input [3:0] low_sig
|
||||
.high(high_sig) , // input [3:0] high_sig
|
||||
.low_gt_9(low_gt_9_sig) , // output low_gt_9_sig
|
||||
.high_eq_9(high_eq_9_sig) , // output high_eq_9_sig
|
||||
.high_gt_9(high_gt_9_sig) // output high_gt_9_sig
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,169 @@
|
||||
//==============================================================
|
||||
// Test ALU shifter core block
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_shifter_core;
|
||||
|
||||
// ----------------- INPUT -----------------
|
||||
logic [7:0] db; // Input data bus
|
||||
logic shift_in; // Input bit to be shifted in
|
||||
logic shift_left; // Input control to left-shift
|
||||
logic shift_right; // Input control to right-shift
|
||||
|
||||
// ----------------- OUTPUT -----------------
|
||||
wire shift_db0; // db[0] for shift logic
|
||||
wire shift_db7; // db[7] for shift logic
|
||||
wire [3:0] out_high; // To internal ALU bus, high nibble
|
||||
wire [3:0] out_low; // ..low nibble
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK(arg) \
|
||||
assert({out_high,out_low}==arg);
|
||||
|
||||
initial begin
|
||||
db = 8'h00;
|
||||
shift_left = 0;
|
||||
shift_right = 0;
|
||||
shift_in = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test load without shifting
|
||||
db = 8'hAA;
|
||||
#1 `CHECK(8'hAA);
|
||||
db = 8'h55;
|
||||
#1 `CHECK(8'h55);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test right shift, no carry-in
|
||||
#1 db = 8'b00000001;
|
||||
shift_right = 1;
|
||||
shift_in = 0;
|
||||
#1 `CHECK(8'b00000000);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b00000001);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b00000010);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b00000100);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b00001000);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b00010000);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b00100000);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b01000000);
|
||||
|
||||
// With carry-in
|
||||
#1 db = 8'b00000001;
|
||||
shift_in = 1;
|
||||
#1 `CHECK(8'b10000000);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b10000001);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b10000010);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b10000100);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b10001000);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b10010000);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b10100000);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b11000000);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test left shift, no carry-in
|
||||
#1 db = 8'b00000001;
|
||||
shift_right = 0;
|
||||
shift_left = 1;
|
||||
shift_in = 0;
|
||||
#1 `CHECK(8'b00000010);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b00000100);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b00001000);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b00010000);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b00100000);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b01000000);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b10000000);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b00000000);
|
||||
|
||||
// With carry-in
|
||||
#1 db = 8'b00000001;
|
||||
shift_in = 1;
|
||||
#1 `CHECK(8'b00000011);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b00000101);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b00001001);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b00010001);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b00100001);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b01000001);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b10000001);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b00000001);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test right shift, no carry-in - special SRA instruction
|
||||
// This instruction simply duplicates bit [7] instead of using CY
|
||||
#1 db = 8'b00000001;
|
||||
shift_right = 1;
|
||||
shift_left = 0;
|
||||
shift_in = shift_db7;
|
||||
#1 `CHECK(8'b10000000);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b10000001);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b10000010);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b10000100);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b10001000);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b10010000);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b10100000);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b11000000);
|
||||
|
||||
// With carry-in
|
||||
#1 db = 8'b00000001;
|
||||
shift_in = 1;
|
||||
#1 `CHECK(8'b10000000);
|
||||
db = 8'b00000010;
|
||||
#1 `CHECK(8'b10000001);
|
||||
db = 8'b00000100;
|
||||
#1 `CHECK(8'b10000010);
|
||||
db = 8'b00001000;
|
||||
#1 `CHECK(8'b10000100);
|
||||
db = 8'b00010000;
|
||||
#1 `CHECK(8'b10001000);
|
||||
db = 8'b00100000;
|
||||
#1 `CHECK(8'b10010000);
|
||||
db = 8'b01000000;
|
||||
#1 `CHECK(8'b10100000);
|
||||
db = 8'b10000000;
|
||||
#1 `CHECK(8'b11000000);
|
||||
|
||||
#1 $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate shifter core block and assign identical nets and variables
|
||||
//--------------------------------------------------------------
|
||||
|
||||
alu_shifter_core alu_shifter_core_inst( .* );
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,184 @@
|
||||
//==============================================================
|
||||
// Test ALU slice
|
||||
//==============================================================
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
module test_slice;
|
||||
|
||||
// ----------------- INPUT -----------------
|
||||
reg [3:0] op1_sig; // Operand 1
|
||||
reg [3:0] op2_sig; // Operand 2
|
||||
reg cy_in_sig; // Carry in (to slice D)
|
||||
reg R_sig; // Operation control "R"
|
||||
reg S_sig; // Operation control "S"
|
||||
reg V_sig; // Operation control "V"
|
||||
|
||||
// ----------------- OUTPUT -----------------
|
||||
wire cy_out_sig; // Carry out (from slice A)
|
||||
wire [3:0] result_sig; // Result bits
|
||||
|
||||
// ----------------- CONNECTIONS -----------------
|
||||
wire cy_out_D_sig; // Carry out from slice D into slice C
|
||||
wire cy_out_C_sig; // Carry out from slice C into slice B
|
||||
wire cy_out_B_sig; // Carry out from slice B into slice A
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK(arg) \
|
||||
assert(result_sig==arg);
|
||||
|
||||
initial begin
|
||||
op1_sig = '0;
|
||||
op2_sig = '0;
|
||||
cy_in_sig = 0;
|
||||
R_sig = 0;
|
||||
S_sig = 0;
|
||||
V_sig = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test ADD/ADC: R=0 S=0 V=0 Cin for ADC operation
|
||||
R_sig = 0;
|
||||
S_sig = 0;
|
||||
V_sig = 0;
|
||||
op1_sig = 4'h0; // 0 + 0 + 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(0);
|
||||
cy_in_sig = 1; // 0 + 0 + 1 = 1
|
||||
#1 `CHECK(1);
|
||||
op1_sig = 4'h2; // 2 + 8 + 0 = A
|
||||
op2_sig = 4'h8;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'hA);
|
||||
cy_in_sig = 1; // 2 + 8 + 1 = B
|
||||
#1 `CHECK(4'hB);
|
||||
op1_sig = 4'hB; // B + 4 + 0 = F
|
||||
op2_sig = 4'h4;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'hF);
|
||||
cy_in_sig = 1; // B + 4 + 1 = 0 + CY
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'hD; // D + 6 + 0 = 3 + CY
|
||||
op2_sig = 4'h6;
|
||||
cy_in_sig = 0;
|
||||
#1 `CHECK(4'h3);
|
||||
cy_in_sig = 1; // D + 6 + 1 = 4 + CY
|
||||
#1 `CHECK(4'h4);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test XOR: R=1 S=0 V=0 Cin=0
|
||||
#1
|
||||
R_sig = 1;
|
||||
S_sig = 0;
|
||||
V_sig = 0;
|
||||
cy_in_sig = 0;
|
||||
op1_sig = 4'h0; // 0 ^ 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 ^ C = F
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'hF);
|
||||
op1_sig = 4'h6; // 6 ^ 3 = 5
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h5);
|
||||
op1_sig = 4'hF; // F ^ F = 0
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'h0);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test AND: R=0 S=1 V=0 Cin=1
|
||||
#1
|
||||
R_sig = 0;
|
||||
S_sig = 1;
|
||||
V_sig = 0;
|
||||
cy_in_sig = 1;
|
||||
op1_sig = 4'h0; // 0 & 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 & C = 0
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h6; // 6 & 3 = 2
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h2);
|
||||
op1_sig = 4'hF; // F & F = F
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'hF);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test OR: R=1 S=1 V=1 Cin=0
|
||||
#1
|
||||
R_sig = 1;
|
||||
S_sig = 1;
|
||||
V_sig = 1;
|
||||
cy_in_sig = 0;
|
||||
op1_sig = 4'h0; // 0 | 0 = 0
|
||||
op2_sig = 4'h0;
|
||||
#1 `CHECK(4'h0);
|
||||
op1_sig = 4'h3; // 3 | C = F
|
||||
op2_sig = 4'hC;
|
||||
#1 `CHECK(4'hF);
|
||||
op1_sig = 4'h6; // 6 | 3 = 7
|
||||
op2_sig = 4'h3;
|
||||
#1 `CHECK(4'h7);
|
||||
op1_sig = 4'hF; // F | F = F
|
||||
op2_sig = 4'hF;
|
||||
#1 `CHECK(4'hF);
|
||||
|
||||
#1 $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate 4 ALU slice units, daisy-chained; MSB is slice A
|
||||
//
|
||||
// slice_A slice_B slice_C slice_D
|
||||
// cy_out <= [3] [2] [1] [0] <= cy_in
|
||||
//--------------------------------------------------------------
|
||||
alu_slice slice_A
|
||||
(
|
||||
.op1(op1_sig[3]) , // input op1_sig
|
||||
.op2(op2_sig[3]) , // input op2_sig
|
||||
.cy_in(cy_out_B_sig) , // input cy_in_sig
|
||||
.R(R_sig) , // input R_sig
|
||||
.S(S_sig) , // input S_sig
|
||||
.V(V_sig) , // input V_sig
|
||||
.cy_out(cy_out_sig) , // output cy_out_sig
|
||||
.result(result_sig[3]) // output result_sig
|
||||
);
|
||||
|
||||
alu_slice slice_B
|
||||
(
|
||||
.op1(op1_sig[2]) , // input op1_sig
|
||||
.op2(op2_sig[2]) , // input op2_sig
|
||||
.cy_in(cy_out_C_sig) , // input cy_in_sig
|
||||
.R(R_sig) , // input R_sig
|
||||
.S(S_sig) , // input S_sig
|
||||
.V(V_sig) , // input V_sig
|
||||
.cy_out(cy_out_B_sig) , // output cy_out_sig
|
||||
.result(result_sig[2]) // output result_sig
|
||||
);
|
||||
|
||||
alu_slice slice_C
|
||||
(
|
||||
.op1(op1_sig[1]) , // input op1_sig
|
||||
.op2(op2_sig[1]) , // input op2_sig
|
||||
.cy_in(cy_out_D_sig) , // input cy_in_sig
|
||||
.R(R_sig) , // input R_sig
|
||||
.S(S_sig) , // input S_sig
|
||||
.V(V_sig) , // input V_sig
|
||||
.cy_out(cy_out_C_sig) , // output cy_out_sig
|
||||
.result(result_sig[1]) // output result_sig
|
||||
);
|
||||
|
||||
alu_slice slice_D
|
||||
(
|
||||
.op1(op1_sig[0]) , // input op1_sig
|
||||
.op2(op2_sig[0]) , // input op2_sig
|
||||
.cy_in(cy_in_sig) , // input cy_in_sig
|
||||
.R(R_sig) , // input R_sig
|
||||
.S(S_sig) , // input S_sig
|
||||
.V(V_sig) , // input V_sig
|
||||
.cy_out(cy_out_D_sig) , // output cy_out_sig
|
||||
.result(result_sig[0]) // output result_sig
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user