251 lines
5.5 KiB
Verilog
251 lines
5.5 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Tue Oct 21 20:41:52 2014"
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module alu_control(
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alu_shift_db0,
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alu_shift_db7,
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ctl_shift_en,
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alu_low_gt_9,
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alu_high_gt_9,
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alu_high_eq_9,
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ctl_daa_oe,
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ctl_alu_op_low,
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alu_parity_out,
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flags_cf,
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flags_zf,
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flags_pf,
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flags_sf,
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ctl_cond_short,
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alu_vf_out,
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iff2,
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ctl_alu_core_hf,
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ctl_eval_cond,
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repeat_en,
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flags_cf_latch,
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flags_hf2,
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flags_hf,
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ctl_66_oe,
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clk,
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ctl_pf_sel,
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op543,
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alu_shift_in,
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alu_shift_right,
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alu_shift_left,
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shift_cf_out,
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alu_parity_in,
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flags_cond_true,
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daa_cf_out,
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pf_sel,
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alu_op_low,
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alu_core_cf_in,
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db
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);
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input wire alu_shift_db0;
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input wire alu_shift_db7;
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input wire ctl_shift_en;
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input wire alu_low_gt_9;
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input wire alu_high_gt_9;
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input wire alu_high_eq_9;
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input wire ctl_daa_oe;
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input wire ctl_alu_op_low;
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input wire alu_parity_out;
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input wire flags_cf;
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input wire flags_zf;
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input wire flags_pf;
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input wire flags_sf;
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input wire ctl_cond_short;
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input wire alu_vf_out;
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input wire iff2;
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input wire ctl_alu_core_hf;
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input wire ctl_eval_cond;
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input wire repeat_en;
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input wire flags_cf_latch;
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input wire flags_hf2;
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input wire flags_hf;
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input wire ctl_66_oe;
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input wire clk;
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input wire [1:0] ctl_pf_sel;
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input wire [2:0] op543;
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output wire alu_shift_in;
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output wire alu_shift_right;
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output wire alu_shift_left;
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output wire shift_cf_out;
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output wire alu_parity_in;
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output reg flags_cond_true;
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output wire daa_cf_out;
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output wire pf_sel;
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output wire alu_op_low;
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output wire alu_core_cf_in;
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output wire [7:0] db;
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wire condition;
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wire [7:0] out;
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wire [1:0] sel;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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reg DFFE_latch_pf_tmp;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_8;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_10;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_18;
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assign alu_op_low = ctl_alu_op_low;
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assign daa_cf_out = SYNTHESIZED_WIRE_21;
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assign SYNTHESIZED_WIRE_22 = 0;
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assign SYNTHESIZED_WIRE_18 = 1;
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assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1;
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assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz;
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assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz;
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assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz;
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assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz;
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assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz;
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assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz;
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assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz;
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assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz;
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assign alu_shift_right = ctl_shift_en & op543[0];
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assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp;
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assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe;
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assign sel[0] = op543[1];
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assign out[1] = SYNTHESIZED_WIRE_20;
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assign out[2] = SYNTHESIZED_WIRE_20;
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assign out[5] = SYNTHESIZED_WIRE_21;
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assign out[6] = SYNTHESIZED_WIRE_21;
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assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7;
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assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8;
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assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9;
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assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9;
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assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe;
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assign SYNTHESIZED_WIRE_0 = ~op543[0];
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assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10;
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assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0];
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assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11;
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assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
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assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf;
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assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf;
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assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf;
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always@(posedge clk)
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begin
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if (ctl_eval_cond)
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begin
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flags_cond_true <= condition;
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end
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end
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alu_mux_4 b2v_inst_cond_mux(
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.in0(flags_zf),
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.in1(flags_cf),
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.in2(flags_pf),
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.in3(flags_sf),
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.sel(sel),
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.out(SYNTHESIZED_WIRE_1));
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alu_mux_4 b2v_inst_pf_sel(
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.in0(alu_parity_out),
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.in1(alu_vf_out),
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.in2(iff2),
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.in3(repeat_en),
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.sel(ctl_pf_sel),
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.out(pf_sel));
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alu_mux_8 b2v_inst_shift_mux(
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.in0(alu_shift_db7),
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.in1(alu_shift_db0),
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.in2(flags_cf_latch),
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.in3(flags_cf_latch),
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.in4(SYNTHESIZED_WIRE_22),
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.in5(alu_shift_db7),
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.in6(SYNTHESIZED_WIRE_18),
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.in7(SYNTHESIZED_WIRE_22),
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.sel(op543),
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.out(alu_shift_in));
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always@(posedge clk)
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begin
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if (ctl_alu_op_low)
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begin
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DFFE_latch_pf_tmp <= alu_parity_out;
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end
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end
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assign SYNTHESIZED_WIRE_7 = ~op543[0];
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assign SYNTHESIZED_WIRE_11 = ~op543[0];
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assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short;
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assign out[3] = 0;
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assign out[7] = 0;
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assign out[0] = 0;
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assign out[4] = 0;
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endmodule
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