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Merge branch 'sdram'

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This commit is contained in:
Adrian Scripca
2022-04-06 14:02:22 +03:00
parent f114ff0549 9966f9a3a6
commit 1f14c8c3bd
401 changed files with 615659 additions and 422586 deletions
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output_files/greybox_tmp/cbx_args.txt
-36
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@@ -1,36 +0,0 @@
ADDRESS_REG_B=CLOCK1
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INDATA_REG_B=CLOCK1
INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_TYPE=altsyncram
NUMWORDS_A=16384
NUMWORDS_B=16384
OPERATION_MODE=BIDIR_DUAL_PORT
OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=CLOCK0
OUTDATA_REG_B=CLOCK1
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
WIDTHAD_A=14
WIDTHAD_B=14
WIDTH_A=8
WIDTH_B=8
WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK1
DEVICE_FAMILY="Cyclone IV E"
address_a
address_b
clock0
clock1
data_a
data_b
wren_a
wren_b
q_a
q_b
output_files/led_patterns.mif
-32
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@@ -1,32 +0,0 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=8;
DEPTH=8;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 129;
1 : 66;
2 : 36;
3 : 24;
4 : 36;
5 : 66;
6 : 129;
7 : 255;
END;
output_files/pll_i2s.qip
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output_files/pll_video.qip
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output_files/ram_video.qip
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output_files/rom_scr.qip
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output_files/sdram_simple.vhd
+738
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@@ -0,0 +1,738 @@
------------------------------------------------------
-- FSM for a SDRAM controller
--
-- Version 0.1 - Ready to simulate
--
-- Author: Mike Field (hamster@snap.net.nz)
--
-- Feel free to use it however you would like, but
-- just drop me an email to say thanks.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- library unisim;
-- use unisim.vcomponents.all;
entity sdram_controller2 is
generic (
HIGH_BIT: integer := 24;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 12
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture rtl of sdram_controller2 is
type reg is record
address : std_logic_vector(ADDRESS_BITS-1 downto 0);
bank : std_logic_vector( 1 downto 0);
init_counter : std_logic_vector(14 downto 0);
rf_counter : integer;
rf_pending : std_logic;
rd_pending : std_logic;
wr_pending : std_logic;
act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
act_ba : std_logic_vector(1 downto 0);
data_out_low : std_logic_vector(15 downto 0);
req_addr_q : std_logic_vector(HIGH_BIT downto 2);
req_data_write: std_logic_vector(31 downto 0);
req_mask : std_logic_vector(3 downto 0);
data_out_valid: std_logic;
dq_masks : std_logic_vector(1 downto 0);
tristate : std_logic;
end record;
signal r : reg;
signal n : reg;
signal rstate : std_logic_vector(8 downto 0);
signal nstate : std_logic_vector(8 downto 0);
signal rdata_write : std_logic_vector(15 downto 0);
signal ndata_write : std_logic_vector(15 downto 0);
-- Vectors for each SDRAM 'command'
--- CS_N, RAS_N, CAS_N, WE_N
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
-- State assignments
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
signal addr_bank: std_logic_vector(1 downto 0);
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
signal addr_col : std_logic_vector(7 downto 0);
signal captured : std_logic_vector(15 downto 0);
signal busy: std_logic;
constant tOPD: time := 2.1 ns;
constant tHZ: time := 8 ns;
signal dram_dq_dly : std_logic_vector(15 downto 0);
-- Debug only
signal debug_cmd: std_logic_vector(3 downto 0);
signal not_clock_100_delayed_3ns: std_logic;
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
attribute IOB: string;
signal i_DRAM_CS_N: std_logic;
attribute IOB of i_DRAM_CS_N: signal is "true";
signal i_DRAM_RAS_N: std_logic;
attribute IOB of i_DRAM_RAS_N: signal is "true";
signal i_DRAM_CAS_N: std_logic;
attribute IOB of i_DRAM_CAS_N: signal is "true";
signal i_DRAM_WE_N: std_logic;
attribute IOB of i_DRAM_WE_N: signal is "true";
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
attribute IOB of i_DRAM_ADDR: signal is "true";
signal i_DRAM_BA: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_BA: signal is "true";
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_DQM: signal is "true";
attribute IOB of rdata_write: signal is "true";
attribute IOB of captured: signal is "true";
signal i_DRAM_CLK: std_logic;
attribute fsm_encoding: string;
attribute fsm_encoding of nstate: signal is "user";
attribute fsm_encoding of rstate: signal is "user";
begin
debug_cmd <= rstate(3 downto 0);
-- Addressing is in 32 bit words - twice that of the DRAM width,
-- so each burst of four access two system words.
--addr_row <= address(23 downto 11);
--addr_bank <= address(10 downto 9);
process(r.req_addr_q)
begin
addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
-- (24-2) downto (24-2 - 2 - 13 - 1)
-- 22 downto 6
addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
addr_col <= (others => '0');
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
r.req_addr_q(8 downto 2) & "0";
end process;
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
clock: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "ASYNC")
port map (
D0 => '1',
D1 => '0',
Q => i_DRAM_CLK,
C0 => clock_100_delayed_3ns,
C1 => not_clock_100_delayed_3ns,
CE => '1',
R => '0',
S => '0'
);
DRAM_CKE <= '1';
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
i_DRAM_CS_N <= transport rstate(3) after tOPD;
DRAM_CS_N <= i_DRAM_CS_N;
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
DRAM_RAS_N <= i_DRAM_RAS_N;
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
DRAM_CAS_N <= i_DRAM_CAS_N;
i_DRAM_WE_N <= transport rstate(0) after tOPD;
DRAM_WE_N <= i_DRAM_WE_N;
i_DRAM_ADDR <= transport r.address after tOPD;
DRAM_ADDR <= i_DRAM_ADDR;
i_DRAM_BA <= transport r.bank after tOPD;
DRAM_BA <= i_DRAM_BA;
i_DRAM_DQM <= transport r.dq_masks after tOPD;
DRAM_DQM <= i_DRAM_DQM;
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
data_out_valid <= r.data_out_valid;
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
begin
-- copy the existing values
n <= r;
nstate <= rstate;
ndata_write <= rdata_write;
if req_read = '1' then
n.rd_pending <= '1';
if r.rd_pending='0' then
n.req_addr_q <= address;
end if;
end if;
if req_write = '1' then
n.wr_pending <= '1';
if r.wr_pending='0' then
n.req_addr_q <= address;
-- Queue data here
n.req_data_write <= data_in;
n.req_mask <= data_mask;
end if;
end if;
n.dq_masks <= "11";
-- first off, do we need to perform a refresh cycle ASAP?
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
n.rf_counter <= 0;
n.rf_pending <= '1';
else
-- only start looking for refreshes outside of the initialisation state.
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
n.rf_counter <= r.rf_counter + 1;
end if;
end if;
-- Set the data bus into HIZ, high and low bytes masked
--DRAM_DQ <= (others => 'Z');
n.tristate <= '0';
n.init_counter <= r.init_counter-1;
--ndata_write <= (others => DontCareValue);
n.data_out_valid <= '0'; -- alvie- here, no ?
-- Process the FSM
case rstate(8 downto 4) is
when s_init_nop_id => --s_init_nop(8 downto 4) =>
nstate <= s_init_nop;
n.address <= (others => '0');
n.bank <= (others => '0');
n.act_ba <= (others => '0');
n.rf_counter <= 0;
-- n.data_out_valid <= '1'; -- alvie- not here
-- T-130, precharge all banks.
if r.init_counter = "000000010000010" then
nstate <= s_init_pre;
n.address(10) <= '1';
end if;
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
nstate <= s_init_ref;
end if;
-- T-3, the load mode register
if r.init_counter = 3 then
nstate <= s_init_mrs;
-- Mode register is as follows:
-- resvd wr_b OpMd CAS=3 Seq bust=1
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
-- resvd
n.bank <= "00";
end if;
-- T-1 The switch to the FSM (first command will be a NOP
if r.init_counter = 1 then
nstate <= s_idle;
end if;
------------------------------
-- The Idle section
------------------------------
when s_idle_id =>
nstate <= s_idle;
-- do we have to activate a row?
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
-- refreshes take priority over everything
if r.rf_pending = '1' then
nstate <= s_rf0;
n.rf_pending <= '0';
end if;
------------------------------
-- Row activation
-- s_ra2 is also the "idle with active row" state and provides
-- a resting point between operations on the same row
------------------------------
when s_ra0_id =>
nstate <= s_ra1;
when s_ra1_id =>
nstate <= s_ra2;
when s_ra2_id=>
-- we can stay in this state until we have something to do
nstate <= s_ra2;
n.tristate<='0';
if r.rf_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
else
-- If there is a read pending, deactivate the row
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
end if;
-- unless we have a read to perform on the same row? do that instead
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_rd0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks <= "00";
n.rd_pending <= '0';
--n.tristate<='1';
end if;
-- unless we have a write on the same row? writes take priroty over reads
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_wr0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
ndata_write <= r.req_data_write(31 downto 16);
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= not r.req_mask(3 downto 2);
n.wr_pending <= '0';
--n.tristate <= '0';
end if;
end if;
-- nstate <= s_dr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending;
-- n.wr_pending <= r.wr_pending;
--n.tristate <= '0';
--end if;
------------------------------------------------------
-- Deactivate the current row and return to idle state
------------------------------------------------------
when s_dr0_id =>
nstate <= s_dr1;
when s_dr1_id =>
nstate <= s_idle;
------------------------------
-- The Refresh section
------------------------------
when s_rf0_id =>
nstate <= s_rf1;
when s_rf1_id =>
nstate <= s_rf2;
when s_rf2_id =>
nstate <= s_rf3;
when s_rf3_id =>
nstate <= s_rf4;
when s_rf4_id =>
nstate <= s_rf5;
when s_rf5_id =>
nstate <= s_idle;
------------------------------
-- The Write section
------------------------------
when s_wr0_id =>
nstate <= s_wr3;
n.bank <= addr_bank;
n.address(0) <= '1';
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
--DRAM_DQ <= rdata_write;
n.dq_masks<= not r.req_mask(1 downto 0);
n.tristate <= '0';
when s_wr1_id => null;
when s_wr2_id =>
nstate <= s_dr0;
n.address(10) <= '1';
when s_wr3_id =>
-- Default to the idle+row active state
nstate <= s_ra2;
--DRAM_DQ <= rdata_write;
n.data_out_valid<='1'; -- alvie- ack write
n.tristate <= '0';
n.dq_masks<= "11";
-- If there is a read or write then deactivate the row
--if r.rd_pending = '1' or r.wr_pending = '1' then
-- nstate <= s_dr0;
-- n.address(10) <= '1';
--end if;
-- But if there is a read pending in the same row, do that
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_rd0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
-- --n.act_ba <= addr_bank;
-- n.dq_masks <= "00";
-- n.rd_pending <= '0';
--end if;
-- unless there is a write pending in the same row, do that
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_wr0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
--n.act_ba <= addr_bank;
-- n.dq_masks<= "00";
-- n.wr_pending <= '0';
--end if;
-- But always try and refresh if one is pending!
if r.rf_pending = '1' then
nstate <= s_wr2; --dr0;
--n.address(10) <= '1';
end if;
------------------------------
-- The Read section
------------------------------
when s_rd0_id => -- 10001
nstate <= s_rd1;
n.tristate<='1';
n.dq_masks <= "00";
n.address(0)<='1';
when s_rd1_id => -- 10010
nstate <= s_rd2;
n.dq_masks <= "00";
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd3; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
end if;
when s_rd2_id => -- 10011
nstate <= s_rd7;
n.dq_masks <= "00";
n.tristate<='1';
when s_rd3_id => -- 10100
nstate <= s_rd4;
n.dq_masks <= "00";
n.address(0) <= '1';
n.tristate<='1';
-- Data is still not ready...
when s_rd4_id => -- 10101
nstate <= s_rd5;
n.dq_masks <= "00";
--n.address(0)<='1';
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd5; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
else
nstate <= s_rd6; -- NOTE: not correct
end if;
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending; -- Keep request
--end if;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_rd5_id =>
-- If a refresh is pending then always deactivate the row
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
--end if;
n.address(0) <= '1';
nstate <= s_rd4; -- Another request came, and we can pipeline -
n.dq_masks <= "00";
n.tristate<='1';
when s_rd6_id =>
nstate <= s_rd7;
n.dq_masks<= "00";
n.tristate<='1';
when s_rd7_id =>
nstate <= s_ra2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
n.tristate<='1';
when s_rd8_id => null;
when s_rd9_id => null;
-- The Deactivate row during read section
------------------------------
when s_drdr0_id =>
nstate <= s_drdr1;
when s_drdr1_id =>
nstate <= s_drdr2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_drdr2_id =>
nstate <= s_idle;
if r.rf_pending = '1' then
nstate <= s_rf0;
end if;
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
when others =>
nstate <= s_init_nop;
end case;
end process;
--- The clock driven logic
process (clock_100, n)
begin
if clock_100'event and clock_100 = '1' then
if rst='1' then
rstate <= (others => '0');
r.address <= (others => '0');
r.bank <= (others => '0');
r.init_counter <= "100000000000000";
-- synopsys translate_off
r.init_counter <= "000000100000000";
-- synopsys translate_on
r.rf_counter <= 0;
r.rf_pending <= '0';
r.rd_pending <= '0';
r.wr_pending <= '0';
r.act_row <= (others => '0');
r.data_out_low <= (others => '0');
r.data_out_valid <= '0';
r.dq_masks <= "11";
r.tristate<='1';
else
r <= n;
rstate <= nstate;
rdata_write <= ndata_write;
end if;
end if;
end process;
dram_dq_dly <= transport dram_dq after 1.9 ns;
-- process (clock_100_delayed_3ns, dram_dq_dly)
-- begin
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
-- captured <= dram_dq_dly;
-- end if;
-- end process;
process (clock_100)
begin
if falling_edge(clock_100) then
captured <= dram_dq_dly;
end if;
end process;
end rtl;
output_files/sdram_simple.vhd.bak
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------------------------------------------------------
-- FSM for a SDRAM controller
--
-- Version 0.1 - Ready to simulate
--
-- Author: Mike Field (hamster@snap.net.nz)
--
-- Feel free to use it however you would like, but
-- just drop me an email to say thanks.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_controller is
generic (
HIGH_BIT: integer := 24;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 12
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture rtl of sdram_controller is
type reg is record
address : std_logic_vector(ADDRESS_BITS-1 downto 0);
bank : std_logic_vector( 1 downto 0);
init_counter : std_logic_vector(14 downto 0);
rf_counter : integer;
rf_pending : std_logic;
rd_pending : std_logic;
wr_pending : std_logic;
act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
act_ba : std_logic_vector(1 downto 0);
data_out_low : std_logic_vector(15 downto 0);
req_addr_q : std_logic_vector(HIGH_BIT downto 2);
req_data_write: std_logic_vector(31 downto 0);
req_mask : std_logic_vector(3 downto 0);
data_out_valid: std_logic;
dq_masks : std_logic_vector(1 downto 0);
tristate : std_logic;
end record;
signal r : reg;
signal n : reg;
signal rstate : std_logic_vector(8 downto 0);
signal nstate : std_logic_vector(8 downto 0);
signal rdata_write : std_logic_vector(15 downto 0);
signal ndata_write : std_logic_vector(15 downto 0);
-- Vectors for each SDRAM 'command'
--- CS_N, RAS_N, CAS_N, WE_N
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
-- State assignments
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
signal addr_bank: std_logic_vector(1 downto 0);
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
signal addr_col : std_logic_vector(7 downto 0);
signal captured : std_logic_vector(15 downto 0);
signal busy: std_logic;
constant tOPD: time := 2.1 ns;
constant tHZ: time := 8 ns;
signal dram_dq_dly : std_logic_vector(15 downto 0);
-- Debug only
signal debug_cmd: std_logic_vector(3 downto 0);
signal not_clock_100_delayed_3ns: std_logic;
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
attribute IOB: string;
signal i_DRAM_CS_N: std_logic;
attribute IOB of i_DRAM_CS_N: signal is "true";
signal i_DRAM_RAS_N: std_logic;
attribute IOB of i_DRAM_RAS_N: signal is "true";
signal i_DRAM_CAS_N: std_logic;
attribute IOB of i_DRAM_CAS_N: signal is "true";
signal i_DRAM_WE_N: std_logic;
attribute IOB of i_DRAM_WE_N: signal is "true";
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
attribute IOB of i_DRAM_ADDR: signal is "true";
signal i_DRAM_BA: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_BA: signal is "true";
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_DQM: signal is "true";
attribute IOB of rdata_write: signal is "true";
attribute IOB of captured: signal is "true";
signal i_DRAM_CLK: std_logic;
attribute fsm_encoding: string;
attribute fsm_encoding of nstate: signal is "user";
attribute fsm_encoding of rstate: signal is "user";
begin
debug_cmd <= rstate(3 downto 0);
-- Addressing is in 32 bit words - twice that of the DRAM width,
-- so each burst of four access two system words.
--addr_row <= address(23 downto 11);
--addr_bank <= address(10 downto 9);
process(r.req_addr_q)
begin
addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
-- (24-2) downto (24-2 - 2 - 13 - 1)
-- 22 downto 6
addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
addr_col <= (others => '0');
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
r.req_addr_q(8 downto 2) & "0";
end process;
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
clock: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "ASYNC")
port map (
D0 => '1',
D1 => '0',
Q => i_DRAM_CLK,
C0 => clock_100_delayed_3ns,
C1 => not_clock_100_delayed_3ns,
CE => '1',
R => '0',
S => '0'
);
DRAM_CKE <= '1';
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
i_DRAM_CS_N <= transport rstate(3) after tOPD;
DRAM_CS_N <= i_DRAM_CS_N;
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
DRAM_RAS_N <= i_DRAM_RAS_N;
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
DRAM_CAS_N <= i_DRAM_CAS_N;
i_DRAM_WE_N <= transport rstate(0) after tOPD;
DRAM_WE_N <= i_DRAM_WE_N;
i_DRAM_ADDR <= transport r.address after tOPD;
DRAM_ADDR <= i_DRAM_ADDR;
i_DRAM_BA <= transport r.bank after tOPD;
DRAM_BA <= i_DRAM_BA;
i_DRAM_DQM <= transport r.dq_masks after tOPD;
DRAM_DQM <= i_DRAM_DQM;
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
data_out_valid <= r.data_out_valid;
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
begin
-- copy the existing values
n <= r;
nstate <= rstate;
ndata_write <= rdata_write;
if req_read = '1' then
n.rd_pending <= '1';
if r.rd_pending='0' then
n.req_addr_q <= address;
end if;
end if;
if req_write = '1' then
n.wr_pending <= '1';
if r.wr_pending='0' then
n.req_addr_q <= address;
-- Queue data here
n.req_data_write <= data_in;
n.req_mask <= data_mask;
end if;
end if;
n.dq_masks <= "11";
-- first off, do we need to perform a refresh cycle ASAP?
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
n.rf_counter <= 0;
n.rf_pending <= '1';
else
-- only start looking for refreshes outside of the initialisation state.
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
n.rf_counter <= r.rf_counter + 1;
end if;
end if;
-- Set the data bus into HIZ, high and low bytes masked
--DRAM_DQ <= (others => 'Z');
n.tristate <= '0';
n.init_counter <= r.init_counter-1;
--ndata_write <= (others => DontCareValue);
n.data_out_valid <= '0'; -- alvie- here, no ?
-- Process the FSM
case rstate(8 downto 4) is
when s_init_nop_id => --s_init_nop(8 downto 4) =>
nstate <= s_init_nop;
n.address <= (others => '0');
n.bank <= (others => '0');
n.act_ba <= (others => '0');
n.rf_counter <= 0;
-- n.data_out_valid <= '1'; -- alvie- not here
-- T-130, precharge all banks.
if r.init_counter = "000000010000010" then
nstate <= s_init_pre;
n.address(10) <= '1';
end if;
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
nstate <= s_init_ref;
end if;
-- T-3, the load mode register
if r.init_counter = 3 then
nstate <= s_init_mrs;
-- Mode register is as follows:
-- resvd wr_b OpMd CAS=3 Seq bust=1
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
-- resvd
n.bank <= "00";
end if;
-- T-1 The switch to the FSM (first command will be a NOP
if r.init_counter = 1 then
nstate <= s_idle;
end if;
------------------------------
-- The Idle section
------------------------------
when s_idle_id =>
nstate <= s_idle;
-- do we have to activate a row?
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
-- refreshes take priority over everything
if r.rf_pending = '1' then
nstate <= s_rf0;
n.rf_pending <= '0';
end if;
------------------------------
-- Row activation
-- s_ra2 is also the "idle with active row" state and provides
-- a resting point between operations on the same row
------------------------------
when s_ra0_id =>
nstate <= s_ra1;
when s_ra1_id =>
nstate <= s_ra2;
when s_ra2_id=>
-- we can stay in this state until we have something to do
nstate <= s_ra2;
n.tristate<='0';
if r.rf_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
else
-- If there is a read pending, deactivate the row
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
end if;
-- unless we have a read to perform on the same row? do that instead
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_rd0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks <= "00";
n.rd_pending <= '0';
--n.tristate<='1';
end if;
-- unless we have a write on the same row? writes take priroty over reads
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_wr0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
ndata_write <= r.req_data_write(31 downto 16);
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= not r.req_mask(3 downto 2);
n.wr_pending <= '0';
--n.tristate <= '0';
end if;
end if;
-- nstate <= s_dr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending;
-- n.wr_pending <= r.wr_pending;
--n.tristate <= '0';
--end if;
------------------------------------------------------
-- Deactivate the current row and return to idle state
------------------------------------------------------
when s_dr0_id =>
nstate <= s_dr1;
when s_dr1_id =>
nstate <= s_idle;
------------------------------
-- The Refresh section
------------------------------
when s_rf0_id =>
nstate <= s_rf1;
when s_rf1_id =>
nstate <= s_rf2;
when s_rf2_id =>
nstate <= s_rf3;
when s_rf3_id =>
nstate <= s_rf4;
when s_rf4_id =>
nstate <= s_rf5;
when s_rf5_id =>
nstate <= s_idle;
------------------------------
-- The Write section
------------------------------
when s_wr0_id =>
nstate <= s_wr3;
n.bank <= addr_bank;
n.address(0) <= '1';
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
--DRAM_DQ <= rdata_write;
n.dq_masks<= not r.req_mask(1 downto 0);
n.tristate <= '0';
when s_wr1_id => null;
when s_wr2_id =>
nstate <= s_dr0;
n.address(10) <= '1';
when s_wr3_id =>
-- Default to the idle+row active state
nstate <= s_ra2;
--DRAM_DQ <= rdata_write;
n.data_out_valid<='1'; -- alvie- ack write
n.tristate <= '0';
n.dq_masks<= "11";
-- If there is a read or write then deactivate the row
--if r.rd_pending = '1' or r.wr_pending = '1' then
-- nstate <= s_dr0;
-- n.address(10) <= '1';
--end if;
-- But if there is a read pending in the same row, do that
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_rd0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
-- --n.act_ba <= addr_bank;
-- n.dq_masks <= "00";
-- n.rd_pending <= '0';
--end if;
-- unless there is a write pending in the same row, do that
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_wr0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
--n.act_ba <= addr_bank;
-- n.dq_masks<= "00";
-- n.wr_pending <= '0';
--end if;
-- But always try and refresh if one is pending!
if r.rf_pending = '1' then
nstate <= s_wr2; --dr0;
--n.address(10) <= '1';
end if;
------------------------------
-- The Read section
------------------------------
when s_rd0_id => -- 10001
nstate <= s_rd1;
n.tristate<='1';
n.dq_masks <= "00";
n.address(0)<='1';
when s_rd1_id => -- 10010
nstate <= s_rd2;
n.dq_masks <= "00";
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd3; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
end if;
when s_rd2_id => -- 10011
nstate <= s_rd7;
n.dq_masks <= "00";
n.tristate<='1';
when s_rd3_id => -- 10100
nstate <= s_rd4;
n.dq_masks <= "00";
n.address(0) <= '1';
n.tristate<='1';
-- Data is still not ready...
when s_rd4_id => -- 10101
nstate <= s_rd5;
n.dq_masks <= "00";
--n.address(0)<='1';
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd5; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
else
nstate <= s_rd6; -- NOTE: not correct
end if;
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending; -- Keep request
--end if;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_rd5_id =>
-- If a refresh is pending then always deactivate the row
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
--end if;
n.address(0) <= '1';
nstate <= s_rd4; -- Another request came, and we can pipeline -
n.dq_masks <= "00";
n.tristate<='1';
when s_rd6_id =>
nstate <= s_rd7;
n.dq_masks<= "00";
n.tristate<='1';
when s_rd7_id =>
nstate <= s_ra2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
n.tristate<='1';
when s_rd8_id => null;
when s_rd9_id => null;
-- The Deactivate row during read section
------------------------------
when s_drdr0_id =>
nstate <= s_drdr1;
when s_drdr1_id =>
nstate <= s_drdr2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_drdr2_id =>
nstate <= s_idle;
if r.rf_pending = '1' then
nstate <= s_rf0;
end if;
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
when others =>
nstate <= s_init_nop;
end case;
end process;
--- The clock driven logic
process (clock_100, n)
begin
if clock_100'event and clock_100 = '1' then
if rst='1' then
rstate <= (others => '0');
r.address <= (others => '0');
r.bank <= (others => '0');
r.init_counter <= "100000000000000";
-- synopsys translate_off
r.init_counter <= "000000100000000";
-- synopsys translate_on
r.rf_counter <= 0;
r.rf_pending <= '0';
r.rd_pending <= '0';
r.wr_pending <= '0';
r.act_row <= (others => '0');
r.data_out_low <= (others => '0');
r.data_out_valid <= '0';
r.dq_masks <= "11";
r.tristate<='1';
else
r <= n;
rstate <= nstate;
rdata_write <= ndata_write;
end if;
end if;
end process;
dram_dq_dly <= transport dram_dq after 1.9 ns;
-- process (clock_100_delayed_3ns, dram_dq_dly)
-- begin
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
-- captured <= dram_dq_dly;
-- end if;
-- end process;
process (clock_100)
begin
if falling_edge(clock_100) then
captured <= dram_dq_dly;
end if;
end process;
end rtl;
output_files/spectrum.asm.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
Assembler report for spectrum
Sat Apr 2 15:53:36 2022
Wed Apr 6 13:58:19 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Apr 2 15:53:36 2022 ;
; Assembler Status ; Successful - Wed Apr 6 13:58:19 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ;
+----------------+-----------------------+
; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x0056105B ;
; Checksum ; 0x0056105B ;
; JTAG usercode ; 0x0059A13C ;
; Checksum ; 0x0059A13C ;
+----------------+-----------------------+
@@ -173,13 +173,13 @@ Default Value : On
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sat Apr 2 15:53:34 2022
Info: Processing started: Wed Apr 6 13:58:17 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 385 megabytes
Info: Processing ended: Sat Apr 2 15:53:36 2022
Info: Peak virtual memory: 387 megabytes
Info: Processing ended: Wed Apr 6 13:58:19 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.done
+1 -1
View File
@@ -1 +1 @@
Sat Apr 2 15:53:46 2022
Wed Apr 6 13:58:30 2022
output_files/spectrum.eda.rpt
+5 -5
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum
Sat Apr 2 15:53:46 2022
Wed Apr 6 13:58:30 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sat Apr 2 15:53:46 2022 ;
; EDA Netlist Writer Status ; Successful - Wed Apr 6 13:58:30 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sat Apr 2 15:53:43 2022
Info: Processing started: Wed Apr 6 13:58:26 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
@@ -100,8 +100,8 @@ Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 380 megabytes
Info: Processing ended: Sat Apr 2 15:53:46 2022
Info: Elapsed time: 00:00:03
Info: Processing ended: Wed Apr 6 13:58:30 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
output_files/spectrum.fit.rpt
+10824 -7612
View File
File diff suppressed because it is too large Load Diff
output_files/spectrum.fit.summary
+7 -7
View File
@@ -1,16 +1,16 @@
Fitter Status : Successful - Sat Apr 2 15:53:32 2022
Fitter Status : Successful - Wed Apr 6 13:58:15 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Device : EP4CE22F17C6
Timing Models : Final
Total logic elements : 2,376 / 22,320 ( 11 % )
Total combinational functions : 2,258 / 22,320 ( 10 % )
Dedicated logic registers : 591 / 22,320 ( 3 % )
Total registers : 600
Total pins : 75 / 154 ( 49 % )
Total logic elements : 2,743 / 22,320 ( 12 % )
Total combinational functions : 2,624 / 22,320 ( 12 % )
Dedicated logic registers : 700 / 22,320 ( 3 % )
Total registers : 729
Total pins : 120 / 154 ( 78 % )
Total virtual pins : 0
Total memory bits : 524,288 / 608,256 ( 86 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )
Total PLLs : 2 / 4 ( 50 % )
output_files/spectrum.flow.rpt
+101 -23
View File
@@ -1,5 +1,5 @@
Flow report for spectrum
Sat Apr 2 15:53:46 2022
Wed Apr 6 13:58:30 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,22 +40,22 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Sat Apr 2 15:53:46 2022 ;
; Flow Status ; Successful - Wed Apr 6 13:58:30 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Total logic elements ; 2,376 / 22,320 ( 11 % ) ;
; Total combinational functions ; 2,258 / 22,320 ( 10 % ) ;
; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ;
; Total registers ; 600 ;
; Total pins ; 75 / 154 ( 49 % ) ;
; Total logic elements ; 2,743 / 22,320 ( 12 % ) ;
; Total combinational functions ; 2,624 / 22,320 ( 12 % ) ;
; Dedicated logic registers ; 700 / 22,320 ( 3 % ) ;
; Total registers ; 729 ;
; Total pins ; 120 / 154 ( 78 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 524,288 / 608,256 ( 86 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
; Total PLLs ; 2 / 4 ( 50 % ) ;
+------------------------------------+--------------------------------------------+
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/02/2022 15:52:58 ;
; Start date & time ; 04/06/2022 13:57:37 ;
; Main task ; Compilation ;
; Revision Name ; spectrum ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164890397819294
Value : 0.164924265739740
Default Value : --
Entity Name : --
Section Id : --
@@ -91,6 +91,18 @@ Default Value : <None>
Entity Name : --
Section Id : --
Assignment Name : ENABLE_LOGIC_ANALYZER_INTERFACE
Value : Off
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : ENABLE_SIGNALTAP
Value : Off
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_NAME
Value : ROM: 1-PORT
Default Value : --
@@ -133,6 +145,18 @@ Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_NAME
Value : ALTPLL
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_NAME
Value : ALTPLL
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
@@ -175,6 +199,18 @@ Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MAX_CORE_JUNCTION_TEMP
Value : 85
Default Value : --
@@ -241,6 +277,30 @@ Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MISC_FILE
Value : sdram_clk_gen_bb.v
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MISC_FILE
Value : sdram_clk_gen.ppf
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MISC_FILE
Value : pll_sdram_bb.v
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MISC_FILE
Value : pll_sdram.ppf
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
Value : 1.2V
Default Value : --
@@ -265,11 +325,29 @@ Default Value : --
Entity Name : --
Section Id : Top
Assignment Name : POWER_BOARD_THERMAL_MODEL
Value : None (CONSERVATIVE)
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : POWER_PRESET_COOLING_SOLUTION
Value : 23 MM HEAT SINK WITH 200 LFPM AIRFLOW
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : PROJECT_OUTPUT_DIRECTORY
Value : output_files
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : USE_SIGNALTAP_FILE
Value : output_files/stp1.stp
Default Value : --
Entity Name : --
Section Id : --
+--------------------------------------------------------------------------------+
@@ -278,40 +356,40 @@ Section Id : --
; Flow Elapsed Time ;
+--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis
Elapsed Time : 00:00:12
Elapsed Time : 00:00:15
Average Processors Used : 1.0
Peak Virtual Memory : 441 MB
Total CPU Time (on all processors) : 00:00:12
Peak Virtual Memory : 446 MB
Total CPU Time (on all processors) : 00:00:14
Module Name : Fitter
Elapsed Time : 00:00:21
Elapsed Time : 00:00:23
Average Processors Used : 1.0
Peak Virtual Memory : 634 MB
Total CPU Time (on all processors) : 00:00:21
Peak Virtual Memory : 645 MB
Total CPU Time (on all processors) : 00:00:23
Module Name : Assembler
Elapsed Time : 00:00:02
Average Processors Used : 1.0
Peak Virtual Memory : 385 MB
Peak Virtual Memory : 387 MB
Total CPU Time (on all processors) : 00:00:02
Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:04
Average Processors Used : 1.0
Peak Virtual Memory : 440 MB
Total CPU Time (on all processors) : 00:00:03
Peak Virtual Memory : 441 MB
Total CPU Time (on all processors) : 00:00:04
Module Name : EDA Netlist Writer
Elapsed Time : 00:00:03
Elapsed Time : 00:00:04
Average Processors Used : 1.0
Peak Virtual Memory : 372 MB
Peak Virtual Memory : 368 MB
Total CPU Time (on all processors) : 00:00:03
Module Name : Total
Elapsed Time : 00:00:42
Elapsed Time : 00:00:48
Average Processors Used : --
Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:41
Total CPU Time (on all processors) : 00:00:46
+--------------------------------------------------------------------------------+
output_files/spectrum.jdi
+1 -1
View File
@@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="4f424ba9a0f5c16836a4"/>
<hash md5_digest_80b="52d41130cb1428434bde"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+1918 -158
View File
File diff suppressed because it is too large Load Diff
output_files/spectrum.map.smsg
+1
View File
@@ -1,2 +1,3 @@
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(19): object "nRESET" differs only in case from object "nreset" in the same scope
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(22): object "CLK" differs only in case from object "clk" in the same scope
Warning (10273): Verilog HDL warning at sdram_controller.v(166): extended using "x" or "z"
output_files/spectrum.map.summary
+7 -7
View File
@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Sat Apr 2 15:53:10 2022
Analysis & Synthesis Status : Successful - Wed Apr 6 13:57:51 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Total logic elements : 2,523
Total combinational functions : 2,255
Dedicated logic registers : 592
Total registers : 592
Total pins : 75
Total logic elements : 2,885
Total combinational functions : 2,614
Dedicated logic registers : 714
Total registers : 714
Total pins : 120
Total virtual pins : 0
Total memory bits : 524,288
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1
Total PLLs : 2
output_files/spectrum.pin
+47 -47
View File
@@ -71,8 +71,8 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
VCCIO8 : A1 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
kempston[1] : A4 : input : 3.3-V LVTTL : : 8 : Y
kempston[3] : A5 : input : 3.3-V LVTTL : : 8 : Y
buzzer_out : A6 : output : 3.3-V LVTTL : : 8 : Y
AUD_XCK : A7 : output : 3.3-V LVTTL : : 8 : Y
GND+ : A8 : : : : 8 :
@@ -86,9 +86,9 @@ LED[0] : A15 : output : 3.3-V LVTTL :
VCCIO7 : A16 : power : : 3.3V : 7 :
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
GND : B2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
kempston_gnd : B3 : output : 3.3-V LVTTL : : 8 : Y
kempston[0] : B4 : input : 3.3-V LVTTL : : 8 : Y
kempston[2] : B5 : input : 3.3-V LVTTL : : 8 : Y
raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y
PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y
GND+ : B8 : : : : 8 :
@@ -101,7 +101,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : :
GND : B15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
DRAM_WE_N : C2 : output : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
VCCIO8 : C4 : power : : 3.3V : 8 :
GND : C5 : gnd : : : :
@@ -120,7 +120,7 @@ LED[4] : D1 : output : 3.3-V LVTTL :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
VCCD_PLL3 : D4 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
kempston[4] : D5 : input : 3.3-V LVTTL : : 8 : Y
PS2_CLK : D6 : input : 3.3-V LVTTL : : 8 : Y
GND : D7 : gnd : : : :
AUD_ADCDAT : D8 : input : 3.3-V LVTTL : : 8 : Y
@@ -164,8 +164,8 @@ GPIO_1[0] : F13 : output : 3.3-V LVTTL :
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 :
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 3.3-V LVTTL : : 6 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
DRAM_DQ[1] : G1 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_DQ[0] : G2 : bidir : 3.3-V LVTTL : : 1 : Y
VCCIO1 : G3 : power : : 3.3V : 1 :
GND : G4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
@@ -196,8 +196,8 @@ MSEL0 : H13 : : :
CONF_DONE : H14 : : : : 6 :
GND : H15 : gnd : : : :
GND : H16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 :
DRAM_DQ[6] : J1 : bidir : 3.3-V LVTTL : : 2 : Y
DRAM_DQ[5] : J2 : bidir : 3.3-V LVTTL : : 2 : Y
nCE : J3 : : : : 1 :
TDO : J4 : output : : : 1 :
TMS : J5 : input : : : 1 :
@@ -208,15 +208,15 @@ GND : J9 : gnd : :
GND : J10 : gnd : : : :
GND : J11 : gnd : : : :
VCCINT : J12 : power : : 1.2V : :
GPIO_1[32] : J13 : output : 3.3-V LVTTL : : 5 : Y
GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y
turbo_button : J13 : input : 3.3-V LVTTL : : 5 : Y
kempston_autofire_button : J14 : input : 3.3-V LVTTL : : 5 : Y
KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y
GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 :
DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y
DRAM_DQ[4] : K2 : bidir : 3.3-V LVTTL : : 2 : Y
VCCIO2 : K3 : power : : 3.3V : 2 :
GND : K4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
DRAM_DQ[3] : K5 : bidir : 3.3-V LVTTL : : 2 : Y
GND : K6 : gnd : : : :
VCCINT : K7 : power : : 1.2V : :
GND : K8 : gnd : : : :
@@ -228,14 +228,14 @@ GND : K13 : gnd : :
VCCIO5 : K14 : power : : 3.3V : 5 :
GPIO_1[31] : K15 : output : 3.3-V LVTTL : : 5 : Y
GPIO_1[17] : K16 : output : 3.3-V LVTTL : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 :
DRAM_CAS_N : L1 : output : 3.3-V LVTTL : : 2 : Y
DRAM_RAS_N : L2 : output : 3.3-V LVTTL : : 2 : Y
LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 :
DRAM_ADDR[12] : L4 : output : 3.3-V LVTTL : : 2 : Y
VCCA1 : L5 : power : : 2.5V : :
VCCINT : L6 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 :
DRAM_CKE : L7 : output : 3.3-V LVTTL : : 3 : Y
DRAM_DQ[2] : L8 : bidir : 3.3-V LVTTL : : 3 : Y
GND : L9 : gnd : : : :
GND : L10 : gnd : : : :
GND : L11 : gnd : : : :
@@ -249,9 +249,9 @@ GND+ : M2 : : :
VCCIO2 : M3 : power : : 3.3V : 2 :
GND : M4 : gnd : : : :
GNDA1 : M5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 :
DRAM_BA[1] : M6 : output : 3.3-V LVTTL : : 3 : Y
DRAM_BA[0] : M7 : output : 3.3-V LVTTL : : 3 : Y
DRAM_ADDR[3] : M8 : output : 3.3-V LVTTL : : 3 : Y
VCCINT : M9 : power : : 1.2V : :
GPIO_1[28] : M10 : output : 3.3-V LVTTL : : 4 : Y
VCCINT : M11 : power : : 1.2V : :
@@ -260,14 +260,14 @@ GND : M13 : gnd : :
VCCIO5 : M14 : power : : 3.3V : 5 :
SW[3] : M15 : input : 3.3-V LVTTL : : 5 : Y
GND+ : M16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 :
DRAM_ADDR[11] : N1 : output : 3.3-V LVTTL : : 2 : Y
DRAM_ADDR[10] : N2 : output : 3.3-V LVTTL : : 2 : Y
DRAM_DQ[14] : N3 : bidir : 3.3-V LVTTL : : 3 : Y
VCCD_PLL1 : N4 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 :
DRAM_ADDR[1] : N5 : output : 3.3-V LVTTL : : 3 : Y
DRAM_ADDR[2] : N6 : output : 3.3-V LVTTL : : 3 : Y
GND : N7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 :
DRAM_ADDR[6] : N8 : output : 3.3-V LVTTL : : 3 : Y
GPIO_1[14] : N9 : output : 3.3-V LVTTL : : 4 : Y
GND : N10 : gnd : : : :
GPIO_1[15] : N11 : output : 3.3-V LVTTL : : 4 : Y
@@ -276,14 +276,14 @@ VCCD_PLL4 : N13 : power : : 1.2V
GPIO_1[27] : N14 : output : 3.3-V LVTTL : : 5 : Y
GPIO_1[24] : N15 : output : 3.3-V LVTTL : : 5 : Y
GPIO_1[23] : N16 : output : 3.3-V LVTTL : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 :
DRAM_ADDR[9] : P1 : output : 3.3-V LVTTL : : 2 : Y
DRAM_ADDR[0] : P2 : output : 3.3-V LVTTL : : 2 : Y
DRAM_DQ[13] : P3 : bidir : 3.3-V LVTTL : : 3 : Y
VCCIO3 : P4 : power : : 3.3V : 3 :
GND : P5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 :
DRAM_CS_N : P6 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : P7 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 :
DRAM_ADDR[4] : P8 : output : 3.3-V LVTTL : : 3 : Y
GPIO_1[13] : P9 : output : 3.3-V LVTTL : : 4 : Y
VCCIO4 : P10 : power : : 3.3V : 4 :
GPIO_1[10] : P11 : output : 3.3-V LVTTL : : 4 : Y
@@ -292,13 +292,13 @@ VCCIO4 : P13 : power : : 3.3V
GPIO_1[25] : P14 : output : 3.3-V LVTTL : : 4 : Y
GPIO_1[20] : P15 : output : 3.3-V LVTTL : : 5 : Y
GPIO_1[21] : P16 : output : 3.3-V LVTTL : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
DRAM_ADDR[8] : R1 : output : 3.3-V LVTTL : : 2 : Y
GND : R2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 :
DRAM_DQ[11] : R3 : bidir : 3.3-V LVTTL : : 3 : Y
DRAM_CLK : R4 : output : 3.3-V LVTTL : : 3 : Y
DRAM_DQ[12] : R5 : bidir : 3.3-V LVTTL : : 3 : Y
DRAM_DQM[0] : R6 : output : 3.3-V LVTTL : : 3 : Y
DRAM_DQ[7] : R7 : bidir : 3.3-V LVTTL : : 3 : Y
CLOCK_50 : R8 : input : 3.3-V LVTTL : : 3 : Y
GND+ : R9 : : : : 4 :
GPIO_1[11] : R10 : output : 3.3-V LVTTL : : 4 : Y
@@ -309,12 +309,12 @@ GPIO_1[22] : R14 : output : 3.3-V LVTTL :
GND : R15 : gnd : : : :
GPIO_1[18] : R16 : output : 3.3-V LVTTL : : 5 : Y
VCCIO3 : T1 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 :
DRAM_DQ[9] : T2 : bidir : 3.3-V LVTTL : : 3 : Y
DRAM_DQ[10] : T3 : bidir : 3.3-V LVTTL : : 3 : Y
DRAM_DQ[8] : T4 : bidir : 3.3-V LVTTL : : 3 : Y
DRAM_DQM[1] : T5 : output : 3.3-V LVTTL : : 3 : Y
DRAM_ADDR[7] : T6 : output : 3.3-V LVTTL : : 3 : Y
DRAM_ADDR[5] : T7 : output : 3.3-V LVTTL : : 3 : Y
SW[1] : T8 : input : 3.3-V LVTTL : : 3 : Y
GND+ : T9 : : : : 4 :
GPIO_1[8] : T10 : output : 3.3-V LVTTL : : 4 : Y
output_files/spectrum.sof
BIN
View File
Binary file not shown.
output_files/spectrum.sta.rpt
+37916 -20365
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File diff suppressed because it is too large Load Diff
output_files/spectrum.sta.summary
+92 -56
View File
@@ -3,23 +3,23 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -18.425
TNS : -546.891
Slack : -18.476
TNS : -808.800
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -6.923
TNS : -271.506
Slack : -7.513
TNS : -282.972
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.745
TNS : -42.191
Slack : -4.734
TNS : -42.279
Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.261
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.915
TNS : -2.915
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.342
Slack : 70.299
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
@@ -30,16 +30,28 @@ Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pl
Slack : 0.357
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.357
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.358
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.517
Slack : 0.382
TNS : 0.000
Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -6.263
TNS : -464.840
Slack : -6.210
TNS : -460.961
Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.657
Slack : 3.689
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.752
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -51,107 +63,131 @@ Slack : 19.602
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 20.597
Slack : 20.593
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 35.503
Slack : 35.490
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -17.572
TNS : -524.603
Slack : -17.646
TNS : -768.789
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -6.192
TNS : -241.805
Slack : -6.953
TNS : -254.832
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.414
TNS : -39.436
Slack : -4.416
TNS : -39.535
Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.951
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.786
TNS : -2.786
Slack : 70.438
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.297
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.298
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.311
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.312
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.312
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.467
Slack : 0.333
TNS : 0.000
Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -5.773
TNS : -427.930
Slack : -5.734
TNS : -425.150
Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.347
Slack : 3.370
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.748
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 9.489
Slack : 9.488
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 19.601
Slack : 19.598
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 20.590
Slack : 20.589
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 35.491
Slack : 35.487
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -15.171
TNS : -440.252
Slack : -15.170
TNS : -635.207
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -4.743
TNS : -163.399
Slack : -5.647
TNS : -193.116
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -3.815
TNS : -35.260
Slack : -3.810
TNS : -35.303
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.784
TNS : -2.784
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.112
Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 6.131
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.177
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 70.800
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.178
Slack : 0.179
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.201
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.728
TNS : -362.420
Slack : -4.684
TNS : -359.024
Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 2.503
Slack : 2.507
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.784
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
@@ -167,7 +203,7 @@ Slack : 20.600
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 35.535
Slack : 35.525
TNS : 0.000
------------------------------------------------------------
output_files/stp1.stp
+180
View File
@@ -0,0 +1,180 @@
<session jtag_chain="USB-Blaster [5-4.2]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<signal_set global_temp="1" is_expanded="true" name="signal_set: 2022/04/05 10:32:38 #0">
<clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="current_state.state_init" tap_mode="classic"/>
<wire name="current_state.state_read" tap_mode="classic"/>
<wire name="current_state.state_read_idle" tap_mode="classic"/>
<wire name="current_state.state_write" tap_mode="classic"/>
<wire name="current_state.state_write_idle" tap_mode="classic"/>
<wire name="next_state.state_init" tap_mode="classic"/>
<wire name="next_state.state_read" tap_mode="classic"/>
<wire name="next_state.state_read_idle" tap_mode="classic"/>
<wire name="next_state.state_write" tap_mode="classic"/>
<wire name="next_state.state_write_idle" tap_mode="classic"/>
<wire name="CLOCK_50" tap_mode="probeonly"/>
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
</trigger_input_vec>
<data_input_vec>
<wire name="current_state.state_init" tap_mode="classic"/>
<wire name="current_state.state_read" tap_mode="classic"/>
<wire name="current_state.state_read_idle" tap_mode="classic"/>
<wire name="current_state.state_write" tap_mode="classic"/>
<wire name="current_state.state_write_idle" tap_mode="classic"/>
<wire name="next_state.state_init" tap_mode="classic"/>
<wire name="next_state.state_read" tap_mode="classic"/>
<wire name="next_state.state_read_idle" tap_mode="classic"/>
<wire name="next_state.state_write" tap_mode="classic"/>
<wire name="next_state.state_write_idle" tap_mode="classic"/>
<wire name="CLOCK_50" tap_mode="probeonly"/>
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="current_state.state_init" tap_mode="classic"/>
<wire name="current_state.state_read" tap_mode="classic"/>
<wire name="current_state.state_read_idle" tap_mode="classic"/>
<wire name="current_state.state_write" tap_mode="classic"/>
<wire name="current_state.state_write_idle" tap_mode="classic"/>
<wire name="next_state.state_init" tap_mode="classic"/>
<wire name="next_state.state_read" tap_mode="classic"/>
<wire name="next_state.state_read_idle" tap_mode="classic"/>
<wire name="next_state.state_write" tap_mode="classic"/>
<wire name="next_state.state_write_idle" tap_mode="classic"/>
<wire name="CLOCK_50" tap_mode="probeonly"/>
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<unified_setup_data_view>
<node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<node mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<node data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<node data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
<node data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
<node data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
<node data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
</node>
<node mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<node data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
<node data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
<node data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
<node data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
<node data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
</node>
</unified_setup_data_view>
<data_view>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
<net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
</bus>
<bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
<net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
<net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
<net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
</bus>
</data_view>
<setup_view>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
<net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
</bus>
<bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
<net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
<net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
<net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
<net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
</bus>
</setup_view>
<trigger_in_editor/>
<trigger_out_editor/>
</presentation>
<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2022/04/05 10:37:05 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
<events use_custom_flow_control="no">
<level editor="basic_or" enabled="yes" name="condition1" type="advanced">
<power_up enabled="yes">
<power_up_expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
</power_up_expression>
</power_up>
<expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
</expression>
<op_node/>
</level>
</events>
<storage_qualifier_events>
<transitional>111111111111
<pwr_up_transitional>111111111111</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
</trigger>
</signal_set>
<position_info>
<single attribute="active tab" value="0"/>
</position_info>
</instance>
<mnemonics>
<table name="current_state_table" width="5">
<symbol name="state_init" value="00001"/>
<symbol name="state_read" value="00010"/>
<symbol name="state_read_idle" value="00100"/>
<symbol name="state_write" value="01000"/>
<symbol name="state_write_idle" value="10000"/>
</table>
<table name="next_state_table" width="5">
<symbol name="state_init" value="00001"/>
<symbol name="state_read" value="00010"/>
<symbol name="state_read_idle" value="00100"/>
<symbol name="state_write" value="01000"/>
<symbol name="state_write_idle" value="10000"/>
</table>
</mnemonics>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="config widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
<multi attribute="column width" size="23" value="34,34,200,74,68,70,88,88,98,98,88,88,643,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="frame size" size="2" value="3840,2032"/>
<multi attribute="jtag widget size" size="2" value="715,200"/>
</global_info>
<static_plugin_mnemonics/>
</session>