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de0-zx-spectrum/output_files/spectrum.sta.rpt
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TimeQuest Timing Analyzer report for spectrum
Wed Apr 6 13:58:24 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
16. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
17. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
21. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
22. Slow 1200mV 85C Model Hold: 'CLOCK_50'
23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
24. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
25. Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
27. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
28. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
29. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
30. Setup Times
31. Hold Times
32. Clock to Output Times
33. Minimum Clock to Output Times
34. Propagation Delay
35. Minimum Propagation Delay
36. Output Enable Times
37. Minimum Output Enable Times
38. Output Disable Times
39. Minimum Output Disable Times
40. Slow 1200mV 85C Model Metastability Report
41. Slow 1200mV 0C Model Fmax Summary
42. Slow 1200mV 0C Model Setup Summary
43. Slow 1200mV 0C Model Hold Summary
44. Slow 1200mV 0C Model Recovery Summary
45. Slow 1200mV 0C Model Removal Summary
46. Slow 1200mV 0C Model Minimum Pulse Width Summary
47. Slow 1200mV 0C Model Setup: 'CLOCK_50'
48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
50. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
51. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
52. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
54. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
55. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
56. Slow 1200mV 0C Model Hold: 'CLOCK_50'
57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
59. Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
60. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
61. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
62. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
63. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
64. Setup Times
65. Hold Times
66. Clock to Output Times
67. Minimum Clock to Output Times
68. Propagation Delay
69. Minimum Propagation Delay
70. Output Enable Times
71. Minimum Output Enable Times
72. Output Disable Times
73. Minimum Output Disable Times
74. Slow 1200mV 0C Model Metastability Report
75. Fast 1200mV 0C Model Setup Summary
76. Fast 1200mV 0C Model Hold Summary
77. Fast 1200mV 0C Model Recovery Summary
78. Fast 1200mV 0C Model Removal Summary
79. Fast 1200mV 0C Model Minimum Pulse Width Summary
80. Fast 1200mV 0C Model Setup: 'CLOCK_50'
81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
83. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
84. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
85. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
86. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
88. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
89. Fast 1200mV 0C Model Hold: 'CLOCK_50'
90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
93. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
94. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
95. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
96. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
97. Setup Times
98. Hold Times
99. Clock to Output Times
100. Minimum Clock to Output Times
101. Propagation Delay
102. Minimum Propagation Delay
103. Output Enable Times
104. Minimum Output Enable Times
105. Output Disable Times
106. Minimum Output Disable Times
107. Fast 1200mV 0C Model Metastability Report
108. Multicorner Timing Analysis Summary
109. Setup Times
110. Hold Times
111. Clock to Output Times
112. Minimum Clock to Output Times
113. Propagation Delay
114. Minimum Propagation Delay
115. Board Trace Model Assignments
116. Input Transition Times
117. Signal Integrity Metrics (Slow 1200mv 0c Model)
118. Signal Integrity Metrics (Slow 1200mv 85c Model)
119. Signal Integrity Metrics (Fast 1200mv 0c Model)
120. Setup Transfers
121. Hold Transfers
122. Recovery Transfers
123. Removal Transfers
124. Report TCCS
125. Report RSKM
126. Unconstrained Paths
127. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; SDC File List ;
+--------------------------------------------------------------------------------+
SDC File Path : spectrum.sdc
Status : OK
Read at : Wed Apr 6 13:58:21 2022
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : beep
Type : Base
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { ula:ula_|beep }
Clock Name : CLOCK_50
Type : Base
Period : 20.000
Frequency : 50.0 MHz
Rise : 0.000
Fall : 10.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 3.000
Fall : 8.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase : 108.0
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 39.716
Frequency : 25.18 MHz
Rise : 0.000
Fall : 19.858
Duty Cycle : 50.00
Divide by : 280
Multiply by : 141
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 71.489
Frequency : 13.99 MHz
Rise : 0.000
Fall : 35.744
Duty Cycle : 50.00
Divide by : 168
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Type : Generated
Period : 41.702
Frequency : 23.98 MHz
Rise : 0.000
Fall : 20.851
Duty Cycle : 50.00
Divide by : 98
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 48.81 MHz
Restricted Fmax : 48.81 MHz
Clock Name : CLOCK_50
Note :
Fmax : 127.71 MHz
Restricted Fmax : 127.71 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 148.39 MHz
Restricted Fmax : 148.39 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 172.89 MHz
Restricted Fmax : 172.89 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 840.34 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -18.476
End Point TNS : -808.800
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -7.513
End Point TNS : -282.972
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.734
End Point TNS : -42.279
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 3.261
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 70.299
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.344
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.357
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.357
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.358
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.382
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.517
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -6.210
End Point TNS : -460.961
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.689
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.752
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.488
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.602
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.593
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.490
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -18.476
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.297
Slack : -18.463
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.284
Slack : -18.424
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 8.254
Slack : -18.421
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 8.251
Slack : -18.405
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 8.235
Slack : -18.370
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.191
Slack : -18.327
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.148
Slack : -18.296
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.117
Slack : -18.259
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.080
Slack : -18.230
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.051
Slack : -18.227
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.048
Slack : -18.205
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 8.026
Slack : -18.178
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 8.008
Slack : -18.166
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.996
Slack : -18.079
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.900
Slack : -18.056
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.877
Slack : -18.035
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.876
Slack : -18.016
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.857
Slack : -18.002
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.832
Slack : -17.989
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.810
Slack : -17.982
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.823
Slack : -17.978
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.543
Slack : -17.955
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 7.506
Slack : -17.928
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.482
Slack : -17.924
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.745
Slack : -17.923
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.744
Slack : -17.920
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.741
Slack : -17.910
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.731
Slack : -17.889
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 7.456
Slack : -17.880
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.701
Slack : -17.880
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 7.442
Slack : -17.875
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.716
Slack : -17.866
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.687
Slack : -17.855
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.420
Slack : -17.854
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.675
Slack : -17.852
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 7.404
Slack : -17.832
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.662
Slack : -17.816
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.657
Slack : -17.807
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 7.358
Slack : -17.780
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.621
Slack : -17.747
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.568
Slack : -17.746
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 7.315
Slack : -17.688
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.529
Slack : -17.665
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.215
Slack : -17.638
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.479
Slack : -17.624
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.185
Slack : -17.623
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.173
Slack : -17.587
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.428
Slack : -17.584
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.425
Slack : -17.575
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.416
Slack : -17.572
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.393
Slack : -17.571
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.412
Slack : -17.542
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.103
Slack : -17.518
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 7.070
Slack : -17.517
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.358
Slack : -17.515
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.065
Slack : -17.513
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.078
Slack : -17.507
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.068
Slack : -17.506
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.069
Slack : -17.484
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.325
Slack : -17.472
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.022
Slack : -17.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.012
Slack : -17.452
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.293
Slack : -17.442
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.000
Slack : -17.436
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.999
Slack : -17.434
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.253
Data Delay : 7.255
Slack : -17.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.984
Slack : -17.426
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.985
Slack : -17.426
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.267
Slack : -17.424
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.974
Slack : -17.424
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 6.991
Slack : -17.417
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.976
Slack : -17.414
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.973
Slack : -17.414
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.255
Slack : -17.412
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.972
Slack : -17.410
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.251
Slack : -17.402
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.952
Slack : -17.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.948
Slack : -17.387
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.939
Slack : -17.379
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.942
Slack : -17.367
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.923
Slack : -17.365
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.923
Slack : -17.364
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.922
Slack : -17.359
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.200
Slack : -17.353
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.912
Slack : -17.346
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.187
Slack : -17.340
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.181
Slack : -17.316
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.157
Slack : -17.310
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.151
Slack : -17.281
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 6.850
Slack : -17.277
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.829
Slack : -17.274
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.824
Slack : -17.273
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.833
Slack : -17.270
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.831
Slack : -17.255
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.096
Slack : -17.252
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 6.806
Slack : -17.229
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.787
Slack : -17.221
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.771
Slack : -17.208
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.767
Slack : -17.204
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.766
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -7.513
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.158
Data Delay : 5.779
Slack : -7.251
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.150
Data Delay : 5.509
Slack : -7.249
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.148
Data Delay : 5.505
Slack : -7.223
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 5.044
Slack : -7.220
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.149
Data Delay : 5.477
Slack : -7.144
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.268
Data Delay : 4.984
Slack : -7.116
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.960
Slack : -7.112
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.960
Slack : -7.092
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.149
Data Delay : 5.349
Slack : -7.056
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.880
Slack : -7.026
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.880
Slack : -7.025
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.261
Data Delay : 4.872
Slack : -7.003
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 4.812
Slack : -6.994
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.255
Data Delay : 4.847
Slack : -6.970
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.296
Data Delay : 4.782
Slack : -6.959
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.816
Slack : -6.958
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.300
Data Delay : 4.766
Slack : -6.935
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.750
Slack : -6.929
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.150
Data Delay : 5.187
Slack : -6.927
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.159
Data Delay : 5.194
Slack : -6.926
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.755
Slack : -6.915
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 4.736
Slack : -6.914
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.739
Slack : -6.911
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 4.729
Slack : -6.908
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.282
Data Delay : 4.734
Slack : -6.906
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.750
Slack : -6.900
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.748
Slack : -6.879
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.694
Slack : -6.875
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.151
Data Delay : 5.134
Slack : -6.874
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.150
Data Delay : 5.132
Slack : -6.867
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.678
Slack : -6.867
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.151
Data Delay : 5.126
Slack : -6.857
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 4.674
Slack : -6.856
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.721
Slack : -6.845
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 4.658
Slack : -6.809
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.660
Slack : -6.804
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.652
Slack : -6.800
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.263
Data Delay : 4.645
Slack : -6.788
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.604
Slack : -6.787
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.255
Data Delay : 4.640
Slack : -6.768
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.150
Data Delay : 5.026
Slack : -6.765
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.589
Slack : -6.760
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.575
Slack : -6.738
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.586
Slack : -6.737
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.565
Slack : -6.732
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 4.551
Slack : -6.729
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.151
Data Delay : 4.988
Slack : -6.720
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.267
Data Delay : 4.561
Slack : -6.695
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 4.504
Slack : -6.691
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 4.497
Slack : -6.676
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.250
Data Delay : 4.534
Slack : -6.664
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.479
Slack : -6.655
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.519
Slack : -6.651
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.508
Slack : -6.649
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 4.763
Slack : -6.647
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.501
Slack : -6.646
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.277
Data Delay : 4.477
Slack : -6.645
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.460
Slack : -6.644
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.509
Slack : -6.643
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.507
Slack : -6.641
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.286
Data Delay : 4.463
Slack : -6.640
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 4.453
Slack : -6.636
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.501
Slack : -6.635
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.450
Slack : -6.629
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.473
Slack : -6.618
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.270
Data Delay : 4.456
Slack : -6.615
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.452
Slack : -6.613
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.233
Data Delay : 4.488
Slack : -6.610
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.438
Slack : -6.607
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.453
Slack : -6.603
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.418
Slack : -6.596
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.425
Slack : -6.595
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.423
Slack : -6.590
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.447
Slack : -6.588
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.417
Slack : -6.582
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.155
Data Delay : 4.845
Slack : -6.565
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.150
Data Delay : 4.823
Slack : -6.553
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.369
Slack : -6.529
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.288
Data Delay : 4.349
Slack : -6.529
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.633
Slack : -6.514
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 4.320
Slack : -6.473
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.319
Slack : -6.472
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.301
Slack : -6.470
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.295
Slack : -6.462
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.145
Data Delay : 4.715
Slack : -6.442
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.265
Data Delay : 4.285
Slack : -6.433
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.249
Slack : -6.431
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.294
Data Delay : 4.245
Slack : -6.421
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.151
Data Delay : 4.680
Slack : -6.419
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.275
Slack : -6.417
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.148
Data Delay : 4.673
Slack : -6.409
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.298
Data Delay : 4.219
Slack : -6.402
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.217
Slack : -6.391
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.251
Slack : -6.386
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.140
Data Delay : 4.634
Slack : -6.356
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.238
Data Delay : 4.226
Slack : -6.355
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 4.173
Slack : -6.355
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 4.224
Slack : -6.349
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.165
Slack : -6.348
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.238
Data Delay : 4.218
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.734
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.952
Slack : -4.734
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.952
Slack : -4.725
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 2.816
Slack : -4.269
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 2.817
Slack : -4.269
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 2.817
Slack : -4.269
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 2.817
Slack : -4.269
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 2.817
Slack : -4.269
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 2.817
Slack : -3.587
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 2.160
Slack : -3.154
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.161
Data Delay : 1.694
Slack : 16.936
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.479
Slack : 16.937
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.478
Slack : 16.963
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.452
Slack : 16.963
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.452
Slack : 16.963
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.452
Slack : 16.963
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.452
Slack : 16.963
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.452
Slack : 16.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.451
Slack : 16.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.451
Slack : 16.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.451
Slack : 16.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.451
Slack : 16.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.451
Slack : 17.071
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.344
Slack : 17.098
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.317
Slack : 17.098
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.317
Slack : 17.098
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.317
Slack : 17.098
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.317
Slack : 17.098
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.317
Slack : 17.177
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.238
Slack : 17.190
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.225
Slack : 17.190
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.225
Slack : 17.191
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.224
Slack : 17.191
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.224
Slack : 17.204
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.211
Slack : 17.204
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.211
Slack : 17.204
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.211
Slack : 17.204
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.211
Slack : 17.204
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.211
Slack : 17.206
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.209
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.325
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.090
Slack : 17.325
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.090
Slack : 17.363
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.054
Slack : 17.363
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.054
Slack : 17.364
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.053
Slack : 17.364
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.053
Slack : 17.382
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.033
Slack : 17.409
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.006
Slack : 17.409
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.006
Slack : 17.409
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.006
Slack : 17.409
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.006
Slack : 17.409
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.006
Slack : 17.425
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.992
Slack : 17.425
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.992
Slack : 17.425
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.992
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.991
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.991
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.991
Slack : 17.431
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.984
Slack : 17.431
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.984
Slack : 17.460
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.955
Slack : 17.460
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.955
Slack : 17.498
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.919
Slack : 17.498
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.919
Slack : 17.560
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.857
Slack : 17.560
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.857
Slack : 17.560
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.857
Slack : 17.599
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.148
Slack : 17.599
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.148
Slack : 17.599
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.148
Slack : 17.599
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.148
Slack : 17.599
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.148
Slack : 17.600
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.147
Slack : 17.600
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.147
Slack : 17.600
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.147
Slack : 17.600
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.147
Slack : 17.600
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.147
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.813
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.813
Slack : 17.633
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.784
Slack : 17.633
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.784
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.666
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.751
Slack : 17.666
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.751
Slack : 17.666
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.751
Slack : 17.695
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.722
Slack : 17.695
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.722
Slack : 17.695
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.722
Slack : 17.695
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.722
Slack : 17.695
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.722
Slack : 17.696
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.721
Slack : 17.696
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.721
Slack : 17.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.013
Slack : 17.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.013
Slack : 17.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.099
Data Delay : 3.013
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 3.261
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.587
Slack : 3.412
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.436
Slack : 3.574
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 6.245
Slack : 3.580
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.268
Slack : 3.583
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.265
Slack : 3.618
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 6.196
Slack : 3.682
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 6.132
Slack : 3.686
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.162
Slack : 3.695
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 6.124
Slack : 3.754
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 6.060
Slack : 3.760
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 6.057
Slack : 3.761
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 6.053
Slack : 3.769
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.079
Slack : 3.769
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 6.048
Slack : 3.792
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 6.010
Slack : 3.827
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.021
Slack : 3.834
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.987
Slack : 3.855
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.992
Slack : 3.860
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 5.957
Slack : 3.862
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.959
Slack : 3.865
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.953
Slack : 3.874
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.940
Slack : 3.883
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.964
Slack : 3.895
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.949
Slack : 3.920
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.926
Slack : 3.920
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.896
Slack : 3.921
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.893
Slack : 3.923
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.921
Slack : 3.925
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.889
Slack : 3.926
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.922
Slack : 3.931
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.917
Slack : 3.935
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.886
Slack : 3.956
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.891
Slack : 3.956
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.862
Slack : 3.959
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.862
Slack : 3.964
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.884
Slack : 3.969
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.849
Slack : 3.980
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.867
Slack : 3.983
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.863
Slack : 3.996
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.848
Slack : 4.002
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.812
Slack : 4.015
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 5.802
Slack : 4.020
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.824
Slack : 4.021
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.793
Slack : 4.023
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.099
Data Delay : 5.778
Slack : 4.031
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.817
Slack : 4.037
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.809
Slack : 4.044
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.777
Slack : 4.050
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.795
Slack : 4.091
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.723
Slack : 4.096
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.750
Slack : 4.106
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.741
Slack : 4.107
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.714
Slack : 4.111
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.707
Slack : 4.150
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.698
Slack : 4.154
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.665
Slack : 4.161
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.660
Slack : 4.168
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.651
Slack : 4.176
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.669
Slack : 4.180
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.634
Slack : 4.189
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.625
Slack : 4.195
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.624
Slack : 4.219
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 5.583
Slack : 4.220
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.601
Slack : 4.228
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 5.574
Slack : 4.234
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.585
Slack : 4.271
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.552
Slack : 4.287
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.561
Slack : 4.289
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.557
Slack : 4.294
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.526
Slack : 4.301
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.522
Slack : 4.312
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.502
Slack : 4.316
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.527
Slack : 4.320
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.499
Slack : 4.339
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 5.478
Slack : 4.341
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.477
Slack : 4.346
From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.056
Data Delay : 5.496
Slack : 4.362
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 5.487
Slack : 4.362
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.461
Slack : 4.375
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.441
Slack : 4.379
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.101
Data Delay : 5.420
Slack : 4.394
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.454
Slack : 4.401
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.420
Slack : 4.407
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.413
Slack : 4.422
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.425
Slack : 4.422
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.401
Slack : 4.424
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.392
Slack : 4.425
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.099
Data Delay : 5.376
Slack : 4.425
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 5.377
Slack : 4.429
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.387
Slack : 4.429
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.387
Slack : 4.431
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.101
Data Delay : 5.368
Slack : 4.435
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.099
Data Delay : 5.366
Slack : 4.436
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.104
Data Delay : 5.360
Slack : 4.437
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.409
Slack : 4.438
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 5.364
Slack : 4.438
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 5.364
Slack : 4.440
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.389
Slack : 4.440
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.406
Slack : 4.441
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.072
Data Delay : 5.387
+--------------------------------------------------------------------------------+
Slack : 0.530
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.749
Slack : 0.533
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.752
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 70.299
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.058
Data Delay : 1.127
Slack : 70.762
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.063
Data Delay : 0.659
Slack : 70.763
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.062
Data Delay : 0.659
+--------------------------------------------------------------------------------+
Slack : 0.547
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.782
Slack : 0.552
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.771
Slack : 0.553
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.788
Slack : 0.346
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.773
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.148
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.794
Slack : 0.567
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.786
Slack : 0.573
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.792
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.808
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.796
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.807
Slack : 0.591
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.810
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.811
Slack : 0.602
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.836
Slack : 0.631
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.850
Slack : 0.633
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.852
Slack : 0.653
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.242
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.592
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.592
Slack : 0.373
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.592
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.375
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.594
Slack : 0.375
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.594
Slack : 0.375
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.594
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.622
Slack : 0.404
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.623
Slack : 0.412
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.645
Slack : 0.425
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.644
Slack : 0.430
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.649
Slack : 0.436
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.655
Slack : 0.479
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.698
Slack : 0.481
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.700
Slack : 0.481
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.700
Slack : 0.482
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.701
Slack : 0.506
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.725
Slack : 0.524
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.113
Slack : 0.541
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.130
Slack : 0.542
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.777
Slack : 0.544
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.779
Slack : 0.545
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.780
Slack : 0.555
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.790
Slack : 0.557
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.776
Slack : 0.561
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.562
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.781
Slack : 0.563
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.567
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.786
Slack : 0.568
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.787
Slack : 0.569
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.158
Slack : 0.573
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.792
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.795
Slack : 0.576
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 0.793
Slack : 0.579
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.812
Slack : 0.579
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.812
Slack : 0.582
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.169
Slack : 0.583
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.802
Slack : 1.041
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.907
Slack : 0.596
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.829
Slack : 0.631
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.864
Slack : 0.673
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.260
Slack : 0.693
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.913
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.936
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.924
Slack : 0.721
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.940
Slack : 0.753
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.342
Slack : 0.761
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.406
Data Delay : 1.324
Slack : 0.761
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.406
Data Delay : 1.324
Slack : 0.761
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.406
Data Delay : 1.324
Slack : 0.761
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.406
Data Delay : 1.324
Slack : 0.761
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.406
Data Delay : 1.324
Slack : 0.763
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.997
Slack : 0.765
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 0.629
Slack : 0.766
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.353
Slack : 0.780
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 0.997
Slack : 0.784
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.003
Slack : 0.785
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 1.002
Slack : 0.787
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.006
Slack : 0.787
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.006
Slack : 0.802
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.260
Data Delay : 0.699
Slack : 1.289
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.127
Slack : 0.819
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.054
Slack : 0.822
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.041
Slack : 0.829
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 1.053
Slack : 0.829
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.416
Slack : 0.832
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.067
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.654
Slack : 0.834
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.834
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.669
Slack : 0.835
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.835
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 1.472
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.290
Data Delay : 1.339
Slack : 0.851
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.854
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.830
Slack : 1.612
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.832
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 1.758
Slack : 1.633
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.851
Slack : 1.645
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.865
Slack : 0.358
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.872
Slack : 1.673
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.892
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.898
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.933
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.940
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.942
Slack : 1.729
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 1.595
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.953
Slack : 1.735
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.955
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.552
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.772
Slack : 1.757
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.562
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.782
Slack : 0.674
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.894
Slack : 0.776
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.020
Slack : 0.812
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.032
Slack : 0.826
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.046
Slack : 0.828
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.072
Slack : 0.828
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.072
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.073
Slack : 0.840
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.060
Slack : 0.842
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.062
Slack : 0.856
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.074
Slack : 0.934
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.154
Slack : 0.936
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.155
Slack : 0.947
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.065
Data Delay : 1.169
Slack : 0.995
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.239
Slack : 1.042
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.268
Slack : 1.046
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.272
Slack : 1.099
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.272
Data Delay : 0.984
Slack : 1.134
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.354
Slack : 1.154
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.373
Slack : 1.166
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.071
Data Delay : 1.394
Slack : 1.204
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.448
Slack : 1.226
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.244
Data Delay : 1.139
Slack : 1.228
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.272
Data Delay : 1.113
Slack : 1.230
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.450
Slack : 1.237
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.463
Slack : 1.245
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.472
Slack : 1.246
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.466
Slack : 1.276
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.502
Slack : 1.285
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.505
Slack : 1.285
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.505
Slack : 1.285
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.505
Slack : 1.285
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.505
Slack : 1.288
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.508
Slack : 1.288
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.532
Slack : 1.324
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.551
Slack : 1.332
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.576
Slack : 1.343
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.587
Slack : 1.351
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.272
Data Delay : 1.236
Slack : 1.360
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.578
Slack : 1.361
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.588
Slack : 1.368
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.244
Data Delay : 1.281
Slack : 1.369
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.589
Slack : 1.373
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.591
Slack : 1.374
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.244
Data Delay : 1.287
Slack : 1.380
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.605
Slack : 1.382
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.607
Slack : 1.420
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.639
Slack : 1.438
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.682
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.415
Data Delay : 2.021
Slack : 1.454
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.272
Data Delay : 1.339
Slack : 1.455
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.680
Slack : 1.543
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.763
Slack : 1.555
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.774
Slack : 1.562
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.782
Slack : 1.564
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.784
Slack : 1.564
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.789
Slack : 1.571
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.815
Slack : 1.580
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.798
Slack : 1.581
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.800
Slack : 1.587
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.805
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.605
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.824
Slack : 1.615
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.834
Slack : 1.617
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.244
Data Delay : 1.530
Slack : 1.620
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.847
Slack : 1.620
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.847
Slack : 1.620
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.847
Slack : 1.620
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.847
Slack : 1.639
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.864
Slack : 1.646
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.865
Slack : 1.654
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.087
Data Delay : 1.898
Slack : 1.675
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.894
Slack : 1.683
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.910
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.357
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.361
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.779
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 1.003
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.358
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.362
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.580
Slack : 0.557
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.775
Slack : 0.558
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.776
Slack : 0.559
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.777
Slack : 0.560
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.778
Slack : 0.560
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.778
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.563
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.563
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.564
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.782
Slack : 0.570
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.788
Slack : 0.570
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.788
Slack : 0.571
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.789
Slack : 0.571
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.789
Slack : 0.572
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.790
Slack : 0.573
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.791
Slack : 0.573
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.791
Slack : 0.573
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.791
Slack : 0.574
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.792
Slack : 0.575
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.793
Slack : 0.575
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.793
Slack : 0.581
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.799
Slack : 0.593
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.812
Slack : 0.594
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.813
Slack : 0.613
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.832
Slack : 0.617
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.836
Slack : 0.704
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.923
Slack : 0.814
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.032
Slack : 0.832
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.050
Slack : 0.834
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.834
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.835
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.053
Slack : 0.836
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.054
Slack : 0.836
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.054
Slack : 0.845
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.063
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.064
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.064
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.066
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.066
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.849
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.851
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.069
Slack : 0.851
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.069
Slack : 0.852
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.070
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.077
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.077
Slack : 0.860
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.078
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.079
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.079
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.864
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.082
Slack : 0.864
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.082
Slack : 0.879
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.098
Slack : 0.886
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.105
Slack : 0.942
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.160
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.945
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.163
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.947
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.165
Slack : 0.948
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.166
Slack : 0.955
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.173
Slack : 0.956
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.174
Slack : 0.956
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.174
Slack : 0.957
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.175
Slack : 0.957
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.175
Slack : 0.957
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.175
Slack : 0.958
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.176
Slack : 0.959
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.959
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.959
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.960
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.178
Slack : 0.960
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.178
Slack : 0.961
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.179
Slack : 0.961
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.179
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.963
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.181
Slack : 0.971
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.189
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.382
From Node : debouncer:debounce_autofire|r_State
To Node : debouncer:debounce_autofire|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.577
Slack : 0.382
From Node : debouncer:debounce_turbo|r_State
To Node : debouncer:debounce_turbo|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.577
Slack : 0.391
From Node : debouncer:debounce_turbo|r_Count[20]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.610
Slack : 0.391
From Node : debouncer:debounce_autofire|r_Count[20]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.610
Slack : 0.559
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.559
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.560
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.779
Slack : 0.560
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.779
Slack : 0.560
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.778
Slack : 0.560
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.779
Slack : 0.561
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.779
Slack : 0.561
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.562
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.781
Slack : 0.562
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.781
Slack : 0.562
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.563
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.563
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.563
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.563
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.565
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.784
Slack : 0.565
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.784
Slack : 0.565
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.784
Slack : 0.565
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.783
Slack : 0.565
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.783
Slack : 0.565
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.783
Slack : 0.567
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.786
Slack : 0.568
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.787
Slack : 0.568
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.786
Slack : 0.568
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.787
Slack : 0.569
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.788
Slack : 0.569
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.787
Slack : 0.569
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.788
Slack : 0.572
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.572
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.576
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.795
Slack : 0.577
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.796
Slack : 0.577
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.796
Slack : 0.577
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.796
Slack : 0.577
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.796
Slack : 0.577
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.795
Slack : 0.580
From Node : debouncer:debounce_turbo|r_Count[6]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.799
Slack : 0.834
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.834
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.834
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.834
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.835
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.835
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.835
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.053
Slack : 0.835
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.838
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.057
Slack : 0.838
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.057
Slack : 0.840
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.059
Slack : 0.840
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.059
Slack : 0.840
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.058
Slack : 0.840
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.058
Slack : 0.840
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.058
Slack : 0.843
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.059
Slack : 0.847
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.847
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.847
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.847
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.848
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.849
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.849
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.849
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.849
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.849
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.849
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.849
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.850
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.069
Slack : 0.850
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.069
Slack : 0.851
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.851
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.851
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.851
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.851
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.070
Slack : 0.851
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.069
Slack : 0.852
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.071
Slack : 0.852
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.071
Slack : 0.852
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.070
Slack : 0.854
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.073
Slack : 0.855
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.074
Slack : 0.855
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.074
Slack : 0.855
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.073
Slack : 0.856
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.075
Slack : 0.856
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.075
Slack : 0.856
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.074
Slack : 0.857
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.076
Slack : 0.857
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.076
Slack : 0.857
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.075
Slack : 0.858
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.077
Slack : 0.858
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.077
Slack : 0.858
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.076
Slack : 0.859
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.078
Slack : 0.859
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.075
Slack : 0.859
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.078
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -6.210
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 4.331
Slack : -6.210
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 4.329
Slack : -6.210
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.328
Slack : -6.210
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 4.327
Slack : -6.209
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.327
Slack : -5.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 4.060
Slack : -5.958
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.195
Data Delay : 4.047
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.923
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.176
Data Delay : 3.907
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.924
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.924
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.924
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.924
Slack : -5.704
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.924
Slack : -5.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.910
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.171
Data Delay : 3.901
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.909
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.171
Data Delay : 3.901
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.171
Data Delay : 3.901
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.171
Data Delay : 3.901
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.911
Slack : -5.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 3.922
Slack : -5.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 3.922
Slack : -5.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 3.922
Slack : -5.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 3.922
Slack : -5.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.169
Data Delay : 3.922
Slack : -5.371
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.161
Data Delay : 3.911
Slack : -5.353
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.177
Data Delay : 3.909
Slack : -5.350
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 3.923
Slack : -5.350
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 3.923
Slack : -5.350
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 3.923
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.188
Data Delay : 3.910
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.912
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.343
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.909
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.911
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.911
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.911
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.178
Data Delay : 3.899
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.542
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.543
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.542
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.533
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.557
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.595
Data Delay : 3.543
Slack : 3.723
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.543
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.587
Data Delay : 3.556
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.587
Data Delay : 3.556
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.587
Data Delay : 3.556
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.587
Data Delay : 3.556
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.587
Data Delay : 3.556
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.233
Data Delay : 3.534
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.543
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.233
Data Delay : 3.534
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.233
Data Delay : 3.534
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.233
Data Delay : 3.534
Slack : 4.071
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.557
Slack : 4.071
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.557
Slack : 4.071
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.557
Slack : 4.071
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.557
Slack : 4.071
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.557
Slack : 4.072
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.556
Slack : 4.072
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.556
Slack : 4.072
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.556
Slack : 4.072
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.556
Slack : 4.072
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.556
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 3.542
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.557
Slack : 4.073
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.557
Slack : 4.280
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.190
Data Delay : 3.655
Slack : 4.292
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.192
Data Delay : 3.669
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 3.909
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.908
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 3.907
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.225
Data Delay : 3.912
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.909
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.593
Actual Width : 20.809
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.605
Actual Width : 20.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.605
Actual Width : 20.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.605
Actual Width : 20.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.606
Actual Width : 20.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.693
Actual Width : 20.848
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.694
Actual Width : 20.878
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.695
Actual Width : 20.879
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.490
Actual Width : 35.706
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.730
Actual Width : 35.730
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.730
Actual Width : 35.730
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.758
Actual Width : 35.758
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.759
Actual Width : 35.759
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 2.982
Fall : 3.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 2.346
Fall : 2.671
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 2.083
Fall : 2.452
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 2.910
Fall : 3.266
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 2.982
Fall : 3.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 2.249
Fall : 2.595
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : 3.159
Fall : 3.711
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.214
Fall : 3.753
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : 3.437
Fall : 4.028
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 5.217
Fall : 5.573
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 4.464
Fall : 4.789
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 4.077
Fall : 4.446
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 5.217
Fall : 5.573
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 4.615
Fall : 4.935
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 4.296
Fall : 4.642
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 4.842
Fall : 5.311
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.275
Fall : 1.518
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.868
Fall : 3.098
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -1.367
Fall : -1.724
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -1.480
Fall : -1.794
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -1.367
Fall : -1.724
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -1.610
Fall : -1.927
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -2.297
Fall : -2.537
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -1.553
Fall : -1.892
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : -1.675
Fall : -2.234
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.655
Fall : -3.175
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : -1.937
Fall : -2.527
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -2.942
Fall : -3.255
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -3.082
Fall : -3.396
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -3.216
Fall : -3.573
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -2.942
Fall : -3.255
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -3.369
Fall : -3.649
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -3.039
Fall : -3.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -3.799
Fall : -4.258
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.657
Fall : -0.891
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.973
Fall : -1.211
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.228
Fall : 10.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 9.909
Fall : 10.038
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.954
Fall : 10.011
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 10.123
Fall : 10.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 9.672
Fall : 9.707
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.228
Fall : 10.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 9.897
Fall : 9.931
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 9.384
Fall : 9.506
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.974
Fall : 9.978
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.944
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.782
Fall : 9.780
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.280
Fall : 9.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.654
Fall : 9.659
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.391
Fall : 9.410
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.589
Fall : 9.640
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.681
Fall : 9.690
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.944
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.894
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.419
Fall : 3.334
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.004
Fall : 6.086
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.305
Fall : 5.354
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.578
Fall : 5.696
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.445
Fall : 5.512
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.941
Fall : 6.086
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.645
Fall : 5.775
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.004
Fall : 6.051
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.996
Fall : 5.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.954
Fall : 6.010
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.903
Fall : 5.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.870
Fall : 5.876
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.883
Fall : 5.889
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.883
Fall : 5.889
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.873
Fall : 5.891
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.904
Fall : 5.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.904
Fall : 5.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.941
Fall : 5.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.091
Fall : 8.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.500
Fall : 7.498
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.943
Fall : 8.029
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.038
Fall : 8.056
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.578
Fall : 7.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.091
Fall : 8.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.839
Fall : 7.890
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.255
Fall : 7.347
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.712
Fall : 7.706
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.632
Fall : 7.649
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.222
Fall : 7.219
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.315
Fall : 7.384
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.565
Fall : 7.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.471
Fall : 7.581
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.421
Fall : 7.433
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.623
Fall : 7.649
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.465
Fall : 7.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.632
Fall : 7.645
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.550
Fall : 8.202
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.550
Fall : 8.202
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.928
Fall : 6.937
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.512
Fall : 6.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.524
Fall : 6.454
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.553
Fall : 6.432
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.279
Fall : 6.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.725
Fall : 6.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.725
Fall : 6.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.651
Fall : 6.615
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.698
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.230
Fall : 6.171
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.418
Fall : 7.417
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.698
Fall : 8.650
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 8.740
Fall : 8.736
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.821
Fall : 8.816
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.612
Fall : 7.634
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.738
Fall : 8.739
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.874
Fall : 8.896
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.418
Fall : 7.417
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 8.389
Fall : 8.422
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.341
Fall : 7.353
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.307
Fall : 8.297
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.049
Fall : 8.038
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.374
Fall : 8.371
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.341
Fall : 7.353
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.108
Fall : 8.143
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.668
Fall : 8.665
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.481
Fall : 7.480
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.315
Fall : 8.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.901
Fall : 2.814
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.876
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.998
Fall : 2.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.438
Fall : 4.524
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.691
Fall : 4.745
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.949
Fall : 5.047
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.820
Fall : 4.867
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.294
Fall : 5.421
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.013
Fall : 5.123
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.406
Fall : 5.449
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.438
Fall : 4.524
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.293
Fall : 5.342
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 4.880
Fall : 4.891
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 4.848
Fall : 4.850
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.860
Fall : 4.863
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.860
Fall : 4.863
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 4.850
Fall : 4.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.880
Fall : 4.886
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.880
Fall : 4.886
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.919
Fall : 4.939
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.003
Fall : 2.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.164
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.093
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.436
Fall : 6.455
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.457
Fall : 6.534
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.813
Fall : 6.750
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.010
Fall : 7.107
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.622
Fall : 6.673
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.079
Fall : 7.091
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.774
Fall : 6.865
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.436
Fall : 6.455
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.759
Fall : 6.790
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.164
Fall : 5.193
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.115
Fall : 6.099
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.874
Fall : 5.919
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.560
Fall : 6.663
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.164
Fall : 5.193
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.430
Fall : 6.437
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.568
Fall : 6.634
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.515
Fall : 5.513
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.685
Fall : 6.735
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 4.248
Fall : 4.209
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 6.286
Fall : 5.965
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 4.306
Fall : 4.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.248
Fall : 4.209
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.260
Fall : 4.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.998
Fall : 3.874
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 4.353
Fall : 4.239
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.998
Fall : 3.874
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.923
Fall : 4.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.923
Fall : 4.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.461
Fall : 2.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.838
Fall : 3.798
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.312
Fall : 4.282
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.256
Fall : 4.155
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 4.287
Fall : 4.239
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.838
Fall : 3.798
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.457
Fall : 2.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.456
Fall : 2.369
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.479
Fall : 4.115
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.458
Fall : 2.371
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.551
Fall : 2.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.760
RF :
FR :
FF : 4.845
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 6.879
RF : 6.888
FR : 7.195
FF : 7.213
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 6.687
RF : 6.671
FR : 7.003
FF : 6.996
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 4.492
FR : 4.693
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 7.200
RF : 7.173
FR : 7.560
FF : 7.542
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 7.015
RF : 6.950
FR : 7.322
FF : 7.358
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 4.319
FR : 4.499
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 8.089
RF : 8.112
FR : 8.436
FF : 8.468
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 6.945
RF : 6.980
FR : 7.315
FF : 7.315
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 6.211
FR : 6.117
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 7.927
RF : 7.949
FR : 8.239
FF : 8.269
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 7.621
RF : 7.586
FR : 7.940
FF : 7.914
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 4.174
FR : 4.361
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 7.468
RF : 7.451
FR : 7.805
FF : 7.797
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 7.041
RF : 7.069
FR : 7.371
FF : 7.371
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 6.462
FR : 7.117
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 7.844
RF :
FR :
FF : 8.324
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.881
RF :
FR :
FF : 7.298
Input Port : raw_loader_in
Output Port : LED[1]
RR : 5.229
RF :
FR :
FF : 5.518
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.617
RF :
FR :
FF : 4.706
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 6.643
RF : 6.647
FR : 6.957
FF : 6.970
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 6.462
RF : 6.443
FR : 6.777
FF : 6.767
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 4.352
FR : 4.553
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 6.951
RF : 6.921
FR : 7.308
FF : 7.287
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 6.777
RF : 6.675
FR : 7.034
FF : 7.114
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 4.189
FR : 4.370
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 7.617
RF : 7.013
FR : 7.365
FF : 7.976
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 6.711
RF : 6.740
FR : 7.074
FF : 7.073
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 6.081
FR : 5.988
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 7.547
RF : 7.445
FR : 7.749
FF : 7.858
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 7.360
RF : 7.322
FR : 7.677
FF : 7.648
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 4.045
FR : 4.232
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 7.212
RF : 7.191
FR : 7.547
FF : 7.535
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 6.796
RF : 6.734
FR : 7.075
FF : 7.121
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 6.308
FR : 6.961
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 7.572
RF :
FR :
FF : 8.037
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.609
RF :
FR :
FF : 7.014
Input Port : raw_loader_in
Output Port : LED[1]
RR : 5.060
RF :
FR :
FF : 5.344
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.697
Fall : 5.575
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.873
Fall : 5.751
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.873
Fall : 5.751
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.822
Fall : 5.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.934
Fall : 5.814
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 5.846
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.697
Fall : 5.575
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.697
Fall : 5.575
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.988
Fall : 5.855
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.681
Fall : 4.559
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.851
Fall : 4.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.851
Fall : 4.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.774
Fall : 4.641
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.904
Fall : 4.784
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.942
Fall : 4.820
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.681
Fall : 4.559
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.681
Fall : 4.559
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.933
Fall : 4.800
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 5.619
1 to Hi-Z : 5.741
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 5.773
1 to Hi-Z : 5.895
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 5.773
1 to Hi-Z : 5.895
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.703
1 to Hi-Z : 5.836
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 5.921
1 to Hi-Z : 6.041
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.902
1 to Hi-Z : 6.024
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 5.619
1 to Hi-Z : 5.741
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 5.619
1 to Hi-Z : 5.741
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.942
1 to Hi-Z : 6.075
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.609
1 to Hi-Z : 4.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 4.756
1 to Hi-Z : 4.878
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 4.756
1 to Hi-Z : 4.878
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.660
1 to Hi-Z : 4.793
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.893
1 to Hi-Z : 5.013
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 4.880
1 to Hi-Z : 5.002
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.609
1 to Hi-Z : 4.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.609
1 to Hi-Z : 4.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.890
1 to Hi-Z : 5.023
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 50.81 MHz
Restricted Fmax : 50.81 MHz
Clock Name : CLOCK_50
Note :
Fmax : 141.8 MHz
Restricted Fmax : 141.8 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 165.32 MHz
Restricted Fmax : 165.32 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 190.88 MHz
Restricted Fmax : 190.88 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 951.47 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -17.646
End Point TNS : -768.789
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.953
End Point TNS : -254.832
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.416
End Point TNS : -39.535
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 3.951
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 70.438
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.300
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.311
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.312
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.312
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.333
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -5.734
End Point TNS : -425.150
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.370
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.748
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.488
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.598
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.589
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.487
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -17.646
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.437
Slack : -17.634
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.425
Slack : -17.578
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.378
Slack : -17.577
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.377
Slack : -17.565
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.365
Slack : -17.539
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.330
Slack : -17.522
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.313
Slack : -17.473
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.264
Slack : -17.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.218
Slack : -17.407
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.198
Slack : -17.401
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.192
Slack : -17.396
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.187
Slack : -17.363
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.163
Slack : -17.336
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.136
Slack : -17.284
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.095
Slack : -17.283
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.074
Slack : -17.257
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.821
Slack : -17.241
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 7.032
Slack : -17.240
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.050
Slack : -17.219
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.029
Slack : -17.198
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.989
Slack : -17.197
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.748
Slack : -17.196
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 6.996
Slack : -17.189
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.742
Slack : -17.173
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.725
Slack : -17.153
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.964
Slack : -17.145
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.936
Slack : -17.140
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.706
Slack : -17.126
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.917
Slack : -17.124
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.915
Slack : -17.117
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.681
Slack : -17.110
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.901
Slack : -17.103
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.665
Slack : -17.095
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.886
Slack : -17.088
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.879
Slack : -17.068
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.859
Slack : -17.047
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.858
Slack : -17.045
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 6.845
Slack : -17.029
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.580
Slack : -17.015
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.825
Slack : -16.977
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 6.547
Slack : -16.972
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.763
Slack : -16.968
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.779
Slack : -16.952
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.763
Slack : -16.907
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.457
Slack : -16.877
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.427
Slack : -16.872
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.432
Slack : -16.856
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.667
Slack : -16.829
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.640
Slack : -16.825
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.375
Slack : -16.814
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.374
Slack : -16.814
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.605
Slack : -16.814
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.375
Slack : -16.807
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.617
Slack : -16.806
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.617
Slack : -16.801
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.611
Slack : -16.779
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.343
Slack : -16.755
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.305
Slack : -16.751
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.309
Slack : -16.749
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.305
Slack : -16.748
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.306
Slack : -16.741
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.551
Slack : -16.740
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.300
Slack : -16.732
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.543
Slack : -16.732
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.282
Slack : -16.729
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.279
Slack : -16.727
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.285
Slack : -16.722
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.532
Slack : -16.718
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.279
Slack : -16.717
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.276
Slack : -16.716
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.274
Slack : -16.713
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.265
Slack : -16.705
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.515
Slack : -16.703
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.261
Slack : -16.695
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.247
Slack : -16.689
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.500
Slack : -16.686
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.477
Slack : -16.675
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.486
Slack : -16.662
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.228
Slack : -16.659
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.209
Slack : -16.653
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.209
Slack : -16.645
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.455
Slack : -16.635
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.196
Slack : -16.633
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.191
Slack : -16.607
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.165
Slack : -16.605
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.163
Slack : -16.594
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.147
Slack : -16.589
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.399
Slack : -16.583
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.393
Slack : -16.560
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.370
Slack : -16.544
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.102
Slack : -16.537
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.087
Slack : -16.534
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.093
Slack : -16.522
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.086
Slack : -16.514
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.064
Slack : -16.508
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.070
Slack : -16.505
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.063
Slack : -16.502
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.061
Slack : -16.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 6.069
Slack : -16.495
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.047
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.953
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.193
Data Delay : 5.246
Slack : -6.701
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.987
Slack : -6.683
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.184
Data Delay : 4.967
Slack : -6.671
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.185
Data Delay : 4.956
Slack : -6.576
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.184
Data Delay : 4.860
Slack : -6.431
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.523
Slack : -6.424
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.193
Data Delay : 4.717
Slack : -6.392
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.678
Slack : -6.381
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.667
Slack : -6.374
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.185
Data Delay : 4.659
Slack : -6.368
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.654
Slack : -6.365
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 4.480
Slack : -6.342
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 4.460
Slack : -6.310
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.006
Data Delay : 4.404
Slack : -6.307
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.426
Slack : -6.304
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 4.431
Slack : -6.278
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.564
Slack : -6.272
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.398
Slack : -6.271
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.980
Data Delay : 4.391
Slack : -6.228
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.514
Slack : -6.213
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.299
Slack : -6.198
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.279
Slack : -6.196
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.020
Data Delay : 4.276
Slack : -6.185
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.284
Slack : -6.180
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.272
Slack : -6.177
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.022
Data Delay : 4.255
Slack : -6.166
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.282
Slack : -6.155
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.283
Slack : -6.153
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.252
Slack : -6.146
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 4.264
Slack : -6.143
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.233
Slack : -6.143
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.191
Data Delay : 4.434
Slack : -6.132
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.228
Slack : -6.119
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.205
Slack : -6.114
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.201
Slack : -6.101
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.237
Slack : -6.098
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.017
Data Delay : 4.181
Slack : -6.093
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.177
Slack : -6.081
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.367
Slack : -6.067
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 4.190
Slack : -6.062
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.979
Data Delay : 4.183
Slack : -6.062
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.186
Slack : -6.047
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.135
Slack : -6.045
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.164
Slack : -6.022
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.121
Slack : -6.019
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.983
Data Delay : 4.136
Slack : -6.004
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.180
Data Delay : 4.284
Slack : -5.999
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.998
Data Delay : 4.101
Slack : -5.992
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.186
Data Delay : 4.278
Slack : -5.978
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.066
Slack : -5.976
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.744
Data Delay : 4.332
Slack : -5.970
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.057
Slack : -5.963
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.048
Slack : -5.960
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.047
Slack : -5.960
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.095
Slack : -5.953
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.044
Slack : -5.952
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.184
Data Delay : 4.236
Slack : -5.950
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.062
Slack : -5.935
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.020
Slack : -5.934
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.020
Data Delay : 4.014
Slack : -5.934
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.996
Data Delay : 4.038
Slack : -5.929
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 4.039
Slack : -5.926
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.174
Data Delay : 4.200
Slack : -5.924
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 4.034
Slack : -5.922
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.009
Slack : -5.912
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.040
Slack : -5.910
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 4.039
Slack : -5.908
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.022
Data Delay : 3.986
Slack : -5.905
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.041
Slack : -5.905
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.035
Slack : -5.898
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.033
Slack : -5.894
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.007
Data Delay : 3.987
Slack : -5.892
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.028
Slack : -5.886
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 3.985
Slack : -5.881
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.192
Data Delay : 4.173
Slack : -5.879
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 3.977
Slack : -5.873
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 3.972
Slack : -5.872
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 3.998
Slack : -5.871
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.983
Data Delay : 3.988
Slack : -5.869
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.953
Data Delay : 4.016
Slack : -5.866
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 3.984
Slack : -5.858
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 3.957
Slack : -5.847
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.179
Data Delay : 4.126
Slack : -5.842
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.180
Data Delay : 4.122
Slack : -5.838
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.011
Data Delay : 3.927
Slack : -5.838
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.023
Data Delay : 3.915
Slack : -5.838
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.755
Data Delay : 4.183
Slack : -5.823
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 3.915
Slack : -5.795
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.006
Data Delay : 3.889
Slack : -5.791
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.999
Data Delay : 3.892
Slack : -5.774
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 3.892
Slack : -5.767
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.193
Data Delay : 4.060
Slack : -5.754
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 3.883
Slack : -5.731
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.968
Data Delay : 3.863
Slack : -5.722
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 3.810
Slack : -5.714
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 3.830
Slack : -5.707
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 3.813
Slack : -5.704
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 3.790
Slack : -5.698
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 3.784
Slack : -5.692
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 3.779
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.416
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 2.590
Slack : -4.401
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.693
Slack : -4.401
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.693
Slack : -3.992
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 2.580
Slack : -3.992
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 2.580
Slack : -3.992
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 2.580
Slack : -3.992
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 2.580
Slack : -3.992
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 2.580
Slack : -3.380
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 1.991
Slack : -2.977
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.201
Data Delay : 1.557
Slack : 17.325
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.153
Slack : 17.325
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.153
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.132
Slack : 17.439
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.039
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.536
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.942
Slack : 17.552
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.925
Slack : 17.552
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.925
Slack : 17.552
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.925
Slack : 17.552
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.925
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.921
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.921
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.921
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.921
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.921
Slack : 17.572
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.906
Slack : 17.592
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.885
Slack : 17.592
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.885
Slack : 17.592
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.885
Slack : 17.592
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.885
Slack : 17.592
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.885
Slack : 17.666
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.811
Slack : 17.666
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.811
Slack : 17.698
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.780
Slack : 17.698
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.780
Slack : 17.698
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.780
Slack : 17.698
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.780
Slack : 17.723
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.755
Slack : 17.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.734
Slack : 17.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.734
Slack : 17.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.734
Slack : 17.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.734
Slack : 17.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.734
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.724
Slack : 17.763
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.714
Slack : 17.763
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.714
Slack : 17.799
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.678
Slack : 17.799
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.678
Slack : 17.812
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.666
Slack : 17.812
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.666
Slack : 17.868
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.610
Slack : 17.868
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.610
Slack : 17.868
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.610
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.569
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.569
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.864
Slack : 17.945
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.533
Slack : 17.945
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.533
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.965
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.513
Slack : 17.965
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.513
Slack : 17.965
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.513
Slack : 17.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.495
Slack : 17.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.495
Slack : 17.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.495
Slack : 17.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.495
Slack : 18.001
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.477
Slack : 18.001
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.477
Slack : 18.001
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.477
Slack : 18.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.750
Slack : 18.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.750
Slack : 18.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.072
Data Delay : 2.750
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 3.951
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.906
Slack : 4.102
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.755
Slack : 4.191
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.639
Slack : 4.234
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.623
Slack : 4.246
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.586
Slack : 4.252
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.605
Slack : 4.305
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.527
Slack : 4.348
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.509
Slack : 4.352
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.468
Slack : 4.355
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.473
Slack : 4.372
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.460
Slack : 4.376
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.456
Slack : 4.381
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.449
Slack : 4.382
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.446
Slack : 4.412
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.445
Slack : 4.440
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.390
Slack : 4.443
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.385
Slack : 4.461
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.396
Slack : 4.469
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.363
Slack : 4.471
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 5.356
Slack : 4.472
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.364
Slack : 4.498
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.338
Slack : 4.505
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.327
Slack : 4.509
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.346
Slack : 4.512
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 5.342
Slack : 4.522
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.310
Slack : 4.526
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.326
Slack : 4.528
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.302
Slack : 4.535
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.320
Slack : 4.549
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.308
Slack : 4.551
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.277
Slack : 4.552
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.300
Slack : 4.554
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.303
Slack : 4.558
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.278
Slack : 4.569
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.250
Slack : 4.570
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 5.259
Slack : 4.572
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 5.282
Slack : 4.580
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.256
Slack : 4.583
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.274
Slack : 4.585
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.247
Slack : 4.595
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.260
Slack : 4.600
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.232
Slack : 4.612
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.240
Slack : 4.617
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.238
Slack : 4.618
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 5.236
Slack : 4.634
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.218
Slack : 4.636
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.194
Slack : 4.647
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.210
Slack : 4.653
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.183
Slack : 4.660
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 5.194
Slack : 4.663
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.169
Slack : 4.668
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.187
Slack : 4.713
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.123
Slack : 4.713
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.117
Slack : 4.718
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.112
Slack : 4.726
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.131
Slack : 4.746
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.086
Slack : 4.749
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 5.108
Slack : 4.759
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.077
Slack : 4.765
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.090
Slack : 4.771
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.061
Slack : 4.778
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.052
Slack : 4.787
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.033
Slack : 4.801
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.019
Slack : 4.811
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.019
Slack : 4.815
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 5.021
Slack : 4.840
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 4.990
Slack : 4.860
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.072
Data Delay : 4.971
Slack : 4.861
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 4.968
Slack : 4.865
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.066
Data Delay : 4.974
Slack : 4.870
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 4.985
Slack : 4.871
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 4.986
Slack : 4.872
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 4.986
Slack : 4.875
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 4.957
Slack : 4.902
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.066
Data Delay : 4.937
Slack : 4.904
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 4.949
Slack : 4.911
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 4.916
Slack : 4.933
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.895
Slack : 4.935
From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 4.917
Slack : 4.937
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 4.900
Slack : 4.943
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.066
Data Delay : 4.896
Slack : 4.966
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 4.861
Slack : 4.972
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 4.879
Slack : 4.976
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 4.843
Slack : 4.976
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 4.844
Slack : 4.977
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 4.880
Slack : 4.978
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.069
Data Delay : 4.858
Slack : 4.982
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.062
Data Delay : 4.861
Slack : 4.982
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 4.862
Slack : 4.985
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 4.835
Slack : 4.986
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 4.868
Slack : 4.986
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 4.834
Slack : 4.986
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 4.833
Slack : 4.992
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.088
Data Delay : 4.825
Slack : 4.998
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 4.860
Slack : 4.998
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 4.829
Slack : 4.998
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 4.829
Slack : 5.015
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 4.840
Slack : 5.016
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.066
Data Delay : 4.823
Slack : 5.016
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 4.813
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 70.438
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.049
Data Delay : 0.997
Slack : 70.846
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.055
Data Delay : 0.583
Slack : 70.846
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.055
Data Delay : 0.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.300
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.519
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.322
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.535
Slack : 0.338
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.338
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.359
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.558
Slack : 0.360
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.559
Slack : 0.368
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.579
Slack : 0.381
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.581
Slack : 0.384
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.583
Slack : 0.384
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.583
Slack : 0.432
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.631
Slack : 0.434
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.633
Slack : 0.435
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.634
Slack : 0.435
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.634
Slack : 0.450
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.649
Slack : 0.476
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.008
Slack : 0.484
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.016
Slack : 0.487
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.700
Slack : 0.489
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.702
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.703
Slack : 0.500
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.700
Slack : 0.500
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.713
Slack : 0.501
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.033
Slack : 0.504
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.505
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.506
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.507
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.706
Slack : 0.509
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.708
Slack : 0.515
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.714
Slack : 0.517
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.713
Slack : 0.520
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.719
Slack : 0.521
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.732
Slack : 0.521
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.732
Slack : 0.522
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.721
Slack : 0.526
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.737
Slack : 0.528
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.728
Slack : 0.533
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.385
Data Delay : 1.062
Slack : 0.559
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.770
Slack : 0.618
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.385
Data Delay : 1.147
Slack : 0.632
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.832
Slack : 0.633
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.832
Slack : 0.645
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.858
Slack : 0.658
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.857
Slack : 0.677
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.209
Slack : 0.682
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.385
Data Delay : 1.211
Slack : 0.686
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.263
Data Delay : 0.567
Slack : 0.690
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.903
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.897
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.363
Data Delay : 1.212
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.363
Data Delay : 1.212
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.363
Data Delay : 1.212
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.363
Data Delay : 1.212
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.363
Data Delay : 1.212
Slack : 0.705
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.901
Slack : 0.706
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.905
Slack : 0.713
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.912
Slack : 0.718
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.917
Slack : 0.720
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.231
Data Delay : 0.633
Slack : 0.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.944
Slack : 0.735
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.948
Slack : 0.736
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.385
Data Delay : 1.265
Slack : 0.738
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.951
Slack : 0.739
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.952
Slack : 0.744
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.745
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.958
Slack : 0.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.959
Slack : 0.748
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.953
Slack : 0.748
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.749
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.749
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.765
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.976
Slack : 0.765
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.976
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.496
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.696
Slack : 0.498
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.698
Slack : 0.508
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.708
Slack : 0.604
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.804
Slack : 0.720
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.919
Slack : 0.720
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.941
Slack : 0.741
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.941
Slack : 0.747
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.947
Slack : 0.754
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.954
Slack : 0.754
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.975
Slack : 0.755
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.976
Slack : 0.756
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.977
Slack : 0.777
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.976
Slack : 0.839
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.038
Slack : 0.858
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.057
Slack : 0.868
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.069
Slack : 0.913
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.134
Slack : 0.952
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.157
Slack : 0.961
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.166
Slack : 0.994
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.242
Data Delay : 0.896
Slack : 1.014
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.214
Slack : 1.048
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.247
Slack : 1.079
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.286
Slack : 1.096
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.317
Slack : 1.097
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.297
Slack : 1.108
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.215
Data Delay : 1.037
Slack : 1.110
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.310
Slack : 1.117
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.322
Slack : 1.119
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.242
Data Delay : 1.021
Slack : 1.137
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.342
Slack : 1.164
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.363
Slack : 1.164
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.363
Slack : 1.164
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.363
Slack : 1.164
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.363
Slack : 1.170
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.391
Slack : 1.171
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.376
Slack : 1.172
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.372
Slack : 1.197
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.402
Slack : 1.212
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.242
Data Delay : 1.114
Slack : 1.214
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.435
Slack : 1.222
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.421
Slack : 1.225
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.424
Slack : 1.225
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.446
Slack : 1.230
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.435
Slack : 1.242
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.441
Slack : 1.248
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.215
Data Delay : 1.177
Slack : 1.249
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.454
Slack : 1.252
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.457
Slack : 1.256
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.215
Data Delay : 1.185
Slack : 1.295
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.494
Slack : 1.303
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.524
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.304
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.815
Slack : 1.322
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.242
Data Delay : 1.224
Slack : 1.338
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.543
Slack : 1.388
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.588
Slack : 1.399
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.598
Slack : 1.403
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.603
Slack : 1.408
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.607
Slack : 1.415
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.614
Slack : 1.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.627
Slack : 1.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.627
Slack : 1.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.627
Slack : 1.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.627
Slack : 1.427
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.627
Slack : 1.432
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.653
Slack : 1.434
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.639
Slack : 1.437
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.637
Slack : 1.449
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.648
Slack : 1.469
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.674
Slack : 1.469
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.674
Slack : 1.469
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.674
Slack : 1.469
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.674
Slack : 1.470
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.669
Slack : 1.471
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.215
Data Delay : 1.400
Slack : 1.478
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.677
Slack : 1.497
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.702
Slack : 1.498
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.697
Slack : 1.514
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.735
Slack : 1.517
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.716
Slack : 1.522
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.721
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.312
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.313
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.511
Slack : 0.313
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.511
Slack : 0.321
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.519
Slack : 0.499
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.698
Slack : 0.501
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.700
Slack : 0.501
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.699
Slack : 0.502
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.503
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.504
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.505
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.506
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.507
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.705
Slack : 0.512
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.710
Slack : 0.512
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.710
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.514
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.712
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.517
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.715
Slack : 0.517
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.715
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.716
Slack : 0.519
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.718
Slack : 0.534
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.733
Slack : 0.534
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.733
Slack : 0.546
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.745
Slack : 0.551
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.750
Slack : 0.634
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.833
Slack : 0.730
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.929
Slack : 0.743
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.942
Slack : 0.746
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.945
Slack : 0.748
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.748
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.946
Slack : 0.749
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.750
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.948
Slack : 0.751
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.949
Slack : 0.752
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.752
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.753
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.754
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.755
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.954
Slack : 0.757
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.955
Slack : 0.758
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.956
Slack : 0.759
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.957
Slack : 0.759
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.759
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.760
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.958
Slack : 0.760
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.958
Slack : 0.760
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.959
Slack : 0.761
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.959
Slack : 0.762
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.960
Slack : 0.762
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.960
Slack : 0.762
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.961
Slack : 0.763
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.961
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.769
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.967
Slack : 0.769
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.967
Slack : 0.770
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.968
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.788
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.987
Slack : 0.793
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.992
Slack : 0.832
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.031
Slack : 0.835
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.034
Slack : 0.837
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.036
Slack : 0.837
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.035
Slack : 0.838
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.037
Slack : 0.839
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.037
Slack : 0.839
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.038
Slack : 0.842
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.041
Slack : 0.844
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.042
Slack : 0.845
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.044
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.044
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.044
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.045
Slack : 0.848
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.046
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.047
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.047
Slack : 0.849
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.047
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.048
Slack : 0.850
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.048
Slack : 0.851
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.050
Slack : 0.853
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.051
Slack : 0.854
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.052
Slack : 0.855
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.053
Slack : 0.855
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.054
Slack : 0.855
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.054
Slack : 0.856
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.054
Slack : 0.856
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.055
Slack : 0.857
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.055
Slack : 0.858
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.056
Slack : 0.859
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.058
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.312
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.320
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.710
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.915
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.333
From Node : debouncer:debounce_autofire|r_State
To Node : debouncer:debounce_autofire|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.511
Slack : 0.333
From Node : debouncer:debounce_turbo|r_State
To Node : debouncer:debounce_turbo|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.511
Slack : 0.348
From Node : debouncer:debounce_turbo|r_Count[20]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.547
Slack : 0.349
From Node : debouncer:debounce_autofire|r_Count[20]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.547
Slack : 0.502
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.503
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.504
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.702
Slack : 0.505
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.505
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.506
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.506
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.506
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.506
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.704
Slack : 0.507
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.706
Slack : 0.507
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.705
Slack : 0.508
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.707
Slack : 0.508
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.707
Slack : 0.509
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.708
Slack : 0.509
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.707
Slack : 0.509
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.708
Slack : 0.510
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.709
Slack : 0.510
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.709
Slack : 0.510
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.708
Slack : 0.510
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.708
Slack : 0.514
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.713
Slack : 0.515
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.713
Slack : 0.517
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.716
Slack : 0.517
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.716
Slack : 0.517
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.716
Slack : 0.517
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.716
Slack : 0.519
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.718
Slack : 0.519
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.717
Slack : 0.522
From Node : debouncer:debounce_turbo|r_Count[6]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.721
Slack : 0.747
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.946
Slack : 0.748
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.748
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.748
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.748
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.749
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.749
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.750
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.949
Slack : 0.750
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.948
Slack : 0.750
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.948
Slack : 0.750
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.949
Slack : 0.751
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 0.948
Slack : 0.751
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.751
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.751
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.949
Slack : 0.751
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.752
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.752
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.753
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.753
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.951
Slack : 0.753
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.753
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.951
Slack : 0.754
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.754
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.755
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.954
Slack : 0.755
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.953
Slack : 0.757
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.956
Slack : 0.758
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.758
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.758
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.758
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.759
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.759
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.759
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.759
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.957
Slack : 0.759
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.957
Slack : 0.760
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.959
Slack : 0.760
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.959
Slack : 0.760
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.958
Slack : 0.761
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.761
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.761
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.761
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.762
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.961
Slack : 0.762
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.960
Slack : 0.763
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.962
Slack : 0.764
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.963
Slack : 0.764
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.963
Slack : 0.764
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.962
Slack : 0.764
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.962
Slack : 0.765
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.964
Slack : 0.765
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.964
Slack : 0.766
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.965
Slack : 0.766
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.964
Slack : 0.766
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.964
Slack : 0.768
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 0.965
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -5.734
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.933
Slack : -5.734
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.931
Slack : -5.734
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.930
Slack : -5.733
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.929
Slack : -5.733
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.092
Data Delay : 3.928
Slack : -5.494
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 3.668
Slack : -5.484
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.116
Data Delay : 3.657
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.101
Data Delay : 3.534
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.255
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.550
Slack : -5.255
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.550
Slack : -5.255
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.550
Slack : -5.255
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.550
Slack : -5.255
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.550
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.095
Data Delay : 3.530
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.538
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.095
Data Delay : 3.530
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.095
Data Delay : 3.530
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.095
Data Delay : 3.530
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -5.246
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.540
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 3.548
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 3.548
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 3.548
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 3.548
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.209
Data Delay : 3.548
Slack : -4.960
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.201
Data Delay : 3.540
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.537
Slack : -4.942
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.215
Data Delay : 3.536
Slack : -4.938
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.549
Slack : -4.938
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.549
Slack : -4.938
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.549
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.227
Data Delay : 3.539
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.933
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.228
Data Delay : 3.540
Slack : -4.932
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.217
Data Delay : 3.528
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.598
Data Delay : 3.196
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.599
Data Delay : 3.197
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.599
Data Delay : 3.197
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.599
Data Delay : 3.197
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.198
Slack : 3.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.588
Data Delay : 3.186
Slack : 3.377
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.209
Slack : 3.377
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.209
Slack : 3.377
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.209
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.194
Slack : 3.384
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.586
Data Delay : 3.198
Slack : 3.398
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.571
Data Delay : 3.197
Slack : 3.402
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.209
Slack : 3.402
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.209
Slack : 3.402
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.209
Slack : 3.402
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.209
Slack : 3.402
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.579
Data Delay : 3.209
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.194
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.273
Data Delay : 3.197
Slack : 3.697
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.188
Slack : 3.697
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.188
Slack : 3.697
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.188
Slack : 3.697
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.188
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.209
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.209
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.211
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.211
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.211
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.211
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.211
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.209
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.209
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.209
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.209
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.209
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.257
Data Delay : 3.196
Slack : 3.884
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.226
Data Delay : 3.283
Slack : 3.898
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.227
Data Delay : 3.298
Slack : 4.106
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.254
Data Delay : 3.530
Slack : 4.106
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.252
Data Delay : 3.528
Slack : 4.106
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.526
Slack : 4.106
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.251
Data Delay : 3.527
Slack : 4.106
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.526
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.851
Actual Width : 5.001
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.496
Actual Width : 9.726
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[9]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[6]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[8]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[9]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[10]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[11]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[12]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[2]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[6]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[8]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[9]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.668
Actual Width : 20.884
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.695
Actual Width : 20.845
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.696
Actual Width : 20.846
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.697
Actual Width : 20.852
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.700
Actual Width : 20.855
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.702
Actual Width : 20.857
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.703
Actual Width : 20.887
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.703
Actual Width : 20.887
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.703
Actual Width : 20.887
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.703
Actual Width : 20.887
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.487
Actual Width : 35.703
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.489
Actual Width : 35.705
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.600
Actual Width : 35.784
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.601
Actual Width : 35.785
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.727
Actual Width : 35.727
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.729
Actual Width : 35.729
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.760
Actual Width : 35.760
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.761
Actual Width : 35.761
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 2.750
Fall : 2.995
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 2.161
Fall : 2.433
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 1.949
Fall : 2.264
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 2.688
Fall : 2.988
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 2.750
Fall : 2.995
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 2.083
Fall : 2.380
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : 2.794
Fall : 3.243
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.036
Fall : 3.389
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : 3.044
Fall : 3.515
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 4.708
Fall : 5.013
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 4.016
Fall : 4.288
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 3.671
Fall : 3.986
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 4.708
Fall : 5.013
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 4.196
Fall : 4.441
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 3.914
Fall : 4.203
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 4.436
Fall : 4.761
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.138
Fall : 1.341
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.589
Fall : 2.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -1.329
Fall : -1.636
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -1.427
Fall : -1.697
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -1.329
Fall : -1.636
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -1.526
Fall : -1.822
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -2.137
Fall : -2.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -1.483
Fall : -1.777
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : -1.419
Fall : -1.876
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.529
Fall : -2.866
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : -1.649
Fall : -2.117
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -2.653
Fall : -2.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -2.798
Fall : -3.068
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -2.941
Fall : -3.248
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -2.653
Fall : -2.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -3.046
Fall : -3.299
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -2.752
Fall : -3.046
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -3.483
Fall : -3.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.586
Fall : -0.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.849
Fall : -1.071
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 9.235
Fall : 9.132
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.964
Fall : 8.893
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.034
Fall : 8.888
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 9.159
Fall : 9.077
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 8.739
Fall : 8.696
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 9.235
Fall : 9.132
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.940
Fall : 8.877
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.481
Fall : 8.437
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.014
Fall : 8.932
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.962
Fall : 8.871
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.800
Fall : 8.713
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.400
Fall : 8.326
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.685
Fall : 8.594
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.445
Fall : 8.392
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.664
Fall : 8.649
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.722
Fall : 8.655
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.962
Fall : 8.871
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.918
Fall : 8.805
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.992
Fall : 2.917
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.974
Fall : 2.902
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.053
Fall : 2.959
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.972
Fall : 2.900
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.461
Fall : 5.467
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.788
Fall : 4.759
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.047
Fall : 5.081
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.960
Fall : 4.974
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.428
Fall : 5.467
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.108
Fall : 5.147
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.461
Fall : 5.392
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.510
Fall : 4.536
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.431
Fall : 5.403
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.319
Fall : 5.394
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.290
Fall : 5.351
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.301
Fall : 5.365
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.301
Fall : 5.365
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.290
Fall : 5.366
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.319
Fall : 5.388
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.319
Fall : 5.388
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.293
Fall : 5.397
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.057
Fall : 2.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.468
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.400
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.358
Fall : 7.270
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.806
Fall : 6.701
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.271
Fall : 7.200
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.331
Fall : 7.270
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.888
Fall : 6.877
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.358
Fall : 7.256
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.121
Fall : 7.071
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.608
Fall : 6.556
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.026
Fall : 6.959
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.930
Fall : 6.849
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.562
Fall : 6.475
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.634
Fall : 6.601
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.853
Fall : 6.788
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.814
Fall : 6.745
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.763
Fall : 6.706
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.903
Fall : 6.849
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.825
Fall : 6.761
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.930
Fall : 6.832
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 7.720
Fall : 7.262
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 7.720
Fall : 7.262
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.306
Fall : 6.242
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 5.935
Fall : 5.822
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 5.947
Fall : 5.831
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.517
Fall : 6.349
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 5.965
Fall : 5.799
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 5.705
Fall : 5.626
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.517
Fall : 6.349
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.517
Fall : 6.349
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.597
Fall : 2.522
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.139
Fall : 6.025
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.139
Fall : 6.025
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.055
Fall : 5.987
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.107
Fall : 5.976
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 5.673
Fall : 5.574
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.595
Fall : 2.520
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.361
Fall : 3.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.594
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.647
Fall : 2.553
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.648
Fall : 2.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.675
Fall : 6.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.814
Fall : 7.700
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.914
Fall : 7.793
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.007
Fall : 7.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.884
Fall : 6.830
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.900
Fall : 7.785
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.017
Fall : 7.947
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.675
Fall : 6.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.590
Fall : 7.547
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.601
Fall : 6.539
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.487
Fall : 7.400
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.249
Fall : 7.157
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.554
Fall : 7.455
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.601
Fall : 6.539
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.339
Fall : 7.308
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.808
Fall : 7.734
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.758
Fall : 6.696
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.500
Fall : 7.427
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.621
Fall : 2.545
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.602
Fall : 2.530
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.681
Fall : 2.587
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.002
Fall : 4.024
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.228
Fall : 4.206
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.477
Fall : 4.495
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.394
Fall : 4.390
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.841
Fall : 4.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.536
Fall : 4.558
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.916
Fall : 4.847
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.002
Fall : 4.024
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.829
Fall : 4.797
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 4.397
Fall : 4.467
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 4.369
Fall : 4.426
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.379
Fall : 4.439
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.379
Fall : 4.439
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 4.369
Fall : 4.440
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.397
Fall : 4.462
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.397
Fall : 4.462
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.373
Fall : 4.471
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.685
Fall : 2.591
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.091
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.022
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.885
Fall : 5.812
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.887
Fall : 5.848
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.220
Fall : 6.049
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 6.425
Fall : 6.385
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.051
Fall : 6.022
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.464
Fall : 6.364
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.162
Fall : 6.130
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.885
Fall : 5.812
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.182
Fall : 6.136
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.696
Fall : 4.646
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.570
Fall : 5.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.352
Fall : 5.306
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 5.926
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.696
Fall : 4.646
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.890
Fall : 5.834
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.953
Fall : 5.917
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.046
Fall : 4.982
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.092
Fall : 6.016
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.879
Fall : 3.818
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.663
Fall : 5.258
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.932
Fall : 3.854
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.879
Fall : 3.818
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.890
Fall : 3.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.661
Fall : 3.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.989
Fall : 3.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.661
Fall : 3.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.518
Fall : 4.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.518
Fall : 4.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.241
Fall : 2.165
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.499
Fall : 3.444
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.947
Fall : 3.877
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.907
Fall : 3.758
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.915
Fall : 3.830
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.499
Fall : 3.444
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.237
Fall : 2.161
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.236
Fall : 2.160
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.005
Fall : 3.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.238
Fall : 2.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.290
Fall : 2.196
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.291
Fall : 2.197
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.281
RF :
FR :
FF : 4.438
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 6.287
RF : 6.221
FR : 6.551
FF : 6.493
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 6.070
RF : 5.980
FR : 6.334
FF : 6.252
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 4.092
FR : 4.238
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 6.588
RF : 6.490
FR : 6.895
FF : 6.805
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 6.362
RF : 6.225
FR : 6.629
FF : 6.576
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 3.897
FR : 4.014
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 7.364
RF : 7.269
FR : 7.661
FF : 7.574
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 6.313
RF : 6.258
FR : 6.620
FF : 6.534
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 5.571
FR : 5.363
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 7.218
RF : 7.124
FR : 7.455
FF : 7.369
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 6.929
RF : 6.814
FR : 7.198
FF : 7.091
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 3.795
FR : 3.949
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 6.803
RF : 6.673
FR : 7.092
FF : 6.970
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 6.424
RF : 6.383
FR : 6.706
FF : 6.647
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 5.697
FR : 6.366
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 7.137
RF :
FR :
FF : 7.416
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.286
RF :
FR :
FF : 6.563
Input Port : raw_loader_in
Output Port : LED[1]
RR : 4.774
RF :
FR :
FF : 4.979
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.142
RF :
FR :
FF : 4.299
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 6.059
RF : 5.996
FR : 6.323
FF : 6.266
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 5.855
RF : 5.766
FR : 6.119
FF : 6.036
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 3.955
FR : 4.103
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 6.349
RF : 6.252
FR : 6.656
FF : 6.565
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 6.135
RF : 5.966
FR : 6.357
FF : 6.348
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 3.770
FR : 3.888
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 6.936
RF : 6.273
FR : 6.676
FF : 7.110
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 6.089
RF : 6.032
FR : 6.391
FF : 6.307
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 5.444
FR : 5.238
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 6.862
RF : 6.658
FR : 7.001
FF : 6.992
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 6.679
RF : 6.566
FR : 6.950
FF : 6.843
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 3.668
FR : 3.824
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 6.558
RF : 6.431
FR : 6.846
FF : 6.725
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 6.192
RF : 6.075
FR : 6.428
FF : 6.413
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 5.547
FR : 6.219
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.875
RF :
FR :
FF : 7.154
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.030
RF :
FR :
FF : 6.299
Input Port : raw_loader_in
Output Port : LED[1]
RR : 4.610
RF :
FR :
FF : 4.813
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.133
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.292
Fall : 5.150
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.292
Fall : 5.150
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.281
Fall : 5.156
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.377
Fall : 5.266
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.382
Fall : 5.240
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.133
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.133
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.433
Fall : 5.308
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.230
Fall : 4.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.383
Fall : 4.241
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.383
Fall : 4.241
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.340
Fall : 4.215
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.461
Fall : 4.350
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.469
Fall : 4.327
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.230
Fall : 4.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.230
Fall : 4.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.486
Fall : 4.361
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.987
1 to Hi-Z : 5.129
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 5.112
1 to Hi-Z : 5.254
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 5.112
1 to Hi-Z : 5.254
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.135
1 to Hi-Z : 5.260
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 5.317
1 to Hi-Z : 5.428
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.233
1 to Hi-Z : 5.375
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.987
1 to Hi-Z : 5.129
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.987
1 to Hi-Z : 5.129
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.329
1 to Hi-Z : 5.454
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.089
1 to Hi-Z : 4.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 4.210
1 to Hi-Z : 4.352
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 4.210
1 to Hi-Z : 4.352
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.201
1 to Hi-Z : 4.326
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.404
1 to Hi-Z : 4.515
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 4.326
1 to Hi-Z : 4.468
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.089
1 to Hi-Z : 4.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.089
1 to Hi-Z : 4.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.386
1 to Hi-Z : 4.511
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -15.170
End Point TNS : -635.207
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -5.647
End Point TNS : -193.116
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -3.810
End Point TNS : -35.303
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 6.131
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 70.800
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.179
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.186
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.201
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.684
End Point TNS : -359.024
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 2.507
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.784
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.208
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.609
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.525
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -15.170
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.221
Slack : -15.168
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.219
Slack : -15.161
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.206
Slack : -15.156
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.201
Slack : -15.151
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.202
Slack : -15.132
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.177
Slack : -15.086
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.131
Slack : -15.069
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.120
Slack : -15.068
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.113
Slack : -15.060
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.105
Slack : -15.046
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.091
Slack : -15.040
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.085
Slack : -15.026
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.077
Slack : -15.005
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.050
Slack : -14.983
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.028
Slack : -14.973
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 5.018
Slack : -14.970
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 5.021
Slack : -14.908
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.953
Slack : -14.884
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.929
Slack : -14.876
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.921
Slack : -14.875
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.920
Slack : -14.871
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.916
Slack : -14.859
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.904
Slack : -14.853
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.023
Data Delay : 4.904
Slack : -14.852
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.897
Slack : -14.850
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.895
Slack : -14.792
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.851
Slack : -14.778
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.823
Slack : -14.745
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.804
Slack : -14.740
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.800
Slack : -14.724
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.624
Slack : -14.697
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.587
Slack : -14.696
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.589
Slack : -14.682
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.727
Slack : -14.676
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.579
Slack : -14.644
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.544
Slack : -14.644
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.535
Slack : -14.642
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.701
Slack : -14.636
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.696
Slack : -14.628
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.528
Slack : -14.618
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.509
Slack : -14.607
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.652
Slack : -14.599
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.659
Slack : -14.599
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.504
Slack : -14.564
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.624
Slack : -14.505
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.396
Slack : -14.492
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.390
Slack : -14.484
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.544
Slack : -14.477
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.536
Slack : -14.468
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.358
Slack : -14.464
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.361
Slack : -14.461
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.521
Slack : -14.455
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.515
Slack : -14.454
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.514
Slack : -14.433
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.492
Slack : -14.430
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.475
Slack : -14.427
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.324
Slack : -14.412
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.312
Slack : -14.411
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.309
Slack : -14.395
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.454
Slack : -14.395
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.454
Slack : -14.390
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.279
Slack : -14.390
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.287
Slack : -14.388
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.286
Slack : -14.384
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.443
Slack : -14.381
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.276
Slack : -14.380
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.182
Data Delay : 4.272
Slack : -14.371
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.261
Slack : -14.370
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.265
Slack : -14.364
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.259
Slack : -14.364
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.267
Slack : -14.363
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.259
Slack : -14.361
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.420
Slack : -14.358
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.253
Slack : -14.351
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.411
Slack : -14.351
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.240
Slack : -14.347
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.242
Slack : -14.345
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.242
Slack : -14.343
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.403
Slack : -14.337
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.234
Slack : -14.333
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.392
Slack : -14.332
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.223
Slack : -14.328
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.217
Slack : -14.327
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.224
Slack : -14.324
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.384
Slack : -14.324
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.214
Slack : -14.323
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.221
Slack : -14.312
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.371
Slack : -14.310
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.205
Slack : -14.299
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.192
Slack : -14.290
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.186
Slack : -14.287
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.192
Slack : -14.279
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.338
Slack : -14.276
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.015
Data Delay : 4.335
Slack : -14.273
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.169
Slack : -14.266
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.163
Slack : -14.259
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.155
Slack : -14.254
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.144
Slack : -14.253
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.313
Slack : -14.247
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.147
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -5.647
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.048
Data Delay : 3.688
Slack : -5.505
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.053
Data Delay : 3.541
Slack : -5.496
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.531
Slack : -5.487
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.053
Data Delay : 3.523
Slack : -5.388
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.055
Data Delay : 3.422
Slack : -5.297
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.052
Data Delay : 3.334
Slack : -5.269
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.048
Data Delay : 3.310
Slack : -5.262
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.297
Slack : -5.257
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.053
Data Delay : 3.293
Slack : -5.252
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.053
Data Delay : 3.288
Slack : -5.240
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.275
Slack : -5.173
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.051
Data Delay : 3.211
Slack : -5.171
From Node : kempston[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.206
Slack : -5.075
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.058
Data Delay : 3.106
Slack : -5.071
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.106
Slack : -5.054
From Node : kempston[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.052
Data Delay : 3.091
Slack : -5.041
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.062
Data Delay : 3.068
Slack : -5.037
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 3.072
Slack : -5.003
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.049
Data Delay : 3.043
Slack : -4.988
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.060
Data Delay : 3.017
Slack : -4.980
From Node : kempston[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.058
Data Delay : 3.011
Slack : -4.888
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.049
Data Delay : 2.928
Slack : -4.841
From Node : kempston[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.056
Data Delay : 2.874
Slack : -4.818
From Node : kempston[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.057
Data Delay : 2.850
Slack : -4.296
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 3.011
Slack : -4.234
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.968
Slack : -4.218
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.359
Data Delay : 2.948
Slack : -4.203
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.936
Slack : -4.179
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.919
Slack : -4.171
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.887
Slack : -4.150
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.884
Slack : -4.146
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.885
Slack : -4.141
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.846
Slack : -4.141
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.851
Slack : -4.131
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.840
Slack : -4.130
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.836
Slack : -4.127
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.842
Slack : -4.094
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.834
Slack : -4.093
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.808
Slack : -4.093
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.815
Slack : -4.092
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.811
Slack : -4.090
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.811
Slack : -4.088
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.822
Slack : -4.081
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.814
Slack : -4.078
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.789
Slack : -4.077
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 2.785
Slack : -4.070
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 2.783
Slack : -4.069
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.779
Slack : -4.065
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.799
Slack : -4.050
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.797
Slack : -4.046
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.780
Slack : -4.035
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.353
Data Delay : 2.771
Slack : -4.031
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.765
Slack : -4.027
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.765
Slack : -3.992
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.706
Slack : -3.979
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.701
Slack : -3.972
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.677
Slack : -3.971
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.683
Slack : -3.964
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.364
Data Delay : 2.689
Slack : -3.963
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.360
Data Delay : 2.692
Slack : -3.962
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.710
Slack : -3.956
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.671
Slack : -3.956
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.202
Data Delay : 2.843
Slack : -3.948
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.675
Slack : -3.938
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.643
Slack : -3.933
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.643
Slack : -3.931
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.382
Data Delay : 2.638
Slack : -3.926
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.674
Slack : -3.925
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.665
Slack : -3.925
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.667
Slack : -3.924
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.633
Slack : -3.921
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.670
Slack : -3.916
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.665
Slack : -3.912
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.621
Slack : -3.911
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.631
Slack : -3.911
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.637
Slack : -3.910
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.641
Slack : -3.907
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.638
Slack : -3.906
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.627
Slack : -3.903
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.619
Slack : -3.902
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.635
Slack : -3.901
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.622
Slack : -3.899
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.620
Slack : -3.897
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 2.610
Slack : -3.894
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.636
Slack : -3.892
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.601
Slack : -3.891
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.631
Slack : -3.887
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.643
Slack : -3.882
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.594
Slack : -3.882
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.386
Data Delay : 2.585
Slack : -3.858
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.209
Data Delay : 2.738
Slack : -3.835
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.567
Slack : -3.828
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.539
Slack : -3.824
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.558
Slack : -3.819
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.529
Slack : -3.810
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.521
Slack : -3.805
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.366
Data Delay : 2.528
Slack : -3.793
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.509
Slack : -3.792
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.537
Slack : -3.784
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.489
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -3.810
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.955
Slack : -3.810
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.955
Slack : -3.765
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 1.841
Slack : -3.559
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.881
Slack : -3.559
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.881
Slack : -3.559
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.881
Slack : -3.559
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.881
Slack : -3.559
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.881
Slack : -3.160
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 1.495
Slack : -2.963
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 1.285
Slack : 18.646
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.914
Slack : 18.646
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.914
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.659
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.901
Slack : 18.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.827
Slack : 18.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.814
Slack : 18.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.814
Slack : 18.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.814
Slack : 18.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.814
Slack : 18.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.814
Slack : 18.783
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.777
Slack : 18.788
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.772
Slack : 18.789
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.771
Slack : 18.789
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.771
Slack : 18.789
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.771
Slack : 18.789
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.771
Slack : 18.796
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.764
Slack : 18.796
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.764
Slack : 18.796
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.764
Slack : 18.796
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.764
Slack : 18.796
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.764
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.759
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.759
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.759
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.759
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.759
Slack : 18.853
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.707
Slack : 18.853
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.707
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.665
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.652
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.652
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.652
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.652
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.652
Slack : 18.911
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.652
Slack : 18.911
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.652
Slack : 18.912
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.651
Slack : 18.912
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.651
Slack : 18.917
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.646
Slack : 18.917
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.646
Slack : 18.917
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.646
Slack : 18.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.642
Slack : 18.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.642
Slack : 18.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.645
Slack : 18.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.645
Slack : 18.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.645
Slack : 18.926
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.634
Slack : 18.926
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.634
Slack : 18.974
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.589
Slack : 18.974
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.589
Slack : 18.980
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.583
Slack : 18.980
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.583
Slack : 18.980
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.583
Slack : 19.022
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.718
Slack : 19.022
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.718
Slack : 19.022
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.718
Slack : 19.022
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.718
Slack : 19.022
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.718
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.717
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.717
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.717
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.717
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.717
Slack : 19.031
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.529
Slack : 19.031
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.529
Slack : 19.039
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.524
Slack : 19.039
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.524
Slack : 19.045
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.518
Slack : 19.045
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.518
Slack : 19.045
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.518
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.511
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.511
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.076
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.487
Slack : 19.076
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.487
Slack : 19.077
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.486
Slack : 19.077
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.486
Slack : 19.085
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.655
Slack : 19.085
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.655
Slack : 19.085
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.098
Data Delay : 1.655
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 6.131
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.777
Slack : 6.191
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.697
Slack : 6.206
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.702
Slack : 6.293
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.615
Slack : 6.314
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.574
Slack : 6.322
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.586
Slack : 6.340
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.546
Slack : 6.351
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.557
Slack : 6.353
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.534
Slack : 6.369
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.511
Slack : 6.395
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.492
Slack : 6.395
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.491
Slack : 6.408
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.479
Slack : 6.419
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.489
Slack : 6.421
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.466
Slack : 6.422
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.463
Slack : 6.433
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.458
Slack : 6.444
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.464
Slack : 6.448
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.443
Slack : 6.454
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.453
Slack : 6.462
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.425
Slack : 6.463
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.424
Slack : 6.469
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.438
Slack : 6.470
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.417
Slack : 6.482
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.405
Slack : 6.490
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.396
Slack : 6.494
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.397
Slack : 6.500
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.408
Slack : 6.500
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.380
Slack : 6.504
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.375
Slack : 6.505
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.403
Slack : 6.506
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.385
Slack : 6.515
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.392
Slack : 6.516
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.389
Slack : 6.527
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.380
Slack : 6.529
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.379
Slack : 6.531
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.374
Slack : 6.539
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.348
Slack : 6.544
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.344
Slack : 6.547
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.359
Slack : 6.552
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.354
Slack : 6.553
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.332
Slack : 6.558
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.329
Slack : 6.559
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.349
Slack : 6.561
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.326
Slack : 6.564
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.316
Slack : 6.570
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.318
Slack : 6.572
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.316
Slack : 6.577
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.328
Slack : 6.578
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.309
Slack : 6.579
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.327
Slack : 6.583
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.324
Slack : 6.589
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.316
Slack : 6.593
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.295
Slack : 6.609
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.278
Slack : 6.614
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.292
Slack : 6.620
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.286
Slack : 6.630
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.278
Slack : 6.631
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.256
Slack : 6.631
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.249
Slack : 6.635
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.244
Slack : 6.638
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.242
Slack : 6.643
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.263
Slack : 6.653
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 3.235
Slack : 6.658
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.233
Slack : 6.661
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 3.228
Slack : 6.665
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.222
Slack : 6.669
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.065
Data Delay : 3.206
Slack : 6.678
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.063
Data Delay : 3.199
Slack : 6.684
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.201
Slack : 6.690
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.201
Slack : 6.690
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.063
Data Delay : 3.187
Slack : 6.691
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.194
Slack : 6.693
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.194
Slack : 6.699
From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.036
Data Delay : 3.204
Slack : 6.702
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.206
Slack : 6.707
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.180
Slack : 6.709
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.178
Slack : 6.720
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.167
Slack : 6.725
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.166
Slack : 6.742
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.137
Slack : 6.748
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.143
Slack : 6.748
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.157
Slack : 6.748
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 3.132
Slack : 6.749
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.159
Slack : 6.754
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.137
Slack : 6.754
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.131
Slack : 6.760
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 3.133
Slack : 6.764
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.121
Slack : 6.764
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.121
Slack : 6.766
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.113
Slack : 6.769
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.138
Slack : 6.771
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.116
Slack : 6.773
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.106
Slack : 6.774
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.032
Data Delay : 3.133
Slack : 6.778
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 3.115
Slack : 6.781
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.043
Data Delay : 3.116
Slack : 6.787
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.042
Data Delay : 3.111
Slack : 6.787
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.030
Data Delay : 3.122
Slack : 6.793
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.036
Data Delay : 3.110
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 70.800
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.032
Data Delay : 0.644
Slack : 71.080
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.037
Data Delay : 0.359
Slack : 71.080
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.037
Data Delay : 0.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.179
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.307
Slack : 0.183
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.317
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.195
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.316
Slack : 0.195
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.316
Slack : 0.211
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.331
Slack : 0.213
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.333
Slack : 0.216
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.344
Slack : 0.221
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.342
Slack : 0.227
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.347
Slack : 0.230
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.350
Slack : 0.251
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.372
Slack : 0.252
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.373
Slack : 0.253
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.374
Slack : 0.254
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.375
Slack : 0.273
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.393
Slack : 0.281
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.599
Slack : 0.287
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.418
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.419
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.607
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.420
Slack : 0.295
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.426
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.417
Slack : 0.300
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.301
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.301
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.302
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.423
Slack : 0.303
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.423
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.426
Slack : 0.308
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.428
Slack : 0.310
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.438
Slack : 0.311
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.431
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.630
Slack : 0.314
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.442
Slack : 0.315
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.436
Slack : 0.316
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.233
Data Delay : 0.633
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.448
Slack : 0.341
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.469
Slack : 0.364
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.485
Slack : 0.367
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.498
Slack : 0.370
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.491
Slack : 0.371
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.233
Data Delay : 0.688
Slack : 0.376
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.497
Slack : 0.401
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.529
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.708
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.708
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.708
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.708
Slack : 0.403
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.708
Slack : 0.404
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.334
Slack : 0.413
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.533
Slack : 0.413
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.731
Slack : 0.416
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.535
Slack : 0.417
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.537
Slack : 0.419
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.538
Slack : 0.424
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.545
Slack : 0.426
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.137
Data Delay : 0.373
Slack : 0.436
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.567
Slack : 0.437
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.557
Slack : 0.437
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.568
Slack : 0.446
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.571
Slack : 0.447
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.578
Slack : 0.448
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.579
Slack : 0.449
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.450
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.581
Slack : 0.451
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.582
Slack : 0.452
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.233
Data Delay : 0.769
Slack : 0.459
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.587
Slack : 0.463
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.582
Slack : 0.463
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.591
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.187
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.193
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.297
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.417
Slack : 0.298
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.418
Slack : 0.298
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.418
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.301
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.424
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.306
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.426
Slack : 0.306
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.426
Slack : 0.306
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.426
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.311
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.431
Slack : 0.317
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.438
Slack : 0.320
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.441
Slack : 0.326
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.447
Slack : 0.330
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.451
Slack : 0.372
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.493
Slack : 0.441
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.561
Slack : 0.446
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.566
Slack : 0.448
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.449
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.449
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.454
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.574
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.575
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.575
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.575
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.575
Slack : 0.457
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.459
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.579
Slack : 0.460
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.465
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.585
Slack : 0.465
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.585
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.587
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.587
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.587
Slack : 0.468
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.588
Slack : 0.468
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.588
Slack : 0.469
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.590
Slack : 0.473
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.594
Slack : 0.509
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.629
Slack : 0.511
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.631
Slack : 0.511
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.631
Slack : 0.511
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.631
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.632
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.632
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.632
Slack : 0.514
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.634
Slack : 0.514
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.634
Slack : 0.514
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.634
Slack : 0.515
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.635
Slack : 0.516
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.636
Slack : 0.517
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.637
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.638
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.638
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.638
Slack : 0.520
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.640
Slack : 0.521
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.641
Slack : 0.521
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.641
Slack : 0.521
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.641
Slack : 0.521
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.641
Slack : 0.523
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.643
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.644
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.644
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.644
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.644
Slack : 0.525
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.646
Slack : 0.526
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.646
Slack : 0.527
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.647
Slack : 0.527
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.647
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.294
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.295
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.300
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.353
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.474
Slack : 0.415
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.551
Slack : 0.418
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.539
Slack : 0.443
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.564
Slack : 0.447
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.583
Slack : 0.447
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.583
Slack : 0.451
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.587
Slack : 0.453
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.574
Slack : 0.456
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.459
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.580
Slack : 0.493
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.616
Slack : 0.506
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.626
Slack : 0.511
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.632
Slack : 0.545
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.681
Slack : 0.550
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.675
Slack : 0.554
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.679
Slack : 0.578
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.142
Data Delay : 0.520
Slack : 0.606
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.726
Slack : 0.607
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.728
Slack : 0.631
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.758
Slack : 0.643
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.127
Data Delay : 0.600
Slack : 0.647
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.142
Data Delay : 0.589
Slack : 0.660
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.781
Slack : 0.661
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.797
Slack : 0.662
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.787
Slack : 0.673
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.794
Slack : 0.678
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.803
Slack : 0.678
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.799
Slack : 0.686
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.811
Slack : 0.703
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.824
Slack : 0.703
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.824
Slack : 0.703
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.824
Slack : 0.703
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.824
Slack : 0.706
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.142
Data Delay : 0.648
Slack : 0.710
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.846
Slack : 0.716
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.852
Slack : 0.719
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.844
Slack : 0.719
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.844
Slack : 0.720
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.845
Slack : 0.721
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.857
Slack : 0.724
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.127
Data Delay : 0.681
Slack : 0.726
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.127
Data Delay : 0.683
Slack : 0.734
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.855
Slack : 0.736
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.861
Slack : 0.739
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.860
Slack : 0.743
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.864
Slack : 0.756
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.876
Slack : 0.758
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.142
Data Delay : 0.700
Slack : 0.775
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.900
Slack : 0.791
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 0.927
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.228
Data Delay : 1.141
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.949
Slack : 0.830
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.951
Slack : 0.830
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.951
Slack : 0.833
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.954
Slack : 0.835
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.960
Slack : 0.846
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.966
Slack : 0.849
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.970
Slack : 0.849
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.970
Slack : 0.849
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.970
Slack : 0.849
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.970
Slack : 0.849
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.970
Slack : 0.858
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.978
Slack : 0.860
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.127
Data Delay : 0.817
Slack : 0.860
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.980
Slack : 0.863
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.984
Slack : 0.872
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.993
Slack : 0.873
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.993
Slack : 0.877
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.052
Data Delay : 1.013
Slack : 0.879
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.004
Slack : 0.882
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.002
Slack : 0.894
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.019
Slack : 0.907
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.142
Data Delay : 0.849
Slack : 0.908
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.033
Slack : 0.909
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.034
Slack : 0.909
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.034
Slack : 0.909
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 1.034
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.193
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.416
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.542
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.201
From Node : debouncer:debounce_autofire|r_State
To Node : debouncer:debounce_autofire|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.022
Data Delay : 0.307
Slack : 0.201
From Node : debouncer:debounce_turbo|r_State
To Node : debouncer:debounce_turbo|r_State
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.022
Data Delay : 0.307
Slack : 0.205
From Node : debouncer:debounce_turbo|r_Count[20]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.325
Slack : 0.205
From Node : debouncer:debounce_autofire|r_Count[20]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.325
Slack : 0.298
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.418
Slack : 0.299
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.300
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.301
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.302
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.302
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.422
Slack : 0.303
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.423
Slack : 0.303
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.423
Slack : 0.304
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.424
Slack : 0.304
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.424
Slack : 0.305
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.305
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.306
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.426
Slack : 0.306
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.426
Slack : 0.308
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.428
Slack : 0.308
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.428
Slack : 0.309
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.429
Slack : 0.309
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.429
Slack : 0.309
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.429
Slack : 0.309
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.429
Slack : 0.310
From Node : debouncer:debounce_turbo|r_Count[6]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.430
Slack : 0.447
From Node : debouncer:debounce_autofire|r_Count[3]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.567
Slack : 0.448
From Node : debouncer:debounce_turbo|r_Count[1]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : debouncer:debounce_turbo|r_Count[3]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : debouncer:debounce_autofire|r_Count[19]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : debouncer:debounce_autofire|r_Count[1]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.449
From Node : debouncer:debounce_turbo|r_Count[19]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.449
From Node : debouncer:debounce_turbo|r_Count[17]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.449
From Node : debouncer:debounce_autofire|r_Count[17]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.449
From Node : debouncer:debounce_autofire|r_Count[9]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.569
Slack : 0.451
From Node : debouncer:debounce_turbo|r_Count[15]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.451
From Node : debouncer:debounce_turbo|r_Count[9]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.569
Slack : 0.451
From Node : debouncer:debounce_autofire|r_Count[15]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.451
From Node : debouncer:debounce_autofire|r_Count[7]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.451
From Node : debouncer:debounce_autofire|r_Count[5]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.451
From Node : debouncer:debounce_autofire|r_Count[13]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.452
From Node : debouncer:debounce_turbo|r_Count[13]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.572
Slack : 0.457
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.457
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.457
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[7]
To Node : debouncer:debounce_turbo|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[11]
To Node : debouncer:debounce_turbo|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_turbo|r_Count[5]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : debouncer:debounce_autofire|r_Count[11]
To Node : debouncer:debounce_autofire|r_Count[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.459
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.579
Slack : 0.460
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.460
From Node : debouncer:debounce_turbo|r_Count[0]
To Node : debouncer:debounce_turbo|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.460
From Node : debouncer:debounce_turbo|r_Count[2]
To Node : debouncer:debounce_turbo|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.460
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.460
From Node : debouncer:debounce_autofire|r_Count[0]
To Node : debouncer:debounce_autofire|r_Count[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.461
From Node : debouncer:debounce_turbo|r_Count[18]
To Node : debouncer:debounce_turbo|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_turbo|r_Count[16]
To Node : debouncer:debounce_turbo|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_turbo|r_Count[4]
To Node : debouncer:debounce_turbo|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_autofire|r_Count[2]
To Node : debouncer:debounce_autofire|r_Count[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_autofire|r_Count[16]
To Node : debouncer:debounce_autofire|r_Count[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.461
From Node : debouncer:debounce_autofire|r_Count[4]
To Node : debouncer:debounce_autofire|r_Count[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.462
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.582
Slack : 0.462
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.582
Slack : 0.462
From Node : debouncer:debounce_autofire|r_Count[18]
To Node : debouncer:debounce_autofire|r_Count[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.582
Slack : 0.463
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.583
Slack : 0.463
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.583
Slack : 0.463
From Node : debouncer:debounce_autofire|r_Count[8]
To Node : debouncer:debounce_autofire|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.583
Slack : 0.464
From Node : debouncer:debounce_turbo|r_Count[10]
To Node : debouncer:debounce_turbo|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.464
From Node : debouncer:debounce_autofire|r_Count[10]
To Node : debouncer:debounce_autofire|r_Count[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.464
From Node : debouncer:debounce_autofire|r_Count[6]
To Node : debouncer:debounce_autofire|r_Count[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.584
Slack : 0.465
From Node : debouncer:debounce_turbo|r_Count[8]
To Node : debouncer:debounce_turbo|r_Count[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.583
Slack : 0.465
From Node : debouncer:debounce_turbo|r_Count[12]
To Node : debouncer:debounce_turbo|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.585
Slack : 0.465
From Node : debouncer:debounce_autofire|r_Count[12]
To Node : debouncer:debounce_autofire|r_Count[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.585
Slack : 0.466
From Node : debouncer:debounce_turbo|r_Count[14]
To Node : debouncer:debounce_turbo|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.586
Slack : 0.466
From Node : debouncer:debounce_autofire|r_Count[14]
To Node : debouncer:debounce_autofire|r_Count[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.586
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.782
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.780
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.230
Data Delay : 2.777
Slack : -4.683
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.780
Slack : -4.683
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.778
Slack : -4.572
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 2.648
Slack : -4.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.251
Data Delay : 2.639
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.573
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.573
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.572
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.573
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.573
Slack : -4.427
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.573
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.426
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.236
Data Delay : 2.561
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.223
Data Delay : 2.569
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.231
Data Delay : 2.560
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.231
Data Delay : 2.560
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.231
Data Delay : 2.560
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.231
Data Delay : 2.560
Slack : -4.249
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.571
Slack : -4.249
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.571
Slack : -4.249
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.571
Slack : -4.249
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.571
Slack : -4.249
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.571
Slack : -4.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.049
Data Delay : 2.569
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.572
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.572
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.572
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.045
Data Delay : 2.563
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.569
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.568
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.044
Data Delay : 2.558
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
Slack : -4.192
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.562
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.218
Data Delay : 1.939
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.940
Slack : 2.554
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.208
Data Delay : 1.930
Slack : 2.560
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.216
Data Delay : 1.944
Slack : 2.560
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.216
Data Delay : 1.944
Slack : 2.560
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.216
Data Delay : 1.944
Slack : 2.562
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.207
Data Delay : 1.937
Slack : 2.569
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.940
Slack : 2.573
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.944
Slack : 2.573
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.944
Slack : 2.573
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.944
Slack : 2.573
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.944
Slack : 2.573
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.203
Data Delay : 1.944
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.022
Data Delay : 1.940
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.013
Data Delay : 1.932
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.013
Data Delay : 1.932
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.013
Data Delay : 1.932
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.013
Data Delay : 1.932
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.008
Data Delay : 1.934
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.758
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.944
Slack : 2.759
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.020
Data Delay : 1.947
Slack : 2.759
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.020
Data Delay : 1.947
Slack : 2.759
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.020
Data Delay : 1.947
Slack : 2.759
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.020
Data Delay : 1.947
Slack : 2.759
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.020
Data Delay : 1.947
Slack : 2.886
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.019
Data Delay : 2.009
Slack : 2.891
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.016
Data Delay : 2.017
Slack : 2.997
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.009
Data Delay : 2.146
Slack : 2.997
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.144
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.145
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.005
Data Delay : 2.143
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.004
Data Delay : 2.142
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
Slack : 19.612
Actual Width : 19.842
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.612
Actual Width : 19.842
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.612
Actual Width : 19.842
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.648
Actual Width : 20.864
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.652
Actual Width : 20.836
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.525
Actual Width : 35.741
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.526
Actual Width : 35.742
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.562
Actual Width : 35.746
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.563
Actual Width : 35.747
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.741
Actual Width : 35.741
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.742
Actual Width : 35.742
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.747
Actual Width : 35.747
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 1.699
Fall : 2.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 1.363
Fall : 2.048
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 1.240
Fall : 1.933
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 1.677
Fall : 2.333
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 1.699
Fall : 2.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 1.293
Fall : 1.980
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : 1.775
Fall : 2.591
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.722
Fall : 2.653
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : 1.939
Fall : 2.782
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 3.051
Fall : 3.707
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 2.615
Fall : 3.300
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 2.408
Fall : 3.101
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 3.051
Fall : 3.707
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 2.654
Fall : 3.322
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 2.546
Fall : 3.233
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 2.690
Fall : 3.565
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 0.736
Fall : 1.327
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.567
Fall : 2.174
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -0.705
Fall : -1.385
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -0.766
Fall : -1.438
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -0.705
Fall : -1.385
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -0.954
Fall : -1.482
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -1.226
Fall : -1.838
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -0.814
Fall : -1.488
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : -0.910
Fall : -1.730
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.415
Fall : -2.313
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : -1.060
Fall : -1.890
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -1.705
Fall : -2.281
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -1.721
Fall : -2.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -1.828
Fall : -2.508
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -1.705
Fall : -2.281
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -1.871
Fall : -2.483
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -1.708
Fall : -2.382
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.085
Fall : -2.924
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.377
Fall : -0.959
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.536
Fall : -1.088
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.969
Fall : 6.090
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.682
Fall : 5.945
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.678
Fall : 5.927
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.918
Fall : 6.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.666
Fall : 5.781
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.969
Fall : 6.090
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.782
Fall : 5.888
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.503
Fall : 5.672
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.813
Fall : 5.924
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.809
Fall : 5.901
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.720
Fall : 5.798
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.438
Fall : 5.603
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.646
Fall : 5.732
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.533
Fall : 5.601
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.610
Fall : 5.732
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.668
Fall : 5.744
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.805
Fall : 5.888
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.809
Fall : 5.901
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.001
Fall : 1.946
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.979
Fall : 1.928
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.052
Fall : 1.980
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.055
Fall : 1.983
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.977
Fall : 1.926
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.998
Fall : 1.943
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.053
Fall : 1.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.533
Fall : 3.638
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.099
Fall : 3.170
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.264
Fall : 3.395
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.180
Fall : 3.297
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.446
Fall : 3.638
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.315
Fall : 3.446
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.477
Fall : 3.607
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.941
Fall : 3.024
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.453
Fall : 3.593
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 3.529
Fall : 3.461
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 3.513
Fall : 3.447
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 3.521
Fall : 3.453
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 3.521
Fall : 3.453
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 3.510
Fall : 3.443
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 3.533
Fall : 3.464
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 3.533
Fall : 3.464
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 3.529
Fall : 3.479
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.053
Fall : 1.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.057
Fall : 1.985
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.958
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.905
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.722
Fall : 4.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.343
Fall : 4.425
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.521
Fall : 4.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.677
Fall : 4.819
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.389
Fall : 4.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.722
Fall : 4.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.564
Fall : 4.673
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.241
Fall : 4.364
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.430
Fall : 4.558
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.450
Fall : 4.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.196
Fall : 4.274
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.284
Fall : 4.386
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.405
Fall : 4.507
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.310
Fall : 4.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.346
Fall : 4.469
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.450
Fall : 4.529
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.321
Fall : 4.438
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.426
Fall : 4.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 5.244
Fall : 5.062
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.244
Fall : 5.062
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.952
Fall : 4.028
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.709
Fall : 3.763
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.715
Fall : 3.770
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 4.038
Fall : 4.112
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.700
Fall : 3.729
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.576
Fall : 3.589
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.038
Fall : 4.112
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.038
Fall : 4.112
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.880
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.880
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.799
Fall : 3.843
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.791
Fall : 3.851
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.534
Fall : 3.572
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.712
Fall : 1.657
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.709
Fall : 1.654
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.708
Fall : 1.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.245
Fall : 2.951
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.711
Fall : 1.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.755
Fall : 1.683
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.758
Fall : 1.686
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.294
Fall : 4.375
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.038
Fall : 5.019
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.016
Fall : 5.109
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.044
Fall : 5.159
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.369
Fall : 4.471
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.022
Fall : 5.129
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.081
Fall : 5.174
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.294
Fall : 4.375
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.780
Fall : 4.902
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.240
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.794
Fall : 4.862
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.650
Fall : 4.705
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.787
Fall : 4.861
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.240
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.668
Fall : 4.774
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.972
Fall : 5.036
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.316
Fall : 4.410
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.780
Fall : 4.882
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.802
Fall : 1.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.609
Fall : 2.688
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.736
Fall : 2.807
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 2.891
Fall : 3.012
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.808
Fall : 2.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.063
Fall : 3.244
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.940
Fall : 3.061
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.124
Fall : 3.246
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.609
Fall : 2.688
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.062
Fall : 3.196
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 2.928
Fall : 2.862
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 2.913
Fall : 2.848
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.920
Fall : 2.854
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.920
Fall : 2.854
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 2.909
Fall : 2.845
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.932
Fall : 2.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.932
Fall : 2.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.931
Fall : 2.884
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.677
Fall : 3.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.679
Fall : 3.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.846
Fall : 3.941
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.010
Fall : 4.156
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.724
Fall : 3.842
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.993
Fall : 4.114
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.820
Fall : 3.962
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.677
Fall : 3.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.914
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 2.945
Fall : 3.017
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.472
Fall : 3.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.367
Fall : 3.452
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.754
Fall : 3.859
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 2.945
Fall : 3.017
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.629
Fall : 3.730
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.711
Fall : 3.824
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.126
Fall : 3.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.894
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.438
Fall : 2.484
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.974
Fall : 3.782
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.454
Fall : 2.513
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.438
Fall : 2.484
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.444
Fall : 2.490
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.267
Fall : 2.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.465
Fall : 2.447
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.267
Fall : 2.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.789
Fall : 2.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.789
Fall : 2.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.202
Fall : 2.223
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.468
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.426
Fall : 2.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.449
Fall : 2.491
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.202
Fall : 2.223
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.879
RF :
FR :
FF : 3.248
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 3.948
RF : 4.040
FR : 4.626
FF : 4.725
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 3.860
RF : 3.903
FR : 4.539
FF : 4.589
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 2.630
FR : 3.223
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 4.172
RF : 4.262
FR : 4.858
FF : 4.955
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 4.068
RF : 4.084
FR : 4.716
FF : 4.795
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 2.519
FR : 3.078
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 4.628
RF : 4.747
FR : 5.277
FF : 5.403
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 4.035
RF : 4.111
FR : 4.705
FF : 4.762
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 3.961
FR : 4.321
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 4.513
RF : 4.613
FR : 5.181
FF : 5.281
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 4.398
RF : 4.452
FR : 5.031
FF : 5.092
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 2.439
FR : 3.023
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 4.303
RF : 4.397
FR : 4.983
FF : 5.084
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 4.067
RF : 4.165
FR : 4.739
FF : 4.819
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 4.030
FR : 4.929
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 4.506
RF :
FR :
FF : 5.349
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.990
RF :
FR :
FF : 4.790
Input Port : raw_loader_in
Output Port : LED[1]
RR : 3.087
RF :
FR :
FF : 3.775
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.791
RF :
FR :
FF : 3.164
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 3.814
RF : 3.901
FR : 4.486
FF : 4.580
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 3.732
RF : 3.773
FR : 4.405
FF : 4.453
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 2.547
FR : 3.137
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 4.029
RF : 4.114
FR : 4.709
FF : 4.801
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 3.933
RF : 3.925
FR : 4.550
FF : 4.648
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 2.445
FR : 3.001
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 4.354
RF : 4.138
FR : 4.707
FF : 5.142
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 3.901
RF : 3.973
FR : 4.566
FF : 4.619
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 3.887
FR : 4.243
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 4.297
RF : 4.333
FR : 4.909
FF : 5.048
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 4.249
RF : 4.300
FR : 4.878
FF : 4.936
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 2.365
FR : 2.946
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 4.157
RF : 4.246
FR : 4.831
FF : 4.927
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 3.929
RF : 3.972
FR : 4.566
FF : 4.670
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 3.943
FR : 4.839
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 4.350
RF :
FR :
FF : 5.184
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.831
RF :
FR :
FF : 4.623
Input Port : raw_loader_in
Output Port : LED[1]
RR : 2.986
RF :
FR :
FF : 3.666
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.312
Fall : 3.219
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.403
Fall : 3.310
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.403
Fall : 3.310
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.363
Fall : 3.289
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.461
Fall : 3.396
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.472
Fall : 3.379
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.312
Fall : 3.219
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.312
Fall : 3.219
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.483
Fall : 3.409
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.727
Fall : 2.634
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.814
Fall : 2.721
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 2.814
Fall : 2.721
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.766
Fall : 2.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 2.866
Fall : 2.801
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.881
Fall : 2.788
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 2.727
Fall : 2.634
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.727
Fall : 2.634
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 2.881
Fall : 2.807
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 3.315
1 to Hi-Z : 3.408
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 3.409
1 to Hi-Z : 3.502
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 3.409
1 to Hi-Z : 3.502
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 3.388
1 to Hi-Z : 3.462
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 3.542
1 to Hi-Z : 3.607
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 3.495
1 to Hi-Z : 3.588
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 3.315
1 to Hi-Z : 3.408
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 3.315
1 to Hi-Z : 3.408
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 3.542
1 to Hi-Z : 3.616
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 2.729
1 to Hi-Z : 2.822
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 2.819
1 to Hi-Z : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 2.819
1 to Hi-Z : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 2.789
1 to Hi-Z : 2.863
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 2.944
1 to Hi-Z : 3.009
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 2.901
1 to Hi-Z : 2.994
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 2.729
1 to Hi-Z : 2.822
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 2.729
1 to Hi-Z : 2.822
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 2.937
1 to Hi-Z : 3.011
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -18.476
Hold : 0.179
Recovery : -6.210
Removal : 2.507
Minimum Pulse Width : 4.748
Clock : CLOCK_50
Setup : -18.476
Hold : 0.201
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 9.208
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 3.261
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 4.748
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -7.513
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 19.598
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : 70.299
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 35.487
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -4.734
Hold : 0.179
Recovery : -6.210
Removal : 2.507
Minimum Pulse Width : 20.589
Clock : Design-wide TNS
Setup : -1134.051
Hold : 0.0
Recovery : -460.961
Removal : 0.0
Minimum Pulse Width : 0.0
Clock : CLOCK_50
Setup : -808.800
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 0.000
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -282.972
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : 0.000
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -42.279
Hold : 0.000
Recovery : -460.961
Removal : 0.000
Minimum Pulse Width : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 2.982
Fall : 3.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 2.346
Fall : 2.671
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 2.083
Fall : 2.452
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 2.910
Fall : 3.266
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 2.982
Fall : 3.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 2.249
Fall : 2.595
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : 3.159
Fall : 3.711
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.214
Fall : 3.753
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : 3.437
Fall : 4.028
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : 5.217
Fall : 5.573
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : 4.464
Fall : 4.789
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : 4.077
Fall : 4.446
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : 5.217
Fall : 5.573
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : 4.615
Fall : 4.935
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : 4.296
Fall : 4.642
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 4.842
Fall : 5.311
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.275
Fall : 1.518
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.868
Fall : 3.098
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -0.705
Fall : -1.385
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -0.766
Fall : -1.438
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -0.705
Fall : -1.385
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -0.954
Fall : -1.482
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -1.226
Fall : -1.838
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -0.814
Fall : -1.488
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston_autofire_button
Clock Port : CLOCK_50
Rise : -0.910
Fall : -1.730
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.415
Fall : -2.313
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : turbo_button
Clock Port : CLOCK_50
Rise : -1.060
Fall : -1.890
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : kempston[*]
Clock Port : CLOCK_50
Rise : -1.705
Fall : -2.281
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[0]
Clock Port : CLOCK_50
Rise : -1.721
Fall : -2.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[1]
Clock Port : CLOCK_50
Rise : -1.828
Fall : -2.508
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[2]
Clock Port : CLOCK_50
Rise : -1.705
Fall : -2.281
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[3]
Clock Port : CLOCK_50
Rise : -1.871
Fall : -2.483
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : kempston[4]
Clock Port : CLOCK_50
Rise : -1.708
Fall : -2.382
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.085
Fall : -2.924
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.377
Fall : -0.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.536
Fall : -1.071
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.228
Fall : 10.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 9.909
Fall : 10.038
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.954
Fall : 10.011
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 10.123
Fall : 10.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 9.672
Fall : 9.707
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.228
Fall : 10.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 9.897
Fall : 9.931
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 9.384
Fall : 9.506
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.974
Fall : 9.978
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.944
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.782
Fall : 9.780
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.280
Fall : 9.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.654
Fall : 9.659
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.391
Fall : 9.410
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.589
Fall : 9.640
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.681
Fall : 9.690
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.944
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.894
Fall : 9.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.419
Fall : 3.334
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.004
Fall : 6.086
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.305
Fall : 5.354
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.578
Fall : 5.696
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.445
Fall : 5.512
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.941
Fall : 6.086
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.645
Fall : 5.775
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.004
Fall : 6.051
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.996
Fall : 5.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.954
Fall : 6.010
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.903
Fall : 5.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.870
Fall : 5.876
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.883
Fall : 5.889
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.883
Fall : 5.889
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.873
Fall : 5.891
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.904
Fall : 5.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.904
Fall : 5.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.941
Fall : 5.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.091
Fall : 8.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.500
Fall : 7.498
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.943
Fall : 8.029
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.038
Fall : 8.056
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.578
Fall : 7.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.091
Fall : 8.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.839
Fall : 7.890
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.255
Fall : 7.347
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.712
Fall : 7.706
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.632
Fall : 7.649
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.222
Fall : 7.219
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.315
Fall : 7.384
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.565
Fall : 7.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.471
Fall : 7.581
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.421
Fall : 7.433
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.623
Fall : 7.649
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.465
Fall : 7.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.632
Fall : 7.645
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.550
Fall : 8.202
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.550
Fall : 8.202
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.928
Fall : 6.937
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.512
Fall : 6.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.524
Fall : 6.454
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.553
Fall : 6.432
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.279
Fall : 6.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 7.146
Fall : 7.041
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.725
Fall : 6.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.725
Fall : 6.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.651
Fall : 6.615
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.698
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.230
Fall : 6.171
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.294
Fall : 4.375
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.038
Fall : 5.019
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.016
Fall : 5.109
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.044
Fall : 5.159
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.369
Fall : 4.471
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.022
Fall : 5.129
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.081
Fall : 5.174
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.294
Fall : 4.375
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.780
Fall : 4.902
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.240
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.794
Fall : 4.862
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.650
Fall : 4.705
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.787
Fall : 4.861
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.240
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.668
Fall : 4.774
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.972
Fall : 5.036
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.316
Fall : 4.410
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.780
Fall : 4.882
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.802
Fall : 1.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.609
Fall : 2.688
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.736
Fall : 2.807
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 2.891
Fall : 3.012
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.808
Fall : 2.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.063
Fall : 3.244
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.940
Fall : 3.061
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.124
Fall : 3.246
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.609
Fall : 2.688
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.062
Fall : 3.196
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 2.928
Fall : 2.862
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 2.913
Fall : 2.848
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.920
Fall : 2.854
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.920
Fall : 2.854
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 2.909
Fall : 2.845
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.932
Fall : 2.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.932
Fall : 2.865
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.931
Fall : 2.884
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.677
Fall : 3.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.679
Fall : 3.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.846
Fall : 3.941
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.010
Fall : 4.156
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.724
Fall : 3.842
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.993
Fall : 4.114
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.820
Fall : 3.962
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.677
Fall : 3.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.914
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 2.945
Fall : 3.017
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.472
Fall : 3.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.367
Fall : 3.452
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.754
Fall : 3.859
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 2.945
Fall : 3.017
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.629
Fall : 3.730
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.711
Fall : 3.824
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.126
Fall : 3.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.894
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.438
Fall : 2.484
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.974
Fall : 3.782
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.454
Fall : 2.513
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.438
Fall : 2.484
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.444
Fall : 2.490
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.267
Fall : 2.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.465
Fall : 2.447
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.267
Fall : 2.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.789
Fall : 2.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.789
Fall : 2.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.202
Fall : 2.223
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.468
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.426
Fall : 2.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.449
Fall : 2.491
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.202
Fall : 2.223
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.760
RF :
FR :
FF : 4.845
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 6.879
RF : 6.888
FR : 7.195
FF : 7.213
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 6.687
RF : 6.671
FR : 7.003
FF : 6.996
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 4.492
FR : 4.693
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 7.200
RF : 7.173
FR : 7.560
FF : 7.542
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 7.015
RF : 6.950
FR : 7.322
FF : 7.358
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 4.319
FR : 4.499
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 8.089
RF : 8.112
FR : 8.436
FF : 8.468
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 6.945
RF : 6.980
FR : 7.315
FF : 7.315
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 6.211
FR : 6.117
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 7.927
RF : 7.949
FR : 8.239
FF : 8.269
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 7.621
RF : 7.586
FR : 7.940
FF : 7.914
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 4.174
FR : 4.361
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 7.468
RF : 7.451
FR : 7.805
FF : 7.797
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 7.041
RF : 7.069
FR : 7.371
FF : 7.371
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 6.462
FR : 7.117
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 7.844
RF :
FR :
FF : 8.324
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.881
RF :
FR :
FF : 7.298
Input Port : raw_loader_in
Output Port : LED[1]
RR : 5.229
RF :
FR :
FF : 5.518
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.791
RF :
FR :
FF : 3.164
Input Port : kempston[0]
Output Port : DRAM_DQ[3]
RR : 3.814
RF : 3.901
FR : 4.486
FF : 4.580
Input Port : kempston[0]
Output Port : GPIO_1[19]
RR : 3.732
RF : 3.773
FR : 4.405
FF : 4.453
Input Port : kempston[0]
Output Port : LED[3]
RR :
RF : 2.547
FR : 3.137
FF :
Input Port : kempston[1]
Output Port : DRAM_DQ[2]
RR : 4.029
RF : 4.114
FR : 4.709
FF : 4.801
Input Port : kempston[1]
Output Port : GPIO_1[18]
RR : 3.933
RF : 3.925
FR : 4.550
FF : 4.648
Input Port : kempston[1]
Output Port : LED[4]
RR :
RF : 2.445
FR : 3.001
FF :
Input Port : kempston[2]
Output Port : DRAM_DQ[1]
RR : 4.354
RF : 4.138
FR : 4.707
FF : 5.142
Input Port : kempston[2]
Output Port : GPIO_1[17]
RR : 3.901
RF : 3.973
FR : 4.566
FF : 4.619
Input Port : kempston[2]
Output Port : LED[5]
RR :
RF : 3.887
FR : 4.243
FF :
Input Port : kempston[3]
Output Port : DRAM_DQ[0]
RR : 4.297
RF : 4.333
FR : 4.909
FF : 5.048
Input Port : kempston[3]
Output Port : GPIO_1[16]
RR : 4.249
RF : 4.300
FR : 4.878
FF : 4.936
Input Port : kempston[3]
Output Port : LED[6]
RR :
RF : 2.365
FR : 2.946
FF :
Input Port : kempston[4]
Output Port : DRAM_DQ[4]
RR : 4.157
RF : 4.246
FR : 4.831
FF : 4.927
Input Port : kempston[4]
Output Port : GPIO_1[20]
RR : 3.929
RF : 3.972
FR : 4.566
FF : 4.670
Input Port : kempston[4]
Output Port : LED[7]
RR :
RF : 3.943
FR : 4.839
FF :
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 4.350
RF :
FR :
FF : 5.184
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.831
RF :
FR :
FF : 4.623
Input Port : raw_loader_in
Output Port : LED[1]
RR : 2.986
RF :
FR :
FF : 3.666
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : kempston_gnd
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : SW[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : raw_loader_in
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston[4]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : turbo_button
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : kempston_autofire_button
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_DAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_CLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : AUD_ADCDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : kempston_gnd
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : kempston_gnd
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : kempston_gnd
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 1552
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1182
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1972
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 120
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1154
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1425
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 1552
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1182
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1972
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 120
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1154
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1425
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Recovery Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Removal Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 4
Hold : 4
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 0
Hold : 0
Property : Unconstrained Output Port Paths
Setup : 0
Hold : 0
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Apr 6 13:58:20 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'spectrum.sdc'
Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port
Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection
Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]}
Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin
Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock
Warning (332125): Found combinational loop of 518 nodes
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|dataa"
Warning (332126): Node "z80_|alu_|db[7]~19|dataa"
Warning (332126): Node "z80_|alu_|db[7]~19|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|dataa"
Warning (332126): Node "z80_|alu_|db[7]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~3|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~3|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~6|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~7|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|datac"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|datab"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~18|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~19|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~23|combout"
Warning (332126): Node "z80_|alu_|db[0]~18|dataa"
Warning (332126): Node "z80_|alu_|db[0]~18|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~12|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~13|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~13|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~17|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datac"
Warning (332126): Node "z80_|alu_|db[1]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~21|datac"
Warning (332126): Node "z80_|alu_control_|db[1]~21|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~22|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~22|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~9|dataa"
Warning (332126): Node "z80_|bus_control_|db[1]~9|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa"
Warning (332126): Node "z80_|bus_control_|db[1]~10|combout"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|datab"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~22|dataa"
Warning (332126): Node "z80_|alu_|db[1]~15|datac"
Warning (332126): Node "z80_|alu_|db[1]~15|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~21|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~13|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout"
Warning (332126): Node "z80_|alu_|db[1]~15|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~9|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~10|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~11|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~11|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|datac"
Warning (332126): Node "z80_|alu_|db[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout"
Warning (332126): Node "z80_|alu_|db[2]~11|datab"
Warning (332126): Node "z80_|alu_|db[2]~11|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa"
Warning (332126): Node "z80_|alu_control_|db[2]~27|datac"
Warning (332126): Node "z80_|alu_control_|db[2]~27|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|datad"
Warning (332126): Node "z80_|alu_control_|db[2]~28|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~13|datad"
Warning (332126): Node "z80_|bus_control_|db[2]~13|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~14|datab"
Warning (332126): Node "z80_|bus_control_|db[2]~14|combout"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|datac"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa"
Warning (332126): Node "z80_|alu_|db[2]~11|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~27|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~0|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~0|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~1|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~1|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~5|combout"
Warning (332126): Node "z80_|alu_|db[3]~13|datab"
Warning (332126): Node "z80_|alu_|db[3]~13|combout"
Warning (332126): Node "z80_|alu_|db[3]~14|datac"
Warning (332126): Node "z80_|alu_|db[3]~14|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~25|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|datac"
Warning (332126): Node "z80_|alu_|db[4]~10|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~14|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~19|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|datad"
Warning (332126): Node "z80_|alu_|db[5]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~10|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~10|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~13|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|dataa"
Warning (332126): Node "z80_|alu_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~3|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa"
Warning (332126): Node "z80_|alu_control_|db[6]~17|dataa"
Warning (332126): Node "z80_|alu_control_|db[6]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~18|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~18|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~7|datab"
Warning (332126): Node "z80_|bus_control_|db[6]~7|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~8|datab"
Warning (332126): Node "z80_|bus_control_|db[6]~8|combout"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|datac"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~18|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~17|datad"
Warning (332126): Node "z80_|alu_|db[6]~21|datac"
Warning (332126): Node "z80_|alu_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout"
Warning (332126): Node "z80_|alu_|db[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~12|datad"
Warning (332126): Node "z80_|alu_control_|db[5]~12|combout"
Warning (332126): Node "z80_|alu_|db[5]~23|datab"
Warning (332126): Node "z80_|alu_|db[5]~23|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~9|datad"
Warning (332126): Node "z80_|alu_control_|db[5]~9|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~12|dataa"
Warning (332126): Node "z80_|bus_control_|db[5]~16|datad"
Warning (332126): Node "z80_|bus_control_|db[5]~16|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~3|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~3|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~4|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~4|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~5|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~7|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~7|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~8|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~8|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~11|datac"
Warning (332126): Node "z80_|alu_control_|db[5]~9|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~16|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~16|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab"
Warning (332126): Node "z80_|alu_|db[5]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa"
Warning (332126): Node "z80_|alu_|db[4]~8|datab"
Warning (332126): Node "z80_|alu_|db[4]~8|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~29|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~29|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~30|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~30|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~31|combout"
Warning (332126): Node "z80_|bus_control_|db[4]~18|datab"
Warning (332126): Node "z80_|bus_control_|db[4]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~20|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~14|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~3|datad"
Warning (332126): Node "z80_|alu_|db[4]~8|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~29|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~1|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~9|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datab"
Warning (332126): Node "z80_|alu_|db[3]~13|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datac"
Warning (332126): Node "z80_|alu_control_|db[3]~35|combout"
Warning (332126): Node "z80_|bus_control_|db[3]~20|datab"
Warning (332126): Node "z80_|bus_control_|db[3]~20|combout"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datab"
Warning (332126): Node "z80_|alu_control_|db[3]~33|datab"
Warning (332126): Node "z80_|alu_control_|db[3]~33|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~34|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~20|datab"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~14|datab"
Warning (332126): Node "z80_|alu_|db[3]~14|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~34|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~19|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datac"
Warning (332126): Node "z80_|alu_|db[0]~17|dataa"
Warning (332126): Node "z80_|alu_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_|db[0]~18|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~23|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~23|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~25|datab"
Warning (332126): Node "z80_|alu_control_|db[0]~25|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~11|datab"
Warning (332126): Node "z80_|bus_control_|db[0]~11|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~12|datac"
Warning (332126): Node "z80_|bus_control_|db[0]~12|combout"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|datac"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~24|datad"
Warning (332126): Node "z80_|alu_control_|db[0]~24|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~25|datac"
Warning (332126): Node "z80_|alu_|db[0]~17|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~25|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~2|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|datab"
Warning (332126): Node "z80_|alu_control_|db[7]~14|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~14|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~15|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~15|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~4|datad"
Warning (332126): Node "z80_|bus_control_|db[7]~4|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~6|datac"
Warning (332126): Node "z80_|bus_control_|db[7]~6|combout"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|datab"
Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~15|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~14|datad"
Warning (332126): Node "z80_|alu_|db[7]~19|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa"
Critical Warning (332081): Design contains combinational loop of 518 nodes. Estimating the delays through the loop.
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -18.476
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -18.476 -808.800 CLOCK_50
Info (332119): -7.513 -282.972 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.734 -42.279 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 3.261 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 70.299 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.344
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.358 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.382 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -6.210
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.210 -460.961 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.689
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.689 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.752
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.488 0.000 CLOCK_50
Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.593 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.490 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -17.646
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -17.646 -768.789 CLOCK_50
Info (332119): -6.953 -254.832 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.416 -39.535 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 3.951 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 70.438 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.300
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.312 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.333 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -5.734
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -5.734 -425.150 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.370
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.370 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.748
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.748 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.488 0.000 CLOCK_50
Info (332119): 19.598 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.589 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.487 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -15.170
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -15.170 -635.207 CLOCK_50
Info (332119): -5.647 -193.116 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -3.810 -35.303 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 6.131 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 70.800 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.179
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.179 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.201 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -4.684
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.684 -359.024 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 2.507
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 2.507 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.784
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.784 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.208 0.000 CLOCK_50
Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.525 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 545 warnings
Info: Peak virtual memory: 441 megabytes
Info: Processing ended: Wed Apr 6 13:58:24 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
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