WIP: sdram support

PLLJ_PLLSPE_INFO.txt

@@ -1,3 +1,8 @@
+PLL_Name	sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1
+PLLJITTER	35
+PLLSPEmax	84
+PLLSPEmin	-53
+
 PLL_Name	ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1
 PLLJITTER	NA
 PLLSPEmax	84

db/sdram_clk_gen_altpll.v

@@ -0,0 +1,96 @@
+//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="3000" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sdram_clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+//CBXI_INSTANCE_NAME="spectrum_sdram_controller_sdram_sdram_clk_gen_sdram_clk_pll_altpll_altpll_component"
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+
+
+
+//synthesis_resources = cycloneive_pll 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  sdram_clk_gen_altpll
+	( 
+	clk,
+	inclk) /* synthesis synthesis_clearbox=1 */;
+	output   [4:0]  clk;
+	input   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [4:0]   wire_pll1_clk;
+	wire  wire_pll1_fbout;
+
+	cycloneive_pll   pll1
+	( 
+	.activeclock(),
+	.clk(wire_pll1_clk),
+	.clkbad(),
+	.fbin(wire_pll1_fbout),
+	.fbout(wire_pll1_fbout),
+	.inclk(inclk),
+	.locked(),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.vcooverrange(),
+	.vcounderrange()
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.areset(1'b0),
+	.clkswitch(1'b0),
+	.configupdate(1'b0),
+	.pfdena(1'b1),
+	.phasecounterselect({3{1'b0}}),
+	.phasestep(1'b0),
+	.phaseupdown(1'b0),
+	.scanclk(1'b0),
+	.scanclkena(1'b1),
+	.scandata(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pll1.bandwidth_type = "auto",
+		pll1.clk0_divide_by = 1,
+		pll1.clk0_duty_cycle = 50,
+		pll1.clk0_multiply_by = 2,
+		pll1.clk0_phase_shift = "0",
+		pll1.clk1_divide_by = 1,
+		pll1.clk1_duty_cycle = 50,
+		pll1.clk1_multiply_by = 2,
+		pll1.clk1_phase_shift = "3000",
+		pll1.compensate_clock = "clk0",
+		pll1.inclk0_input_frequency = 20000,
+		pll1.operation_mode = "normal",
+		pll1.pll_type = "auto",
+		pll1.lpm_type = "cycloneive_pll";
+	assign
+		clk = {wire_pll1_clk[4:0]};
+endmodule //sdram_clk_gen_altpll
+//VALID FILE

db/spectrum.asm.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900269993 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr  1 18:55:41 2022 " "Processing started: Fri Apr  1 18:55:41 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr  2 14:51:09 2022 " "Processing started: Sat Apr  2 14:51:09 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648900271169 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648900271197 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr  1 18:55:43 2022 " "Processing ended: Fri Apr  1 18:55:43 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr  2 14:51:11 2022 " "Processing ended: Sat Apr  2 14:51:11 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648900271509 ""}

db/spectrum.cbx.xml

@@ -4,6 +4,7 @@
 		<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram16:ram0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_7ti2.tdf"/>
 		<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram32:ram1|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_g9i1.tdf"/>
 		<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" CBX_FILE_NAME="sdram_clk_gen_altpll.v"/>
 		<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ula:ula_|pll:pll_|altpll:altpll_component" CBX_FILE_NAME="pll_altpll.v"/>
 	</PROJECT>
 </LOG_ROOT>

db/spectrum.cmp.logdb

@@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000
 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
 IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
 IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,75;9;75;0;0;75;75;0;75;75;0;0;0;0;41;0;0;41;0;0;2;0;0;0;0;0;0;75;0;0,
+IO_RULES_MATRIX,Total Pass,114;29;114;0;0;114;114;0;114;114;0;0;0;0;57;0;0;57;0;0;10;0;0;0;0;0;0;114;0;0,
 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;66;0;75;75;0;0;75;0;0;75;75;75;75;34;75;75;34;75;75;73;75;75;75;75;75;75;0;75;75,
+IO_RULES_MATRIX,Total Inapplicable,0;85;0;114;114;0;0;114;0;0;114;114;114;114;57;114;114;57;114;114;104;114;114;114;114;114;114;0;114;114,
 IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
 IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
@@ -98,8 +98,47 @@ IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass
 IO_RULES_MATRIX,GPIO_1[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,GPIO_1[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,buzzer_out,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQM[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQM[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_RAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_WE_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,

db/spectrum.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 Version_Index = 318808576
-Creation_Time = Wed Mar 30 18:55:53 2022
+Creation_Time = Sat Apr  2 13:37:52 2022

db/spectrum.eda.qmsg

@@ -1,12 +1,12 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900279498 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr  1 18:55:50 2022 " "Processing started: Fri Apr  1 18:55:50 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr  2 14:51:19 2022 " "Processing started: Sat Apr  2 14:51:19 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280426 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280767 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281107 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281449 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281719 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281988 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282253 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282522 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr  1 18:55:53 2022 " "Processing ended: Fri Apr  1 18:55:53 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr  2 14:51:22 2022 " "Processing ended: Sat Apr  2 14:51:22 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""}

db/spectrum.hier_info

@@ -1,80 +1,119 @@
 |spectrum
-LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
+LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
-LED[1] << <GND>
+LED[1] <= <GND>
-LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE
+LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
-LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
+LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
-LED[4] << <GND>
+LED[4] <= <GND>
-LED[5] << <GND>
+LED[5] <= <GND>
-LED[6] << <GND>
+LED[6] <= <GND>
-LED[7] << <GND>
+LED[7] <= <GND>
-CLOCK_50 => CLOCK_50.IN3
+CLOCK_50 => CLOCK_50.IN4
 KEY[0] => reset.IN1
 KEY[1] => nNMI.IN1
 PS2_CLK => PS2_CLK.IN1
 PS2_DAT => PS2_DAT.IN1
 I2C_SCLK <> ula:ula_.I2C_SCLK
 I2C_SDAT <> ula:ula_.I2C_SDAT
-AUD_XCK << ula:ula_.AUD_XCK
+AUD_XCK <= ula:ula_.AUD_XCK
-AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK
+AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK
-AUD_DACLRCK << ula:ula_.AUD_DACLRCK
+AUD_DACLRCK <= ula:ula_.AUD_DACLRCK
-AUD_BCLK << ula:ula_.AUD_BCLK
+AUD_BCLK <= ula:ula_.AUD_BCLK
-AUD_DACDAT << ula:ula_.AUD_DACDAT
+AUD_DACDAT <= ula:ula_.AUD_DACDAT
 AUD_ADCDAT => AUD_ADCDAT.IN1
-VGA_R[0] << ula:ula_.VGA_R
+VGA_R[0] <= ula:ula_.VGA_R
-VGA_R[1] << ula:ula_.VGA_R
+VGA_R[1] <= ula:ula_.VGA_R
-VGA_R[2] << ula:ula_.VGA_R
+VGA_R[2] <= ula:ula_.VGA_R
-VGA_R[3] << ula:ula_.VGA_R
+VGA_R[3] <= ula:ula_.VGA_R
-VGA_G[0] << ula:ula_.VGA_G
+VGA_G[0] <= ula:ula_.VGA_G
-VGA_G[1] << ula:ula_.VGA_G
+VGA_G[1] <= ula:ula_.VGA_G
-VGA_G[2] << ula:ula_.VGA_G
+VGA_G[2] <= ula:ula_.VGA_G
-VGA_G[3] << ula:ula_.VGA_G
+VGA_G[3] <= ula:ula_.VGA_G
-VGA_B[0] << ula:ula_.VGA_B
+VGA_B[0] <= ula:ula_.VGA_B
-VGA_B[1] << ula:ula_.VGA_B
+VGA_B[1] <= ula:ula_.VGA_B
-VGA_B[2] << ula:ula_.VGA_B
+VGA_B[2] <= ula:ula_.VGA_B
-VGA_B[3] << ula:ula_.VGA_B
+VGA_B[3] <= ula:ula_.VGA_B
-VGA_HS << ula:ula_.VGA_HS
+VGA_HS <= ula:ula_.VGA_HS
-VGA_VS << ula:ula_.VGA_VS
+VGA_VS <= ula:ula_.VGA_VS
 SW[0] => ~NO_FANOUT~
 SW[1] => LED[0].DATAIN
 SW[1] => comb.OUTPUTSELECT
 SW[2] => SW[2].IN1
 SW[3] => ~NO_FANOUT~
-GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
+GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK
-GPIO_1[25] << z80_top_direct_n:z80_.nHALT
+GPIO_1[25] <= z80_top_direct_n:z80_.nHALT
-GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
+GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH
-GPIO_1[27] << z80_top_direct_n:z80_.nWR
+GPIO_1[27] <= z80_top_direct_n:z80_.nWR
-GPIO_1[28] << z80_top_direct_n:z80_.nRD
+GPIO_1[28] <= z80_top_direct_n:z80_.nRD
-GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
+GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ
-GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
+GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ
-GPIO_1[31] << z80_top_direct_n:z80_.nM1
+GPIO_1[31] <= z80_top_direct_n:z80_.nM1
-GPIO_1[32] << <GND>
+GPIO_1[32] <= <GND>
-GPIO_1[33] << <GND>
+GPIO_1[33] <= <GND>
-buzzer_out << ula:ula_.beep
+buzzer_out <= ula:ula_.beep
 raw_loader_in => raw_loader_in.IN1
+DRAM_BA[0] <= sdram_controller:sdram_.DRAM_BA
+DRAM_BA[1] <= sdram_controller:sdram_.DRAM_BA
+DRAM_DQM[0] <= sdram_controller:sdram_.DRAM_DQM
+DRAM_DQM[1] <= sdram_controller:sdram_.DRAM_DQM
+DRAM_RAS_N <= sdram_controller:sdram_.DRAM_RAS_N
+DRAM_CAS_N <= sdram_controller:sdram_.DRAM_CAS_N
+DRAM_CKE <= sdram_controller:sdram_.DRAM_CKE
+DRAM_CLK <= sdram_controller:sdram_.DRAM_CLK
+DRAM_WE_N <= sdram_controller:sdram_.DRAM_WE_N
+DRAM_CS_N <= sdram_controller:sdram_.DRAM_CS_N
+DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[3] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[4] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[5] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[6] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[7] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[8] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[9] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[10] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[11] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_ADDR[0] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[1] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[2] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[3] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[4] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[5] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[6] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[7] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[8] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[9] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[10] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[11] <= sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[12] <= sdram_controller:sdram_.DRAM_ADDR
 
 
 |spectrum|rom0:rom
@@ -1991,6 +2030,296 @@ sel[1] => _.IN0
 sel[1] => _.IN0
 
 
+|spectrum|sdram_controller:sdram_
+CLOCK_50 => sdram_clk_gen:sdram_clk_pll.inclk0
+DRAM_ADDR[0] <= r.address[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[1] <= r.address[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[2] <= r.address[2].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[3] <= r.address[3].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[4] <= r.address[4].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[5] <= r.address[5].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[6] <= r.address[6].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[7] <= r.address[7].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[8] <= r.address[8].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[9] <= r.address[9].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[10] <= r.address[10].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[11] <= r.address[11].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[12] <= r.address[12].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_BA[0] <= r.bank[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_BA[1] <= r.bank[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_CAS_N <= r.state[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_CKE <= <VCC>
+DRAM_CLK <= sdram_clk_gen:sdram_clk_pll.c1
+DRAM_CS_N <= r.state[3].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_DQ[0] <> DRAM_DQ[0]
+DRAM_DQ[1] <> DRAM_DQ[1]
+DRAM_DQ[2] <> DRAM_DQ[2]
+DRAM_DQ[3] <> DRAM_DQ[3]
+DRAM_DQ[4] <> DRAM_DQ[4]
+DRAM_DQ[5] <> DRAM_DQ[5]
+DRAM_DQ[6] <> DRAM_DQ[6]
+DRAM_DQ[7] <> DRAM_DQ[7]
+DRAM_DQ[8] <> DRAM_DQ[8]
+DRAM_DQ[9] <> DRAM_DQ[9]
+DRAM_DQ[10] <> DRAM_DQ[10]
+DRAM_DQ[11] <> DRAM_DQ[11]
+DRAM_DQ[12] <> DRAM_DQ[12]
+DRAM_DQ[13] <> DRAM_DQ[13]
+DRAM_DQ[14] <> DRAM_DQ[14]
+DRAM_DQ[15] <> DRAM_DQ[15]
+DRAM_DQM[0] <= r.dq_masks[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_DQM[1] <= r.dq_masks[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_RAS_N <= r.state[2].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_WE_N <= r.state[0].DB_MAX_OUTPUT_PORT_TYPE
+address[0] => ~NO_FANOUT~
+address[1] => n.DATAB
+address[1] => n.DATAB
+address[1] => Mux22.IN36
+address[2] => n.DATAB
+address[2] => n.DATAB
+address[2] => Mux21.IN36
+address[3] => n.DATAB
+address[3] => n.DATAB
+address[3] => Mux20.IN36
+address[4] => n.DATAB
+address[4] => n.DATAB
+address[4] => Mux19.IN36
+address[5] => n.DATAB
+address[5] => n.DATAB
+address[5] => Mux18.IN36
+address[6] => n.DATAB
+address[6] => n.DATAB
+address[6] => Mux17.IN36
+address[7] => n.DATAB
+address[7] => n.DATAB
+address[7] => Mux16.IN36
+address[8] => n.DATAB
+address[8] => n.DATAB
+address[8] => Mux15.IN36
+address[9] => n.DATAB
+address[9] => n.DATAB
+address[9] => n.DATAB
+address[9] => Mux26.IN36
+address[10] => n.DATAB
+address[10] => n.DATAB
+address[10] => n.DATAB
+address[10] => Mux25.IN36
+address[11] => Equal7.IN25
+address[11] => n.DATAB
+address[11] => n.DATAB
+address[12] => Equal7.IN24
+address[12] => n.DATAB
+address[12] => n.DATAB
+address[13] => Equal7.IN23
+address[13] => n.DATAB
+address[13] => n.DATAB
+address[14] => Equal7.IN22
+address[14] => n.DATAB
+address[14] => n.DATAB
+address[15] => Equal7.IN21
+address[15] => n.DATAB
+address[15] => n.DATAB
+address[16] => Equal7.IN20
+address[16] => n.DATAB
+address[16] => n.DATAB
+address[17] => Equal7.IN19
+address[17] => n.DATAB
+address[17] => n.DATAB
+address[18] => Equal7.IN18
+address[18] => n.DATAB
+address[18] => n.DATAB
+address[19] => Equal7.IN17
+address[19] => n.DATAB
+address[19] => n.DATAB
+address[20] => Equal7.IN16
+address[20] => n.DATAB
+address[20] => n.DATAB
+address[21] => Equal7.IN15
+address[21] => n.DATAB
+address[21] => n.DATAB
+address[22] => Equal7.IN14
+address[22] => n.DATAB
+address[22] => n.DATAB
+address[23] => Equal7.IN13
+address[23] => n.DATAB
+address[23] => n.DATAB
+req_read => n.OUTPUTSELECT
+req_write => n.OUTPUTSELECT
+data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= r.data_out_low[2].DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= r.data_out_low[3].DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= r.data_out_low[4].DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= r.data_out_low[5].DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= r.data_out_low[6].DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= r.data_out_low[7].DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= r.data_out_low[8].DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= r.data_out_low[9].DB_MAX_OUTPUT_PORT_TYPE
+data_out[10] <= r.data_out_low[10].DB_MAX_OUTPUT_PORT_TYPE
+data_out[11] <= r.data_out_low[11].DB_MAX_OUTPUT_PORT_TYPE
+data_out[12] <= r.data_out_low[12].DB_MAX_OUTPUT_PORT_TYPE
+data_out[13] <= r.data_out_low[13].DB_MAX_OUTPUT_PORT_TYPE
+data_out[14] <= r.data_out_low[14].DB_MAX_OUTPUT_PORT_TYPE
+data_out[15] <= r.data_out_low[15].DB_MAX_OUTPUT_PORT_TYPE
+data_out[16] <= captured[0].DB_MAX_OUTPUT_PORT_TYPE
+data_out[17] <= captured[1].DB_MAX_OUTPUT_PORT_TYPE
+data_out[18] <= captured[2].DB_MAX_OUTPUT_PORT_TYPE
+data_out[19] <= captured[3].DB_MAX_OUTPUT_PORT_TYPE
+data_out[20] <= captured[4].DB_MAX_OUTPUT_PORT_TYPE
+data_out[21] <= captured[5].DB_MAX_OUTPUT_PORT_TYPE
+data_out[22] <= captured[6].DB_MAX_OUTPUT_PORT_TYPE
+data_out[23] <= captured[7].DB_MAX_OUTPUT_PORT_TYPE
+data_out[24] <= captured[8].DB_MAX_OUTPUT_PORT_TYPE
+data_out[25] <= captured[9].DB_MAX_OUTPUT_PORT_TYPE
+data_out[26] <= captured[10].DB_MAX_OUTPUT_PORT_TYPE
+data_out[27] <= captured[11].DB_MAX_OUTPUT_PORT_TYPE
+data_out[28] <= captured[12].DB_MAX_OUTPUT_PORT_TYPE
+data_out[29] <= captured[13].DB_MAX_OUTPUT_PORT_TYPE
+data_out[30] <= captured[14].DB_MAX_OUTPUT_PORT_TYPE
+data_out[31] <= captured[15].DB_MAX_OUTPUT_PORT_TYPE
+data_out_valid <= r.data_out_valid.DB_MAX_OUTPUT_PORT_TYPE
+data_in[0] => Mux72.IN30
+data_in[0] => Mux72.IN31
+data_in[1] => Mux3.IN30
+data_in[1] => Mux3.IN31
+data_in[2] => Mux2.IN30
+data_in[2] => Mux2.IN31
+data_in[3] => Mux1.IN30
+data_in[3] => Mux1.IN31
+data_in[4] => Mux0.IN30
+data_in[4] => Mux0.IN31
+data_in[5] => Mux73.IN30
+data_in[5] => Mux73.IN31
+data_in[6] => Mux74.IN30
+data_in[6] => Mux74.IN31
+data_in[7] => Mux75.IN30
+data_in[7] => Mux75.IN31
+data_in[8] => Mux76.IN30
+data_in[8] => Mux76.IN31
+data_in[9] => Mux77.IN30
+data_in[9] => Mux77.IN31
+data_in[10] => Mux78.IN30
+data_in[10] => Mux78.IN31
+data_in[11] => Mux79.IN30
+data_in[11] => Mux79.IN31
+data_in[12] => Mux80.IN30
+data_in[12] => Mux80.IN31
+data_in[13] => Mux81.IN30
+data_in[13] => Mux81.IN31
+data_in[14] => Mux82.IN30
+data_in[14] => Mux82.IN31
+data_in[15] => Mux83.IN30
+data_in[15] => Mux83.IN31
+data_in[16] => Mux72.IN28
+data_in[16] => Mux72.IN29
+data_in[17] => Mux3.IN28
+data_in[17] => Mux3.IN29
+data_in[18] => Mux2.IN28
+data_in[18] => Mux2.IN29
+data_in[19] => Mux1.IN28
+data_in[19] => Mux1.IN29
+data_in[20] => Mux0.IN28
+data_in[20] => Mux0.IN29
+data_in[21] => Mux73.IN28
+data_in[21] => Mux73.IN29
+data_in[22] => Mux74.IN28
+data_in[22] => Mux74.IN29
+data_in[23] => Mux75.IN28
+data_in[23] => Mux75.IN29
+data_in[24] => Mux76.IN28
+data_in[24] => Mux76.IN29
+data_in[25] => Mux77.IN28
+data_in[25] => Mux77.IN29
+data_in[26] => Mux78.IN28
+data_in[26] => Mux78.IN29
+data_in[27] => Mux79.IN28
+data_in[27] => Mux79.IN29
+data_in[28] => Mux80.IN28
+data_in[28] => Mux80.IN29
+data_in[29] => Mux81.IN28
+data_in[29] => Mux81.IN29
+data_in[30] => Mux82.IN28
+data_in[30] => Mux82.IN29
+data_in[31] => Mux83.IN28
+data_in[31] => Mux83.IN29
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
+inclk0 => sub_wire4[0].IN1
+c0 <= altpll:altpll_component.clk
+c1 <= altpll:altpll_component.clk
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
+inclk[0] => sdram_clk_gen_altpll:auto_generated.inclk[0]
+inclk[1] => sdram_clk_gen_altpll:auto_generated.inclk[1]
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <> <GND>
+clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
+clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
+clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
+clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= <GND>
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+fref <= <GND>
+icdrclk <= <GND>
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated
+clk[0] <= pll1.CLK
+clk[1] <= pll1.CLK1
+clk[2] <= pll1.CLK2
+clk[3] <= pll1.CLK3
+clk[4] <= pll1.CLK4
+inclk[0] => pll1.CLK
+inclk[1] => pll1.CLK1
+
+
 |spectrum|ula:ula_
 CLOCK_50 => CLOCK_50.IN1
 turbo => clocks:clocks_.turbo

db/spectrum.lpc.html

@@ -1424,6 +1424,54 @@
 <TD >0</TD>
 </TR>
 <TR >
+<TD >sdram_|sdram_clk_pll|altpll_component|auto_generated</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sdram_|sdram_clk_pll</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sdram_</TD>
+<TD >59</TD>
+<TD >33</TD>
+<TD >1</TD>
+<TD >33</TD>
+<TD >56</TD>
+<TD >33</TD>
+<TD >33</TD>
+<TD >33</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
 <TD >ram1|altsyncram_component|auto_generated|mux2</TD>
 <TD >34</TD>
 <TD >0</TD>

db/spectrum.lpc.txt

@@ -1321,6 +1321,51 @@ Unused Bidir      : 0
 Input only Bidir  : 0
 Output only Bidir : 0
 
+Hierarchy         : sdram_|sdram_clk_pll|altpll_component|auto_generated
+Input             : 2
+Constant Input    : 0
+Unused Input      : 0
+Floating Input    : 0
+Output            : 5
+Constant Output   : 0
+Unused Output     : 0
+Floating Output   : 0
+Bidir             : 0
+Constant Bidir    : 0
+Unused Bidir      : 0
+Input only Bidir  : 0
+Output only Bidir : 0
+
+Hierarchy         : sdram_|sdram_clk_pll
+Input             : 1
+Constant Input    : 0
+Unused Input      : 0
+Floating Input    : 0
+Output            : 2
+Constant Output   : 0
+Unused Output     : 0
+Floating Output   : 0
+Bidir             : 0
+Constant Bidir    : 0
+Unused Bidir      : 0
+Input only Bidir  : 0
+Output only Bidir : 0
+
+Hierarchy         : sdram_
+Input             : 59
+Constant Input    : 33
+Unused Input      : 1
+Floating Input    : 33
+Output            : 56
+Constant Output   : 33
+Unused Output     : 33
+Floating Output   : 33
+Bidir             : 16
+Constant Bidir    : 0
+Unused Bidir      : 0
+Input only Bidir  : 0
+Output only Bidir : 0
+
 Hierarchy         : ram1|altsyncram_component|auto_generated|mux2
 Input             : 34
 Constant Input    : 0

greybox_tmp/cbx_args.txt

@@ -1,16 +1,12 @@
 BANDWIDTH_TYPE=AUTO
-CLK0_DIVIDE_BY=143
+CLK0_DIVIDE_BY=1
 CLK0_DUTY_CYCLE=50
-CLK0_MULTIPLY_BY=72
+CLK0_MULTIPLY_BY=2
 CLK0_PHASE_SHIFT=0
-CLK1_DIVIDE_BY=25
+CLK1_DIVIDE_BY=1
 CLK1_DUTY_CYCLE=50
-CLK1_MULTIPLY_BY=7
+CLK1_MULTIPLY_BY=2
-CLK1_PHASE_SHIFT=0
+CLK1_PHASE_SHIFT=3000
-CLK2_DIVIDE_BY=25
-CLK2_DUTY_CYCLE=50
-CLK2_MULTIPLY_BY=12
-CLK2_PHASE_SHIFT=0
 COMPENSATE_CLOCK=CLK0
 INCLK0_INPUT_FREQUENCY=20000
 INTENDED_DEVICE_FAMILY="Cyclone IV E"
@@ -27,7 +23,7 @@ PORT_CONFIGUPDATE=PORT_UNUSED
 PORT_FBIN=PORT_UNUSED
 PORT_INCLK0=PORT_USED
 PORT_INCLK1=PORT_UNUSED
-PORT_LOCKED=PORT_USED
+PORT_LOCKED=PORT_UNUSED
 PORT_PFDENA=PORT_UNUSED
 PORT_PHASECOUNTERSELECT=PORT_UNUSED
 PORT_PHASEDONE=PORT_UNUSED
@@ -44,7 +40,7 @@ PORT_SCANREAD=PORT_UNUSED
 PORT_SCANWRITE=PORT_UNUSED
 PORT_clk0=PORT_USED
 PORT_clk1=PORT_USED
-PORT_clk2=PORT_USED
+PORT_clk2=PORT_UNUSED
 PORT_clk3=PORT_UNUSED
 PORT_clk4=PORT_UNUSED
 PORT_clk5=PORT_UNUSED
@@ -58,7 +54,6 @@ PORT_extclk0=PORT_UNUSED
 PORT_extclk1=PORT_UNUSED
 PORT_extclk2=PORT_UNUSED
 PORT_extclk3=PORT_UNUSED
-SELF_RESET_ON_LOSS_LOCK=OFF
 WIDTH_CLOCK=5
 DEVICE_FAMILY="Cyclone IV E"
 CBX_AUTO_BLACKBOX=ALL
@@ -66,5 +61,3 @@ inclk
 inclk
 clk
 clk
-clk
-locked

incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig

@@ -1 +1 @@
-10e1a0c80ecdc93e9346871a78e4d333
+fddacec392eaa469e7503e0701c963ef

output_files/spectrum.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for spectrum
-Fri Apr  1 18:55:43 2022
+Sat Apr  2 14:51:11 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -37,7 +37,7 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Apr  1 18:55:43 2022 ;
+; Assembler Status      ; Successful - Sat Apr  2 14:51:11 2022 ;
 ; Revision Name         ; spectrum                              ;
 ; Top-level Entity Name ; spectrum                              ;
 ; Family                ; Cyclone IV E                          ;
@@ -162,8 +162,8 @@ Default Value : On
 ; Option         ; Setting               ;
 +----------------+-----------------------+
 ; Device         ; EP4CE22F17C6          ;
-; JTAG usercode  ; 0x0056423F            ;
+; JTAG usercode  ; 0x0058B9EB            ;
-; Checksum       ; 0x0056423F            ;
+; Checksum       ; 0x0058B9EB            ;
 +----------------+-----------------------+
 
 
@@ -173,13 +173,13 @@ Default Value : On
 Info: *******************************************************************
 Info: Running Quartus II 32-bit Assembler
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Fri Apr  1 18:55:41 2022
+    Info: Processing started: Sat Apr  2 14:51:09 2022
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 385 megabytes
+    Info: Peak virtual memory: 383 megabytes
-    Info: Processing ended: Fri Apr  1 18:55:43 2022
+    Info: Processing ended: Sat Apr  2 14:51:11 2022
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

output_files/spectrum.done

@@ -1 +1 @@
-Fri Apr  1 18:55:53 2022
+Sat Apr  2 14:51:22 2022

output_files/spectrum.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for spectrum
-Fri Apr  1 18:55:53 2022
+Sat Apr  2 14:51:22 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -36,7 +36,7 @@ applicable agreement for further details.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Fri Apr  1 18:55:53 2022 ;
+; EDA Netlist Writer Status ; Successful - Sat Apr  2 14:51:22 2022 ;
 ; Revision Name             ; spectrum                              ;
 ; Top-level Entity Name     ; spectrum                              ;
 ; Family                    ; Cyclone IV E                          ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
 Info: *******************************************************************
 Info: Running Quartus II 32-bit EDA Netlist Writer
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Fri Apr  1 18:55:50 2022
+    Info: Processing started: Sat Apr  2 14:51:19 2022
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
 Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
@@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
 Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 380 megabytes
+    Info: Peak virtual memory: 379 megabytes
-    Info: Processing ended: Fri Apr  1 18:55:53 2022
+    Info: Processing ended: Sat Apr  2 14:51:22 2022
     Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:03
 

output_files/spectrum.fit.summary

@@ -1,16 +1,16 @@
-Fitter Status : Successful - Fri Apr  1 18:55:39 2022
+Fitter Status : Successful - Sat Apr  2 14:51:07 2022
 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
 Revision Name : spectrum
 Top-level Entity Name : spectrum
 Family : Cyclone IV E
 Device : EP4CE22F17C6
 Timing Models : Final
-Total logic elements : 2,396 / 22,320 ( 11 % )
+Total logic elements : 2,609 / 22,320 ( 12 % )
-    Total combinational functions : 2,272 / 22,320 ( 10 % )
+    Total combinational functions : 2,490 / 22,320 ( 11 % )
-    Dedicated logic registers : 591 / 22,320 ( 3 % )
+    Dedicated logic registers : 635 / 22,320 ( 3 % )
-Total registers : 600
+Total registers : 664
-Total pins : 75 / 154 ( 49 % )
+Total pins : 114 / 154 ( 74 % )
 Total virtual pins : 0
 Total memory bits : 524,288 / 608,256 ( 86 % )
 Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
-Total PLLs : 1 / 4 ( 25 % )
+Total PLLs : 2 / 4 ( 50 % )

output_files/spectrum.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for spectrum
-Fri Apr  1 18:55:53 2022
+Sat Apr  2 14:51:22 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -40,22 +40,22 @@ applicable agreement for further details.
 +---------------------------------------------------------------------------------+
 ; Flow Summary                                                                    ;
 +------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Fri Apr  1 18:55:53 2022      ;
+; Flow Status                        ; Successful - Sat Apr  2 14:51:22 2022      ;
 ; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
 ; Revision Name                      ; spectrum                                   ;
 ; Top-level Entity Name              ; spectrum                                   ;
 ; Family                             ; Cyclone IV E                               ;
 ; Device                             ; EP4CE22F17C6                               ;
 ; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 2,396 / 22,320 ( 11 % )                    ;
+; Total logic elements               ; 2,609 / 22,320 ( 12 % )                    ;
-;     Total combinational functions  ; 2,272 / 22,320 ( 10 % )                    ;
+;     Total combinational functions  ; 2,490 / 22,320 ( 11 % )                    ;
-;     Dedicated logic registers      ; 591 / 22,320 ( 3 % )                       ;
+;     Dedicated logic registers      ; 635 / 22,320 ( 3 % )                       ;
-; Total registers                    ; 600                                        ;
+; Total registers                    ; 664                                        ;
-; Total pins                         ; 75 / 154 ( 49 % )                          ;
+; Total pins                         ; 114 / 154 ( 74 % )                         ;
 ; Total virtual pins                 ; 0                                          ;
 ; Total memory bits                  ; 524,288 / 608,256 ( 86 % )                 ;
 ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                            ;
-; Total PLLs                         ; 1 / 4 ( 25 % )                             ;
+; Total PLLs                         ; 2 / 4 ( 50 % )                             ;
 +------------------------------------+--------------------------------------------+
 
 
@@ -64,7 +64,7 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 04/01/2022 18:55:04 ;
+; Start date & time ; 04/02/2022 14:50:31 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; spectrum            ;
 +-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
 ; Flow Non-Default Global Settings                                               ;
 +--------------------------------------------------------------------------------+
 Assignment Name : COMPILER_SIGNATURE_ID
-Value           : 0.164882850457192
+Value           : 0.164890023113286
 Default Value   : --
 Entity Name     : --
 Section Id      : --
@@ -133,6 +133,12 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : IP_TOOL_NAME
+Value           : ALTPLL
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : IP_TOOL_VERSION
 Value           : 13.1
 Default Value   : --
@@ -175,6 +181,12 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : IP_TOOL_VERSION
+Value           : 13.1
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : MAX_CORE_JUNCTION_TEMP
 Value           : 85
 Default Value   : --
@@ -241,6 +253,18 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : MISC_FILE
+Value           : sdram_clk_gen_bb.v
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : MISC_FILE
+Value           : sdram_clk_gen.ppf
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
 Value           : 1.2V
 Default Value   : --
@@ -278,40 +302,40 @@ Section Id      : --
 ; Flow Elapsed Time                                                              ;
 +--------------------------------------------------------------------------------+
 Module Name                        : Analysis & Synthesis
-Elapsed Time                       : 00:00:13
+Elapsed Time                       : 00:00:14
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 441 MB
+Peak Virtual Memory                : 446 MB
-Total CPU Time (on all processors) : 00:00:13
+Total CPU Time (on all processors) : 00:00:14
 
 Module Name                        : Fitter
 Elapsed Time                       : 00:00:21
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 639 MB
+Peak Virtual Memory                : 641 MB
 Total CPU Time (on all processors) : 00:00:21
 
 Module Name                        : Assembler
 Elapsed Time                       : 00:00:02
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 385 MB
+Peak Virtual Memory                : 383 MB
 Total CPU Time (on all processors) : 00:00:02
 
 Module Name                        : TimeQuest Timing Analyzer
-Elapsed Time                       : 00:00:04
+Elapsed Time                       : 00:00:03
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 437 MB
+Peak Virtual Memory                : 445 MB
 Total CPU Time (on all processors) : 00:00:04
 
 Module Name                        : EDA Netlist Writer
 Elapsed Time                       : 00:00:03
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 372 MB
+Peak Virtual Memory                : 371 MB
 Total CPU Time (on all processors) : 00:00:03
 
 Module Name                        : Total
 Elapsed Time                       : 00:00:43
 Average Processors Used            : --
 Peak Virtual Memory                : --
-Total CPU Time (on all processors) : 00:00:43
+Total CPU Time (on all processors) : 00:00:44
 +--------------------------------------------------------------------------------+
 
 

output_files/spectrum.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="8380d13cf466db2d8054"/>
+    <hash md5_digest_80b="e17a9ad4e9f9aba40443"/>
   </project>
   <file_info>
     <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>

output_files/spectrum.map.summary

@@ -1,14 +1,14 @@
-Analysis & Synthesis Status : Successful - Fri Apr  1 18:55:17 2022
+Analysis & Synthesis Status : Successful - Sat Apr  2 14:50:45 2022
 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
 Revision Name : spectrum
 Top-level Entity Name : spectrum
 Family : Cyclone IV E
-Total logic elements : 2,537
+Total logic elements : 2,751
-    Total combinational functions : 2,269
+    Total combinational functions : 2,480
-    Dedicated logic registers : 592
+    Dedicated logic registers : 649
-Total registers : 592
+Total registers : 649
-Total pins : 75
+Total pins : 114
 Total virtual pins : 0
 Total memory bits : 524,288
 Embedded Multiplier 9-bit elements : 0
-Total PLLs : 1
+Total PLLs : 2

output_files/spectrum.pin

@@ -101,7 +101,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :
 GND                          : B15       : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 6         :                
 ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1        : input  : 3.3-V LVTTL       :         : 1         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+DRAM_WE_N                    : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
 VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
 GND                          : C5        : gnd    :                   :         :           :                
@@ -164,8 +164,8 @@ GPIO_1[0]                    : F13       : output : 3.3-V LVTTL       :
 RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 6         :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 6         :                
 ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16       : output : 3.3-V LVTTL       :         : 6         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1        :        :                   :         : 1         :                
+DRAM_DQ[1]                   : G1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2        :        :                   :         : 1         :                
+DRAM_DQ[0]                   : G2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 VCCIO1                       : G3        : power  :                   : 3.3V    : 1         :                
 GND                          : G4        : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
@@ -196,8 +196,8 @@ MSEL0                        : H13       :        :                   :
 CONF_DONE                    : H14       :        :                   :         : 6         :                
 GND                          : H15       : gnd    :                   :         :           :                
 GND                          : H16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 2         :                
+DRAM_DQ[6]                   : J1        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 2         :                
+DRAM_DQ[5]                   : J2        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 nCE                          : J3        :        :                   :         : 1         :                
 TDO                          : J4        : output :                   :         : 1         :                
 TMS                          : J5        : input  :                   :         : 1         :                
@@ -212,11 +212,11 @@ GPIO_1[32]                   : J13       : output : 3.3-V LVTTL       :
 GPIO_1[33]                   : J14       : output : 3.3-V LVTTL       :         : 5         : Y              
 KEY[0]                       : J15       : input  : 3.3-V LVTTL       :         : 5         : Y              
 GPIO_1[30]                   : J16       : output : 3.3-V LVTTL       :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1        :        :                   :         : 2         :                
+DRAM_DQ[15]                  : K1        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2        :        :                   :         : 2         :                
+DRAM_DQ[4]                   : K2        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
 GND                          : K4        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K5        :        :                   :         : 2         :                
+DRAM_DQ[3]                   : K5        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 GND                          : K6        : gnd    :                   :         :           :                
 VCCINT                       : K7        : power  :                   : 1.2V    :           :                
 GND                          : K8        : gnd    :                   :         :           :                
@@ -228,14 +228,14 @@ GND                          : K13       : gnd    :                   :
 VCCIO5                       : K14       : power  :                   : 3.3V    : 5         :                
 GPIO_1[31]                   : K15       : output : 3.3-V LVTTL       :         : 5         : Y              
 GPIO_1[17]                   : K16       : output : 3.3-V LVTTL       :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1        :        :                   :         : 2         :                
+DRAM_CAS_N                   : L1        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2        :        :                   :         : 2         :                
+DRAM_RAS_N                   : L2        : output : 3.3-V LVTTL       :         : 2         : Y              
 LED[7]                       : L3        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4        :        :                   :         : 2         :                
+DRAM_ADDR[12]                : L4        : output : 3.3-V LVTTL       :         : 2         : Y              
 VCCA1                        : L5        : power  :                   : 2.5V    :           :                
 VCCINT                       : L6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 3         :                
+DRAM_CKE                     : L7        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 3         :                
+DRAM_DQ[2]                   : L8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 GND                          : L9        : gnd    :                   :         :           :                
 GND                          : L10       : gnd    :                   :         :           :                
 GND                          : L11       : gnd    :                   :         :           :                
@@ -249,9 +249,9 @@ GND+                         : M2        :        :                   :
 VCCIO2                       : M3        : power  :                   : 3.3V    : 2         :                
 GND                          : M4        : gnd    :                   :         :           :                
 GNDA1                        : M5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3         :                
+DRAM_BA[1]                   : M6        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3         :                
+DRAM_BA[0]                   : M7        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3         :                
+DRAM_ADDR[3]                 : M8        : output : 3.3-V LVTTL       :         : 3         : Y              
 VCCINT                       : M9        : power  :                   : 1.2V    :           :                
 GPIO_1[28]                   : M10       : output : 3.3-V LVTTL       :         : 4         : Y              
 VCCINT                       : M11       : power  :                   : 1.2V    :           :                
@@ -260,14 +260,14 @@ GND                          : M13       : gnd    :                   :
 VCCIO5                       : M14       : power  :                   : 3.3V    : 5         :                
 SW[3]                        : M15       : input  : 3.3-V LVTTL       :         : 5         : Y              
 GND+                         : M16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+DRAM_ADDR[11]                : N1        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+DRAM_ADDR[10]                : N2        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3        :        :                   :         : 3         :                
+DRAM_DQ[14]                  : N3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 VCCD_PLL1                    : N4        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 3         :                
+DRAM_ADDR[1]                 : N5        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+DRAM_ADDR[2]                 : N6        : output : 3.3-V LVTTL       :         : 3         : Y              
 GND                          : N7        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3         :                
+DRAM_ADDR[6]                 : N8        : output : 3.3-V LVTTL       :         : 3         : Y              
 GPIO_1[14]                   : N9        : output : 3.3-V LVTTL       :         : 4         : Y              
 GND                          : N10       : gnd    :                   :         :           :                
 GPIO_1[15]                   : N11       : output : 3.3-V LVTTL       :         : 4         : Y              
@@ -276,14 +276,14 @@ VCCD_PLL4                    : N13       : power  :                   : 1.2V
 GPIO_1[27]                   : N14       : output : 3.3-V LVTTL       :         : 5         : Y              
 GPIO_1[24]                   : N15       : output : 3.3-V LVTTL       :         : 5         : Y              
 GPIO_1[23]                   : N16       : output : 3.3-V LVTTL       :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+DRAM_ADDR[9]                 : P1        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+DRAM_ADDR[0]                 : P2        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 3         :                
+DRAM_DQ[13]                  : P3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 VCCIO3                       : P4        : power  :                   : 3.3V    : 3         :                
 GND                          : P5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 3         :                
+DRAM_CS_N                    : P6        : output : 3.3-V LVTTL       :         : 3         : Y              
 VCCIO3                       : P7        : power  :                   : 3.3V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3         :                
+DRAM_ADDR[4]                 : P8        : output : 3.3-V LVTTL       :         : 3         : Y              
 GPIO_1[13]                   : P9        : output : 3.3-V LVTTL       :         : 4         : Y              
 VCCIO4                       : P10       : power  :                   : 3.3V    : 4         :                
 GPIO_1[10]                   : P11       : output : 3.3-V LVTTL       :         : 4         : Y              
@@ -292,13 +292,13 @@ VCCIO4                       : P13       : power  :                   : 3.3V
 GPIO_1[25]                   : P14       : output : 3.3-V LVTTL       :         : 4         : Y              
 GPIO_1[20]                   : P15       : output : 3.3-V LVTTL       :         : 5         : Y              
 GPIO_1[21]                   : P16       : output : 3.3-V LVTTL       :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+DRAM_ADDR[8]                 : R1        : output : 3.3-V LVTTL       :         : 2         : Y              
 GND                          : R2        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3        :        :                   :         : 3         :                
+DRAM_DQ[11]                  : R3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4        :        :                   :         : 3         :                
+DRAM_CLK                     : R4        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3         :                
+DRAM_DQ[12]                  : R5        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3         :                
+DRAM_DQM[0]                  : R6        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 3         :                
+DRAM_DQ[7]                   : R7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 CLOCK_50                     : R8        : input  : 3.3-V LVTTL       :         : 3         : Y              
 GND+                         : R9        :        :                   :         : 4         :                
 GPIO_1[11]                   : R10       : output : 3.3-V LVTTL       :         : 4         : Y              
@@ -309,12 +309,12 @@ GPIO_1[22]                   : R14       : output : 3.3-V LVTTL       :
 GND                          : R15       : gnd    :                   :         :           :                
 GPIO_1[18]                   : R16       : output : 3.3-V LVTTL       :         : 5         : Y              
 VCCIO3                       : T1        : power  :                   : 3.3V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T2        :        :                   :         : 3         :                
+DRAM_DQ[9]                   : T2        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 3         :                
+DRAM_DQ[10]                  : T3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 3         :                
+DRAM_DQ[8]                   : T4        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 3         :                
+DRAM_DQM[1]                  : T5        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T6        :        :                   :         : 3         :                
+DRAM_ADDR[7]                 : T6        : output : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3         :                
+DRAM_ADDR[5]                 : T7        : output : 3.3-V LVTTL       :         : 3         : Y              
 SW[1]                        : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
 GND+                         : T9        :        :                   :         : 4         :                
 GPIO_1[8]                    : T10       : output : 3.3-V LVTTL       :         : 4         : Y              

output_files/spectrum.sta.summary

@@ -3,23 +3,23 @@ TimeQuest Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
-Slack : -18.123
+Slack : -18.571
-TNS   : -549.338
+TNS   : -821.372
 
 Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -7.533
+Slack : -7.747
-TNS   : -284.813
+TNS   : -287.138
 
 Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.740
+Slack : -4.731
-TNS   : -42.810
+TNS   : -41.432
 
 Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -2.914
+Slack : -2.915
-TNS   : -2.914
+TNS   : -2.915
 
-Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Type  : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.210
+Slack : 3.503
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
@@ -27,19 +27,31 @@ Slack : 0.342
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.344
+Slack : 0.342
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
 Slack : 0.357
 TNS   : 0.000
 
+Type  : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.359
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.373
+TNS   : 0.000
+
 Type  : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -6.223
+Slack : -6.212
-TNS   : -459.348
+TNS   : -460.730
 
 Type  : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.698
+Slack : 3.666
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.752
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -51,7 +63,7 @@ Slack : 19.602
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 20.595
+Slack : 20.597
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
@@ -59,43 +71,55 @@ Slack : 35.503
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -17.311
+Slack : -17.727
-TNS   : -526.609
+TNS   : -781.205
 
 Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -6.686
+Slack : -6.896
-TNS   : -253.661
+TNS   : -255.894
 
 Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.428
+Slack : -4.422
-TNS   : -40.009
+TNS   : -38.759
 
 Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -2.785
+Slack : -2.786
-TNS   : -2.785
+TNS   : -2.786
+
+Type  : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.148
+TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : 0.298
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.300
+Slack : 0.298
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
-Slack : 0.304
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
 Slack : 0.311
 TNS   : 0.000
 
+Type  : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.339
+TNS   : 0.000
+
 Type  : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -5.744
+Slack : -5.735
-TNS   : -423.582
+TNS   : -424.927
 
 Type  : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.374
+Slack : 3.339
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.748
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
@@ -103,7 +127,7 @@ Slack : 9.489
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 19.600
+Slack : 19.596
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
@@ -115,31 +139,39 @@ Slack : 35.491
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -14.971
+Slack : -15.243
-TNS   : -442.545
+TNS   : -641.328
 
 Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -4.979
+Slack : -4.921
-TNS   : -171.124
+TNS   : -171.346
 
 Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -3.775
+Slack : -3.770
-TNS   : -35.541
+TNS   : -34.841
 
 Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : -2.784
 TNS   : -2.784
 
+Type  : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 6.261
+TNS   : 0.000
+
 Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
-Slack : -0.053
+Slack : 0.098
-TNS   : -0.089
+TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : 0.177
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.178
+Slack : 0.177
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.186
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
@@ -147,11 +179,15 @@ Slack : 0.186
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.693
+Slack : -4.684
-TNS   : -358.284
+TNS   : -358.844
 
 Type  : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 2.518
+Slack : 2.507
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.783
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'

sdram.vhdl

@@ -0,0 +1,510 @@
+------------------------------------------------------
+-- FSM for a SDRAM controller
+--
+-- Version 0.1 - Ready to simulate
+--
+-- Author: Mike Field (hamster@snap.net.nz)
+--
+-- Feel free to use it however you would like, but
+-- just drop me an email to say thanks.
+-------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sdram_controller is
+   PORT (
+   CLOCK_50      : IN STD_LOGIC;
+   
+   -- Signals to/from the SDRAM chip
+   DRAM_ADDR   : OUT   STD_LOGIC_VECTOR (12 downto 0);
+   DRAM_BA      : OUT   STD_LOGIC_VECTOR (1 downto 0);
+   DRAM_CAS_N   : OUT   STD_LOGIC;
+   DRAM_CKE      : OUT   STD_LOGIC;
+   DRAM_CLK      : OUT   STD_LOGIC;
+   DRAM_CS_N   : OUT   STD_LOGIC;
+   DRAM_DQ      : INOUT STD_LOGIC_VECTOR(15 downto 0);
+   DRAM_DQM      : OUT   STD_LOGIC_VECTOR(1 downto 0);
+   DRAM_RAS_N   : OUT   STD_LOGIC;
+   DRAM_WE_N    : OUT   STD_LOGIC;
+   
+   --- Inputs from rest of the system
+   address      : IN     STD_LOGIC_VECTOR (23 downto 0);
+   req_read      : IN     STD_LOGIC;
+   req_write   : IN     STD_LOGIC;
+   data_out      : OUT     STD_LOGIC_VECTOR (31 downto 0);
+   data_out_valid : OUT     STD_LOGIC;
+   data_in      : IN     STD_LOGIC_VECTOR (31 downto 0)
+   );
+end entity;
+   
+   
+architecture rtl of sdram_controller is
+
+   
+   type reg is record
+      state       : std_logic_vector(8 downto 0);
+
+      address     : std_logic_vector(12 downto 0);
+      bank         : std_logic_vector( 1 downto 0);
+
+      init_counter: std_logic_vector(14 downto 0);
+      rf_counter   : std_logic_vector( 9 downto 0);
+      rf_pending    : std_logic;
+
+      rd_pending    : std_logic;
+      wr_pending    : std_logic;
+      act_row       : std_logic_vector(12 downto 0);
+
+      data_out_low: std_logic_vector(15 downto 0);
+      data_out_valid : std_logic;
+
+      dq_masks      : std_logic_vector(1 downto 0);
+   end record;
+   component sdram_clk_gen
+   PORT
+   (
+      inclk0: IN  STD_LOGIC;
+      c0      : OUT STD_LOGIC;
+      c1      : OUT STD_LOGIC
+   );
+   end component;
+
+   -- note to self - this constant should be "(others => '0')" when not simulating!!!
+   signal r : reg := ((others => '0'), (others => '0'), 
+                      (others => '0'), "000000000001000", (others => '0'), 
+                      '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'));
+   signal n : reg;
+   
+   -- Vectors for each SDRAM 'command'
+   --- CS_N, RAS_N, CAS_N, WE_N 
+   constant cmd_nop   : std_logic_vector(3 downto 0) := "0111";
+   constant cmd_read  : std_logic_vector(3 downto 0) := "0101";   -- Must be sure A10 is low.
+   constant cmd_write : std_logic_vector(3 downto 0) := "0100";
+   constant cmd_act   : std_logic_vector(3 downto 0) := "0011";
+   constant cmd_pre   : std_logic_vector(3 downto 0) := "0010";  -- Must set A10 to '1'.
+   constant cmd_ref   : std_logic_vector(3 downto 0) := "0001";
+   constant cmd_mrs     : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
+   -- State assignments
+   constant s_init_nop  : std_logic_vector(8 downto 0) := "00000" & cmd_nop;
+   constant s_init_pre  : std_logic_vector(8 downto 0) := "00000" & cmd_pre;
+   constant s_init_ref  : std_logic_vector(8 downto 0) := "00000" & cmd_ref;
+   constant s_init_mrs  : std_logic_vector(8 downto 0) := "00000" & cmd_mrs;
+   
+   constant s_idle  : std_logic_vector(8 downto 0) := "00001" & cmd_nop;
+   
+   constant s_rf0   : std_logic_vector(8 downto 0) := "00010" & cmd_ref;
+   constant s_rf1   : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
+   constant s_rf2   : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
+   constant s_rf3   : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
+   constant s_rf4   : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
+   constant s_rf5   : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
+
+   constant s_ra0   : std_logic_vector(8 downto 0) := "01000" & cmd_act;
+   constant s_ra1   : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
+   constant s_ra2   : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
+
+   constant s_dr0   : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
+   constant s_dr1   : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
+
+   constant s_wr0   : std_logic_vector(8 downto 0) := "01101" & cmd_write;
+   constant s_wr1   : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
+   constant s_wr2   : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
+   constant s_wr3   : std_logic_vector(8 downto 0) := "10000" & cmd_nop;
+
+   constant s_rd0   : std_logic_vector(8 downto 0) := "10001" & cmd_read;
+   constant s_rd1   : std_logic_vector(8 downto 0) := "10010" & cmd_nop;
+   constant s_rd2   : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
+   constant s_rd3   : std_logic_vector(8 downto 0) := "10100" & cmd_nop;
+   constant s_rd4   : std_logic_vector(8 downto 0) := "10101" & cmd_read;
+   constant s_rd5   : std_logic_vector(8 downto 0) := "10110" & cmd_nop;
+   constant s_rd6   : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
+   constant s_rd7   : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
+   constant s_rd8   : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
+   constant s_rd9   : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
+
+   constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
+   constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
+   constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
+   
+   signal addr_row : std_logic_vector(12 downto 0);
+   signal addr_bank: std_logic_vector(1 downto 0);
+   signal addr_col : std_logic_vector(9 downto 0);
+
+   signal captured : std_logic_vector(15 downto 0);
+   
+   signal clock_100          : std_logic;
+   signal clock_100_delayed_3ns : std_logic;
+begin
+   -- Addressing is in 32 bit words - twice that of the DRAM width,
+   -- so each burst of four access two system words.
+   addr_row  <= address(23 downto 11);
+   addr_bank <= address(10 downto 9);
+   addr_col  <= address(8 downto  1) & "00";
+   
+sdram_clk_pll: sdram_clk_gen
+
+   -- Generate the 100MHz clock and the same phase shifted by 3ns
+   PORT MAP
+   (
+      inclk0    => CLOCK_50,
+      c0         => clock_100,
+      c1         => clock_100_delayed_3ns
+   );
+
+   DRAM_CLK         <= clock_100_delayed_3ns;
+   DRAM_CKE       <= '1';
+   DRAM_CS_N       <= r.state(3);
+   DRAM_RAS_N       <= r.state(2);
+   DRAM_CAS_N       <= r.state(1);
+   DRAM_WE_N       <= r.state(0);
+   DRAM_ADDR      <= r.address;
+   DRAM_BA          <= r.bank;
+   DATA_OUT         <= captured & r.data_out_low;
+   DRAM_DQM       <= r.dq_masks;
+   data_out_valid <= r.data_out_valid;
+
+   process (r, address, req_read, req_write, addr_row, addr_bank, addr_col, data_in, captured)
+   begin
+      -- copy the existing values
+      n <= r;
+      if req_read = '1' then
+         n.rd_pending <= '1';
+      end if;
+      
+      if req_write = '1' then
+         n.wr_pending <= '1';
+      end if;
+      
+      n.dq_masks     <= "11";
+      
+      -- first off, do we need to perform a refresh cycle ASAP?
+      if r.rf_counter = 770 then -- 781 = 64,000,000ns / 8192 / 10ns
+         n.rf_counter <= (others => '0');
+         n.rf_pending <= '1';
+      else
+         -- only start looking for refreshes outside of the initialisation state.
+         if not(r.state(8 downto 4) = s_init_nop(8 downto 4)) then
+            n.rf_counter <= r.rf_counter + 1;
+         end if;
+      end if;
+      
+      -- Set the data bus into HIZ, high and low bytes masked
+      DRAM_DQ    <= (others => 'Z');
+
+      n.init_counter <= r.init_counter-1;
+      
+      -- Process the FSM
+      case r.state(8 downto 4) is
+         when s_init_nop(8 downto 4) =>
+            n.state     <= s_init_nop;
+            n.address <= (others => '0');
+            n.bank    <= (others => '0');
+            n.rf_counter   <= (others => '0');
+            n.data_out_valid <= '1';
+            
+            -- T-130, precharge all banks.
+            if r.init_counter = "000000010000010" then
+               n.state     <= s_init_pre;
+               n.address(10)   <= '1';
+            end if;
+
+            -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
+            
+            if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
+               n.state     <= s_init_ref;
+            end if;
+            
+            -- T-3, the load mode register 
+            if r.init_counter = 3 then
+               n.state     <= s_init_mrs;
+                           -- Mode register is as follows:
+                           -- resvd   wr_b   OpMd   CAS=3   Seq   bust=4
+                n.address   <= "000" & "0" & "00" & "011" & "0" & "010";
+                           -- resvd
+               n.bank      <= "00";
+            end if;
+
+            
+            -- T-1 The switch to the FSM (first command will be a NOP
+            if r.init_counter = 1 then
+               n.state          <= s_idle;
+            end if;
+
+         ------------------------------
+         -- The Idle section
+         ------------------------------
+         when s_idle(8 downto 4) =>
+            n.state <= s_idle;
+
+            -- do we have to activate a row?
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state        <= s_ra0;
+               n.address     <= addr_row;
+               n.act_row    <= addr_row;
+            end if;
+
+            -- refreshes take priority over everything
+            if r.rf_pending = '1' then
+               n.state        <= s_rf0;
+               n.rf_pending <= '0';
+            end if;
+         ------------------------------
+         -- Row activation
+         -- s_ra2 is also the "idle with active row" state and provides
+         -- a resting point between operations on the same row
+         ------------------------------
+         when s_ra0(8 downto 4) =>
+            n.state        <= s_ra1;
+         when s_ra1(8 downto 4) =>
+            n.state        <= s_ra2;
+         when s_ra2(8 downto 4) =>
+            -- we can stay in this state until we have something to do
+            n.state       <= s_ra2;
+
+            -- If there is a read pending, deactivate the row
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state     <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+            
+            -- unless we have a read to perform on the same row? do that instead
+            if r.rd_pending = '1' and r.act_row = addr_row then
+               n.state     <= s_rd0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks <= "00";
+               n.rd_pending <= '0';
+            end if;
+            
+            -- unless we have a write on the same row? writes take priroty over reads
+            if r.wr_pending = '1' and r.act_row = addr_row then
+               n.state     <= s_wr0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks<= "00";
+               n.wr_pending <= '0';
+            end if;
+            
+            -- But refreshes take piority over everything!
+            if r.rf_pending = '1' then
+               n.state     <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+            
+         ------------------------------------------------------
+         -- Deactivate the current row and return to idle state
+         ------------------------------------------------------
+         when s_dr0(8 downto 4) =>
+            n.state <= s_dr1;
+         when s_dr1(8 downto 4) =>
+            n.state <= s_idle;
+
+         ------------------------------
+         -- The Refresh section
+         ------------------------------
+         when s_rf0(8 downto 4) =>
+            n.state <= s_rf1;
+         when s_rf1(8 downto 4) =>
+            n.state <= s_rf2;
+         when s_rf2(8 downto 4) =>
+            n.state <= s_rf3;
+         when s_rf3(8 downto 4) =>
+            n.state <= s_rf4;
+         when s_rf4(8 downto 4) =>
+            n.state <= s_rf5;
+         when s_rf5(8 downto 4) =>
+            n.state <= s_idle;
+         ------------------------------
+         -- The Write section
+         ------------------------------
+         when s_wr0(8 downto 4) =>
+            n.state    <= s_wr1;
+            n.address <= "000" & addr_col;
+            n.bank    <= addr_bank;
+            DRAM_DQ     <= data_in(15 downto 0);
+            n.dq_masks<= "00";
+         when s_wr1(8 downto 4) =>
+            n.state    <= s_wr2;
+            DRAM_DQ     <= data_in(31 downto 16);
+            n.dq_masks<= "00";
+         when s_wr2(8 downto 4) =>
+            DRAM_DQ     <= data_in(15 downto 0);
+            n.state     <= s_wr3;
+            n.dq_masks<= "00";
+         when s_wr3(8 downto 4) =>
+            -- Default to the idle+row active state
+            n.state     <= s_ra2;
+            DRAM_DQ     <= data_in(31 downto 16);
+            n.dq_masks<= "11";
+            
+            -- If there is a read or write then deactivate the row
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state         <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+
+            -- But if there is a read pending in the same row, do that
+            if r.rd_pending = '1' and r.act_row = addr_row then
+               n.state     <= s_rd0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks <= "00";
+               n.rd_pending <= '0';
+            end if;
+
+            -- unless there is a write pending in the same row, do that
+            if r.wr_pending = '1' and r.act_row = addr_row then
+               n.state     <= s_wr0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks<= "00";
+               n.wr_pending <= '0';
+            end if;
+
+            -- But always try and refresh if one is pending!
+            if r.rf_pending = '1' then
+               n.state       <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+         
+         ------------------------------
+         -- The Read section
+         ------------------------------
+         when s_rd0(8 downto 4) =>
+            n.state <= s_rd1;
+            n.dq_masks <= "00";
+         when s_rd1(8 downto 4) =>
+            n.state <= s_rd2;
+            n.dq_masks <= "00";
+         when s_rd2(8 downto 4) =>
+            n.state <= s_rd3;
+            n.dq_masks <= "00";
+         when s_rd3(8 downto 4) =>
+            -- default is to end the read with the row open
+            n.state <= s_rd7;
+
+            -- otherwise if there is a read or write prepare to deactivate the row.
+            -- (This is overridden if the read/write is to the same page)
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state       <= s_drdr0;
+               n.address(10) <= '1';
+            end if;
+
+            -- override if the write is from the same row
+            if r.wr_pending = '1' and r.act_row = addr_row then
+               n.state <= s_rd7;
+            end if;
+         
+            -- override if the read is from the same row
+            if r.rd_pending = '1' and r.act_row = addr_row then
+               n.state     <= s_rd4;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks<= "00";
+            end if;
+
+               -- If a refresh is pending then always deactivate the row
+            if r.rf_pending = '1' then 
+               n.state <= s_drdr0;
+               n.address(10) <= '1';
+            end if;
+            n.data_out_low <= captured;
+            n.data_out_valid <= '1';   
+         when s_rd4(8 downto 4) =>
+            n.state <= s_rd5;
+            n.dq_masks<= "00";
+         when s_rd5(8 downto 4) =>
+            n.state <= s_rd6;
+            n.data_out_low <= captured;
+            n.data_out_valid <= '1';   
+            n.dq_masks<= "00";
+         when s_rd6(8 downto 4) =>
+            n.state <= s_rd3;
+            n.dq_masks<= "00";
+         when s_rd7(8 downto 4) =>
+            n.state <= s_rd8;
+            n.data_out_low <= captured;
+            n.data_out_valid <= '1';   
+         when s_rd8(8 downto 4) =>
+            n.state <= s_rd9;
+         when s_rd9(8 downto 4) =>
+            -- by default go to the idle-with-row-active state
+            n.state <= s_ra2;
+            n.data_out_low <= captured;
+            n.data_out_valid <= '1';   
+            
+            -- otherwise if there is a read or write prepare to deactivate the row.
+            -- (This is overridden if the read/write is to the same row)
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+            
+            -- this is to catch if a read has turned up since the choices at state s_dr3
+            if r.rd_pending = '1' and r.act_row = addr_row then
+               n.state <= s_rd0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks <= "00";
+               n.rd_pending <= '0';
+            end if;
+
+            -- this is to catch if a read has turned up since the choices at state s_dr3
+            if r.wr_pending = '1' and r.act_row = addr_row then
+               n.state <= s_wr0;
+               n.address <= "000" & addr_col;
+               n.bank    <= addr_bank;
+               n.dq_masks<= "00";
+               n.wr_pending <= '0';
+            end if;
+            
+            if r.rf_pending = '1' then
+               n.state <= s_dr0;
+               n.address(10) <= '1';
+            end if;
+            
+         ------------------------------
+         -- The Deactivate row during read section
+         ------------------------------
+         when s_drdr0(8 downto 4) =>
+            n.state <= s_drdr1;
+         when s_drdr1(8 downto 4) =>
+            n.state <= s_drdr2;
+            n.data_out_low <= captured;
+            n.data_out_valid <= '1';   
+         when s_drdr2(8 downto 4) =>
+            n.state <= s_idle;
+
+            if r.rf_pending = '1' then
+               n.state <= s_rf0;
+            end if;
+            
+            if r.rd_pending = '1' or r.wr_pending = '1' then
+               n.state       <= s_ra0;
+               n.address    <= addr_row;
+               n.act_row    <= addr_row;
+               n.bank       <= addr_bank;
+            end if;
+
+         when others =>
+            n.state <= s_init_nop;
+      end case;
+   end process;
+   
+   --- The clock driven logic
+   process (clock_100, n)
+   begin
+      if clock_100'event and clock_100 = '1' then
+         r <= n;
+      end if;
+   end process;
+
+   process (clock_100_delayed_3ns, dram_dq)
+   begin
+      if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
+         captured <= dram_dq;
+      end if;
+   end process;
+
+end rtl;

sdram_clk_gen.ppf

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="sdram_clk_gen" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

sdram_clk_gen.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_clk_gen.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_clk_gen_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_clk_gen.ppf"]

sdram_clk_gen.v

@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_clk_gen.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_clk_gen (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 2,
+		altpll_component.clk1_phase_shift = "3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sdram_clk_gen",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_clk_gen.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

sdram_clk_gen_bb.v

@@ -0,0 +1,216 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_clk_gen.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module sdram_clk_gen (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_clk_gen.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON