WIP: sdram support

spectrum.sv

@@ -19,7 +19,18 @@ module spectrum(output wire[7:0] LED,
                 input wire[3:0] SW,         // 0 = ROM selection, 1 = enable/disable interrupts, 2 = turbo speed
                 output wire[33:0] GPIO_1,    // Exports CPU chip pins,
 					 output wire buzzer_out,
-					 input wire raw_loader_in
+					 input wire raw_loader_in,
+					 output wire[1:0] DRAM_BA,
+					 output wire[1:0] DRAM_DQM,
+					 output wire DRAM_RAS_N,
+					 output wire DRAM_CAS_N,
+					 output wire DRAM_CKE,
+					 output wire DRAM_CLK,
+					 output wire DRAM_WE_N,
+					 output wire DRAM_CS_N,
+					 inout wire[15:0] DRAM_DQ,
+					 output wire[12:0] DRAM_ADDR
+					 
 );
 `default_nettype none
 
@@ -103,6 +114,7 @@ begin
                     2'b00:  D[7:0] = rom_data;
                     2'b01:  D[7:0] = ram0_data;
                     2'b1?:  D[7:0] = ram1_data;
+//                    2'b1?:  D[7:0] = sdram_out_data[7:0];
                 endcase
             end
         // ---------------------------------- IO read ----------------------------------
@@ -169,6 +181,68 @@ ram32 ram1(
     .wren(ExtRamWE)
 );
 
+
+// 
+// SDRAM for 128K
+//
+
+wire[31:0] sdram_out_data;
+wire sdram_out_valid;
+wire sdram_read_request;
+wire sdram_write_request;
+
+assign sdram_read_request = nIORQ == 1 && nRD == 0 && nWR == 1;
+assign sdram_write_request = ExtRamWE;
+
+sdram_controller sdram_(
+	.CLOCK_50(CLOCK_50),
+	.DRAM_ADDR(DRAM_ADDR),
+	.DRAM_BA(DRAM_BA),
+	.DRAM_CAS_N(DRAM_CAS_N),
+	.DRAM_CKE(DRAM_CKE),
+	.DRAM_CLK(DRAM_CLK),
+	.DRAM_CS_N(DRAM_CS_N),
+	.DRAM_DQ(DRAM_DQ),
+	.DRAM_DQM(DRAM_DQM),
+	.DRAM_RAS_N(DRAM_RAS_N),
+	.DRAM_WE_N(DRAM_WE_N),
+	
+	.address({8'd0, A}),
+	.req_read(sdram_read_request),
+	.req_write(sdram_write_request),
+	.data_out(sdram_out_data),
+	.data_out_valid(sdram_out_valid),
+	.data_in({24'd0, D[7:0]})
+);
+
+/*
+entity sdram_controller is
+   PORT (
+   CLOCK_50      : IN STD_LOGIC;
+   
+   -- Signals to/from the SDRAM chip
+   DRAM_ADDR   : OUT   STD_LOGIC_VECTOR (12 downto 0);
+   DRAM_BA      : OUT   STD_LOGIC_VECTOR (1 downto 0);
+   DRAM_CAS_N   : OUT   STD_LOGIC;
+   DRAM_CKE      : OUT   STD_LOGIC;
+   DRAM_CLK      : OUT   STD_LOGIC;
+   DRAM_CS_N   : OUT   STD_LOGIC;
+   DRAM_DQ      : INOUT STD_LOGIC_VECTOR(15 downto 0);
+   DRAM_DQM      : OUT   STD_LOGIC_VECTOR(1 downto 0);
+   DRAM_RAS_N   : OUT   STD_LOGIC;
+   DRAM_WE_N    : OUT   STD_LOGIC;
+   
+   --- Inputs from rest of the system
+   address      : IN     STD_LOGIC_VECTOR (23 downto 0);
+   req_read      : IN     STD_LOGIC;
+   req_write   : IN     STD_LOGIC;
+   data_out      : OUT     STD_LOGIC_VECTOR (31 downto 0);
+   data_out_valid : OUT     STD_LOGIC;
+   data_in      : IN     STD_LOGIC_VECTOR (31 downto 0)
+   );
+end entity;
+*/
+
 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 // Instantiate ULA
 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~