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WIP: sdram support

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This commit is contained in:
Adrian Scripca
2022-04-02 14:56:02 +03:00
parent d20be0fefc
commit 114238753f
103 changed files with 484005 additions and 418306 deletions
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db/.cmp.kpt
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db/prev_cmp_spectrum.qmsg
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db/sdram_clk_gen_altpll.v
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//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="3000" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sdram_clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
//CBXI_INSTANCE_NAME="spectrum_sdram_controller_sdram_sdram_clk_gen_sdram_clk_pll_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sdram_clk_gen_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 2,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 1,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 2,
pll1.clk1_phase_shift = "3000",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //sdram_clk_gen_altpll
//VALID FILE
db/spectrum.(0).cnf.cdb
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db/spectrum.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:41 2022 " "Processing started: Fri Apr 1 18:55:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:43 2022 " "Processing ended: Fri Apr 1 18:55:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900269993 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:09 2022 " "Processing started: Sat Apr 2 14:51:09 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648900271169 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648900271197 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:11 2022 " "Processing ended: Sat Apr 2 14:51:11 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648900271509 ""}
db/spectrum.asm.rdb
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db/spectrum.cbx.xml
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<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram16:ram0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_7ti2.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram32:ram1|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_g9i1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" CBX_FILE_NAME="sdram_clk_gen_altpll.v"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ula:ula_|pll:pll_|altpll:altpll_component" CBX_FILE_NAME="pll_altpll.v"/>
</PROJECT>
</LOG_ROOT>
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db/spectrum.cmp.logdb
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@@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,75;9;75;0;0;75;75;0;75;75;0;0;0;0;41;0;0;41;0;0;2;0;0;0;0;0;0;75;0;0,
IO_RULES_MATRIX,Total Pass,114;29;114;0;0;114;114;0;114;114;0;0;0;0;57;0;0;57;0;0;10;0;0;0;0;0;0;114;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;66;0;75;75;0;0;75;0;0;75;75;75;75;34;75;75;34;75;75;73;75;75;75;75;75;75;0;75;75,
IO_RULES_MATRIX,Total Inapplicable,0;85;0;114;114;0;0;114;0;0;114;114;114;114;57;114;114;57;114;114;104;114;114;114;114;114;114;0;114;114,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
@@ -98,8 +98,47 @@ IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass
IO_RULES_MATRIX,GPIO_1[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_1[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,buzzer_out,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_BA[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_BA[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQM[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQM[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_RAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_CAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_WE_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_CS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_ADDR[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
db/spectrum.cmp.rdb
BIN
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db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
BIN
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Binary file not shown.
db/spectrum.db_info
+1 -1
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@@ -1,3 +1,3 @@
Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Version_Index = 318808576
Creation_Time = Wed Mar 30 18:55:53 2022
Creation_Time = Sat Apr 2 13:37:52 2022
db/spectrum.eda.qmsg
+12 -12
View File
@@ -1,12 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:50 2022 " "Processing started: Fri Apr 1 18:55:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:53 2022 " "Processing ended: Fri Apr 1 18:55:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900279498 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:19 2022 " "Processing started: Sat Apr 2 14:51:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280426 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280767 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281107 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281449 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281719 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281988 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282253 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282522 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:22 2022 " "Processing ended: Sat Apr 2 14:51:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""}
db/spectrum.fit.qmsg
+77 -72
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File diff suppressed because one or more lines are too long
db/spectrum.hier_info
+392 -63
View File
@@ -1,80 +1,119 @@
|spectrum
LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
LED[1] << <GND>
LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
LED[4] << <GND>
LED[5] << <GND>
LED[6] << <GND>
LED[7] << <GND>
CLOCK_50 => CLOCK_50.IN3
LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= <GND>
LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= <GND>
LED[5] <= <GND>
LED[6] <= <GND>
LED[7] <= <GND>
CLOCK_50 => CLOCK_50.IN4
KEY[0] => reset.IN1
KEY[1] => nNMI.IN1
PS2_CLK => PS2_CLK.IN1
PS2_DAT => PS2_DAT.IN1
I2C_SCLK <> ula:ula_.I2C_SCLK
I2C_SDAT <> ula:ula_.I2C_SDAT
AUD_XCK << ula:ula_.AUD_XCK
AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK
AUD_DACLRCK << ula:ula_.AUD_DACLRCK
AUD_BCLK << ula:ula_.AUD_BCLK
AUD_DACDAT << ula:ula_.AUD_DACDAT
AUD_XCK <= ula:ula_.AUD_XCK
AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK
AUD_DACLRCK <= ula:ula_.AUD_DACLRCK
AUD_BCLK <= ula:ula_.AUD_BCLK
AUD_DACDAT <= ula:ula_.AUD_DACDAT
AUD_ADCDAT => AUD_ADCDAT.IN1
VGA_R[0] << ula:ula_.VGA_R
VGA_R[1] << ula:ula_.VGA_R
VGA_R[2] << ula:ula_.VGA_R
VGA_R[3] << ula:ula_.VGA_R
VGA_G[0] << ula:ula_.VGA_G
VGA_G[1] << ula:ula_.VGA_G
VGA_G[2] << ula:ula_.VGA_G
VGA_G[3] << ula:ula_.VGA_G
VGA_B[0] << ula:ula_.VGA_B
VGA_B[1] << ula:ula_.VGA_B
VGA_B[2] << ula:ula_.VGA_B
VGA_B[3] << ula:ula_.VGA_B
VGA_HS << ula:ula_.VGA_HS
VGA_VS << ula:ula_.VGA_VS
VGA_R[0] <= ula:ula_.VGA_R
VGA_R[1] <= ula:ula_.VGA_R
VGA_R[2] <= ula:ula_.VGA_R
VGA_R[3] <= ula:ula_.VGA_R
VGA_G[0] <= ula:ula_.VGA_G
VGA_G[1] <= ula:ula_.VGA_G
VGA_G[2] <= ula:ula_.VGA_G
VGA_G[3] <= ula:ula_.VGA_G
VGA_B[0] <= ula:ula_.VGA_B
VGA_B[1] <= ula:ula_.VGA_B
VGA_B[2] <= ula:ula_.VGA_B
VGA_B[3] <= ula:ula_.VGA_B
VGA_HS <= ula:ula_.VGA_HS
VGA_VS <= ula:ula_.VGA_VS
SW[0] => ~NO_FANOUT~
SW[1] => LED[0].DATAIN
SW[1] => comb.OUTPUTSELECT
SW[2] => SW[2].IN1
SW[3] => ~NO_FANOUT~
GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
GPIO_1[25] << z80_top_direct_n:z80_.nHALT
GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
GPIO_1[27] << z80_top_direct_n:z80_.nWR
GPIO_1[28] << z80_top_direct_n:z80_.nRD
GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
GPIO_1[31] << z80_top_direct_n:z80_.nM1
GPIO_1[32] << <GND>
GPIO_1[33] << <GND>
buzzer_out << ula:ula_.beep
GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK
GPIO_1[25] <= z80_top_direct_n:z80_.nHALT
GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH
GPIO_1[27] <= z80_top_direct_n:z80_.nWR
GPIO_1[28] <= z80_top_direct_n:z80_.nRD
GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ
GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ
GPIO_1[31] <= z80_top_direct_n:z80_.nM1
GPIO_1[32] <= <GND>
GPIO_1[33] <= <GND>
buzzer_out <= ula:ula_.beep
raw_loader_in => raw_loader_in.IN1
DRAM_BA[0] <= sdram_controller:sdram_.DRAM_BA
DRAM_BA[1] <= sdram_controller:sdram_.DRAM_BA
DRAM_DQM[0] <= sdram_controller:sdram_.DRAM_DQM
DRAM_DQM[1] <= sdram_controller:sdram_.DRAM_DQM
DRAM_RAS_N <= sdram_controller:sdram_.DRAM_RAS_N
DRAM_CAS_N <= sdram_controller:sdram_.DRAM_CAS_N
DRAM_CKE <= sdram_controller:sdram_.DRAM_CKE
DRAM_CLK <= sdram_controller:sdram_.DRAM_CLK
DRAM_WE_N <= sdram_controller:sdram_.DRAM_WE_N
DRAM_CS_N <= sdram_controller:sdram_.DRAM_CS_N
DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[3] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[4] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[5] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[6] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[7] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[8] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[9] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[10] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[11] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ
DRAM_ADDR[0] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[1] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[2] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[3] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[4] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[5] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[6] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[7] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[8] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[9] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[10] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[11] <= sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[12] <= sdram_controller:sdram_.DRAM_ADDR
|spectrum|rom0:rom
@@ -1991,6 +2030,296 @@ sel[1] => _.IN0
sel[1] => _.IN0
|spectrum|sdram_controller:sdram_
CLOCK_50 => sdram_clk_gen:sdram_clk_pll.inclk0
DRAM_ADDR[0] <= r.address[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[1] <= r.address[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[2] <= r.address[2].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[3] <= r.address[3].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[4] <= r.address[4].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[5] <= r.address[5].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[6] <= r.address[6].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[7] <= r.address[7].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[8] <= r.address[8].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[9] <= r.address[9].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[10] <= r.address[10].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[11] <= r.address[11].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[12] <= r.address[12].DB_MAX_OUTPUT_PORT_TYPE
DRAM_BA[0] <= r.bank[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_BA[1] <= r.bank[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_CAS_N <= r.state[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_CKE <= <VCC>
DRAM_CLK <= sdram_clk_gen:sdram_clk_pll.c1
DRAM_CS_N <= r.state[3].DB_MAX_OUTPUT_PORT_TYPE
DRAM_DQ[0] <> DRAM_DQ[0]
DRAM_DQ[1] <> DRAM_DQ[1]
DRAM_DQ[2] <> DRAM_DQ[2]
DRAM_DQ[3] <> DRAM_DQ[3]
DRAM_DQ[4] <> DRAM_DQ[4]
DRAM_DQ[5] <> DRAM_DQ[5]
DRAM_DQ[6] <> DRAM_DQ[6]
DRAM_DQ[7] <> DRAM_DQ[7]
DRAM_DQ[8] <> DRAM_DQ[8]
DRAM_DQ[9] <> DRAM_DQ[9]
DRAM_DQ[10] <> DRAM_DQ[10]
DRAM_DQ[11] <> DRAM_DQ[11]
DRAM_DQ[12] <> DRAM_DQ[12]
DRAM_DQ[13] <> DRAM_DQ[13]
DRAM_DQ[14] <> DRAM_DQ[14]
DRAM_DQ[15] <> DRAM_DQ[15]
DRAM_DQM[0] <= r.dq_masks[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_DQM[1] <= r.dq_masks[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_RAS_N <= r.state[2].DB_MAX_OUTPUT_PORT_TYPE
DRAM_WE_N <= r.state[0].DB_MAX_OUTPUT_PORT_TYPE
address[0] => ~NO_FANOUT~
address[1] => n.DATAB
address[1] => n.DATAB
address[1] => Mux22.IN36
address[2] => n.DATAB
address[2] => n.DATAB
address[2] => Mux21.IN36
address[3] => n.DATAB
address[3] => n.DATAB
address[3] => Mux20.IN36
address[4] => n.DATAB
address[4] => n.DATAB
address[4] => Mux19.IN36
address[5] => n.DATAB
address[5] => n.DATAB
address[5] => Mux18.IN36
address[6] => n.DATAB
address[6] => n.DATAB
address[6] => Mux17.IN36
address[7] => n.DATAB
address[7] => n.DATAB
address[7] => Mux16.IN36
address[8] => n.DATAB
address[8] => n.DATAB
address[8] => Mux15.IN36
address[9] => n.DATAB
address[9] => n.DATAB
address[9] => n.DATAB
address[9] => Mux26.IN36
address[10] => n.DATAB
address[10] => n.DATAB
address[10] => n.DATAB
address[10] => Mux25.IN36
address[11] => Equal7.IN25
address[11] => n.DATAB
address[11] => n.DATAB
address[12] => Equal7.IN24
address[12] => n.DATAB
address[12] => n.DATAB
address[13] => Equal7.IN23
address[13] => n.DATAB
address[13] => n.DATAB
address[14] => Equal7.IN22
address[14] => n.DATAB
address[14] => n.DATAB
address[15] => Equal7.IN21
address[15] => n.DATAB
address[15] => n.DATAB
address[16] => Equal7.IN20
address[16] => n.DATAB
address[16] => n.DATAB
address[17] => Equal7.IN19
address[17] => n.DATAB
address[17] => n.DATAB
address[18] => Equal7.IN18
address[18] => n.DATAB
address[18] => n.DATAB
address[19] => Equal7.IN17
address[19] => n.DATAB
address[19] => n.DATAB
address[20] => Equal7.IN16
address[20] => n.DATAB
address[20] => n.DATAB
address[21] => Equal7.IN15
address[21] => n.DATAB
address[21] => n.DATAB
address[22] => Equal7.IN14
address[22] => n.DATAB
address[22] => n.DATAB
address[23] => Equal7.IN13
address[23] => n.DATAB
address[23] => n.DATAB
req_read => n.OUTPUTSELECT
req_write => n.OUTPUTSELECT
data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= r.data_out_low[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= r.data_out_low[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= r.data_out_low[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= r.data_out_low[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= r.data_out_low[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= r.data_out_low[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= r.data_out_low[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= r.data_out_low[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= r.data_out_low[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= r.data_out_low[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= r.data_out_low[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= r.data_out_low[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= r.data_out_low[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= r.data_out_low[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= captured[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= captured[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[18] <= captured[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[19] <= captured[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[20] <= captured[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[21] <= captured[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[22] <= captured[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[23] <= captured[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[24] <= captured[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[25] <= captured[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[26] <= captured[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[27] <= captured[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[28] <= captured[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[29] <= captured[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[30] <= captured[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[31] <= captured[15].DB_MAX_OUTPUT_PORT_TYPE
data_out_valid <= r.data_out_valid.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => Mux72.IN30
data_in[0] => Mux72.IN31
data_in[1] => Mux3.IN30
data_in[1] => Mux3.IN31
data_in[2] => Mux2.IN30
data_in[2] => Mux2.IN31
data_in[3] => Mux1.IN30
data_in[3] => Mux1.IN31
data_in[4] => Mux0.IN30
data_in[4] => Mux0.IN31
data_in[5] => Mux73.IN30
data_in[5] => Mux73.IN31
data_in[6] => Mux74.IN30
data_in[6] => Mux74.IN31
data_in[7] => Mux75.IN30
data_in[7] => Mux75.IN31
data_in[8] => Mux76.IN30
data_in[8] => Mux76.IN31
data_in[9] => Mux77.IN30
data_in[9] => Mux77.IN31
data_in[10] => Mux78.IN30
data_in[10] => Mux78.IN31
data_in[11] => Mux79.IN30
data_in[11] => Mux79.IN31
data_in[12] => Mux80.IN30
data_in[12] => Mux80.IN31
data_in[13] => Mux81.IN30
data_in[13] => Mux81.IN31
data_in[14] => Mux82.IN30
data_in[14] => Mux82.IN31
data_in[15] => Mux83.IN30
data_in[15] => Mux83.IN31
data_in[16] => Mux72.IN28
data_in[16] => Mux72.IN29
data_in[17] => Mux3.IN28
data_in[17] => Mux3.IN29
data_in[18] => Mux2.IN28
data_in[18] => Mux2.IN29
data_in[19] => Mux1.IN28
data_in[19] => Mux1.IN29
data_in[20] => Mux0.IN28
data_in[20] => Mux0.IN29
data_in[21] => Mux73.IN28
data_in[21] => Mux73.IN29
data_in[22] => Mux74.IN28
data_in[22] => Mux74.IN29
data_in[23] => Mux75.IN28
data_in[23] => Mux75.IN29
data_in[24] => Mux76.IN28
data_in[24] => Mux76.IN29
data_in[25] => Mux77.IN28
data_in[25] => Mux77.IN29
data_in[26] => Mux78.IN28
data_in[26] => Mux78.IN29
data_in[27] => Mux79.IN28
data_in[27] => Mux79.IN29
data_in[28] => Mux80.IN28
data_in[28] => Mux80.IN29
data_in[29] => Mux81.IN28
data_in[29] => Mux81.IN29
data_in[30] => Mux82.IN28
data_in[30] => Mux82.IN29
data_in[31] => Mux83.IN28
data_in[31] => Mux83.IN29
|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
inclk[0] => sdram_clk_gen_altpll:auto_generated.inclk[0]
inclk[1] => sdram_clk_gen_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>
|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
|spectrum|ula:ula_
CLOCK_50 => CLOCK_50.IN1
turbo => clocks:clocks_.turbo
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@@ -1424,6 +1424,54 @@
<TD >0</TD>
</TR>
<TR >
<TD >sdram_|sdram_clk_pll|altpll_component|auto_generated</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >sdram_|sdram_clk_pll</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >sdram_</TD>
<TD >59</TD>
<TD >33</TD>
<TD >1</TD>
<TD >33</TD>
<TD >56</TD>
<TD >33</TD>
<TD >33</TD>
<TD >33</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|mux2</TD>
<TD >34</TD>
<TD >0</TD>
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db/spectrum.lpc.txt
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@@ -1321,6 +1321,51 @@ Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : sdram_|sdram_clk_pll|altpll_component|auto_generated
Input : 2
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 5
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : sdram_|sdram_clk_pll
Input : 1
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : sdram_
Input : 59
Constant Input : 33
Unused Input : 1
Floating Input : 33
Output : 56
Constant Output : 33
Unused Output : 33
Floating Output : 33
Bidir : 16
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram1|altsyncram_component|auto_generated|mux2
Input : 34
Constant Input : 0
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