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Sample memory model with all components

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This commit is contained in:
Adrian Scripca
2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
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db/altsyncram_dui2.tdf
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db/altsyncram_g9i1.tdf
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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=32768 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=15 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION decode_msa (data[1..0], enable)
RETURNS ( eq[3..0]);
FUNCTION decode_f8a (data[1..0])
RETURNS ( eq[3..0]);
FUNCTION mux_6nb (data[31..0], sel[1..0])
RETURNS ( result[7..0]);
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = lut 24 M9K 32 reg 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_g9i1
(
address_a[14..0] : input;
clock0 : input;
data_a[7..0] : input;
q_a[7..0] : output;
wren_a : input;
)
VARIABLE
address_reg_a[1..0] : dffe;
out_address_reg_a[1..0] : dffe;
decode3 : decode_msa;
rden_decode : decode_f8a;
mux2 : mux_6nb;
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_sel[1..0] : WIRE;
address_a_wire[14..0] : WIRE;
rden_decode_addr_sel_a[1..0] : WIRE;
BEGIN
address_reg_a[].clk = clock0;
address_reg_a[].d = address_a_sel[];
out_address_reg_a[].clk = clock0;
out_address_reg_a[].d = address_reg_a[].q;
decode3.data[1..0] = address_a_wire[14..13];
decode3.enable = wren_a;
rden_decode.data[] = rden_decode_addr_sel_a[];
mux2.data[] = ( ram_block1a[31..0].portadataout[0..0]);
mux2.sel[] = out_address_reg_a[].q;
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].ena0 = ( rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);
ram_block1a[31..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[16].portadatain[] = ( data_a[0..0]);
ram_block1a[17].portadatain[] = ( data_a[1..1]);
ram_block1a[18].portadatain[] = ( data_a[2..2]);
ram_block1a[19].portadatain[] = ( data_a[3..3]);
ram_block1a[20].portadatain[] = ( data_a[4..4]);
ram_block1a[21].portadatain[] = ( data_a[5..5]);
ram_block1a[22].portadatain[] = ( data_a[6..6]);
ram_block1a[23].portadatain[] = ( data_a[7..7]);
ram_block1a[24].portadatain[] = ( data_a[0..0]);
ram_block1a[25].portadatain[] = ( data_a[1..1]);
ram_block1a[26].portadatain[] = ( data_a[2..2]);
ram_block1a[27].portadatain[] = ( data_a[3..3]);
ram_block1a[28].portadatain[] = ( data_a[4..4]);
ram_block1a[29].portadatain[] = ( data_a[5..5]);
ram_block1a[30].portadatain[] = ( data_a[6..6]);
ram_block1a[31].portadatain[] = ( data_a[7..7]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
ram_block1a[31..0].portawe = ( decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
address_a_sel[1..0] = address_a[14..13];
address_a_wire[] = address_a[];
q_a[] = mux2.result[];
rden_decode_addr_sel_a[1..0] = address_a_wire[14..13];
END;
--VALID FILE
db/decode_f8a.tdf
+46
View File
@@ -0,0 +1,46 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 4
SUBDESIGN decode_f8a
(
data[1..0] : input;
eq[3..0] : output;
)
VARIABLE
data_wire[1..0] : WIRE;
eq_node[3..0] : WIRE;
eq_wire[3..0] : WIRE;
w_anode261w[2..0] : WIRE;
w_anode275w[2..0] : WIRE;
w_anode284w[2..0] : WIRE;
w_anode293w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
eq[] = eq_node[];
eq_node[3..0] = eq_wire[3..0];
eq_wire[] = ( w_anode293w[2..2], w_anode284w[2..2], w_anode275w[2..2], w_anode261w[2..2]);
w_anode261w[] = ( (w_anode261w[1..1] & (! data_wire[1..1])), (w_anode261w[0..0] & (! data_wire[0..0])), B"1");
w_anode275w[] = ( (w_anode275w[1..1] & (! data_wire[1..1])), (w_anode275w[0..0] & data_wire[0..0]), B"1");
w_anode284w[] = ( (w_anode284w[1..1] & data_wire[1..1]), (w_anode284w[0..0] & (! data_wire[0..0])), B"1");
w_anode293w[] = ( (w_anode293w[1..1] & data_wire[1..1]), (w_anode293w[0..0] & data_wire[0..0]), B"1");
END;
--VALID FILE
db/decode_i8a.tdf
+54
View File
@@ -0,0 +1,54 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 8
SUBDESIGN decode_i8a
(
data[2..0] : input;
eq[5..0] : output;
)
VARIABLE
data_wire[2..0] : WIRE;
eq_node[5..0] : WIRE;
eq_wire[7..0] : WIRE;
w_anode741w[3..0] : WIRE;
w_anode759w[3..0] : WIRE;
w_anode770w[3..0] : WIRE;
w_anode781w[3..0] : WIRE;
w_anode792w[3..0] : WIRE;
w_anode803w[3..0] : WIRE;
w_anode814w[3..0] : WIRE;
w_anode825w[3..0] : WIRE;
BEGIN
data_wire[] = data[];
eq[] = eq_node[];
eq_node[5..0] = eq_wire[5..0];
eq_wire[] = ( w_anode825w[3..3], w_anode814w[3..3], w_anode803w[3..3], w_anode792w[3..3], w_anode781w[3..3], w_anode770w[3..3], w_anode759w[3..3], w_anode741w[3..3]);
w_anode741w[] = ( (w_anode741w[2..2] & (! data_wire[2..2])), (w_anode741w[1..1] & (! data_wire[1..1])), (w_anode741w[0..0] & (! data_wire[0..0])), B"1");
w_anode759w[] = ( (w_anode759w[2..2] & (! data_wire[2..2])), (w_anode759w[1..1] & (! data_wire[1..1])), (w_anode759w[0..0] & data_wire[0..0]), B"1");
w_anode770w[] = ( (w_anode770w[2..2] & (! data_wire[2..2])), (w_anode770w[1..1] & data_wire[1..1]), (w_anode770w[0..0] & (! data_wire[0..0])), B"1");
w_anode781w[] = ( (w_anode781w[2..2] & (! data_wire[2..2])), (w_anode781w[1..1] & data_wire[1..1]), (w_anode781w[0..0] & data_wire[0..0]), B"1");
w_anode792w[] = ( (w_anode792w[2..2] & data_wire[2..2]), (w_anode792w[1..1] & (! data_wire[1..1])), (w_anode792w[0..0] & (! data_wire[0..0])), B"1");
w_anode803w[] = ( (w_anode803w[2..2] & data_wire[2..2]), (w_anode803w[1..1] & (! data_wire[1..1])), (w_anode803w[0..0] & data_wire[0..0]), B"1");
w_anode814w[] = ( (w_anode814w[2..2] & data_wire[2..2]), (w_anode814w[1..1] & data_wire[1..1]), (w_anode814w[0..0] & (! data_wire[0..0])), B"1");
w_anode825w[] = ( (w_anode825w[2..2] & data_wire[2..2]), (w_anode825w[1..1] & data_wire[1..1]), (w_anode825w[0..0] & data_wire[0..0]), B"1");
END;
--VALID FILE
db/decode_msa.tdf
+49
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 4
SUBDESIGN decode_msa
(
data[1..0] : input;
enable : input;
eq[3..0] : output;
)
VARIABLE
data_wire[1..0] : WIRE;
enable_wire : WIRE;
eq_node[3..0] : WIRE;
eq_wire[3..0] : WIRE;
w_anode223w[2..0] : WIRE;
w_anode236w[2..0] : WIRE;
w_anode244w[2..0] : WIRE;
w_anode252w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[3..0] = eq_wire[3..0];
eq_wire[] = ( w_anode252w[2..2], w_anode244w[2..2], w_anode236w[2..2], w_anode223w[2..2]);
w_anode223w[] = ( (w_anode223w[1..1] & (! data_wire[1..1])), (w_anode223w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode236w[] = ( (w_anode236w[1..1] & (! data_wire[1..1])), (w_anode236w[0..0] & data_wire[0..0]), enable_wire);
w_anode244w[] = ( (w_anode244w[1..1] & data_wire[1..1]), (w_anode244w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode252w[] = ( (w_anode252w[1..1] & data_wire[1..1]), (w_anode252w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE
db/decode_psa.tdf
+57
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 8
SUBDESIGN decode_psa
(
data[2..0] : input;
enable : input;
eq[5..0] : output;
)
VARIABLE
data_wire[2..0] : WIRE;
enable_wire : WIRE;
eq_node[5..0] : WIRE;
eq_wire[7..0] : WIRE;
w_anode653w[3..0] : WIRE;
w_anode670w[3..0] : WIRE;
w_anode680w[3..0] : WIRE;
w_anode690w[3..0] : WIRE;
w_anode700w[3..0] : WIRE;
w_anode710w[3..0] : WIRE;
w_anode720w[3..0] : WIRE;
w_anode730w[3..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[5..0] = eq_wire[5..0];
eq_wire[] = ( w_anode730w[3..3], w_anode720w[3..3], w_anode710w[3..3], w_anode700w[3..3], w_anode690w[3..3], w_anode680w[3..3], w_anode670w[3..3], w_anode653w[3..3]);
w_anode653w[] = ( (w_anode653w[2..2] & (! data_wire[2..2])), (w_anode653w[1..1] & (! data_wire[1..1])), (w_anode653w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode670w[] = ( (w_anode670w[2..2] & (! data_wire[2..2])), (w_anode670w[1..1] & (! data_wire[1..1])), (w_anode670w[0..0] & data_wire[0..0]), enable_wire);
w_anode680w[] = ( (w_anode680w[2..2] & (! data_wire[2..2])), (w_anode680w[1..1] & data_wire[1..1]), (w_anode680w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode690w[] = ( (w_anode690w[2..2] & (! data_wire[2..2])), (w_anode690w[1..1] & data_wire[1..1]), (w_anode690w[0..0] & data_wire[0..0]), enable_wire);
w_anode700w[] = ( (w_anode700w[2..2] & data_wire[2..2]), (w_anode700w[1..1] & (! data_wire[1..1])), (w_anode700w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode710w[] = ( (w_anode710w[2..2] & data_wire[2..2]), (w_anode710w[1..1] & (! data_wire[1..1])), (w_anode710w[0..0] & data_wire[0..0]), enable_wire);
w_anode720w[] = ( (w_anode720w[2..2] & data_wire[2..2]), (w_anode720w[1..1] & data_wire[1..1]), (w_anode720w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode730w[] = ( (w_anode730w[2..2] & data_wire[2..2]), (w_anode730w[1..1] & data_wire[1..1]), (w_anode730w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE
db/logic_util_heursitic.dat
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db/mux_6nb.tdf
+53
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 16
SUBDESIGN mux_6nb
(
data[31..0] : input;
result[7..0] : output;
sel[1..0] : input;
)
VARIABLE
result_node[7..0] : WIRE;
sel_node[1..0] : WIRE;
w_data306w[3..0] : WIRE;
w_data336w[3..0] : WIRE;
w_data361w[3..0] : WIRE;
w_data386w[3..0] : WIRE;
w_data411w[3..0] : WIRE;
w_data436w[3..0] : WIRE;
w_data461w[3..0] : WIRE;
w_data486w[3..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( (((w_data486w[1..1] & sel_node[0..0]) & (! (((w_data486w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data486w[2..2]))))) # ((((w_data486w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data486w[2..2]))) & (w_data486w[3..3] # (! sel_node[0..0])))), (((w_data461w[1..1] & sel_node[0..0]) & (! (((w_data461w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data461w[2..2]))))) # ((((w_data461w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data461w[2..2]))) & (w_data461w[3..3] # (! sel_node[0..0])))), (((w_data436w[1..1] & sel_node[0..0]) & (! (((w_data436w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data436w[2..2]))))) # ((((w_data436w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data436w[2..2]))) & (w_data436w[3..3] # (! sel_node[0..0])))), (((w_data411w[1..1] & sel_node[0..0]) & (! (((w_data411w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data411w[2..2]))))) # ((((w_data411w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data411w[2..2]))) & (w_data411w[3..3] # (! sel_node[0..0])))), (((w_data386w[1..1] & sel_node[0..0]) & (! (((w_data386w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data386w[2..2]))))) # ((((w_data386w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data386w[2..2]))) & (w_data386w[3..3] # (! sel_node[0..0])))), (((w_data361w[1..1] & sel_node[0..0]) & (! (((w_data361w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data361w[2..2]))))) # ((((w_data361w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data361w[2..2]))) & (w_data361w[3..3] # (! sel_node[0..0])))), (((w_data336w[1..1] & sel_node[0..0]) & (! (((w_data336w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data336w[2..2]))))) # ((((w_data336w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data336w[2..2]))) & (w_data336w[3..3] # (! sel_node[0..0])))), (((w_data306w[1..1] & sel_node[0..0]) & (! (((w_data306w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data306w[2..2]))))) # ((((w_data306w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data306w[2..2]))) & (w_data306w[3..3] # (! sel_node[0..0])))));
sel_node[] = ( sel[1..0]);
w_data306w[] = ( data[24..24], data[16..16], data[8..8], data[0..0]);
w_data336w[] = ( data[25..25], data[17..17], data[9..9], data[1..1]);
w_data361w[] = ( data[26..26], data[18..18], data[10..10], data[2..2]);
w_data386w[] = ( data[27..27], data[19..19], data[11..11], data[3..3]);
w_data411w[] = ( data[28..28], data[20..20], data[12..12], data[4..4]);
w_data436w[] = ( data[29..29], data[21..21], data[13..13], data[5..5]);
w_data461w[] = ( data[30..30], data[22..22], data[14..14], data[6..6]);
w_data486w[] = ( data[31..31], data[23..23], data[15..15], data[7..7]);
END;
--VALID FILE
db/mux_9nb.tdf
+103
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db/prev_cmp_spectrum.qmsg
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db/spectrum.asm.qmsg
+6 -6
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637238255 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641372452 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:18 2022 " "Processing started: Wed Mar 30 13:47:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641372453 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:56:12 2022 " "Processing started: Wed Mar 30 14:56:12 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641372453 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648641372453 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648641372453 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648637239291 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648641373574 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648637239318 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648641373601 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:19 2022 " "Processing ended: Wed Mar 30 13:47:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648637239598 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "394 " "Peak virtual memory: 394 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641373885 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:13 2022 " "Processing ended: Wed Mar 30 14:56:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641373885 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641373885 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641373885 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648641373885 ""}
db/spectrum.asm.rdb
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db/spectrum.asm_labs.ddb
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db/spectrum.cbx.xml
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@@ -2,6 +2,7 @@
<LOG_ROOT> <LOG_ROOT>
<PROJECT NAME="spectrum"> <PROJECT NAME="spectrum">
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram16:ram0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_bui2.tdf"/> <CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram16:ram0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_bui2.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram32:ram1|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_g9i1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/> <CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/>
</PROJECT> </PROJECT>
</LOG_ROOT> </LOG_ROOT>
db/spectrum.cmp.bpm
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db/spectrum.cmp.cdb
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db/spectrum.cmp.hdb
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db/spectrum.cmp.idb
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db/spectrum.cmp.logdb
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@@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,9;0;9;0;0;9;9;0;9;9;0;0;0;0;1;0;0;1;0;0;0;0;0;0;0;0;0;9;0;0, IO_RULES_MATRIX,Total Pass,43;0;43;0;0;43;43;0;43;43;0;0;0;0;1;0;0;1;0;0;0;0;0;0;0;0;0;43;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;9;0;9;9;0;0;9;0;0;9;9;9;9;8;9;9;8;9;9;9;9;9;9;9;9;9;0;9;9, IO_RULES_MATRIX,Total Inapplicable,0;43;0;43;43;0;0;43;0;0;43;43;43;43;42;43;43;42;43;43;43;43;43;43;43;43;43;0;43;43,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
@@ -42,6 +42,40 @@ IO_RULES_MATRIX,LED[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pas
IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,GPIO_0[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30, IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9, IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
db/spectrum.cmp.rdb
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db/spectrum.eda.qmsg
+12 -12
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@@ -1,12 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637244327 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641378943 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing started: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:56:18 2022 " "Processing started: Wed Mar 30 14:56:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244673 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379358 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244704 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379421 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244734 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379484 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244765 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379548 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244794 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379602 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244820 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379655 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244846 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379707 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244872 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379759 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing ended: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "357 " "Peak virtual memory: 357 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:19 2022 " "Processing ended: Wed Mar 30 14:56:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""}
db/spectrum.fit.qmsg
+49 -49
View File
File diff suppressed because one or more lines are too long
db/spectrum.hier_info
+810 -9
View File
@@ -1,13 +1,47 @@
|spectrum |spectrum
CLOCK_50 => CLOCK_50.IN2 CLOCK_50 => CLOCK_50.IN3
LED[0] <= ram16:ram0.q_a LED[0] <= rom0:rom.q
LED[1] <= ram16:ram0.q_a LED[1] <= rom0:rom.q
LED[2] <= ram16:ram0.q_a LED[2] <= rom0:rom.q
LED[3] <= ram16:ram0.q_a LED[3] <= rom0:rom.q
LED[4] <= rom0:rom.q LED[4] <= ram16:ram0.q_a
LED[5] <= rom0:rom.q LED[5] <= ram16:ram0.q_a
LED[6] <= rom0:rom.q LED[6] <= ram16:ram0.q_a
LED[7] <= rom0:rom.q LED[7] <= ram16:ram0.q_a
GPIO_0[0] <= rom0:rom.q
GPIO_0[1] <= rom0:rom.q
GPIO_0[2] <= rom0:rom.q
GPIO_0[3] <= rom0:rom.q
GPIO_0[4] <= rom0:rom.q
GPIO_0[5] <= rom0:rom.q
GPIO_0[6] <= rom0:rom.q
GPIO_0[7] <= rom0:rom.q
GPIO_0[8] <= ram16:ram0.q_a
GPIO_0[9] <= ram16:ram0.q_a
GPIO_0[10] <= ram16:ram0.q_a
GPIO_0[11] <= ram16:ram0.q_a
GPIO_0[12] <= ram16:ram0.q_a
GPIO_0[13] <= ram16:ram0.q_a
GPIO_0[14] <= ram16:ram0.q_a
GPIO_0[15] <= ram16:ram0.q_a
GPIO_0[16] <= ram32:ram1.q
GPIO_0[17] <= ram32:ram1.q
GPIO_0[18] <= ram32:ram1.q
GPIO_0[19] <= ram32:ram1.q
GPIO_0[20] <= ram32:ram1.q
GPIO_0[21] <= ram32:ram1.q
GPIO_0[22] <= ram32:ram1.q
GPIO_0[23] <= ram32:ram1.q
GPIO_0[24] <= ram16:ram0.q_b
GPIO_0[25] <= ram16:ram0.q_b
GPIO_0[26] <= ram16:ram0.q_b
GPIO_0[27] <= ram16:ram0.q_b
GPIO_0[28] <= ram16:ram0.q_b
GPIO_0[29] <= ram16:ram0.q_b
GPIO_0[30] <= ram16:ram0.q_b
GPIO_0[31] <= ram16:ram0.q_b
GPIO_0[32] <= <GND>
GPIO_0[33] <= <GND>
|spectrum|rom0:rom |spectrum|rom0:rom
@@ -1157,3 +1191,770 @@ sel[0] => result_node[0].IN0
sel[0] => _.IN0 sel[0] => _.IN0
|spectrum|ram32:ram1
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
address[13] => address[13].IN1
address[14] => address[14].IN1
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
|spectrum|ram32:ram1|altsyncram:altsyncram_component
wren_a => altsyncram_g9i1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_g9i1:auto_generated.data_a[0]
data_a[1] => altsyncram_g9i1:auto_generated.data_a[1]
data_a[2] => altsyncram_g9i1:auto_generated.data_a[2]
data_a[3] => altsyncram_g9i1:auto_generated.data_a[3]
data_a[4] => altsyncram_g9i1:auto_generated.data_a[4]
data_a[5] => altsyncram_g9i1:auto_generated.data_a[5]
data_a[6] => altsyncram_g9i1:auto_generated.data_a[6]
data_a[7] => altsyncram_g9i1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_g9i1:auto_generated.address_a[0]
address_a[1] => altsyncram_g9i1:auto_generated.address_a[1]
address_a[2] => altsyncram_g9i1:auto_generated.address_a[2]
address_a[3] => altsyncram_g9i1:auto_generated.address_a[3]
address_a[4] => altsyncram_g9i1:auto_generated.address_a[4]
address_a[5] => altsyncram_g9i1:auto_generated.address_a[5]
address_a[6] => altsyncram_g9i1:auto_generated.address_a[6]
address_a[7] => altsyncram_g9i1:auto_generated.address_a[7]
address_a[8] => altsyncram_g9i1:auto_generated.address_a[8]
address_a[9] => altsyncram_g9i1:auto_generated.address_a[9]
address_a[10] => altsyncram_g9i1:auto_generated.address_a[10]
address_a[11] => altsyncram_g9i1:auto_generated.address_a[11]
address_a[12] => altsyncram_g9i1:auto_generated.address_a[12]
address_a[13] => altsyncram_g9i1:auto_generated.address_a[13]
address_a[14] => altsyncram_g9i1:auto_generated.address_a[14]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_g9i1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_g9i1:auto_generated.q_a[0]
q_a[1] <= altsyncram_g9i1:auto_generated.q_a[1]
q_a[2] <= altsyncram_g9i1:auto_generated.q_a[2]
q_a[3] <= altsyncram_g9i1:auto_generated.q_a[3]
q_a[4] <= altsyncram_g9i1:auto_generated.q_a[4]
q_a[5] <= altsyncram_g9i1:auto_generated.q_a[5]
q_a[6] <= altsyncram_g9i1:auto_generated.q_a[6]
q_a[7] <= altsyncram_g9i1:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>
|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[12] => ram_block1a16.PORTAADDR12
address_a[12] => ram_block1a17.PORTAADDR12
address_a[12] => ram_block1a18.PORTAADDR12
address_a[12] => ram_block1a19.PORTAADDR12
address_a[12] => ram_block1a20.PORTAADDR12
address_a[12] => ram_block1a21.PORTAADDR12
address_a[12] => ram_block1a22.PORTAADDR12
address_a[12] => ram_block1a23.PORTAADDR12
address_a[12] => ram_block1a24.PORTAADDR12
address_a[12] => ram_block1a25.PORTAADDR12
address_a[12] => ram_block1a26.PORTAADDR12
address_a[12] => ram_block1a27.PORTAADDR12
address_a[12] => ram_block1a28.PORTAADDR12
address_a[12] => ram_block1a29.PORTAADDR12
address_a[12] => ram_block1a30.PORTAADDR12
address_a[12] => ram_block1a31.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_msa:decode3.data[0]
address_a[13] => decode_f8a:rden_decode.data[0]
address_a[14] => address_reg_a[1].DATAIN
address_a[14] => decode_msa:decode3.data[1]
address_a[14] => decode_f8a:rden_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[1].CLK
clock0 => out_address_reg_a[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[0] => ram_block1a16.PORTADATAIN
data_a[0] => ram_block1a24.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[1] => ram_block1a17.PORTADATAIN
data_a[1] => ram_block1a25.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[2] => ram_block1a18.PORTADATAIN
data_a[2] => ram_block1a26.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[3] => ram_block1a19.PORTADATAIN
data_a[3] => ram_block1a27.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[4] => ram_block1a20.PORTADATAIN
data_a[4] => ram_block1a28.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[5] => ram_block1a21.PORTADATAIN
data_a[5] => ram_block1a29.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[6] => ram_block1a22.PORTADATAIN
data_a[6] => ram_block1a30.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_a[7] => ram_block1a23.PORTADATAIN
data_a[7] => ram_block1a31.PORTADATAIN
q_a[0] <= mux_6nb:mux2.result[0]
q_a[1] <= mux_6nb:mux2.result[1]
q_a[2] <= mux_6nb:mux2.result[2]
q_a[3] <= mux_6nb:mux2.result[3]
q_a[4] <= mux_6nb:mux2.result[4]
q_a[5] <= mux_6nb:mux2.result[5]
q_a[6] <= mux_6nb:mux2.result[6]
q_a[7] <= mux_6nb:mux2.result[7]
wren_a => decode_msa:decode3.enable
|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3
data[0] => w_anode223w[1].IN0
data[0] => w_anode236w[1].IN1
data[0] => w_anode244w[1].IN0
data[0] => w_anode252w[1].IN1
data[1] => w_anode223w[2].IN0
data[1] => w_anode236w[2].IN0
data[1] => w_anode244w[2].IN1
data[1] => w_anode252w[2].IN1
enable => w_anode223w[1].IN0
enable => w_anode236w[1].IN0
enable => w_anode244w[1].IN0
enable => w_anode252w[1].IN0
eq[0] <= w_anode223w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode236w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
data[0] => w_anode261w[1].IN0
data[0] => w_anode275w[1].IN1
data[0] => w_anode284w[1].IN0
data[0] => w_anode293w[1].IN1
data[1] => w_anode261w[2].IN0
data[1] => w_anode275w[2].IN0
data[1] => w_anode284w[2].IN1
data[1] => w_anode293w[2].IN1
eq[0] <= w_anode261w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode275w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode284w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode293w[2].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
data[0] => _.IN0
data[0] => _.IN0
data[1] => _.IN0
data[1] => _.IN0
data[2] => _.IN0
data[2] => _.IN0
data[3] => _.IN0
data[3] => _.IN0
data[4] => _.IN0
data[4] => _.IN0
data[5] => _.IN0
data[5] => _.IN0
data[6] => _.IN0
data[6] => _.IN0
data[7] => _.IN0
data[7] => _.IN0
data[8] => _.IN0
data[9] => _.IN0
data[10] => _.IN0
data[11] => _.IN0
data[12] => _.IN0
data[13] => _.IN0
data[14] => _.IN0
data[15] => _.IN0
data[16] => _.IN1
data[16] => _.IN1
data[17] => _.IN1
data[17] => _.IN1
data[18] => _.IN1
data[18] => _.IN1
data[19] => _.IN1
data[19] => _.IN1
data[20] => _.IN1
data[20] => _.IN1
data[21] => _.IN1
data[21] => _.IN1
data[22] => _.IN1
data[22] => _.IN1
data[23] => _.IN1
data[23] => _.IN1
data[24] => _.IN0
data[25] => _.IN0
data[26] => _.IN0
data[27] => _.IN0
data[28] => _.IN0
data[29] => _.IN0
data[30] => _.IN0
data[31] => _.IN0
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
db/spectrum.hif
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db/spectrum.lpc.html
+85 -5
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@@ -16,6 +16,86 @@
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR > <TR >
<TD >ram1|altsyncram_component|auto_generated|mux2</TD>
<TD >34</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|rden_decode</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|decode3</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1</TD>
<TD >25</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >8</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|mux5</TD> <TD >ram0|altsyncram_component|auto_generated|mux5</TD>
<TD >17</TD> <TD >17</TD>
<TD >0</TD> <TD >0</TD>
@@ -130,13 +210,13 @@
<TR > <TR >
<TD >ram0</TD> <TD >ram0</TD>
<TD >47</TD> <TD >47</TD>
<TD >21</TD> <TD >10</TD>
<TD >0</TD> <TD >0</TD>
<TD >21</TD> <TD >10</TD>
<TD >16</TD> <TD >16</TD>
<TD >21</TD> <TD >10</TD>
<TD >21</TD> <TD >10</TD>
<TD >21</TD> <TD >10</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
db/spectrum.lpc.rdb
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db/spectrum.lpc.txt
+80 -5
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@@ -1,6 +1,81 @@
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Hierarchy : ram1|altsyncram_component|auto_generated|mux2
Input : 34
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram1|altsyncram_component|auto_generated|rden_decode
Input : 2
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 4
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram1|altsyncram_component|auto_generated|decode3
Input : 3
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 4
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram1|altsyncram_component|auto_generated
Input : 25
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram1
Input : 25
Constant Input : 1
Unused Input : 0
Floating Input : 1
Output : 8
Constant Output : 1
Unused Output : 1
Floating Output : 1
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|mux5 Hierarchy : ram0|altsyncram_component|auto_generated|mux5
Input : 17 Input : 17
Constant Input : 0 Constant Input : 0
@@ -108,13 +183,13 @@ Output only Bidir : 0
Hierarchy : ram0 Hierarchy : ram0
Input : 47 Input : 47
Constant Input : 21 Constant Input : 10
Unused Input : 0 Unused Input : 0
Floating Input : 21 Floating Input : 10
Output : 16 Output : 16
Constant Output : 21 Constant Output : 10
Unused Output : 21 Unused Output : 10
Floating Output : 21 Floating Output : 10
Bidir : 0 Bidir : 0
Constant Bidir : 0 Constant Bidir : 0
Unused Bidir : 0 Unused Bidir : 0
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637241068 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641375310 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:20 2022 " "Processing started: Wed Mar 30 13:47:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:56:15 2022 " "Processing started: Wed Mar 30 14:56:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637241070 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648637241098 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648641375342 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637241220 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648641375496 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241222 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375498 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375542 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375542 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648637241477 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648641375787 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648637241477 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648641375787 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375789 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375789 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648637241608 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648641375920 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241609 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375920 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648637241610 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648641375921 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648637241625 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648641375946 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637241637 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637241637 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641375972 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641375972 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.812 " "Worst-case setup slack is -1.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.812 -85.179 CLOCK_50 " " -1.812 -85.179 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -2.088 " "Worst-case setup slack is -2.088" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.088 -422.664 CLOCK_50 " " -2.088 -422.664 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.337 " "Worst-case hold slack is 0.337" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.337 0.000 CLOCK_50 " " 0.337 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641375977 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641375977 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.480 CLOCK_50 " " -3.000 -119.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -532.995 CLOCK_50 " " -3.000 -532.995 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637241663 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648641376009 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648637241687 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648641376034 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648637242078 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648641376496 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242100 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376535 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242103 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242103 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641376543 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641376543 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.531 " "Worst-case setup slack is -1.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.531 -69.352 CLOCK_50 " " -1.531 -69.352 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.813 " "Worst-case setup slack is -1.813" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.813 -354.793 CLOCK_50 " " -1.813 -354.793 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.312 " "Worst-case hold slack is 0.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 CLOCK_50 " " 0.312 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242107 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376549 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242108 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376550 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.478 CLOCK_50 " " -3.000 -119.478 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -532.816 CLOCK_50 " " -3.000 -532.816 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637242132 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648641376582 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242265 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376739 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242266 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242266 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641376742 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641376742 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.444 " "Worst-case setup slack is -0.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.444 -17.149 CLOCK_50 " " -0.444 -17.149 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -0.824 " "Worst-case setup slack is -0.824" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.824 -117.237 CLOCK_50 " " -0.824 -117.237 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.169 " "Worst-case hold slack is 0.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.169 0.000 CLOCK_50 " " 0.169 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242272 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376750 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242273 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376751 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.404 CLOCK_50 " " -3.000 -99.404 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -347.907 CLOCK_50 " " -3.000 -347.907 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648641377115 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648641377116 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "419 " "Peak virtual memory: 419 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:22 2022 " "Processing ended: Wed Mar 30 13:47:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:17 2022 " "Processing ended: Wed Mar 30 14:56:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""}
db/spectrum.sta.rdb
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db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
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db/spectrum.tiscmp.fast_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_85c.ddb
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db/spectrum.vpr.ammdb
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greybox_tmp/cbx_args.txt
+4 -24
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@@ -1,37 +1,17 @@
ADDRESS_REG_B=CLOCK0
CLOCK_ENABLE_INPUT_A=BYPASS CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS INIT_FILE=led_patterns.mif
INDATA_REG_B=CLOCK0
INIT_FILE=./led_patterns.mif
INTENDED_DEVICE_FAMILY="Cyclone IV E" INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_TYPE=altsyncram NUMWORDS_A=32768
NUMWORDS_A=16384 OPERATION_MODE=SINGLE_PORT
NUMWORDS_B=16384
OPERATION_MODE=BIDIR_DUAL_PORT
OUTDATA_ACLR_A=NONE OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=CLOCK0 OUTDATA_REG_A=CLOCK0
OUTDATA_REG_B=CLOCK0
POWER_UP_UNINITIALIZED=FALSE POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ WIDTHAD_A=15
WIDTHAD_A=14
WIDTHAD_B=14
WIDTH_A=8 WIDTH_A=8
WIDTH_B=8
WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK0
DEVICE_FAMILY="Cyclone IV E" DEVICE_FAMILY="Cyclone IV E"
address_a address_a
address_b
clock0 clock0
data_a
data_b
wren_a
wren_b
q_a q_a
q_b
incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
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output_files/spectrum.asm.rpt
+8 -8
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@@ -1,5 +1,5 @@
Assembler report for spectrum Assembler report for spectrum
Wed Mar 30 13:47:19 2022 Wed Mar 30 14:56:13 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 30 13:47:19 2022 ; ; Assembler Status ; Successful - Wed Mar 30 14:56:13 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ; ; Option ; Setting ;
+----------------+-----------------------+ +----------------+-----------------------+
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x0021F0FE ; ; JTAG usercode ; 0x00342FB4 ;
; Checksum ; 0x0021F0FE ; ; Checksum ; 0x00342FB4 ;
+----------------+-----------------------+ +----------------+-----------------------+
@@ -173,14 +173,14 @@ Default Value : On
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:47:18 2022 Info: Processing started: Wed Mar 30 14:56:12 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 375 megabytes Info: Peak virtual memory: 394 megabytes
Info: Processing ended: Wed Mar 30 13:47:19 2022 Info: Processing ended: Wed Mar 30 14:56:13 2022
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.done
+1 -1
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@@ -1 +1 @@
Wed Mar 30 13:47:24 2022 Wed Mar 30 14:56:19 2022
output_files/spectrum.eda.rpt
+6 -6
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum EDA Netlist Writer report for spectrum
Wed Mar 30 13:47:24 2022 Wed Mar 30 14:56:19 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+ +-------------------------------------------------------------------+
; EDA Netlist Writer Summary ; ; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+ +---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:47:24 2022 ; ; EDA Netlist Writer Status ; Successful - Wed Mar 30 14:56:19 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:47:24 2022 Info: Processing started: Wed Mar 30 14:56:18 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
@@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 347 megabytes Info: Peak virtual memory: 357 megabytes
Info: Processing ended: Wed Mar 30 13:47:24 2022 Info: Processing ended: Wed Mar 30 14:56:19 2022
Info: Elapsed time: 00:00:00 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.fit.rpt
+9478 -3172
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output_files/spectrum.fit.summary
+7 -7
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@@ -1,16 +1,16 @@
Fitter Status : Successful - Wed Mar 30 13:47:16 2022 Fitter Status : Successful - Wed Mar 30 14:56:10 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Device : EP4CE22F17C6 Device : EP4CE22F17C6
Timing Models : Final Timing Models : Final
Total logic elements : 50 / 22,320 ( < 1 % ) Total logic elements : 94 / 22,320 ( < 1 % )
Total combinational functions : 48 / 22,320 ( < 1 % ) Total combinational functions : 90 / 22,320 ( < 1 % )
Dedicated logic registers : 38 / 22,320 ( < 1 % ) Dedicated logic registers : 41 / 22,320 ( < 1 % )
Total registers : 38 Total registers : 41
Total pins : 9 / 154 ( 6 % ) Total pins : 43 / 154 ( 28 % )
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 98,304 / 608,256 ( 16 % ) Total memory bits : 524,288 / 608,256 ( 86 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
output_files/spectrum.flow.rpt
+39 -21
View File
@@ -1,5 +1,5 @@
Flow report for spectrum Flow report for spectrum
Wed Mar 30 13:47:24 2022 Wed Mar 30 14:56:19 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,20 +40,20 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Mar 30 13:47:24 2022 ; ; Flow Status ; Successful - Wed Mar 30 14:56:19 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 50 / 22,320 ( < 1 % ) ; ; Total logic elements ; 94 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 48 / 22,320 ( < 1 % ) ; ; Total combinational functions ; 90 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 41 / 22,320 ( < 1 % ) ;
; Total registers ; 38 ; ; Total registers ; 41 ;
; Total pins ; 9 / 154 ( 6 % ) ; ; Total pins ; 43 / 154 ( 28 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 98,304 / 608,256 ( 16 % ) ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/30/2022 13:47:07 ; ; Start date & time ; 03/30/2022 14:55:59 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
+-------------------+---------------------+ +-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164863722728310 Value : 0.164864135934045
Default Value : -- Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
@@ -103,6 +103,18 @@ Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
Assignment Name : IP_TOOL_NAME
Value : RAM: 1-PORT
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION Assignment Name : IP_TOOL_VERSION
Value : 13.1 Value : 13.1
Default Value : -- Default Value : --
@@ -139,6 +151,12 @@ Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
Assignment Name : MISC_FILE
Value : ram32_bb.v
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
Value : 1.2V Value : 1.2V
Default Value : -- Default Value : --
@@ -178,38 +196,38 @@ Section Id : --
Module Name : Analysis & Synthesis Module Name : Analysis & Synthesis
Elapsed Time : 00:00:01 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 384 MB Peak Virtual Memory : 387 MB
Total CPU Time (on all processors) : 00:00:02 Total CPU Time (on all processors) : 00:00:02
Module Name : Fitter Module Name : Fitter
Elapsed Time : 00:00:07 Elapsed Time : 00:00:09
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 594 MB Peak Virtual Memory : 603 MB
Total CPU Time (on all processors) : 00:00:06 Total CPU Time (on all processors) : 00:00:08
Module Name : Assembler Module Name : Assembler
Elapsed Time : 00:00:01 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 375 MB Peak Virtual Memory : 394 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:02
Module Name : TimeQuest Timing Analyzer Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:02 Elapsed Time : 00:00:02
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 419 MB Peak Virtual Memory : 420 MB
Total CPU Time (on all processors) : 00:00:02 Total CPU Time (on all processors) : 00:00:02
Module Name : EDA Netlist Writer Module Name : EDA Netlist Writer
Elapsed Time : 00:00:00 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 339 MB Peak Virtual Memory : 345 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : Total Module Name : Total
Elapsed Time : 00:00:11 Elapsed Time : 00:00:14
Average Processors Used : -- Average Processors Used : --
Peak Virtual Memory : -- Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:12 Total CPU Time (on all processors) : 00:00:15
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
output_files/spectrum.jdi
+1 -1
View File
@@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="a9c298635caa38134033"/> <hash md5_digest_80b="6802ba978e6c87432815"/>
</project> </project>
<file_info> <file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/> <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+527 -148
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum Analysis & Synthesis report for spectrum
Wed Mar 30 13:47:09 2022 Wed Mar 30 14:56:01 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -16,17 +16,19 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
8. Analysis & Synthesis RAM Summary 8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary 9. Analysis & Synthesis IP Cores Summary
10. Registers Removed During Synthesis 10. Registers Removed During Synthesis
11. Removed Registers Triggering Further Register Optimizations 11. General Register Statistics
12. General Register Statistics 12. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated 13. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated 14. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component 16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
17. altsyncram Parameter Settings by Entity Instance 17. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
18. Port Connectivity Checks: "ram16:ram0" 18. altsyncram Parameter Settings by Entity Instance
19. Port Connectivity Checks: "rom0:rom" 19. Port Connectivity Checks: "ram32:ram1"
20. Elapsed Time Per Partition 20. Port Connectivity Checks: "ram16:ram0"
21. Analysis & Synthesis Messages 21. Port Connectivity Checks: "rom0:rom"
22. Elapsed Time Per Partition
23. Analysis & Synthesis Messages
@@ -52,18 +54,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ; ; Analysis & Synthesis Status ; Successful - Wed Mar 30 14:56:01 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 50 ; ; Total logic elements ; 94 ;
; Total combinational functions ; 48 ; ; Total combinational functions ; 90 ;
; Dedicated logic registers ; 38 ; ; Dedicated logic registers ; 41 ;
; Total registers ; 38 ; ; Total registers ; 41 ;
; Total pins ; 9 ; ; Total pins ; 43 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 98,304 ; ; Total memory bits ; 524,288 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ; ; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -429,6 +431,12 @@ File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
Library : Library :
File Name with User-Entered Path : ram32.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/ram32.v
Library :
File Name with User-Entered Path : altsyncram.tdf File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes Used in Netlist : yes
File Type : Megafunction File Type : Megafunction
@@ -518,6 +526,30 @@ Used in Netlist : yes
File Type : Auto-Generated Megafunction File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
Library : Library :
File Name with User-Entered Path : db/altsyncram_g9i1.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf
Library :
File Name with User-Entered Path : db/decode_msa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_msa.tdf
Library :
File Name with User-Entered Path : db/decode_f8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_f8a.tdf
Library :
File Name with User-Entered Path : db/mux_6nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_6nb.tdf
Library :
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -527,29 +559,29 @@ Library :
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Estimated Total logic elements ; 50 ; ; Estimated Total logic elements ; 94 ;
; ; ; ; ; ;
; Total combinational functions ; 48 ; ; Total combinational functions ; 90 ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 7 ; ; -- 4 input functions ; 24 ;
; -- 3 input functions ; 6 ; ; -- 3 input functions ; 26 ;
; -- <=2 input functions ; 35 ; ; -- <=2 input functions ; 40 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 16 ; ; -- normal mode ; 57 ;
; -- arithmetic mode ; 32 ; ; -- arithmetic mode ; 33 ;
; ; ; ; ; ;
; Total registers ; 38 ; ; Total registers ; 41 ;
; -- Dedicated logic registers ; 38 ; ; -- Dedicated logic registers ; 41 ;
; -- I/O registers ; 0 ; ; -- I/O registers ; 0 ;
; ; ; ; ; ;
; I/O pins ; 9 ; ; I/O pins ; 43 ;
; Total memory bits ; 98304 ; ; Total memory bits ; 524288 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ; ; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 50 ; ; Maximum fan-out ; 105 ;
; Total fan-out ; 401 ; ; Total fan-out ; 1436 ;
; Average fan-out ; 3.46 ; ; Average fan-out ; 5.11 ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
@@ -557,21 +589,21 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum Compilation Hierarchy Node : |spectrum
LC Combinationals : 48 (44) LC Combinationals : 90 (46)
LC Registers : 38 (36) LC Registers : 41 (37)
Memory Bits : 98304 Memory Bits : 524288
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
Pins : 9 Pins : 43
Virtual Pins : 0 Virtual Pins : 0
Full Hierarchy Name : |spectrum Full Hierarchy Name : |spectrum
Library Name : work Library Name : work
Compilation Hierarchy Node : |ram16:ram0| Compilation Hierarchy Node : |ram16:ram0|
LC Combinationals : 0 (0) LC Combinationals : 16 (0)
LC Registers : 0 (0) LC Registers : 0 (0)
Memory Bits : 32768 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -581,9 +613,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component| Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0) LC Combinationals : 16 (0)
LC Registers : 0 (0) LC Registers : 0 (0)
Memory Bits : 32768 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -593,9 +625,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram_bui2:auto_generated| Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
LC Combinationals : 0 (0) LC Combinationals : 16 (0)
LC Registers : 0 (0) LC Registers : 0 (0)
Memory Bits : 32768 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -604,10 +636,94 @@ Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
Library Name : work Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux4|
LC Combinationals : 8 (8)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4
Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux5|
LC Combinationals : 8 (8)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5
Library Name : work
Compilation Hierarchy Node : |ram32:ram1|
LC Combinationals : 20 (0)
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 20 (0)
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
LC Combinationals : 20 (0)
LC Registers : 4 (4)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
Library Name : work
Compilation Hierarchy Node : |decode_f8a:rden_decode|
LC Combinationals : 4 (4)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
Library Name : work
Compilation Hierarchy Node : |mux_6nb:mux2|
LC Combinationals : 16 (16)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
Library Name : work
Compilation Hierarchy Node : |rom0:rom| Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 4 (0) LC Combinationals : 8 (0)
LC Registers : 2 (0) LC Registers : 0 (0)
Memory Bits : 65536 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -617,9 +733,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component| Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 4 (0) LC Combinationals : 8 (0)
LC Registers : 2 (0) LC Registers : 0 (0)
Memory Bits : 65536 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -629,9 +745,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
LC Combinationals : 4 (0) LC Combinationals : 8 (0)
LC Registers : 2 (2) LC Registers : 0 (0)
Memory Bits : 65536 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -641,7 +757,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
Library Name : work Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2| Compilation Hierarchy Node : |mux_3nb:mux2|
LC Combinationals : 4 (4) LC Combinationals : 8 (8)
LC Registers : 0 (0) LC Registers : 0 (0)
Memory Bits : 0 Memory Bits : 0
DSP Elements : 0 DSP Elements : 0
@@ -669,6 +785,16 @@ Port B Width : 8
Size : 131072 Size : 131072
MIF : led_patterns.mif MIF : led_patterns.mif
Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : Single Port
Port A Depth : 32768
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 262144
MIF : led_patterns.mif
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO Type : AUTO
Mode : ROM Mode : ROM
@@ -693,6 +819,14 @@ License Type : N/A
Entity Instance : |spectrum|ram16:ram0 Entity Instance : |spectrum|ram16:ram0
IP Include File : /home/benny/work/fpga/projects/ram16.v IP Include File : /home/benny/work/fpga/projects/ram16.v
Vendor : Altera
IP Core Name : RAM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram32:ram1
IP Include File : /home/benny/work/fpga/projects/ram32.v
Vendor : Altera Vendor : Altera
IP Core Name : ROM: 1-PORT IP Core Name : ROM: 1-PORT
Version : 13.1 Version : 13.1
@@ -704,40 +838,20 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
+-----------------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ; ; Registers Removed During Synthesis ;
+------------------------------------------------------------------------------------------------+----------------------------------------+ +------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; ; Register name ; Reason for Removal ;
+------------------------------------------------------------------------------------------------+----------------------------------------+ +------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
; address[0] ; Merged with A[0] ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
; address[1] ; Merged with A[1] ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
; address[2] ; Merged with A[2] ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
; address[3] ; Merged with A[3] ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
; address[4] ; Merged with A[4] ; ; A[15] ; Lost fanout ;
; address[5] ; Merged with A[5] ; ; Total Number of Removed Registers = 7 ; ;
; address[6] ; Merged with A[6] ; +------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
; address[7] ; Merged with A[7] ;
; address[8] ; Merged with A[8] ;
; address[9] ; Merged with A[9] ;
; address[10] ; Merged with A[10] ;
; address[11] ; Merged with A[11] ;
; address[12] ; Merged with A[12] ;
; address[13] ; Merged with A[13] ;
; A[14,15] ; Lost fanout ;
; Total Number of Removed Registers = 18 ; ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------+
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
+--------------------------------------------------------------------------------+
+------------------------------------------------------+ +------------------------------------------------------+
@@ -745,12 +859,12 @@ Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_compon
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 38 ; ; Total registers ; 41 ;
; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 13 ; ; Number of registers using Clock Enable ; 14 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@@ -777,6 +891,17 @@ To : -
+--------------------------------------------------------------------------------+
; Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; ; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -1207,12 +1332,227 @@ Type : Untyped
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : SINGLE_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 15
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 32768
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_g9i1
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ; ; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+--------------------------------------------+ +-------------------------------------------+--------------------------------------------+
; Name ; Value ; ; Name ; Value ;
+-------------------------------------------+--------------------------------------------+ +-------------------------------------------+--------------------------------------------+
; Number of entity instances ; 2 ; ; Number of entity instances ; 3 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; ; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ; ; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ; ; -- WIDTH_A ; 8 ;
@@ -1235,27 +1575,39 @@ Note: In order to hide this table in the UI and the text report file, please set
; -- OUTDATA_REG_B ; CLOCK0 ; ; -- OUTDATA_REG_B ; CLOCK0 ;
; -- RAM_BLOCK_TYPE ; AUTO ; ; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; ram32:ram1|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 32768 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------+ +-------------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram32:ram1" ;
+--------------------------------------------------------------------------------+
Port : wren
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren[-1]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram16:ram0" ; ; Port Connectivity Checks: "ram16:ram0" ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Port : address_a
Type : Input
Severity : Warning
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : address_a[13..3]
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_a[7..4]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_a Port : wren_a
Type : Input Type : Input
Severity : Warning Severity : Warning
@@ -1271,11 +1623,6 @@ Type : Input
Severity : Info Severity : Info
Details : Stuck at GND Details : Stuck at GND
Port : q_b
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_b Port : wren_b
Type : Input Type : Input
Severity : Warning Severity : Warning
@@ -1292,10 +1639,10 @@ Details : Stuck at GND
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Port Connectivity Checks: "rom0:rom" ; ; Port Connectivity Checks: "rom0:rom" ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Port : q[3..0] Port : address
Type : Output Type : Input
Severity : Info Severity : Warning
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. Details : Input port expression (16 bits) is wider than the input port (14 bits) it drives. The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -1315,7 +1662,7 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:47:07 2022 Info: Processing started: Wed Mar 30 14:55:59 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
@@ -1324,11 +1671,13 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0 Info (12023): Found entity 1: rom0
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
Info (12023): Found entity 1: ram16 Info (12023): Found entity 1: ram16
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
Info (12023): Found entity 1: ram32
Info (12127): Elaborating entity "spectrum" for the top level hierarchy Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at spectrum.v(18): object "RamWE" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22) Warning (10230): Verilog HDL assignment warning at spectrum.v(55): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14) Warning (10230): Verilog HDL assignment warning at spectrum.v(58): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16) Warning (10034): Output port "GPIO_0[33..32]" at spectrum.v(3) has no driver
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
@@ -1393,41 +1742,71 @@ Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|alt
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2" Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
Warning (14284): Synthesized away the following node(s): Info (12128): Elaborating entity "ram32" for hierarchy "ram32:ram1"
Warning (14285): Synthesized away the following RAM node(s): Info (12128): Elaborating entity "altsyncram" for hierarchy "ram32:ram1|altsyncram:altsyncram_component"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4" Info (12130): Elaborated megafunction instantiation "ram32:ram1|altsyncram:altsyncram_component"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5" Info (12133): Instantiated megafunction "ram32:ram1|altsyncram:altsyncram_component" with the following parameter:
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6" Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7" Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8" Info (12134): Parameter "init_file" = "led_patterns.mif"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9" Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11" Info (12134): Parameter "lpm_type" = "altsyncram"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12" Info (12134): Parameter "numwords_a" = "32768"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13" Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14" Info (12134): Parameter "outdata_aclr_a" = "NONE"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15" Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2" Info (12134): Parameter "widthad_a" = "15"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3" Info (12134): Parameter "width_a" = "8"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8" Info (12134): Parameter "width_byteena_a" = "1"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10" Info (12023): Found entity 1: altsyncram_g9i1
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11" Info (12128): Elaborating entity "altsyncram_g9i1" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated"
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
Info (12023): Found entity 1: decode_msa
Info (12128): Elaborating entity "decode_msa" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf
Info (12023): Found entity 1: decode_f8a
Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf
Info (12023): Found entity 1: mux_6nb
Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2"
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "D[7]" is missing source, defaulting to GND
Warning (12110): Net "D[6]" is missing source, defaulting to GND
Warning (12110): Net "D[5]" is missing source, defaulting to GND
Warning (12110): Net "D[4]" is missing source, defaulting to GND
Warning (12110): Net "D[3]" is missing source, defaulting to GND
Warning (12110): Net "D[2]" is missing source, defaulting to GND
Warning (12110): Net "D[1]" is missing source, defaulting to GND
Warning (12110): Net "D[0]" is missing source, defaulting to GND
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "D[7]" is missing source, defaulting to GND
Warning (12110): Net "D[6]" is missing source, defaulting to GND
Warning (12110): Net "D[5]" is missing source, defaulting to GND
Warning (12110): Net "D[4]" is missing source, defaulting to GND
Warning (12110): Net "D[3]" is missing source, defaulting to GND
Warning (12110): Net "D[2]" is missing source, defaulting to GND
Warning (12110): Net "D[1]" is missing source, defaulting to GND
Warning (12110): Net "D[0]" is missing source, defaulting to GND
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "GPIO_0[32]" is stuck at GND
Warning (13410): Pin "GPIO_0[33]" is stuck at GND
Info (286030): Timing-Driven Synthesis is running Info (286030): Timing-Driven Synthesis is running
Info (17049): 2 registers lost all their fanouts during netlist optimizations. Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different Info (21057): Implemented 201 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins Info (21059): Implemented 42 output pins
Info (21061): Implemented 50 logic cells Info (21061): Implemented 94 logic cells
Info (21064): Implemented 12 RAM segments Info (21064): Implemented 64 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 27 warnings
Info: Peak virtual memory: 388 megabytes Info: Peak virtual memory: 395 megabytes
Info: Processing ended: Wed Mar 30 13:47:09 2022 Info: Processing ended: Wed Mar 30 14:56:01 2022
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.map.summary
+7 -7
View File
@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Mar 30 13:47:09 2022 Analysis & Synthesis Status : Successful - Wed Mar 30 14:56:01 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Total logic elements : 50 Total logic elements : 94
Total combinational functions : 48 Total combinational functions : 90
Dedicated logic registers : 38 Dedicated logic registers : 41
Total registers : 38 Total registers : 41
Total pins : 9 Total pins : 43
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 98,304 Total memory bits : 524,288
Embedded Multiplier 9-bit elements : 0 Embedded Multiplier 9-bit elements : 0
Total PLLs : 0 Total PLLs : 0
output_files/spectrum.pin
+38 -38
View File
@@ -33,7 +33,7 @@
-- Bank 5: 2.5V -- Bank 5: 2.5V
-- Bank 6: 2.5V -- Bank 6: 2.5V
-- Bank 7: 3.3V -- Bank 7: 3.3V
-- Bank 8: 2.5V -- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection -- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will -- on the board for unused dedicated pins depends on whether this will
@@ -68,49 +68,49 @@ CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
VCCIO8 : A1 : power : : 2.5V : 8 : VCCIO8 : A1 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : GPIO_0[2] : A2 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : GPIO_0[3] : A3 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : GPIO_0[6] : A4 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : GPIO_0[8] : A5 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : GPIO_0[11] : A6 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : GPIO_0[14] : A7 : output : 3.3-V LVTTL : : 8 : Y
GND+ : A8 : : : : 8 : GND+ : A8 : : : : 8 :
GND+ : A9 : : : : 7 : GND+ : A9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : GPIO_0[30] : A12 : output : 3.3-V LVTTL : : 7 : Y
LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : A16 : power : : 3.3V : 7 : VCCIO7 : A16 : power : : 3.3V : 7 :
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
GND : B2 : gnd : : : : GND : B2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : GPIO_0[4] : B3 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : GPIO_0[5] : B4 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : GPIO_0[7] : B5 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : GPIO_0[10] : B6 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : GPIO_0[12] : B7 : output : 3.3-V LVTTL : : 8 : Y
GND+ : B8 : : : : 8 : GND+ : B8 : : : : 8 :
GND+ : B9 : : : : 7 : GND+ : B9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : GPIO_0[29] : B11 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : GPIO_0[33] : B12 : output : 3.3-V LVTTL : : 7 : Y
LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
GND : B15 : gnd : : : : GND : B15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : GPIO_0[1] : C3 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : C4 : power : : 2.5V : 8 : VCCIO8 : C4 : power : : 3.3V : 8 :
GND : C5 : gnd : : : : GND : C5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : GPIO_0[15] : C6 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : C7 : power : : 2.5V : 8 : VCCIO8 : C7 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : GPIO_0[16] : C8 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : GPIO_0[24] : C9 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : C10 : power : : 3.3V : 7 : VCCIO7 : C10 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : GPIO_0[28] : C11 : output : 3.3-V LVTTL : : 7 : Y
GND : C12 : gnd : : : : GND : C12 : gnd : : : :
VCCIO7 : C13 : power : : 3.3V : 7 : VCCIO7 : C13 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
@@ -118,16 +118,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 :
LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : GPIO_0[0] : D3 : output : 3.3-V LVTTL : : 8 : Y
VCCD_PLL3 : D4 : power : : 1.2V : : VCCD_PLL3 : D4 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : GPIO_0[9] : D5 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : GPIO_0[13] : D6 : output : 3.3-V LVTTL : : 8 : Y
GND : D7 : gnd : : : : GND : D7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : GPIO_0[19] : D8 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 : GPIO_0[25] : D9 : output : 3.3-V LVTTL : : 7 : Y
GND : D10 : gnd : : : : GND : D10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 : GPIO_0[31] : D11 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : GPIO_0[32] : D12 : output : 3.3-V LVTTL : : 7 : Y
VCCD_PLL2 : D13 : power : : 1.2V : : VCCD_PLL2 : D13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 :
@@ -137,12 +137,12 @@ GND : E2 : gnd : :
VCCIO1 : E3 : power : : 3.3V : 1 : VCCIO1 : E3 : power : : 3.3V : 1 :
GND : E4 : gnd : : : : GND : E4 : gnd : : : :
GNDA3 : E5 : gnd : : : : GNDA3 : E5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : GPIO_0[17] : E6 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : GPIO_0[18] : E7 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : GPIO_0[20] : E8 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 : GPIO_0[23] : E9 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 : GPIO_0[27] : E10 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : GPIO_0[26] : E11 : output : 3.3-V LVTTL : : 7 : Y
GNDA2 : E12 : gnd : : : : GNDA2 : E12 : gnd : : : :
GND : E13 : gnd : : : : GND : E13 : gnd : : : :
VCCIO6 : E14 : power : : 2.5V : 6 : VCCIO6 : E14 : power : : 2.5V : 6 :
@@ -155,8 +155,8 @@ nSTATUS : F4 : : :
VCCA3 : F5 : power : : 2.5V : : VCCA3 : F5 : power : : 2.5V : :
GND : F6 : gnd : : : : GND : F6 : gnd : : : :
VCCINT : F7 : power : : 1.2V : : VCCINT : F7 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : GPIO_0[21] : F8 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 : GPIO_0[22] : F9 : output : 3.3-V LVTTL : : 7 : Y
GND : F10 : gnd : : : : GND : F10 : gnd : : : :
VCCINT : F11 : power : : 1.2V : : VCCINT : F11 : power : : 1.2V : :
VCCA2 : F12 : power : : 2.5V : : VCCA2 : F12 : power : : 2.5V : :
output_files/spectrum.sof
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output_files/spectrum.sta.rpt
+10038 -4858
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