From 107dded913ff335fccceaecded6a4f0ca5db7af0 Mon Sep 17 00:00:00 2001 From: Adrian Scripca Date: Wed, 30 Mar 2022 14:57:41 +0300 Subject: [PATCH] Sample memory model with all components --- db/altsyncram_dui2.tdf | 2121 +++ db/altsyncram_g9i1.tdf | 903 + db/decode_f8a.tdf | 46 + db/decode_i8a.tdf | 54 + db/decode_msa.tdf | 49 + db/decode_psa.tdf | 57 + db/logic_util_heursitic.dat | Bin 5588 -> 12848 bytes db/mux_6nb.tdf | 53 + db/mux_9nb.tdf | 103 + db/prev_cmp_spectrum.qmsg | 325 +- db/spectrum.(0).cnf.cdb | Bin 4592 -> 4651 bytes db/spectrum.(0).cnf.hdb | Bin 2221 -> 2376 bytes db/spectrum.(14).cnf.cdb | Bin 0 -> 1938 bytes db/spectrum.(14).cnf.hdb | Bin 0 -> 844 bytes db/spectrum.(15).cnf.cdb | Bin 0 -> 6560 bytes db/spectrum.(15).cnf.hdb | Bin 0 -> 1859 bytes db/spectrum.(16).cnf.cdb | Bin 0 -> 1738 bytes db/spectrum.(16).cnf.hdb | Bin 0 -> 1108 bytes db/spectrum.(17).cnf.cdb | Bin 0 -> 1883 bytes db/spectrum.(17).cnf.hdb | Bin 0 -> 1072 bytes db/spectrum.(18).cnf.cdb | Bin 0 -> 7609 bytes db/spectrum.(18).cnf.hdb | Bin 0 -> 2146 bytes db/spectrum.(19).cnf.cdb | Bin 0 -> 2193 bytes db/spectrum.(19).cnf.hdb | Bin 0 -> 1167 bytes db/spectrum.(20).cnf.cdb | Bin 0 -> 1634 bytes db/spectrum.(20).cnf.hdb | Bin 0 -> 849 bytes db/spectrum.(21).cnf.cdb | Bin 0 -> 4331 bytes db/spectrum.(21).cnf.hdb | Bin 0 -> 1303 bytes db/spectrum.(22).cnf.cdb | Bin 0 -> 1163 bytes db/spectrum.(22).cnf.hdb | Bin 0 -> 872 bytes db/spectrum.(23).cnf.cdb | Bin 0 -> 1251 bytes db/spectrum.(23).cnf.hdb | Bin 0 -> 835 bytes db/spectrum.(24).cnf.cdb | Bin 0 -> 3732 bytes db/spectrum.(24).cnf.hdb | Bin 0 -> 970 bytes db/spectrum.(8).cnf.cdb | Bin 2716 -> 2717 bytes db/spectrum.(8).cnf.hdb | Bin 1433 -> 1432 bytes db/spectrum.asm.qmsg | 12 +- db/spectrum.asm.rdb | Bin 1353 -> 1354 bytes db/spectrum.asm_labs.ddb | Bin 18297 -> 26522 bytes db/spectrum.cbx.xml | 1 + db/spectrum.cmp.bpm | Bin 683 -> 960 bytes db/spectrum.cmp.cdb | Bin 32726 -> 88655 bytes db/spectrum.cmp.hdb | Bin 21175 -> 30515 bytes db/spectrum.cmp.idb | Bin 2992 -> 7039 bytes db/spectrum.cmp.logdb | 38 +- db/spectrum.cmp.rdb | Bin 88114 -> 135175 bytes db/spectrum.eda.qmsg | 24 +- db/spectrum.fit.qmsg | 98 +- db/spectrum.hier_info | 819 +- db/spectrum.hif | Bin 2664 -> 3465 bytes db/spectrum.ipinfo | Bin 445 -> 477 bytes db/spectrum.lpc.html | 90 +- db/spectrum.lpc.rdb | Bin 689 -> 771 bytes db/spectrum.lpc.txt | 85 +- db/spectrum.map.bpm | Bin 692 -> 963 bytes db/spectrum.map.cdb | Bin 16677 -> 32742 bytes db/spectrum.map.hdb | Bin 20363 -> 29585 bytes db/spectrum.map.kpt | Bin 1353 -> 1273 bytes db/spectrum.map.qmsg | 89 +- db/spectrum.map.rdb | Bin 1315 -> 1320 bytes db/spectrum.map_bb.cdb | Bin 1856 -> 2043 bytes db/spectrum.map_bb.hdb | Bin 15614 -> 16443 bytes db/spectrum.pre_map.hdb | Bin 26256 -> 30662 bytes db/spectrum.root_partition.map.reg_db.cdb | Bin 633 -> 479 bytes db/spectrum.routing.rdb | Bin 10399 -> 21151 bytes db/spectrum.rtlv.hdb | Bin 25543 -> 29820 bytes db/spectrum.rtlv_sg.cdb | Bin 33849 -> 43580 bytes db/spectrum.rtlv_sg_swap.cdb | Bin 3703 -> 4849 bytes db/spectrum.sgdiff.cdb | Bin 15176 -> 29014 bytes db/spectrum.sgdiff.hdb | Bin 22957 -> 25538 bytes db/spectrum.sta.qmsg | 84 +- db/spectrum.sta.rdb | Bin 21896 -> 28627 bytes db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb | Bin 20549 -> 58727 bytes db/spectrum.tiscmp.fast_1200mv_0c.ddb | Bin 149642 -> 272119 bytes db/spectrum.tiscmp.slow_1200mv_0c.ddb | Bin 150874 -> 272928 bytes db/spectrum.tiscmp.slow_1200mv_85c.ddb | Bin 150880 -> 272994 bytes db/spectrum.vpr.ammdb | Bin 995 -> 2125 bytes greybox_tmp/cbx_args.txt | 28 +- .../spectrum.root_partition.cmp.ammdb | Bin 981 -> 2092 bytes .../spectrum.root_partition.cmp.cdb | Bin 18289 -> 36771 bytes .../spectrum.root_partition.cmp.hdb | Bin 20697 -> 30061 bytes .../spectrum.root_partition.cmp.rcfdb | Bin 13333 -> 48121 bytes .../spectrum.root_partition.map.cdb | Bin 16342 -> 32485 bytes .../spectrum.root_partition.map.dpi | Bin 2820 -> 3361 bytes .../spectrum.root_partition.map.hbdb.cdb | Bin 1440 -> 1440 bytes .../spectrum.root_partition.map.hbdb.hdb | Bin 20012 -> 29233 bytes .../spectrum.root_partition.map.hdb | Bin 21529 -> 30719 bytes .../spectrum.root_partition.map.kpt | Bin 1361 -> 1282 bytes output_files/spectrum.asm.rpt | 16 +- output_files/spectrum.done | 2 +- output_files/spectrum.eda.rpt | 12 +- output_files/spectrum.fit.rpt | 12650 +++++++++---- output_files/spectrum.fit.summary | 14 +- output_files/spectrum.flow.rpt | 60 +- output_files/spectrum.jdi | 2 +- output_files/spectrum.map.rpt | 675 +- output_files/spectrum.map.summary | 14 +- output_files/spectrum.pin | 76 +- output_files/spectrum.sof | Bin 703948 -> 703948 bytes output_files/spectrum.sta.rpt | 14896 +++++++++++----- output_files/spectrum.sta.summary | 24 +- ram32.qip | 4 + ram32.v | 174 + ram32_bb.v | 124 + simulation/modelsim/spectrum.vo | 6355 ++++++- .../modelsim/spectrum_6_1200mv_0c_slow.vo | 6355 ++++++- .../modelsim/spectrum_6_1200mv_0c_v_slow.sdo | 11232 ++++++++++-- .../modelsim/spectrum_6_1200mv_85c_slow.vo | 6355 ++++++- .../modelsim/spectrum_6_1200mv_85c_v_slow.sdo | 10774 +++++++++-- .../modelsim/spectrum_min_1200mv_0c_fast.vo | 6355 ++++++- .../spectrum_min_1200mv_0c_v_fast.sdo | 10966 ++++++++++-- simulation/modelsim/spectrum_modelsim.xrf | 197 +- simulation/modelsim/spectrum_v.sdo | 10774 +++++++++-- spectrum.qsf | 1 + spectrum.v | 123 +- 115 files changed, 87135 insertions(+), 16174 deletions(-) create mode 100644 db/altsyncram_dui2.tdf create mode 100644 db/altsyncram_g9i1.tdf create mode 100644 db/decode_f8a.tdf create mode 100644 db/decode_i8a.tdf create mode 100644 db/decode_msa.tdf create mode 100644 db/decode_psa.tdf create mode 100644 db/mux_6nb.tdf create mode 100644 db/mux_9nb.tdf create mode 100644 db/spectrum.(14).cnf.cdb create mode 100644 db/spectrum.(14).cnf.hdb create mode 100644 db/spectrum.(15).cnf.cdb create mode 100644 db/spectrum.(15).cnf.hdb create mode 100644 db/spectrum.(16).cnf.cdb create mode 100644 db/spectrum.(16).cnf.hdb create mode 100644 db/spectrum.(17).cnf.cdb create mode 100644 db/spectrum.(17).cnf.hdb create mode 100644 db/spectrum.(18).cnf.cdb create mode 100644 db/spectrum.(18).cnf.hdb create mode 100644 db/spectrum.(19).cnf.cdb create mode 100644 db/spectrum.(19).cnf.hdb create mode 100644 db/spectrum.(20).cnf.cdb create mode 100644 db/spectrum.(20).cnf.hdb create mode 100644 db/spectrum.(21).cnf.cdb create mode 100644 db/spectrum.(21).cnf.hdb create mode 100644 db/spectrum.(22).cnf.cdb create mode 100644 db/spectrum.(22).cnf.hdb create mode 100644 db/spectrum.(23).cnf.cdb create mode 100644 db/spectrum.(23).cnf.hdb create mode 100644 db/spectrum.(24).cnf.cdb create mode 100644 db/spectrum.(24).cnf.hdb create mode 100644 ram32.qip create mode 100644 ram32.v create mode 100644 ram32_bb.v diff --git a/db/altsyncram_dui2.tdf b/db/altsyncram_dui2.tdf new file mode 100644 index 0000000..6f117e9 --- /dev/null +++ b/db/altsyncram_dui2.tdf @@ -0,0 +1,2121 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=49152 NUMWORDS_B=49152 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=16 WIDTHAD_B=16 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_psa (data[2..0], enable) +RETURNS ( eq[5..0]); +FUNCTION decode_i8a (data[2..0]) +RETURNS ( eq[5..0]); +FUNCTION mux_9nb (data[47..0], sel[2..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 112 M9K 48 reg 12 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_dui2 +( + address_a[15..0] : input; + address_b[15..0] : input; + clock0 : input; + data_a[7..0] : input; + data_b[7..0] : input; + q_a[7..0] : output; + q_b[7..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + address_reg_a[2..0] : dffe; + address_reg_b[2..0] : dffe; + out_address_reg_a[2..0] : dffe; + out_address_reg_b[2..0] : dffe; + decode2 : decode_psa; + decode3 : decode_psa; + rden_decode_a : decode_i8a; + rden_decode_b : decode_i8a; + mux4 : mux_9nb; + mux5 : mux_9nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 49152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 49152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[2..0] : WIRE; + address_a_wire[15..0] : WIRE; + address_b_sel[2..0] : WIRE; + address_b_wire[15..0] : WIRE; + w_addr_val_b4w[2..0] : WIRE; + w_addr_val_b8w[2..0] : WIRE; + wren_decode_addr_sel_a[2..0] : WIRE; + wren_decode_addr_sel_b[2..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + out_address_reg_b[].clk = clock0; + out_address_reg_b[].d = address_reg_b[].q; + decode2.data[2..0] = address_a_wire[15..13]; + decode2.enable = wren_a; + decode3.data[] = w_addr_val_b4w[]; + decode3.enable = wren_b; + rden_decode_a.data[] = wren_decode_addr_sel_a[]; + rden_decode_b.data[] = w_addr_val_b8w[]; + mux4.data[] = ( ram_block1a[47..0].portadataout[0..0]); + mux4.sel[] = out_address_reg_a[].q; + mux5.data[] = ( ram_block1a[47..0].portbdataout[0..0]); + mux5.sel[] = out_address_reg_b[].q; + ram_block1a[47..0].clk0 = clock0; + ram_block1a[47..0].clk1 = clock0; + ram_block1a[47..0].ena0 = ( rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]); + ram_block1a[47..0].ena1 = ( rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]); + ram_block1a[47..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[0..0]); + ram_block1a[41].portadatain[] = ( data_a[1..1]); + ram_block1a[42].portadatain[] = ( data_a[2..2]); + ram_block1a[43].portadatain[] = ( data_a[3..3]); + ram_block1a[44].portadatain[] = ( data_a[4..4]); + ram_block1a[45].portadatain[] = ( data_a[5..5]); + ram_block1a[46].portadatain[] = ( data_a[6..6]); + ram_block1a[47].portadatain[] = ( data_a[7..7]); + ram_block1a[47..0].portare = B"111111111111111111111111111111111111111111111111"; + ram_block1a[47..0].portawe = ( decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[47..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[0..0]); + ram_block1a[9].portbdatain[] = ( data_b[1..1]); + ram_block1a[10].portbdatain[] = ( data_b[2..2]); + ram_block1a[11].portbdatain[] = ( data_b[3..3]); + ram_block1a[12].portbdatain[] = ( data_b[4..4]); + ram_block1a[13].portbdatain[] = ( data_b[5..5]); + ram_block1a[14].portbdatain[] = ( data_b[6..6]); + ram_block1a[15].portbdatain[] = ( data_b[7..7]); + ram_block1a[16].portbdatain[] = ( data_b[0..0]); + ram_block1a[17].portbdatain[] = ( data_b[1..1]); + ram_block1a[18].portbdatain[] = ( data_b[2..2]); + ram_block1a[19].portbdatain[] = ( data_b[3..3]); + ram_block1a[20].portbdatain[] = ( data_b[4..4]); + ram_block1a[21].portbdatain[] = ( data_b[5..5]); + ram_block1a[22].portbdatain[] = ( data_b[6..6]); + ram_block1a[23].portbdatain[] = ( data_b[7..7]); + ram_block1a[24].portbdatain[] = ( data_b[0..0]); + ram_block1a[25].portbdatain[] = ( data_b[1..1]); + ram_block1a[26].portbdatain[] = ( data_b[2..2]); + ram_block1a[27].portbdatain[] = ( data_b[3..3]); + ram_block1a[28].portbdatain[] = ( data_b[4..4]); + ram_block1a[29].portbdatain[] = ( data_b[5..5]); + ram_block1a[30].portbdatain[] = ( data_b[6..6]); + ram_block1a[31].portbdatain[] = ( data_b[7..7]); + ram_block1a[32].portbdatain[] = ( data_b[0..0]); + ram_block1a[33].portbdatain[] = ( data_b[1..1]); + ram_block1a[34].portbdatain[] = ( data_b[2..2]); + ram_block1a[35].portbdatain[] = ( data_b[3..3]); + ram_block1a[36].portbdatain[] = ( data_b[4..4]); + ram_block1a[37].portbdatain[] = ( data_b[5..5]); + ram_block1a[38].portbdatain[] = ( data_b[6..6]); + ram_block1a[39].portbdatain[] = ( data_b[7..7]); + ram_block1a[40].portbdatain[] = ( data_b[0..0]); + ram_block1a[41].portbdatain[] = ( data_b[1..1]); + ram_block1a[42].portbdatain[] = ( data_b[2..2]); + ram_block1a[43].portbdatain[] = ( data_b[3..3]); + ram_block1a[44].portbdatain[] = ( data_b[4..4]); + ram_block1a[45].portbdatain[] = ( data_b[5..5]); + ram_block1a[46].portbdatain[] = ( data_b[6..6]); + ram_block1a[47].portbdatain[] = ( data_b[7..7]); + ram_block1a[47..0].portbre = B"111111111111111111111111111111111111111111111111"; + ram_block1a[47..0].portbwe = ( decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[2..0] = address_a[15..13]; + address_a_wire[] = address_a[]; + address_b_sel[2..0] = address_b[15..13]; + address_b_wire[] = address_b[]; + q_a[] = mux4.result[]; + q_b[] = mux5.result[]; + w_addr_val_b4w[2..0] = address_b_wire[15..13]; + w_addr_val_b8w[] = wren_decode_addr_sel_b[]; + wren_decode_addr_sel_a[2..0] = address_a_wire[15..13]; + wren_decode_addr_sel_b[2..0] = address_b_wire[15..13]; +END; +--VALID FILE diff --git a/db/altsyncram_g9i1.tdf b/db/altsyncram_g9i1.tdf new file mode 100644 index 0000000..a73e04e --- /dev/null +++ b/db/altsyncram_g9i1.tdf @@ -0,0 +1,903 @@ +--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=32768 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=15 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_msa (data[1..0], enable) +RETURNS ( eq[3..0]); +FUNCTION decode_f8a (data[1..0]) +RETURNS ( eq[3..0]); +FUNCTION mux_6nb (data[31..0], sel[1..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 24 M9K 32 reg 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_g9i1 +( + address_a[14..0] : input; + clock0 : input; + data_a[7..0] : input; + q_a[7..0] : output; + wren_a : input; +) +VARIABLE + address_reg_a[1..0] : dffe; + out_address_reg_a[1..0] : dffe; + decode3 : decode_msa; + rden_decode : decode_f8a; + mux2 : mux_6nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[1..0] : WIRE; + address_a_wire[14..0] : WIRE; + rden_decode_addr_sel_a[1..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + decode3.data[1..0] = address_a_wire[14..13]; + decode3.enable = wren_a; + rden_decode.data[] = rden_decode_addr_sel_a[]; + mux2.data[] = ( ram_block1a[31..0].portadataout[0..0]); + mux2.sel[] = out_address_reg_a[].q; + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].ena0 = ( rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]); + ram_block1a[31..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = ( decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[1..0] = address_a[14..13]; + address_a_wire[] = address_a[]; + q_a[] = mux2.result[]; + rden_decode_addr_sel_a[1..0] = address_a_wire[14..13]; +END; +--VALID FILE diff --git a/db/decode_f8a.tdf b/db/decode_f8a.tdf new file mode 100644 index 0000000..caed507 --- /dev/null +++ b/db/decode_f8a.tdf @@ -0,0 +1,46 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 4 +SUBDESIGN decode_f8a +( + data[1..0] : input; + eq[3..0] : output; +) +VARIABLE + data_wire[1..0] : WIRE; + eq_node[3..0] : WIRE; + eq_wire[3..0] : WIRE; + w_anode261w[2..0] : WIRE; + w_anode275w[2..0] : WIRE; + w_anode284w[2..0] : WIRE; + w_anode293w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + eq[] = eq_node[]; + eq_node[3..0] = eq_wire[3..0]; + eq_wire[] = ( w_anode293w[2..2], w_anode284w[2..2], w_anode275w[2..2], w_anode261w[2..2]); + w_anode261w[] = ( (w_anode261w[1..1] & (! data_wire[1..1])), (w_anode261w[0..0] & (! data_wire[0..0])), B"1"); + w_anode275w[] = ( (w_anode275w[1..1] & (! data_wire[1..1])), (w_anode275w[0..0] & data_wire[0..0]), B"1"); + w_anode284w[] = ( (w_anode284w[1..1] & data_wire[1..1]), (w_anode284w[0..0] & (! data_wire[0..0])), B"1"); + w_anode293w[] = ( (w_anode293w[1..1] & data_wire[1..1]), (w_anode293w[0..0] & data_wire[0..0]), B"1"); +END; +--VALID FILE diff --git a/db/decode_i8a.tdf b/db/decode_i8a.tdf new file mode 100644 index 0000000..ba7cedf --- /dev/null +++ b/db/decode_i8a.tdf @@ -0,0 +1,54 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 8 +SUBDESIGN decode_i8a +( + data[2..0] : input; + eq[5..0] : output; +) +VARIABLE + data_wire[2..0] : WIRE; + eq_node[5..0] : WIRE; + eq_wire[7..0] : WIRE; + w_anode741w[3..0] : WIRE; + w_anode759w[3..0] : WIRE; + w_anode770w[3..0] : WIRE; + w_anode781w[3..0] : WIRE; + w_anode792w[3..0] : WIRE; + w_anode803w[3..0] : WIRE; + w_anode814w[3..0] : WIRE; + w_anode825w[3..0] : WIRE; + +BEGIN + data_wire[] = data[]; + eq[] = eq_node[]; + eq_node[5..0] = eq_wire[5..0]; + eq_wire[] = ( w_anode825w[3..3], w_anode814w[3..3], w_anode803w[3..3], w_anode792w[3..3], w_anode781w[3..3], w_anode770w[3..3], w_anode759w[3..3], w_anode741w[3..3]); + w_anode741w[] = ( (w_anode741w[2..2] & (! data_wire[2..2])), (w_anode741w[1..1] & (! data_wire[1..1])), (w_anode741w[0..0] & (! data_wire[0..0])), B"1"); + w_anode759w[] = ( (w_anode759w[2..2] & (! data_wire[2..2])), (w_anode759w[1..1] & (! data_wire[1..1])), (w_anode759w[0..0] & data_wire[0..0]), B"1"); + w_anode770w[] = ( (w_anode770w[2..2] & (! data_wire[2..2])), (w_anode770w[1..1] & data_wire[1..1]), (w_anode770w[0..0] & (! data_wire[0..0])), B"1"); + w_anode781w[] = ( (w_anode781w[2..2] & (! data_wire[2..2])), (w_anode781w[1..1] & data_wire[1..1]), (w_anode781w[0..0] & data_wire[0..0]), B"1"); + w_anode792w[] = ( (w_anode792w[2..2] & data_wire[2..2]), (w_anode792w[1..1] & (! data_wire[1..1])), (w_anode792w[0..0] & (! data_wire[0..0])), B"1"); + w_anode803w[] = ( (w_anode803w[2..2] & data_wire[2..2]), (w_anode803w[1..1] & (! data_wire[1..1])), (w_anode803w[0..0] & data_wire[0..0]), B"1"); + w_anode814w[] = ( (w_anode814w[2..2] & data_wire[2..2]), (w_anode814w[1..1] & data_wire[1..1]), (w_anode814w[0..0] & (! data_wire[0..0])), B"1"); + w_anode825w[] = ( (w_anode825w[2..2] & data_wire[2..2]), (w_anode825w[1..1] & data_wire[1..1]), (w_anode825w[0..0] & data_wire[0..0]), B"1"); +END; +--VALID FILE diff --git a/db/decode_msa.tdf b/db/decode_msa.tdf new file mode 100644 index 0000000..5d59867 --- /dev/null +++ b/db/decode_msa.tdf @@ -0,0 +1,49 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data enable eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 4 +SUBDESIGN decode_msa +( + data[1..0] : input; + enable : input; + eq[3..0] : output; +) +VARIABLE + data_wire[1..0] : WIRE; + enable_wire : WIRE; + eq_node[3..0] : WIRE; + eq_wire[3..0] : WIRE; + w_anode223w[2..0] : WIRE; + w_anode236w[2..0] : WIRE; + w_anode244w[2..0] : WIRE; + w_anode252w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[3..0] = eq_wire[3..0]; + eq_wire[] = ( w_anode252w[2..2], w_anode244w[2..2], w_anode236w[2..2], w_anode223w[2..2]); + w_anode223w[] = ( (w_anode223w[1..1] & (! data_wire[1..1])), (w_anode223w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode236w[] = ( (w_anode236w[1..1] & (! data_wire[1..1])), (w_anode236w[0..0] & data_wire[0..0]), enable_wire); + w_anode244w[] = ( (w_anode244w[1..1] & data_wire[1..1]), (w_anode244w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode252w[] = ( (w_anode252w[1..1] & data_wire[1..1]), (w_anode252w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/db/decode_psa.tdf b/db/decode_psa.tdf new file mode 100644 index 0000000..b44a572 --- /dev/null +++ b/db/decode_psa.tdf @@ -0,0 +1,57 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data enable eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 8 +SUBDESIGN decode_psa +( + data[2..0] : input; + enable : input; + eq[5..0] : output; +) +VARIABLE + data_wire[2..0] : WIRE; + enable_wire : WIRE; + eq_node[5..0] : WIRE; + eq_wire[7..0] : WIRE; + w_anode653w[3..0] : WIRE; + w_anode670w[3..0] : WIRE; + w_anode680w[3..0] : WIRE; + w_anode690w[3..0] : WIRE; + w_anode700w[3..0] : WIRE; + w_anode710w[3..0] : WIRE; + w_anode720w[3..0] : WIRE; + w_anode730w[3..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[5..0] = eq_wire[5..0]; + eq_wire[] = ( w_anode730w[3..3], w_anode720w[3..3], w_anode710w[3..3], w_anode700w[3..3], w_anode690w[3..3], w_anode680w[3..3], w_anode670w[3..3], w_anode653w[3..3]); + w_anode653w[] = ( (w_anode653w[2..2] & (! data_wire[2..2])), (w_anode653w[1..1] & (! data_wire[1..1])), (w_anode653w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode670w[] = ( (w_anode670w[2..2] & (! data_wire[2..2])), (w_anode670w[1..1] & (! data_wire[1..1])), (w_anode670w[0..0] & data_wire[0..0]), enable_wire); + w_anode680w[] = ( (w_anode680w[2..2] & (! data_wire[2..2])), (w_anode680w[1..1] & data_wire[1..1]), (w_anode680w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode690w[] = ( (w_anode690w[2..2] & (! data_wire[2..2])), (w_anode690w[1..1] & data_wire[1..1]), (w_anode690w[0..0] & data_wire[0..0]), enable_wire); + w_anode700w[] = ( (w_anode700w[2..2] & data_wire[2..2]), (w_anode700w[1..1] & (! data_wire[1..1])), (w_anode700w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode710w[] = ( (w_anode710w[2..2] & data_wire[2..2]), (w_anode710w[1..1] & (! data_wire[1..1])), (w_anode710w[0..0] & data_wire[0..0]), enable_wire); + w_anode720w[] = ( (w_anode720w[2..2] & data_wire[2..2]), (w_anode720w[1..1] & data_wire[1..1]), (w_anode720w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode730w[] = ( (w_anode730w[2..2] & data_wire[2..2]), (w_anode730w[1..1] & data_wire[1..1]), (w_anode730w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index 4c0e94da68b33690f8a45363e0d7203e6ca03174..8e4a899090cc214bc458ea447806f19509e0726a 100644 GIT binary patch literal 12848 zcmb8l)mBsi006)RMMWf(5(C5n5$r};6}uY~ySuyff9&q=&SQ6Xx4&>_o+lIvE+Tjh zMZzrsw^ZgaRT;I@R@3T{5!)^OXvEr1(_+ZJv+xb5KVBWzSHWEkcMaUNaM!_I4|hZG8{QcFhBm?740j9Mt#G%& z-41sL+?{ZD!QBma58S+*1>Bc#U%`D1_YK^)aNogw5BCGyk8nT1{S5aD+^=xI!Tk>R z2i%`p9OT#S#HyUnPxG`|c!HtC*2R9yW z0^IU&E5J>Jn*=u*ZVKE~xE0~1!L0 z`;rszG?>S*9Bx_tBfaI4 zk;kOGmE^ItG%*=$MBr#_d}*OMzb z1KDT5;|w(Y1xT*D_BRA3>T3R90RAsUmwB#*1a1pfR^%-~ZcMSGs^C?^V09U?%HVS8 z!TynS)vZ569Z^r8bR>tV+_6dvz_>k@aTGT1?iMRR8Oa|!?e2CFwTw^D`-Z&4gNXh| zR*{1_-^%VLx5|X9A{O9FembYRB(C%;Z-#GH;m=(~9zarq`_!f5fyt=1kP1w^HuDcp zQWs&l;S(5LfK|!O8IaCjc}(-dJQ#2JJe8<}#3uP<6Lrwm7z_bqgPm8QxL5jzG)ujC zKh@^lHlwLol1Hy3veOqv=P#J|OJXV+A8jnz*Gfg{f8%IP*UWkn%J7jfZ>3>Lx?HH$ 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"*******************************************************************" 0 0 "Quartus II" 0 -1 1648637244327 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing started: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244673 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244704 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder 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"spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244820 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244846 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244872 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing ended: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641378943 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:56:18 2022 " "Processing started: Wed Mar 30 14:56:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648641378944 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379358 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379421 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379484 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379548 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379602 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379655 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379707 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648641379759 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "357 " "Peak virtual memory: 357 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:19 2022 " "Processing ended: Wed Mar 30 14:56:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648641379818 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index 585bc84..76791cf 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,49 +1,49 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648637230636 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648637230642 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230686 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230687 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230687 ""} -{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3"} } { } 0 119042 "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" 0 0 "Fitter" 0 -1 1648637230752 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648637230771 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648637230784 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648637231004 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 609 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 611 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 613 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 615 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648637231009 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648637231010 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648637231012 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648637231699 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648637231700 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648637231702 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648637231702 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648637231703 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648637231712 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 604 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648637231712 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648637231960 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637231960 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637231961 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637231962 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637231962 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648637231963 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648637231963 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648637231963 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648637231963 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648637231963 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648637231963 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648637231978 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637231985 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648637233010 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637233086 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648637233095 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648637233849 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637233849 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648637234104 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648637234756 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648637234756 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637235213 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648637235213 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648637235213 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648637235226 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637235280 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637235460 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637235507 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637235657 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637235962 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648637236322 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 26 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648637236325 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648637236325 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648637236389 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:16 2022 " "Processing ended: Wed Mar 30 13:47:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648637236676 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648641362509 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648641362515 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648641362555 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648641362556 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648641362556 ""} +{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31 " "Atom \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648641362617 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31"} } { } 0 119042 "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" 0 0 "Fitter" 0 -1 1648641362617 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648641362645 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648641362656 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648641362885 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648641362885 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648641362885 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648641362885 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1872 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648641362891 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1874 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648641362891 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1876 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648641362891 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1878 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648641362891 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1880 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648641362891 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648641362891 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648641362894 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648641362898 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648641363676 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648641363677 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648641363682 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648641363682 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648641363682 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648641363701 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 1869 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648641363701 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648641364026 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648641364027 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648641364028 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648641364029 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648641364030 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648641364031 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648641364031 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648641364032 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648641364032 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648641364033 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648641364033 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648641364074 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648641364074 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648641364080 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648641365184 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648641365287 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648641365298 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648641366819 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648641366820 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648641367140 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Router estimated average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648641368105 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648641368105 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648641368810 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648641368811 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648641368811 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648641368834 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648641368888 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648641369155 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648641369203 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648641369426 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648641369850 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648641370238 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 67 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648641370244 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648641370244 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648641370354 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 118 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 118 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "603 " "Peak virtual memory: 603 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641370791 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:10 2022 " "Processing ended: Wed Mar 30 14:56:10 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641370791 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641370791 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641370791 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648641370791 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index a1ad3e1..ee910a7 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,13 +1,47 @@ |spectrum -CLOCK_50 => CLOCK_50.IN2 -LED[0] <= ram16:ram0.q_a -LED[1] <= ram16:ram0.q_a -LED[2] <= ram16:ram0.q_a -LED[3] <= ram16:ram0.q_a -LED[4] <= rom0:rom.q -LED[5] <= rom0:rom.q -LED[6] <= rom0:rom.q -LED[7] <= rom0:rom.q +CLOCK_50 => CLOCK_50.IN3 +LED[0] <= rom0:rom.q +LED[1] <= rom0:rom.q +LED[2] <= rom0:rom.q +LED[3] <= rom0:rom.q +LED[4] <= ram16:ram0.q_a +LED[5] <= ram16:ram0.q_a +LED[6] <= ram16:ram0.q_a +LED[7] <= ram16:ram0.q_a +GPIO_0[0] <= rom0:rom.q +GPIO_0[1] <= rom0:rom.q +GPIO_0[2] <= rom0:rom.q +GPIO_0[3] <= rom0:rom.q +GPIO_0[4] <= rom0:rom.q +GPIO_0[5] <= rom0:rom.q +GPIO_0[6] <= rom0:rom.q +GPIO_0[7] <= rom0:rom.q +GPIO_0[8] <= ram16:ram0.q_a +GPIO_0[9] <= ram16:ram0.q_a +GPIO_0[10] <= ram16:ram0.q_a +GPIO_0[11] <= ram16:ram0.q_a +GPIO_0[12] <= ram16:ram0.q_a +GPIO_0[13] <= ram16:ram0.q_a +GPIO_0[14] <= ram16:ram0.q_a +GPIO_0[15] <= ram16:ram0.q_a +GPIO_0[16] <= ram32:ram1.q +GPIO_0[17] <= ram32:ram1.q +GPIO_0[18] <= ram32:ram1.q +GPIO_0[19] <= ram32:ram1.q +GPIO_0[20] <= ram32:ram1.q +GPIO_0[21] <= ram32:ram1.q +GPIO_0[22] <= ram32:ram1.q +GPIO_0[23] <= ram32:ram1.q +GPIO_0[24] <= ram16:ram0.q_b +GPIO_0[25] <= ram16:ram0.q_b +GPIO_0[26] <= ram16:ram0.q_b +GPIO_0[27] <= ram16:ram0.q_b +GPIO_0[28] <= ram16:ram0.q_b +GPIO_0[29] <= ram16:ram0.q_b +GPIO_0[30] <= ram16:ram0.q_b +GPIO_0[31] <= ram16:ram0.q_b +GPIO_0[32] <= +GPIO_0[33] <= |spectrum|rom0:rom @@ -1157,3 +1191,770 @@ sel[0] => result_node[0].IN0 sel[0] => _.IN0 +|spectrum|ram32:ram1 +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +address[8] => address[8].IN1 +address[9] => address[9].IN1 +address[10] => address[10].IN1 +address[11] => address[11].IN1 +address[12] => address[12].IN1 +address[13] => address[13].IN1 +address[14] => address[14].IN1 +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +wren => wren.IN1 +q[0] <= altsyncram:altsyncram_component.q_a +q[1] <= altsyncram:altsyncram_component.q_a +q[2] <= altsyncram:altsyncram_component.q_a +q[3] <= altsyncram:altsyncram_component.q_a +q[4] <= altsyncram:altsyncram_component.q_a +q[5] <= altsyncram:altsyncram_component.q_a +q[6] <= altsyncram:altsyncram_component.q_a +q[7] <= altsyncram:altsyncram_component.q_a + + +|spectrum|ram32:ram1|altsyncram:altsyncram_component +wren_a => altsyncram_g9i1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_g9i1:auto_generated.data_a[0] +data_a[1] => altsyncram_g9i1:auto_generated.data_a[1] +data_a[2] => altsyncram_g9i1:auto_generated.data_a[2] +data_a[3] => altsyncram_g9i1:auto_generated.data_a[3] +data_a[4] => altsyncram_g9i1:auto_generated.data_a[4] +data_a[5] => altsyncram_g9i1:auto_generated.data_a[5] +data_a[6] => altsyncram_g9i1:auto_generated.data_a[6] +data_a[7] => altsyncram_g9i1:auto_generated.data_a[7] +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_g9i1:auto_generated.address_a[0] +address_a[1] => altsyncram_g9i1:auto_generated.address_a[1] +address_a[2] => altsyncram_g9i1:auto_generated.address_a[2] +address_a[3] => altsyncram_g9i1:auto_generated.address_a[3] +address_a[4] => altsyncram_g9i1:auto_generated.address_a[4] +address_a[5] => altsyncram_g9i1:auto_generated.address_a[5] +address_a[6] => altsyncram_g9i1:auto_generated.address_a[6] +address_a[7] => altsyncram_g9i1:auto_generated.address_a[7] +address_a[8] => altsyncram_g9i1:auto_generated.address_a[8] +address_a[9] => altsyncram_g9i1:auto_generated.address_a[9] +address_a[10] => altsyncram_g9i1:auto_generated.address_a[10] +address_a[11] => altsyncram_g9i1:auto_generated.address_a[11] +address_a[12] => altsyncram_g9i1:auto_generated.address_a[12] +address_a[13] => altsyncram_g9i1:auto_generated.address_a[13] +address_a[14] => altsyncram_g9i1:auto_generated.address_a[14] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_g9i1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_g9i1:auto_generated.q_a[0] +q_a[1] <= altsyncram_g9i1:auto_generated.q_a[1] +q_a[2] <= altsyncram_g9i1:auto_generated.q_a[2] +q_a[3] <= altsyncram_g9i1:auto_generated.q_a[3] +q_a[4] <= altsyncram_g9i1:auto_generated.q_a[4] +q_a[5] <= altsyncram_g9i1:auto_generated.q_a[5] +q_a[6] <= altsyncram_g9i1:auto_generated.q_a[6] +q_a[7] <= altsyncram_g9i1:auto_generated.q_a[7] +q_b[0] <= +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[8] => ram_block1a16.PORTAADDR8 +address_a[8] => ram_block1a17.PORTAADDR8 +address_a[8] => ram_block1a18.PORTAADDR8 +address_a[8] => ram_block1a19.PORTAADDR8 +address_a[8] => ram_block1a20.PORTAADDR8 +address_a[8] => ram_block1a21.PORTAADDR8 +address_a[8] => ram_block1a22.PORTAADDR8 +address_a[8] => ram_block1a23.PORTAADDR8 +address_a[8] => ram_block1a24.PORTAADDR8 +address_a[8] => ram_block1a25.PORTAADDR8 +address_a[8] => ram_block1a26.PORTAADDR8 +address_a[8] => ram_block1a27.PORTAADDR8 +address_a[8] => ram_block1a28.PORTAADDR8 +address_a[8] => ram_block1a29.PORTAADDR8 +address_a[8] => ram_block1a30.PORTAADDR8 +address_a[8] => ram_block1a31.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[9] => ram_block1a16.PORTAADDR9 +address_a[9] => ram_block1a17.PORTAADDR9 +address_a[9] => ram_block1a18.PORTAADDR9 +address_a[9] => ram_block1a19.PORTAADDR9 +address_a[9] => ram_block1a20.PORTAADDR9 +address_a[9] => ram_block1a21.PORTAADDR9 +address_a[9] => ram_block1a22.PORTAADDR9 +address_a[9] => ram_block1a23.PORTAADDR9 +address_a[9] => ram_block1a24.PORTAADDR9 +address_a[9] => ram_block1a25.PORTAADDR9 +address_a[9] => ram_block1a26.PORTAADDR9 +address_a[9] => ram_block1a27.PORTAADDR9 +address_a[9] => ram_block1a28.PORTAADDR9 +address_a[9] => ram_block1a29.PORTAADDR9 +address_a[9] => ram_block1a30.PORTAADDR9 +address_a[9] => ram_block1a31.PORTAADDR9 +address_a[10] => ram_block1a0.PORTAADDR10 +address_a[10] => ram_block1a1.PORTAADDR10 +address_a[10] => ram_block1a2.PORTAADDR10 +address_a[10] => ram_block1a3.PORTAADDR10 +address_a[10] => ram_block1a4.PORTAADDR10 +address_a[10] => ram_block1a5.PORTAADDR10 +address_a[10] => ram_block1a6.PORTAADDR10 +address_a[10] => ram_block1a7.PORTAADDR10 +address_a[10] => ram_block1a8.PORTAADDR10 +address_a[10] => ram_block1a9.PORTAADDR10 +address_a[10] => ram_block1a10.PORTAADDR10 +address_a[10] => ram_block1a11.PORTAADDR10 +address_a[10] => ram_block1a12.PORTAADDR10 +address_a[10] => ram_block1a13.PORTAADDR10 +address_a[10] => ram_block1a14.PORTAADDR10 +address_a[10] => ram_block1a15.PORTAADDR10 +address_a[10] => ram_block1a16.PORTAADDR10 +address_a[10] => ram_block1a17.PORTAADDR10 +address_a[10] => ram_block1a18.PORTAADDR10 +address_a[10] => ram_block1a19.PORTAADDR10 +address_a[10] => ram_block1a20.PORTAADDR10 +address_a[10] => ram_block1a21.PORTAADDR10 +address_a[10] => ram_block1a22.PORTAADDR10 +address_a[10] => ram_block1a23.PORTAADDR10 +address_a[10] => ram_block1a24.PORTAADDR10 +address_a[10] => ram_block1a25.PORTAADDR10 +address_a[10] => ram_block1a26.PORTAADDR10 +address_a[10] => ram_block1a27.PORTAADDR10 +address_a[10] => ram_block1a28.PORTAADDR10 +address_a[10] => ram_block1a29.PORTAADDR10 +address_a[10] => ram_block1a30.PORTAADDR10 +address_a[10] => ram_block1a31.PORTAADDR10 +address_a[11] => ram_block1a0.PORTAADDR11 +address_a[11] => ram_block1a1.PORTAADDR11 +address_a[11] => ram_block1a2.PORTAADDR11 +address_a[11] => ram_block1a3.PORTAADDR11 +address_a[11] => ram_block1a4.PORTAADDR11 +address_a[11] => ram_block1a5.PORTAADDR11 +address_a[11] => ram_block1a6.PORTAADDR11 +address_a[11] => ram_block1a7.PORTAADDR11 +address_a[11] => ram_block1a8.PORTAADDR11 +address_a[11] => ram_block1a9.PORTAADDR11 +address_a[11] => ram_block1a10.PORTAADDR11 +address_a[11] => ram_block1a11.PORTAADDR11 +address_a[11] => ram_block1a12.PORTAADDR11 +address_a[11] => ram_block1a13.PORTAADDR11 +address_a[11] => ram_block1a14.PORTAADDR11 +address_a[11] => ram_block1a15.PORTAADDR11 +address_a[11] => ram_block1a16.PORTAADDR11 +address_a[11] => ram_block1a17.PORTAADDR11 +address_a[11] => ram_block1a18.PORTAADDR11 +address_a[11] => ram_block1a19.PORTAADDR11 +address_a[11] => ram_block1a20.PORTAADDR11 +address_a[11] => ram_block1a21.PORTAADDR11 +address_a[11] => ram_block1a22.PORTAADDR11 +address_a[11] => ram_block1a23.PORTAADDR11 +address_a[11] => ram_block1a24.PORTAADDR11 +address_a[11] => ram_block1a25.PORTAADDR11 +address_a[11] => ram_block1a26.PORTAADDR11 +address_a[11] => ram_block1a27.PORTAADDR11 +address_a[11] => ram_block1a28.PORTAADDR11 +address_a[11] => ram_block1a29.PORTAADDR11 +address_a[11] => ram_block1a30.PORTAADDR11 +address_a[11] => ram_block1a31.PORTAADDR11 +address_a[12] => ram_block1a0.PORTAADDR12 +address_a[12] => ram_block1a1.PORTAADDR12 +address_a[12] => ram_block1a2.PORTAADDR12 +address_a[12] => ram_block1a3.PORTAADDR12 +address_a[12] => ram_block1a4.PORTAADDR12 +address_a[12] => ram_block1a5.PORTAADDR12 +address_a[12] => ram_block1a6.PORTAADDR12 +address_a[12] => ram_block1a7.PORTAADDR12 +address_a[12] => ram_block1a8.PORTAADDR12 +address_a[12] => ram_block1a9.PORTAADDR12 +address_a[12] => ram_block1a10.PORTAADDR12 +address_a[12] => ram_block1a11.PORTAADDR12 +address_a[12] => ram_block1a12.PORTAADDR12 +address_a[12] => ram_block1a13.PORTAADDR12 +address_a[12] => ram_block1a14.PORTAADDR12 +address_a[12] => ram_block1a15.PORTAADDR12 +address_a[12] => ram_block1a16.PORTAADDR12 +address_a[12] => ram_block1a17.PORTAADDR12 +address_a[12] => ram_block1a18.PORTAADDR12 +address_a[12] => ram_block1a19.PORTAADDR12 +address_a[12] => ram_block1a20.PORTAADDR12 +address_a[12] => ram_block1a21.PORTAADDR12 +address_a[12] => ram_block1a22.PORTAADDR12 +address_a[12] => ram_block1a23.PORTAADDR12 +address_a[12] => ram_block1a24.PORTAADDR12 +address_a[12] => ram_block1a25.PORTAADDR12 +address_a[12] => ram_block1a26.PORTAADDR12 +address_a[12] => ram_block1a27.PORTAADDR12 +address_a[12] => ram_block1a28.PORTAADDR12 +address_a[12] => ram_block1a29.PORTAADDR12 +address_a[12] => ram_block1a30.PORTAADDR12 +address_a[12] => ram_block1a31.PORTAADDR12 +address_a[13] => address_reg_a[0].DATAIN +address_a[13] => decode_msa:decode3.data[0] +address_a[13] => decode_f8a:rden_decode.data[0] +address_a[14] => address_reg_a[1].DATAIN +address_a[14] => decode_msa:decode3.data[1] +address_a[14] => decode_f8a:rden_decode.data[1] +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +clock0 => address_reg_a[1].CLK +clock0 => address_reg_a[0].CLK +clock0 => out_address_reg_a[1].CLK +clock0 => out_address_reg_a[0].CLK +data_a[0] => ram_block1a0.PORTADATAIN +data_a[0] => ram_block1a8.PORTADATAIN +data_a[0] => ram_block1a16.PORTADATAIN +data_a[0] => ram_block1a24.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[1] => ram_block1a9.PORTADATAIN +data_a[1] => ram_block1a17.PORTADATAIN +data_a[1] => ram_block1a25.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[2] => ram_block1a10.PORTADATAIN +data_a[2] => ram_block1a18.PORTADATAIN +data_a[2] => ram_block1a26.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[3] => ram_block1a11.PORTADATAIN +data_a[3] => ram_block1a19.PORTADATAIN +data_a[3] => ram_block1a27.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[4] => ram_block1a12.PORTADATAIN +data_a[4] => ram_block1a20.PORTADATAIN +data_a[4] => ram_block1a28.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[5] => ram_block1a13.PORTADATAIN +data_a[5] => ram_block1a21.PORTADATAIN +data_a[5] => ram_block1a29.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[6] => ram_block1a14.PORTADATAIN +data_a[6] => ram_block1a22.PORTADATAIN +data_a[6] => ram_block1a30.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[7] => ram_block1a15.PORTADATAIN +data_a[7] => ram_block1a23.PORTADATAIN +data_a[7] => ram_block1a31.PORTADATAIN +q_a[0] <= mux_6nb:mux2.result[0] +q_a[1] <= mux_6nb:mux2.result[1] +q_a[2] <= mux_6nb:mux2.result[2] +q_a[3] <= mux_6nb:mux2.result[3] +q_a[4] <= mux_6nb:mux2.result[4] +q_a[5] <= mux_6nb:mux2.result[5] +q_a[6] <= mux_6nb:mux2.result[6] +q_a[7] <= mux_6nb:mux2.result[7] +wren_a => decode_msa:decode3.enable + + +|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3 +data[0] => w_anode223w[1].IN0 +data[0] => w_anode236w[1].IN1 +data[0] => w_anode244w[1].IN0 +data[0] => w_anode252w[1].IN1 +data[1] => w_anode223w[2].IN0 +data[1] => w_anode236w[2].IN0 +data[1] => w_anode244w[2].IN1 +data[1] => w_anode252w[2].IN1 +enable => w_anode223w[1].IN0 +enable => w_anode236w[1].IN0 +enable => w_anode244w[1].IN0 +enable => w_anode252w[1].IN0 +eq[0] <= w_anode223w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= w_anode236w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[2] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[3] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode +data[0] => w_anode261w[1].IN0 +data[0] => w_anode275w[1].IN1 +data[0] => w_anode284w[1].IN0 +data[0] => w_anode293w[1].IN1 +data[1] => w_anode261w[2].IN0 +data[1] => w_anode275w[2].IN0 +data[1] => w_anode284w[2].IN1 +data[1] => w_anode293w[2].IN1 +eq[0] <= w_anode261w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= w_anode275w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[2] <= w_anode284w[2].DB_MAX_OUTPUT_PORT_TYPE +eq[3] <= w_anode293w[2].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 +data[0] => _.IN0 +data[0] => _.IN0 +data[1] => _.IN0 +data[1] => _.IN0 +data[2] => _.IN0 +data[2] => _.IN0 +data[3] => _.IN0 +data[3] => _.IN0 +data[4] => _.IN0 +data[4] => _.IN0 +data[5] => _.IN0 +data[5] => _.IN0 +data[6] => _.IN0 +data[6] => _.IN0 +data[7] => _.IN0 +data[7] => _.IN0 +data[8] => _.IN0 +data[9] => _.IN0 +data[10] => _.IN0 +data[11] => _.IN0 +data[12] => _.IN0 +data[13] => _.IN0 +data[14] => _.IN0 +data[15] => _.IN0 +data[16] => _.IN1 +data[16] => _.IN1 +data[17] => _.IN1 +data[17] => _.IN1 +data[18] => _.IN1 +data[18] => _.IN1 +data[19] => _.IN1 +data[19] => _.IN1 +data[20] => _.IN1 +data[20] => _.IN1 +data[21] => _.IN1 +data[21] => _.IN1 +data[22] => _.IN1 +data[22] => _.IN1 +data[23] => _.IN1 +data[23] => _.IN1 +data[24] => _.IN0 +data[25] => _.IN0 +data[26] => _.IN0 +data[27] => _.IN0 +data[28] => _.IN0 +data[29] => _.IN0 +data[30] => _.IN0 +data[31] => _.IN0 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 + + diff --git a/db/spectrum.hif b/db/spectrum.hif index 36e2c50ce8e4cb96cd73ca36550e8f95894e86fa..9f4b0918b5208650ee18d6888ed5f66c2fcd0473 100644 GIT binary patch literal 3465 zcmV;44R-RZ4*>uG0001Zob6ppbK5u)zO!oogR17Tdx(Pv2@<*KK_}diC66RKlfAG2 z0(7)1%ZVgsCN(qveVY$S5KYRIM^5aRc^M!Zjb?WPV1HmEzubz&>UP-*f)*vOcw(;GjCyff=^JZb32`>7G|V{(Q86q6NG7N{O{I#EnB{tu7K3Su0Rv(wGSFe&g{#=z_ z&sto*>-F>7Q*Ac6d*i2;p0B2>ua=mtmS5-5LR`bOE+QSq)0sB7pR81DxhxixYe!S~WCd>r!;zm;buLa%{n0qJlX)Yh%o~oo z?Vf*^UwV0$V@6rZb4&d`=uO^*$rJg5wuLL6WO(k6+LK^72+xMla5OwCA>6WS@2F%9 z-TJ+-=XbXx?H&-(YNEl#+56$BH{Q=`crodVhmIvSi9F7`D5VM?T>(V zFdX<5lxwE!zgMC9}0LYU`D?AH+1;NgTqsiFnfmV{KwNh{8ERx2_nDpO=sR0JVaM1C?g!%!DI)^X{ z2Eime4f?({(+XCj6)Z*b<;nFlu9%!Q4Z?o=19*&;3t!Iuto>_nc5w!FJD$|li- zDjgIdSh53bgTeVl!m#t-dk^Pvuvb6V`wtD81F2uCSA|J z47z@J+CB^VAFS@zXm&H#t>Cg%waRrnzXsvvmhlD^E^c_)cupGqmAyBCr{2JO;2+lK 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+ram1|altsyncram_component|auto_generated|rden_decode +2 +0 +0 +0 +4 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram1|altsyncram_component|auto_generated|decode3 +3 +0 +0 +0 +4 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram1|altsyncram_component|auto_generated +25 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram1 +25 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + + ram0|altsyncram_component|auto_generated|mux5 17 0 @@ -130,13 +210,13 @@ ram0 47 -21 +10 0 -21 +10 16 -21 -21 -21 +10 +10 +10 0 0 0 diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 06dffbc4dbfa233859c2209f9dd2e2e1c0df54f7..0b06179563a31b3b5e768d33e3f3a12b9478514e 100644 GIT binary patch delta 646 zcmV;10(t$h1%n2VMt_nM00000005E#00000005l;00000000000009600000004La z>{d%_!!QhP_hzu?ai<)&!$u!_omUte47SV8#cNC#Xzh|ZutI^^JL8r z{~Xo^AOm#}>lolktm^=y01u2qcwQnNvv}}5(~`y>Os`^+DD#TZ>PazGOsIg!k3jw@ zk|__V6t$m6lBq}xseB*g?}=Ji#m2O-N;j}gTC-G)`U|^s1JOQ3VHCp*V+k#h6SPEn z2484OffS=zK!0|yWg9n{tsB^i*|3g0j&E2Ii5(tg_^TO$^MWF2&v-Xe4PAr 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""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:07 2022 " "Processing started: Wed Mar 30 13:47:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637227779 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227848 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227850 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227851 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227851 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648637227909 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RamWE spectrum.v(19) " "Verilog HDL or VHDL warning at spectrum.v(19): object \"RamWE\" assigned a value but never read" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1648637227910 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(43) " "Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227911 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(46) " "Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 46 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227912 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 spectrum.v(47) " "Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227912 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227925 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227985 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637227987 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228040 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228040 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228040 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228086 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228086 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228087 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228131 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228131 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228131 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.v" "ram0" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228134 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228138 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637228139 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bui2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bui2 " "Found entity 1: altsyncram_bui2" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228191 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228191 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bui2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated " "Elaborating entity \"altsyncram_bui2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228191 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228237 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_bui2.tdf" "decode2" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228237 ""} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 216 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 256 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 296 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 336 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 376 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 416 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 456 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 496 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 536 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 576 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 616 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 656 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 42 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 64 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 86 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 108 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 218 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 240 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 262 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 284 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1648637228301 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1648637228301 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648637228703 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648637228839 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648637228951 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648637229075 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637229075 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_LCELLS" "50 " "Implemented 50 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Implemented 12 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648637229123 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648637229123 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:09 2022 " "Processing ended: Wed Mar 30 13:47:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641359299 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641359300 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:55:59 2022 " "Processing started: Wed Mar 30 14:55:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641359300 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648641359300 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648641359301 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648641359468 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359535 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359535 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359537 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359538 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/projects/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359539 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359539 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648641359598 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RamWE spectrum.v(18) " "Verilog HDL or VHDL warning at spectrum.v(18): object \"RamWE\" assigned a value but never read" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1648641359599 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(55) " "Verilog HDL assignment warning at spectrum.v(55): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 55 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648641359600 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 spectrum.v(58) " "Verilog HDL assignment warning at spectrum.v(58): truncated value with size 32 to match size of target (16)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 58 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648641359600 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_0\[33..32\] spectrum.v(3) " "Output port \"GPIO_0\[33..32\]\" at spectrum.v(3) has no driver" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 3 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648641359601 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 12 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359613 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359662 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359664 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648641359664 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359712 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359712 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359712 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359754 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359754 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359754 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359796 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359796 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.v" "ram0" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359799 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359803 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359804 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648641359804 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bui2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bui2 " "Found entity 1: altsyncram_bui2" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359852 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bui2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated " "Elaborating entity \"altsyncram_bui2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359852 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359894 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_bui2.tdf" "decode2" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359894 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.v" "ram1" { Text "/home/benny/work/fpga/projects/spectrum.v" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359899 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359903 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/projects/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359904 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/projects/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648641359904 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359952 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359953 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641359994 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641359994 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641359995 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641360036 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641360036 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641360036 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648641360077 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648641360077 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648641360078 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[7\] " "Net \"D\[7\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[7\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[6\] " "Net \"D\[6\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[6\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[5\] " "Net \"D\[5\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[5\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[4\] " "Net \"D\[4\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[4\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[3\] " "Net \"D\[3\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[3\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[2\] " "Net \"D\[2\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[2\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[1\] " "Net \"D\[1\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[1\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[0\] " "Net \"D\[0\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[0\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360108 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[7\] " "Net \"D\[7\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[7\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[6\] " "Net \"D\[6\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[6\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[5\] " "Net \"D\[5\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[5\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[4\] " "Net \"D\[4\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[4\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[3\] " "Net \"D\[3\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[3\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[2\] " "Net \"D\[2\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[2\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[1\] " "Net \"D\[1\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[1\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "D\[0\] " "Net \"D\[0\]\" is missing source, defaulting to GND" { } { { "spectrum.v" "D\[0\]" { Text "/home/benny/work/fpga/projects/spectrum.v" 16 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1648641360109 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648641360565 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_0\[32\] GND " "Pin \"GPIO_0\[32\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648641360598 "|spectrum|GPIO_0[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_0\[33\] GND " "Pin \"GPIO_0\[33\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648641360598 "|spectrum|GPIO_0[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648641360598 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648641360706 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648641360825 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648641360993 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648641360993 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "201 " "Implemented 201 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648641361057 ""} { "Info" "ICUT_CUT_TM_OPINS" "42 " "Implemented 42 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648641361057 ""} { "Info" "ICUT_CUT_TM_LCELLS" "94 " "Implemented 94 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648641361057 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648641361057 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648641361057 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 27 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "395 " "Peak virtual memory: 395 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641361068 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:01 2022 " "Processing ended: Wed Mar 30 14:56:01 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641361068 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641361068 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641361068 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648641361068 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index 1e2c1cedcd14a5c7e9cae5ef56de41cf7940822f..d4d65095ef26051e77ec0dfe1f0a538269e79037 100644 GIT binary patch delta 988 zcmV<210(#S3aAQ@Mt|}N00000000vN00000006N80000000000001Zj00000004La z>{eTE+(Z=i0^(vW;{JdTIs&Pr>Ly+9ZmXtmA*3iMsTMYB#SM=CqWls;m5yb16SXIzaerT#ThqN zG%Na!xfM5oa^+|AI}Ubk7+3iI-~NXY@O^_`@eOyvS4`4VWktbnig@%Vm=9IkX|X!D zv~zfuvi<#RcYiv`W^^De*NhI8MvF2lRFnRsoF->Dsp@TyLn&)YQfOICMpgC&)13TK&+eDP8ag;#EU0DLHeif8(v6aFkYG(m%GuUgs)Xc* zDy?cza9R-zP^C0qDc>#Wj%W($O201o1(2XttCePT?SGFHd=a&iA;75Y?qDNj#;8It z%S$R%;cDL4$O$>oz)BsrJ{10ItGO|-E0lMK#Su{t@Yo$BNVQ{NM-b}&^6@OV;(G0YE$zPYrha2$=p{;|Omw5iT zyu3`l1kX{O^Rk5hr%qad48Yy}UDzTnLple&!MJ}Fqs_(1$rV~)xa9>zu3Rs22fRyH z6ez~ZN!q37-UX&X5=``y64ATz|{pJiEAJc3aJbcErLFq-7dziA> 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z#Rx_$x{G@>xE2!Cl*$#$|0uu(@uX$u#h@7o(Lx_S=YJ4m0Vm7CL5Yr)Gn}RBLV)E~ zH7(_PlvZV!+&_QWITHIsYydM_fB3S2J!zI%leKQ{&ka;XPD-hg`MI%#;_T6byFP&B z*ea-_GIE^nz6c#Rv}%emchk3S zZPu-uv%mSb^vfs)!D)sS4Yw*Ywi{z{9ksBX>H_~&$gyiMq$u5x3FZTucyV$LJcu%N zqrk@?^(qigwiSphr_KGg`SQu<0r~9*pvRp43jhHB|H%I_^#A|> diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index 75e1bec..313dec0 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,42 +1,42 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637241068 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:20 2022 " "Processing started: Wed Mar 30 13:47:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637241070 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648637241098 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637241220 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241222 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648637241477 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648637241477 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648637241608 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241609 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648637241610 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648637241625 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637241637 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637241637 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.812 " "Worst-case setup slack is -1.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.812 -85.179 CLOCK_50 " " -1.812 -85.179 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.480 CLOCK_50 " " -3.000 -119.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637241663 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648637241687 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648637242078 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242100 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242103 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242103 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.531 " "Worst-case setup slack is -1.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.531 -69.352 CLOCK_50 " " -1.531 -69.352 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242107 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242108 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.478 CLOCK_50 " " -3.000 -119.478 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637242132 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242265 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242266 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242266 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.444 " "Worst-case setup slack is -0.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.444 -17.149 CLOCK_50 " " -0.444 -17.149 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242272 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242273 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.404 CLOCK_50 " " -3.000 -99.404 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "419 " "Peak virtual memory: 419 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:22 2022 " "Processing ended: Wed Mar 30 13:47:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648641375310 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 14:56:15 2022 " "Processing started: Wed Mar 30 14:56:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648641375311 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648641375342 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648641375496 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375498 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375542 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648641375542 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648641375787 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648641375787 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375789 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375789 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648641375920 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375920 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648641375921 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648641375946 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641375972 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641375972 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.088 " "Worst-case setup slack is -2.088" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.088 -422.664 CLOCK_50 " " -2.088 -422.664 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375973 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.337 " "Worst-case hold slack is 0.337" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.337 0.000 CLOCK_50 " " 0.337 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375976 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641375977 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641375977 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -532.995 CLOCK_50 " " -3.000 -532.995 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641375978 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648641376009 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648641376034 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648641376496 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376535 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641376543 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641376543 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.813 " "Worst-case setup slack is -1.813" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.813 -354.793 CLOCK_50 " " -1.813 -354.793 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376544 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.312 " "Worst-case hold slack is 0.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 CLOCK_50 " " 0.312 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376548 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376549 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376550 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -532.816 CLOCK_50 " " -3.000 -532.816 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376551 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648641376582 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376739 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648641376742 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648641376742 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.824 " "Worst-case setup slack is -0.824" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.824 -117.237 CLOCK_50 " " -0.824 -117.237 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376744 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.169 " "Worst-case hold slack is 0.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.169 0.000 CLOCK_50 " " 0.169 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376748 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376750 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648641376751 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -347.907 CLOCK_50 " " -3.000 -347.907 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648641376753 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648641377115 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648641377116 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 14:56:17 2022 " "Processing ended: Wed Mar 30 14:56:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648641377180 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index a86674c6653e829faaed15463359cf921b5d30fe..a98fc1f032bcdc8ae88b1cad198bf0bc7b0cb2e6 100644 GIT binary patch literal 28627 zcmaI+bx>T*^T3S)i`znQcMa|m+Y-JJw?2_6XUEbi_EeR+Q0Tes@I zf807%J>4U{ea`gRn)#f;hJu2sL4p2|P*64>7w1Q*W&Yj8+R=fWos)%~g^gU?&Dze4 zoSlb*oSlu8gOinmjh&NRU7lRq{2RHHnYHUjSKmR{|ML*&@P7pqE6o4O|KzOW|8x)N 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@@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 8. Analysis & Synthesis RAM Summary 9. Analysis & Synthesis IP Cores Summary 10. Registers Removed During Synthesis - 11. Removed Registers Triggering Further Register Optimizations - 12. General Register Statistics - 13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated - 14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated + 11. General Register Statistics + 12. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated + 13. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated + 14. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated 15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component - 17. altsyncram Parameter Settings by Entity Instance - 18. Port Connectivity Checks: "ram16:ram0" - 19. Port Connectivity Checks: "rom0:rom" - 20. Elapsed Time Per Partition - 21. Analysis & Synthesis Messages + 17. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component + 18. altsyncram Parameter Settings by Entity Instance + 19. Port Connectivity Checks: "ram32:ram1" + 20. Port Connectivity Checks: "ram16:ram0" + 21. Port Connectivity Checks: "rom0:rom" + 22. Elapsed Time Per Partition + 23. Analysis & Synthesis Messages @@ -52,18 +54,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ; +; Analysis & Synthesis Status ; Successful - Wed Mar 30 14:56:01 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 50 ; -; Total combinational functions ; 48 ; -; Dedicated logic registers ; 38 ; -; Total registers ; 38 ; -; Total pins ; 9 ; +; Total logic elements ; 94 ; +; Total combinational functions ; 90 ; +; Dedicated logic registers ; 41 ; +; Total registers ; 41 ; +; Total pins ; 43 ; ; Total virtual pins ; 0 ; -; Total memory bits ; 98,304 ; +; Total memory bits ; 524,288 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+--------------------------------------------+ @@ -429,6 +431,12 @@ File Type : User Wizard-Generated File File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v Library : +File Name with User-Entered Path : ram32.v +Used in Netlist : yes +File Type : User Wizard-Generated File +File Name with Absolute Path : /home/benny/work/fpga/projects/ram32.v +Library : + File Name with User-Entered Path : altsyncram.tdf Used in Netlist : yes File Type : Megafunction @@ -518,6 +526,30 @@ Used in Netlist : yes File Type : Auto-Generated Megafunction File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf Library : + +File Name with User-Entered Path : db/altsyncram_g9i1.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf +Library : + +File Name with User-Entered Path : db/decode_msa.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_msa.tdf +Library : + +File Name with User-Entered Path : db/decode_f8a.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_f8a.tdf +Library : + +File Name with User-Entered Path : db/mux_6nb.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_6nb.tdf +Library : +--------------------------------------------------------------------------------+ @@ -527,29 +559,29 @@ Library : +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ -; Estimated Total logic elements ; 50 ; +; Estimated Total logic elements ; 94 ; ; ; ; -; Total combinational functions ; 48 ; +; Total combinational functions ; 90 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 7 ; -; -- 3 input functions ; 6 ; -; -- <=2 input functions ; 35 ; +; -- 4 input functions ; 24 ; +; -- 3 input functions ; 26 ; +; -- <=2 input functions ; 40 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 16 ; -; -- arithmetic mode ; 32 ; +; -- normal mode ; 57 ; +; -- arithmetic mode ; 33 ; ; ; ; -; Total registers ; 38 ; -; -- Dedicated logic registers ; 38 ; +; Total registers ; 41 ; +; -- Dedicated logic registers ; 41 ; ; -- I/O registers ; 0 ; ; ; ; -; I/O pins ; 9 ; -; Total memory bits ; 98304 ; +; I/O pins ; 43 ; +; Total memory bits ; 524288 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 50 ; -; Total fan-out ; 401 ; -; Average fan-out ; 3.46 ; +; Maximum fan-out ; 105 ; +; Total fan-out ; 1436 ; +; Average fan-out ; 5.11 ; +---------------------------------------------+----------------+ @@ -557,21 +589,21 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 48 (44) -LC Registers : 38 (36) -Memory Bits : 98304 +LC Combinationals : 90 (46) +LC Registers : 41 (37) +Memory Bits : 524288 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 9 +Pins : 43 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work Compilation Hierarchy Node : |ram16:ram0| -LC Combinationals : 0 (0) +LC Combinationals : 16 (0) LC Registers : 0 (0) -Memory Bits : 32768 +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -581,9 +613,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 0 (0) +LC Combinationals : 16 (0) LC Registers : 0 (0) -Memory Bits : 32768 +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -593,9 +625,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |altsyncram_bui2:auto_generated| -LC Combinationals : 0 (0) +LC Combinationals : 16 (0) LC Registers : 0 (0) -Memory Bits : 32768 +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -604,10 +636,94 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated Library Name : work +Compilation Hierarchy Node : |mux_3nb:mux4| +LC Combinationals : 8 (8) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4 +Library Name : work + +Compilation Hierarchy Node : |mux_3nb:mux5| +LC Combinationals : 8 (8) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5 +Library Name : work + +Compilation Hierarchy Node : |ram32:ram1| +LC Combinationals : 20 (0) +LC Registers : 4 (0) +Memory Bits : 262144 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram32:ram1 +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +LC Combinationals : 20 (0) +LC Registers : 4 (0) +Memory Bits : 262144 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| +LC Combinationals : 20 (0) +LC Registers : 4 (4) +Memory Bits : 262144 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated +Library Name : work + +Compilation Hierarchy Node : |decode_f8a:rden_decode| +LC Combinationals : 4 (4) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode +Library Name : work + +Compilation Hierarchy Node : |mux_6nb:mux2| +LC Combinationals : 16 (16) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 +Library Name : work + Compilation Hierarchy Node : |rom0:rom| -LC Combinationals : 4 (0) -LC Registers : 2 (0) -Memory Bits : 65536 +LC Combinationals : 8 (0) +LC Registers : 0 (0) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -617,9 +733,9 @@ Full Hierarchy Name : |spectrum|rom0:rom Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 4 (0) -LC Registers : 2 (0) -Memory Bits : 65536 +LC Combinationals : 8 (0) +LC Registers : 0 (0) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -629,9 +745,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| -LC Combinationals : 4 (0) -LC Registers : 2 (2) -Memory Bits : 65536 +LC Combinationals : 8 (0) +LC Registers : 0 (0) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -641,7 +757,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |mux_3nb:mux2| -LC Combinationals : 4 (4) +LC Combinationals : 8 (8) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -669,6 +785,16 @@ Port B Width : 8 Size : 131072 MIF : led_patterns.mif +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : Single Port +Port A Depth : 32768 +Port A Width : 8 +Port B Depth : -- +Port B Width : -- +Size : 262144 +MIF : led_patterns.mif + Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Type : AUTO Mode : ROM @@ -693,6 +819,14 @@ License Type : N/A Entity Instance : |spectrum|ram16:ram0 IP Include File : /home/benny/work/fpga/projects/ram16.v +Vendor : Altera +IP Core Name : RAM: 1-PORT +Version : 13.1 +Release Date : N/A +License Type : N/A +Entity Instance : |spectrum|ram32:ram1 +IP Include File : /home/benny/work/fpga/projects/ram32.v + Vendor : Altera IP Core Name : ROM: 1-PORT Version : 13.1 @@ -704,40 +838,20 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+------------------------------------------------------------------------------------------------+----------------------------------------+ -; Register name ; Reason for Removal ; -+------------------------------------------------------------------------------------------------+----------------------------------------+ -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ; -; address[0] ; Merged with A[0] ; -; address[1] ; Merged with A[1] ; -; address[2] ; Merged with A[2] ; -; address[3] ; Merged with A[3] ; -; address[4] ; Merged with A[4] ; -; address[5] ; Merged with A[5] ; -; address[6] ; Merged with A[6] ; -; address[7] ; Merged with A[7] ; -; address[8] ; Merged with A[8] ; -; address[9] ; Merged with A[9] ; -; address[10] ; Merged with A[10] ; -; address[11] ; Merged with A[11] ; -; address[12] ; Merged with A[12] ; -; address[13] ; Merged with A[13] ; -; A[14,15] ; Lost fanout ; -; Total Number of Removed Registers = 18 ; ; -+------------------------------------------------------------------------------------------------+----------------------------------------+ - - -+--------------------------------------------------------------------------------+ -; Removed Registers Triggering Further Register Optimizations ; -+--------------------------------------------------------------------------------+ -Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] -Reason for Removal : Stuck at GNDdue to stuck port data_in -Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] -+--------------------------------------------------------------------------------+ - ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; +; A[15] ; Lost fanout ; +; Total Number of Removed Registers = 7 ; ; ++------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------+ @@ -745,12 +859,12 @@ Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_compon +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 38 ; +; Total registers ; 41 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 13 ; +; Number of registers using Clock Enable ; 14 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -777,6 +891,17 @@ To : - ++--------------------------------------------------------------------------------+ +; Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated ; ++--------------------------------------------------------------------------------+ +Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS +Value : NORMAL_COMPILATION +From : - +To : - ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; +--------------------------------------------------------------------------------+ @@ -1207,12 +1332,227 @@ Type : Untyped Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component ; ++--------------------------------------------------------------------------------+ +Parameter Name : BYTE_SIZE_BLOCK +Value : 8 +Type : Untyped + +Parameter Name : AUTO_CARRY_CHAINS +Value : ON +Type : AUTO_CARRY + +Parameter Name : IGNORE_CARRY_BUFFERS +Value : OFF +Type : IGNORE_CARRY + +Parameter Name : AUTO_CASCADE_CHAINS +Value : ON +Type : AUTO_CASCADE + +Parameter Name : IGNORE_CASCADE_BUFFERS +Value : OFF +Type : IGNORE_CASCADE + +Parameter Name : WIDTH_BYTEENA +Value : 1 +Type : Untyped + +Parameter Name : OPERATION_MODE +Value : SINGLE_PORT +Type : Untyped + +Parameter Name : WIDTH_A +Value : 8 +Type : Signed Integer + +Parameter Name : WIDTHAD_A +Value : 15 +Type : Signed Integer + +Parameter Name : NUMWORDS_A +Value : 32768 +Type : Signed Integer + +Parameter Name : OUTDATA_REG_A +Value : CLOCK0 +Type : Untyped + +Parameter Name : ADDRESS_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : INDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_B +Value : 1 +Type : Untyped + +Parameter Name : WIDTHAD_B +Value : 1 +Type : Untyped + +Parameter Name : NUMWORDS_B +Value : 1 +Type : Untyped + +Parameter Name : INDATA_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : WRCONTROL_WRADDRESS_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : RDCONTROL_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : ADDRESS_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : OUTDATA_REG_B +Value : UNREGISTERED +Type : Untyped + +Parameter Name : BYTEENA_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : INDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : ADDRESS_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : RDCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_BYTEENA_A +Value : 1 +Type : Signed Integer + +Parameter Name : WIDTH_BYTEENA_B +Value : 1 +Type : Untyped + +Parameter Name : RAM_BLOCK_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : BYTE_SIZE +Value : 8 +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS +Value : DONT_CARE +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_A +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_B +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : INIT_FILE +Value : led_patterns.mif +Type : Untyped + +Parameter Name : INIT_FILE_LAYOUT +Value : PORT_A +Type : Untyped + +Parameter Name : MAXIMUM_DEPTH +Value : 0 +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_B +Value : NORMAL +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_B +Value : NORMAL +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_A +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_B +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : ENABLE_ECC +Value : FALSE +Type : Untyped + +Parameter Name : ECC_PIPELINE_STAGE_ENABLED +Value : FALSE +Type : Untyped + +Parameter Name : WIDTH_ECCSTATUS +Value : 3 +Type : Untyped + +Parameter Name : DEVICE_FAMILY +Value : Cyclone IV E +Type : Untyped + +Parameter Name : CBXI_PARAMETER +Value : altsyncram_g9i1 +Type : Untyped ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + +----------------------------------------------------------------------------------------+ ; altsyncram Parameter Settings by Entity Instance ; +-------------------------------------------+--------------------------------------------+ ; Name ; Value ; +-------------------------------------------+--------------------------------------------+ -; Number of entity instances ; 2 ; +; Number of entity instances ; 3 ; ; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; ROM ; ; -- WIDTH_A ; 8 ; @@ -1235,27 +1575,39 @@ Note: In order to hide this table in the UI and the text report file, please set ; -- OUTDATA_REG_B ; CLOCK0 ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; ram32:ram1|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; SINGLE_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 32768 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +-------------------------------------------+--------------------------------------------+ ++--------------------------------------------------------------------------------+ +; Port Connectivity Checks: "ram32:ram1" ; ++--------------------------------------------------------------------------------+ +Port : wren +Type : Input +Severity : Warning +Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. + +Port : wren[-1] +Type : Input +Severity : Info +Details : Stuck at GND ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "ram16:ram0" ; +--------------------------------------------------------------------------------+ -Port : address_a -Type : Input -Severity : Warning -Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. - -Port : address_a[13..3] -Type : Input -Severity : Info -Details : Stuck at GND - -Port : q_a[7..4] -Type : Output -Severity : Info -Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. - Port : wren_a Type : Input Severity : Warning @@ -1271,11 +1623,6 @@ Type : Input Severity : Info Details : Stuck at GND -Port : q_b -Type : Output -Severity : Info -Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. - Port : wren_b Type : Input Severity : Warning @@ -1292,10 +1639,10 @@ Details : Stuck at GND +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "rom0:rom" ; +--------------------------------------------------------------------------------+ -Port : q[3..0] -Type : Output -Severity : Info -Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. +Port : address +Type : Input +Severity : Warning +Details : Input port expression (16 bits) is wider than the input port (14 bits) it drives. The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts. +--------------------------------------------------------------------------------+ @@ -1315,7 +1662,7 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:47:07 2022 + Info: Processing started: Wed Mar 30 14:55:59 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v @@ -1324,11 +1671,13 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom0.v Info (12023): Found entity 1: rom0 Info (12021): Found 1 design units, including 1 entities, in source file ram16.v Info (12023): Found entity 1: ram16 +Info (12021): Found 1 design units, including 1 entities, in source file ram32.v + Info (12023): Found entity 1: ram32 Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22) -Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16) +Warning (10036): Verilog HDL or VHDL warning at spectrum.v(18): object "RamWE" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at spectrum.v(55): truncated value with size 32 to match size of target (22) +Warning (10230): Verilog HDL assignment warning at spectrum.v(58): truncated value with size 32 to match size of target (16) +Warning (10034): Output port "GPIO_0[33..32]" at spectrum.v(3) has no driver Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" @@ -1393,41 +1742,71 @@ Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|alt Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf Info (12023): Found entity 1: decode_jsa Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2" -Warning (14284): Synthesized away the following node(s): - Warning (14285): Synthesized away the following RAM node(s): - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14" - Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10" - Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11" -Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Info (12128): Elaborating entity "ram32" for hierarchy "ram32:ram1" +Info (12128): Elaborating entity "altsyncram" for hierarchy "ram32:ram1|altsyncram:altsyncram_component" +Info (12130): Elaborated megafunction instantiation "ram32:ram1|altsyncram:altsyncram_component" +Info (12133): Instantiated megafunction "ram32:ram1|altsyncram:altsyncram_component" with the following parameter: + Info (12134): Parameter "clock_enable_input_a" = "BYPASS" + Info (12134): Parameter "clock_enable_output_a" = "BYPASS" + Info (12134): Parameter "init_file" = "led_patterns.mif" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "32768" + Info (12134): Parameter "operation_mode" = "SINGLE_PORT" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "CLOCK0" + Info (12134): Parameter "power_up_uninitialized" = "FALSE" + Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" + Info (12134): Parameter "widthad_a" = "15" + Info (12134): Parameter "width_a" = "8" + Info (12134): Parameter "width_byteena_a" = "1" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf + Info (12023): Found entity 1: altsyncram_g9i1 +Info (12128): Elaborating entity "altsyncram_g9i1" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf + Info (12023): Found entity 1: decode_msa +Info (12128): Elaborating entity "decode_msa" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3" +Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf + Info (12023): Found entity 1: decode_f8a +Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode" +Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf + Info (12023): Found entity 1: mux_6nb +Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2" +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "D[7]" is missing source, defaulting to GND + Warning (12110): Net "D[6]" is missing source, defaulting to GND + Warning (12110): Net "D[5]" is missing source, defaulting to GND + Warning (12110): Net "D[4]" is missing source, defaulting to GND + Warning (12110): Net "D[3]" is missing source, defaulting to GND + Warning (12110): Net "D[2]" is missing source, defaulting to GND + Warning (12110): Net "D[1]" is missing source, defaulting to GND + Warning (12110): Net "D[0]" is missing source, defaulting to GND +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "D[7]" is missing source, defaulting to GND + Warning (12110): Net "D[6]" is missing source, defaulting to GND + Warning (12110): Net "D[5]" is missing source, defaulting to GND + Warning (12110): Net "D[4]" is missing source, defaulting to GND + Warning (12110): Net "D[3]" is missing source, defaulting to GND + Warning (12110): Net "D[2]" is missing source, defaulting to GND + Warning (12110): Net "D[1]" is missing source, defaulting to GND + Warning (12110): Net "D[0]" is missing source, defaulting to GND +Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "GPIO_0[32]" is stuck at GND + Warning (13410): Pin "GPIO_0[33]" is stuck at GND Info (286030): Timing-Driven Synthesis is running -Info (17049): 2 registers lost all their fanouts during netlist optimizations. +Info (17049): 1 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 201 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1 input pins - Info (21059): Implemented 8 output pins - Info (21061): Implemented 50 logic cells - Info (21064): Implemented 12 RAM segments -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings - Info: Peak virtual memory: 388 megabytes - Info: Processing ended: Wed Mar 30 13:47:09 2022 + Info (21059): Implemented 42 output pins + Info (21061): Implemented 94 logic cells + Info (21064): Implemented 64 RAM segments +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 27 warnings + Info: Peak virtual memory: 395 megabytes + Info: Processing ended: Wed Mar 30 14:56:01 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 6e13905..1497c8b 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Wed Mar 30 13:47:09 2022 +Analysis & Synthesis Status : Successful - Wed Mar 30 14:56:01 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 50 - Total combinational functions : 48 - Dedicated logic registers : 38 -Total registers : 38 -Total pins : 9 +Total logic elements : 94 + Total combinational functions : 90 + Dedicated logic registers : 41 +Total registers : 41 +Total pins : 43 Total virtual pins : 0 -Total memory bits : 98,304 +Total memory bits : 524,288 Embedded Multiplier 9-bit elements : 0 Total PLLs : 0 diff --git a/output_files/spectrum.pin b/output_files/spectrum.pin index 1fac090..4171e7c 100644 --- a/output_files/spectrum.pin +++ b/output_files/spectrum.pin @@ -33,7 +33,7 @@ -- Bank 5: 2.5V -- Bank 6: 2.5V -- Bank 7: 3.3V - -- Bank 8: 2.5V + -- Bank 8: 3.3V -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. -- It can also be used to report unused dedicated pins. The connection -- on the board for unused dedicated pins depends on whether this will @@ -68,49 +68,49 @@ CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- -VCCIO8 : A1 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +VCCIO8 : A1 : power : : 3.3V : 8 : +GPIO_0[2] : A2 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[3] : A3 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[6] : A4 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[8] : A5 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[11] : A6 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[14] : A7 : output : 3.3-V LVTTL : : 8 : Y GND+ : A8 : : : : 8 : GND+ : A9 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +GPIO_0[30] : A12 : output : 3.3-V LVTTL : : 7 : Y LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y VCCIO7 : A16 : power : : 3.3V : 7 : LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y GND : B2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +GPIO_0[4] : B3 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[5] : B4 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[7] : B5 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[10] : B6 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[12] : B7 : output : 3.3-V LVTTL : : 8 : Y GND+ : B8 : : : : 8 : GND+ : B9 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GPIO_0[29] : B11 : output : 3.3-V LVTTL : : 7 : Y +GPIO_0[33] : B12 : output : 3.3-V LVTTL : : 7 : Y LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : GND : B15 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : -VCCIO8 : C4 : power : : 2.5V : 8 : +GPIO_0[1] : C3 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : C4 : power : : 3.3V : 8 : GND : C5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : -VCCIO8 : C7 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +GPIO_0[15] : C6 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : C7 : power : : 3.3V : 8 : +GPIO_0[16] : C8 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[24] : C9 : output : 3.3-V LVTTL : : 7 : Y VCCIO7 : C10 : power : : 3.3V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +GPIO_0[28] : C11 : output : 3.3-V LVTTL : : 7 : Y GND : C12 : gnd : : : : VCCIO7 : C13 : power : : 3.3V : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : @@ -118,16 +118,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +GPIO_0[0] : D3 : output : 3.3-V LVTTL : : 8 : Y VCCD_PLL3 : D4 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GPIO_0[9] : D5 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[13] : D6 : output : 3.3-V LVTTL : : 8 : Y GND : D7 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 : +GPIO_0[19] : D8 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[25] : D9 : output : 3.3-V LVTTL : : 7 : Y GND : D10 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +GPIO_0[31] : D11 : output : 3.3-V LVTTL : : 7 : Y +GPIO_0[32] : D12 : output : 3.3-V LVTTL : : 7 : Y VCCD_PLL2 : D13 : power : : 1.2V : : RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : @@ -137,12 +137,12 @@ GND : E2 : gnd : : VCCIO1 : E3 : power : : 3.3V : 1 : GND : E4 : gnd : : : : GNDA3 : E5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +GPIO_0[17] : E6 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[18] : E7 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[20] : E8 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[23] : E9 : output : 3.3-V LVTTL : : 7 : Y +GPIO_0[27] : E10 : output : 3.3-V LVTTL : : 7 : Y +GPIO_0[26] : E11 : output : 3.3-V LVTTL : : 7 : Y GNDA2 : E12 : gnd : : : : GND : E13 : gnd : : : : VCCIO6 : E14 : power : : 2.5V : 6 : @@ -155,8 +155,8 @@ nSTATUS : F4 : : : VCCA3 : F5 : power : : 2.5V : : GND : F6 : gnd : : : : VCCINT : F7 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 : +GPIO_0[21] : F8 : output : 3.3-V LVTTL : : 8 : Y +GPIO_0[22] : F9 : output : 3.3-V LVTTL : : 7 : Y GND : F10 : gnd : : : : VCCINT : F11 : power : : 1.2V : : VCCA2 : F12 : power : : 2.5V : : diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 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z{lAkeL(?fc%%jk9Vx7n83L!gw^Ifh9^1YlOO#cs(2^vV)qj874k2MN7^s&YsOnWrW zu=`_;7i8|iQ$=MT*UuWWN@!ze<=UC;*{{sR1hxh;h diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 74f236f..33fb427 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Wed Mar 30 13:47:22 2022 +Wed Mar 30 14:56:17 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -133,7 +133,7 @@ Targets : { CLOCK_50 } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 355.62 MHz +Fmax : 323.83 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -152,8 +152,8 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.812 -End Point TNS : -85.179 +Slack : -2.088 +End Point TNS : -422.664 +--------------------------------------------------------------------------------+ @@ -162,7 +162,7 @@ End Point TNS : -85.179 ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.343 +Slack : 0.337 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -185,7 +185,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -119.480 +End Point TNS : -532.995 +--------------------------------------------------------------------------------+ @@ -193,905 +193,905 @@ End Point TNS : -119.480 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.812 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -2.088 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.125 -Data Delay : 2.616 +Clock Skew : 0.238 +Data Delay : 3.354 -Slack : -1.811 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Slack : -2.086 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.124 -Data Delay : 2.616 +Clock Skew : 0.243 +Data Delay : 3.357 -Slack : -1.811 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Slack : -2.081 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.124 -Data Delay : 2.616 +Clock Skew : 0.262 +Data Delay : 3.371 -Slack : -1.811 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Slack : -2.079 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.124 -Data Delay : 2.616 +Clock Skew : 0.267 +Data Delay : 3.374 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Slack : -2.079 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.236 +Data Delay : 3.343 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Slack : -2.077 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.241 +Data Delay : 3.346 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Slack : -2.073 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.246 +Data Delay : 3.347 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Slack : -2.071 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.251 +Data Delay : 3.350 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Slack : -2.039 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.237 +Data Delay : 3.304 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Slack : -2.037 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.242 +Data Delay : 3.307 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Slack : -1.961 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.237 +Data Delay : 3.226 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Slack : -1.959 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 +Clock Skew : 0.242 +Data Delay : 3.229 -Slack : -1.506 -From Node : counter[2] -To Node : counter[19] +Slack : -1.951 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.438 +Clock Skew : 0.237 +Data Delay : 3.216 -Slack : -1.501 -From Node : counter[15] -To Node : A[13] +Slack : -1.949 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 +Clock Skew : 0.242 +Data Delay : 3.219 -Slack : -1.501 -From Node : counter[15] -To Node : A[12] +Slack : -1.924 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 +Clock Skew : -0.120 +Data Delay : 2.832 -Slack : -1.501 -From Node : counter[15] -To Node : A[11] +Slack : -1.917 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 +Clock Skew : -0.118 +Data Delay : 2.827 -Slack : -1.501 -From Node : counter[15] -To Node : A[10] +Slack : -1.908 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 +Clock Skew : -0.118 +Data Delay : 2.818 -Slack : -1.501 -From Node : counter[15] -To Node : A[9] +Slack : -1.907 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 +Clock Skew : -0.117 +Data Delay : 2.818 -Slack : -1.501 -From Node : counter[15] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.501 -From Node : counter[15] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.786 - -Slack : -1.499 -From Node : counter[14] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.499 -From Node : counter[14] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.290 -Data Delay : 2.784 - -Slack : -1.455 +Slack : -1.881 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.139 -Data Delay : 2.344 +Clock Skew : 0.244 +Data Delay : 3.153 -Slack : -1.436 -From Node : A[0] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 2.354 - -Slack : -1.428 -From Node : counter[1] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.360 - -Slack : -1.424 +Slack : -1.880 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.138 -Data Delay : 2.314 +Clock Skew : 0.243 +Data Delay : 3.151 -Slack : -1.423 +Slack : -1.879 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.141 -Data Delay : 2.310 +Clock Skew : 0.249 +Data Delay : 3.156 -Slack : -1.423 -From Node : counter[0] -To Node : counter[19] +Slack : -1.878 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.355 +Clock Skew : 0.248 +Data Delay : 3.154 -Slack : -1.418 -From Node : A[0] -To Node : A[12] +Slack : -1.877 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 2.336 +Clock Skew : 0.249 +Data Delay : 3.154 -Slack : -1.406 +Slack : -1.876 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.248 +Data Delay : 3.152 + +Slack : -1.875 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.254 +Data Delay : 3.157 + +Slack : -1.874 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.253 +Data Delay : 3.155 + +Slack : -1.871 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.142 -Data Delay : 2.292 +Clock Skew : 0.247 +Data Delay : 3.146 -Slack : -1.401 -From Node : counter[1] +Slack : -1.861 +From Node : counter[14] +To Node : A[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.064 +Data Delay : 2.792 + +Slack : -1.861 +From Node : counter[14] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 +Clock Skew : -0.064 +Data Delay : 2.792 -Slack : -1.401 -From Node : counter[1] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] +Slack : -1.861 +From Node : counter[14] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 +Clock Skew : -0.064 +Data Delay : 2.792 -Slack : -1.401 -From Node : counter[1] -To Node : A[3] +Slack : -1.856 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 +Clock Skew : 0.233 +Data Delay : 3.117 -Slack : -1.401 -From Node : counter[1] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.401 -From Node : counter[1] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.685 - -Slack : -1.399 +Slack : -1.855 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.137 -Data Delay : 2.290 +Clock Skew : 0.248 +Data Delay : 3.131 -Slack : -1.394 -From Node : counter[0] +Slack : -1.854 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.238 +Data Delay : 3.120 + +Slack : -1.854 +From Node : counter[15] +To Node : A[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.064 +Data Delay : 2.785 + +Slack : -1.854 +From Node : counter[15] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 +Clock Skew : -0.064 +Data Delay : 2.785 -Slack : -1.394 -From Node : counter[0] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 - -Slack : -1.394 -From Node : counter[0] +Slack : -1.854 +From Node : counter[15] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 +Clock Skew : -0.064 +Data Delay : 2.785 -Slack : -1.394 -From Node : counter[0] -To Node : A[3] +Slack : -1.844 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 +Clock Skew : 0.262 +Data Delay : 3.134 -Slack : -1.394 -From Node : counter[0] -To Node : A[2] +Slack : -1.842 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 +Clock Skew : 0.267 +Data Delay : 3.137 -Slack : -1.394 -From Node : counter[0] -To Node : A[1] +Slack : -1.833 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.678 +Clock Skew : 0.238 +Data Delay : 3.099 -Slack : -1.391 -From Node : counter[4] -To Node : counter[19] +Slack : -1.831 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.323 +Clock Skew : 0.235 +Data Delay : 3.094 -Slack : -1.390 -From Node : counter[2] -To Node : counter[17] +Slack : -1.831 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.322 +Clock Skew : 0.243 +Data Delay : 3.102 -Slack : -1.385 -From Node : counter[0] -To Node : counter[18] +Slack : -1.829 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.317 +Clock Skew : 0.240 +Data Delay : 3.097 -Slack : -1.384 -From Node : counter[2] -To Node : counter[18] +Slack : -1.827 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.316 +Clock Skew : 0.261 +Data Delay : 3.116 -Slack : -1.382 +Slack : -1.826 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.230 +Data Delay : 3.084 + +Slack : -1.825 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.266 +Data Delay : 3.119 + +Slack : -1.824 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.235 +Data Delay : 3.087 + +Slack : -1.816 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.123 +Data Delay : 2.721 + +Slack : -1.815 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.122 +Data Delay : 2.721 + +Slack : -1.804 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.232 +Data Delay : 3.064 + +Slack : -1.802 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.237 +Data Delay : 3.067 + +Slack : -1.799 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 3.089 + +Slack : -1.797 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.267 +Data Delay : 3.092 + +Slack : -1.795 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.246 +Data Delay : 3.069 + +Slack : -1.795 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.120 +Data Delay : 2.703 + +Slack : -1.794 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.232 +Data Delay : 3.054 + +Slack : -1.794 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.082 + +Slack : -1.793 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.125 +Data Delay : 2.696 + +Slack : -1.792 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.237 +Data Delay : 3.057 + +Slack : -1.792 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.265 +Data Delay : 3.085 + +Slack : -1.791 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.246 +Data Delay : 3.065 + +Slack : -1.790 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.123 +Data Delay : 2.695 + +Slack : -1.789 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.227 +Data Delay : 3.044 + +Slack : -1.789 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.122 +Data Delay : 2.695 + +Slack : -1.789 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.251 +Data Delay : 3.068 + +Slack : -1.789 From Node : counter[1] -To Node : counter[18] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.314 +Clock Skew : -0.062 +Data Delay : 2.722 -Slack : -1.369 -From Node : counter[21] +Slack : -1.789 +From Node : counter[1] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 +Clock Skew : -0.062 +Data Delay : 2.722 -Slack : -1.369 -From Node : counter[21] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 - -Slack : -1.369 -From Node : counter[21] +Slack : -1.789 +From Node : counter[1] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 +Clock Skew : -0.062 +Data Delay : 2.722 -Slack : -1.369 -From Node : counter[21] -To Node : A[3] +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 +Clock Skew : -0.067 +Data Delay : 2.650 -Slack : -1.369 -From Node : counter[21] -To Node : A[2] +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 +Clock Skew : -0.067 +Data Delay : 2.650 -Slack : -1.369 -From Node : counter[21] -To Node : A[1] +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 2.288 +Clock Skew : -0.067 +Data Delay : 2.650 -Slack : -1.367 -From Node : counter[6] +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.788 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.650 + +Slack : -1.787 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.232 +Data Delay : 3.047 + +Slack : -1.786 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.245 +Data Delay : 3.059 + +Slack : -1.784 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.250 +Data Delay : 3.062 + +Slack : -1.783 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.128 +Data Delay : 2.683 + +Slack : -1.783 +From Node : counter[0] +To Node : A[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.716 + +Slack : -1.783 +From Node : counter[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.062 +Data Delay : 2.716 -Slack : -1.367 -From Node : counter[6] -To Node : A[12] +Slack : -1.783 +From Node : counter[0] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.062 +Data Delay : 2.716 -Slack : -1.367 -From Node : counter[6] -To Node : A[11] +Slack : -1.780 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.123 +Data Delay : 2.685 -Slack : -1.367 -From Node : counter[6] -To Node : A[10] +Slack : -1.779 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.125 +Data Delay : 2.682 -Slack : -1.367 -From Node : counter[6] -To Node : A[9] +Slack : -1.779 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.122 +Data Delay : 2.685 -Slack : -1.367 -From Node : counter[6] -To Node : A[8] +Slack : -1.778 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : 0.233 +Data Delay : 3.039 -Slack : -1.367 -From Node : counter[6] -To Node : A[7] +Slack : -1.777 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : -0.120 +Data Delay : 2.685 -Slack : -1.367 -From Node : counter[6] -To Node : A[6] +Slack : -1.776 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.651 +Clock Skew : 0.238 +Data Delay : 3.042 + +Slack : -1.774 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.117 +Data Delay : 2.685 + +Slack : -1.774 +From Node : A[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.118 +Data Delay : 2.684 + +Slack : -1.773 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.116 +Data Delay : 2.685 + +Slack : -1.772 +From Node : A[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.119 +Data Delay : 2.681 +--------------------------------------------------------------------------------+ @@ -1099,114 +1099,105 @@ Data Delay : 2.651 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.343 +Slack : 0.337 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.901 + +Slack : 0.358 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.360 +Slack : 0.361 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.580 -Slack : 0.375 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] +Slack : 0.366 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.594 +Clock Skew : 0.375 +Data Delay : 0.928 -Slack : 0.376 +Slack : 0.371 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.591 + +Slack : 0.391 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.062 Data Delay : 0.610 -Slack : 0.394 -From Node : A[13] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.628 - -Slack : 0.484 -From Node : counter[19] -To Node : counter[20] +Slack : 0.392 +From Node : A[0] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.069 +Data Delay : 0.977 -Slack : 0.486 -From Node : counter[19] -To Node : counter[21] +Slack : 0.429 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.071 +Data Delay : 1.014 -Slack : 0.554 +Slack : 0.478 From Node : A[4] -To Node : A[4] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.788 +Clock Skew : 0.428 +Data Delay : 1.063 -Slack : 0.555 +Slack : 0.556 From Node : A[12] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 0.789 -Slack : 0.555 -From Node : A[6] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.789 - -Slack : 0.555 +Slack : 0.556 From Node : A[2] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 0.789 -Slack : 0.556 -From Node : A[7] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.790 - Slack : 0.556 From Node : counter[14] To Node : counter[14] @@ -1217,40 +1208,40 @@ Clock Skew : 0.062 Data Delay : 0.775 Slack : 0.556 +From Node : counter[10] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.775 + +Slack : 0.556 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.775 + +Slack : 0.557 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.776 - -Slack : 0.557 -From Node : A[10] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.791 - -Slack : 0.557 -From Node : counter[12] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.776 Slack : 0.558 -From Node : A[3] -To Node : A[3] +From Node : A[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.792 +Clock Skew : 0.076 +Data Delay : 0.791 Slack : 0.558 From Node : counter[16] @@ -1261,23 +1252,14 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.777 -Slack : 0.558 -From Node : counter[20] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.792 - Slack : 0.559 -From Node : A[5] -To Node : A[5] +From Node : A[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.793 +Clock Skew : 0.076 +Data Delay : 0.792 Slack : 0.559 From Node : counter[17] @@ -1294,45 +1276,27 @@ To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.779 +Clock Skew : 0.062 +Data Delay : 0.778 -Slack : 0.559 +Slack : 0.560 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.779 -Slack : 0.560 -From Node : A[11] -To Node : A[11] +Slack : 0.561 +From Node : A[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 0.794 -Slack : 0.560 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.780 - -Slack : 0.560 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.780 - Slack : 0.561 From Node : counter[18] To Node : counter[18] @@ -1342,6 +1306,42 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.780 +Slack : 0.561 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : counter[9] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + Slack : 0.563 From Node : counter[19] To Node : counter[19] @@ -1351,51 +1351,24 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.782 -Slack : 0.567 -From Node : counter[10] -To Node : counter[10] +Slack : 0.569 +From Node : A[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.787 +Clock Skew : 0.062 +Data Delay : 0.788 -Slack : 0.567 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.787 - -Slack : 0.570 +Slack : 0.571 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.790 -Slack : 0.571 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.791 - -Slack : 0.571 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.791 - Slack : 0.572 From Node : counter[11] To Node : counter[11] @@ -1406,130 +1379,292 @@ Clock Skew : 0.062 Data Delay : 0.791 Slack : 0.572 -From Node : counter[7] -To Node : counter[7] +From Node : counter[1] +To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.573 +From Node : counter[20] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 Data Delay : 0.792 -Slack : 0.579 -From Node : A[9] -To Node : A[9] +Slack : 0.574 +From Node : counter[5] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.813 +Clock Skew : 0.062 +Data Delay : 0.793 -Slack : 0.579 -From Node : counter[18] -To Node : counter[20] +Slack : 0.575 +From Node : A[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.164 +Clock Skew : 0.076 +Data Delay : 0.808 -Slack : 0.581 -From Node : counter[18] -To Node : counter[21] +Slack : 0.576 +From Node : A[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.166 +Clock Skew : 0.076 +Data Delay : 0.809 -Slack : 0.593 -From Node : counter[17] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.178 - -Slack : 0.595 -From Node : counter[17] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.180 - -Slack : 0.603 -From Node : A[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.026 -Data Delay : 0.816 - -Slack : 0.604 -From Node : A[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.026 -Data Delay : 0.817 - -Slack : 0.681 -From Node : A[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.831 - -Slack : 0.685 -From Node : A[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.835 - -Slack : 0.687 +Slack : 0.577 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.921 +Clock Skew : 0.076 +Data Delay : 0.810 -Slack : 0.689 -From Node : counter[16] -To Node : counter[20] +Slack : 0.579 +From Node : A[5] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.812 + +Slack : 0.580 +From Node : A[11] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.813 + +Slack : 0.588 +From Node : A[4] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.274 +Data Delay : 1.173 -Slack : 0.691 -From Node : counter[16] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.276 - -Slack : 0.703 -From Node : counter[15] -To Node : counter[15] +Slack : 0.589 +From Node : A[14] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.922 +Data Delay : 0.808 + +Slack : 0.590 +From Node : A[4] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.175 + +Slack : 0.593 +From Node : A[13] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.812 + +Slack : 0.614 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.185 + +Slack : 0.616 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.379 +Data Delay : 1.182 + +Slack : 0.624 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.383 +Data Delay : 1.194 + +Slack : 0.633 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.197 + +Slack : 0.636 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.383 +Data Delay : 1.206 + +Slack : 0.638 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.381 +Data Delay : 1.206 + +Slack : 0.639 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.381 +Data Delay : 1.207 + +Slack : 0.640 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.379 +Data Delay : 1.206 + +Slack : 0.640 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.204 + +Slack : 0.649 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.379 +Data Delay : 1.215 + +Slack : 0.649 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.381 +Data Delay : 1.217 + +Slack : 0.649 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.383 +Data Delay : 1.219 + +Slack : 0.658 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.381 +Data Delay : 1.226 + +Slack : 0.664 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.375 +Data Delay : 1.226 + +Slack : 0.670 +From Node : A[0] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.255 + +Slack : 0.672 +From Node : A[0] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.257 + +Slack : 0.687 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 0.899 + +Slack : 0.697 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.023 +Data Delay : 0.907 + +Slack : 0.700 +From Node : A[4] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.285 + +Slack : 0.702 +From Node : A[4] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.287 Slack : 0.703 From Node : counter[13] @@ -1540,159 +1675,159 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.922 -Slack : 0.717 -From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 0.705 +From Node : A[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.026 -Data Delay : 0.930 +Clock Skew : 0.025 +Data Delay : 0.917 + +Slack : 0.708 +From Node : A[8] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 0.920 + +Slack : 0.710 +From Node : A[7] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 0.922 + +Slack : 0.712 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.931 Slack : 0.721 -From Node : A[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +From Node : A[9] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.026 -Data Delay : 0.934 +Clock Skew : 0.025 +Data Delay : 0.933 -Slack : 0.742 -From Node : A[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Slack : 0.727 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.892 +Clock Skew : -0.290 +Data Delay : 0.594 -Slack : 0.746 +Slack : 0.736 +From Node : A[10] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 0.948 + +Slack : 0.752 +From Node : A[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 0.964 + +Slack : 0.752 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.980 +Clock Skew : 0.076 +Data Delay : 0.985 -Slack : 0.753 +Slack : 0.755 From Node : A[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.903 - -Slack : 0.754 -From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.904 - -Slack : 0.767 -From Node : A[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.917 - -Slack : 0.779 -From Node : A[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.929 +Clock Skew : 0.025 +Data Delay : 0.967 Slack : 0.784 -From Node : A[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.037 -Data Delay : 0.934 - -Slack : 0.799 -From Node : counter[14] -To Node : counter[20] +From Node : A[0] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.384 +Data Delay : 1.369 -Slack : 0.801 -From Node : counter[14] -To Node : counter[21] +Slack : 0.806 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.377 + +Slack : 0.809 +From Node : A[5] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.025 +Data Delay : 1.021 + +Slack : 0.812 +From Node : A[4] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.386 +Data Delay : 1.397 + +Slack : 0.814 +From Node : A[4] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.399 Slack : 0.829 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.050 + +Slack : 0.830 From Node : A[2] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 1.063 -Slack : 0.829 -From Node : A[4] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.063 - -Slack : 0.830 -From Node : A[12] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.064 - -Slack : 0.830 -From Node : A[6] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.064 - -Slack : 0.831 -From Node : A[10] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.065 - -Slack : 0.831 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.051 - Slack : 0.831 From Node : counter[14] To Node : counter[15] @@ -1703,8 +1838,8 @@ Clock Skew : 0.062 Data Delay : 1.050 Slack : 0.831 -From Node : counter[12] -To Node : counter[13] +From Node : counter[8] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -1712,13 +1847,22 @@ Clock Skew : 0.062 Data Delay : 1.050 Slack : 0.832 -From Node : counter[20] -To Node : counter[21] +From Node : counter[6] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.066 +Clock Skew : 0.062 +Data Delay : 1.051 + +Slack : 0.832 +From Node : A[10] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 1.065 Slack : 0.833 From Node : counter[16] @@ -1735,16 +1879,16 @@ To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.053 +Clock Skew : 0.062 +Data Delay : 1.052 -Slack : 0.833 +Slack : 0.834 From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 1.053 Slack : 0.835 @@ -1756,95 +1900,23 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.054 -Slack : 0.842 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.062 - -Slack : 0.843 -From Node : counter[10] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.062 - -Slack : 0.844 -From Node : A[7] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.078 - -Slack : 0.845 -From Node : A[3] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.079 - -Slack : 0.845 +Slack : 0.846 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 1.065 -Slack : 0.846 -From Node : A[5] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.080 - -Slack : 0.846 -From Node : A[7] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.080 - Slack : 0.847 -From Node : A[11] -To Node : A[12] +From Node : counter[20] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.081 - -Slack : 0.847 -From Node : counter[5] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.067 - -Slack : 0.847 -From Node : counter[3] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.067 +Clock Skew : 0.062 +Data Delay : 1.066 Slack : 0.847 From Node : counter[17] @@ -1855,149 +1927,77 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.066 -Slack : 0.847 -From Node : A[3] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.081 - -Slack : 0.847 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.067 - Slack : 0.848 -From Node : A[5] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.082 - -Slack : 0.848 -From Node : counter[0] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.068 - -Slack : 0.849 -From Node : counter[15] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.434 - -Slack : 0.849 -From Node : A[11] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.083 - -Slack : 0.849 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.069 - -Slack : 0.849 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.069 - -Slack : 0.849 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.068 - -Slack : 0.850 -From Node : counter[0] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.070 - -Slack : 0.851 -From Node : counter[15] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.436 - -Slack : 0.858 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.078 - -Slack : 0.859 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.078 +Data Delay : 1.067 -Slack : 0.859 +Slack : 0.848 From Node : counter[7] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.079 +Clock Skew : 0.062 +Data Delay : 1.067 -Slack : 0.861 -From Node : counter[11] -To Node : counter[13] +Slack : 0.848 +From Node : counter[15] +To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.080 +Data Delay : 1.067 -Slack : 0.861 -From Node : counter[7] -To Node : counter[9] +Slack : 0.848 +From Node : counter[3] +To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 +Data Delay : 1.067 + +Slack : 0.848 +From Node : A[3] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.076 Data Delay : 1.081 + +Slack : 0.848 +From Node : A[9] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 1.081 + +Slack : 0.848 +From Node : counter[9] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.069 + +Slack : 0.848 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.067 +--------------------------------------------------------------------------------+ @@ -2021,6 +2021,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -2061,6 +2069,302 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -2101,6 +2405,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -2141,6 +2453,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -2179,7 +2499,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4 Slack : -2.174 Actual Width : 1.000 @@ -2187,7 +2507,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -2195,7 +2515,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2203,7 +2523,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2211,7 +2531,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2219,7 +2539,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2227,7 +2547,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5 Slack : -2.174 Actual Width : 1.000 @@ -2235,7 +2555,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -2243,7 +2563,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2251,7 +2571,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2259,7 +2579,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2267,7 +2587,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2275,7 +2595,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6 Slack : -2.174 Actual Width : 1.000 @@ -2283,7 +2603,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -2291,7 +2611,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2299,511 +2619,191 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[0] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[10] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[11] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[12] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[13] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[1] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[2] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[3] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[4] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[5] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[6] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[7] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[8] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[9] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[0] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[10] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[11] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[12] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[14] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[15] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[16] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : -0.009 -Actual Width : 0.221 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : -0.009 -Actual Width : 0.221 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 0.000 -Actual Width : 0.230 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +--------------------------------------------------------------------------------+ @@ -2811,66 +2811,297 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 10.136 +Fall : 10.163 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 9.364 +Fall : 9.344 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 9.457 +Fall : 9.363 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 8.758 +Fall : 8.675 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 9.190 +Fall : 9.237 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 9.262 +Fall : 9.197 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 9.193 +Fall : 9.075 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 8.870 +Fall : 8.811 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 9.462 +Fall : 9.314 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 8.169 +Fall : 8.165 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 7.769 +Fall : 7.723 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 8.654 +Fall : 8.577 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 7.536 +Fall : 7.508 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 9.266 +Fall : 9.145 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 7.532 +Fall : 7.515 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 8.347 +Fall : 8.356 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 9.800 +Fall : 9.526 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 10.073 +Fall : 10.080 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 10.136 +Fall : 10.163 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 9.933 +Fall : 9.935 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 9.469 +Fall : 9.489 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 9.418 +Fall : 9.420 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 9.271 +Fall : 9.281 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 9.411 +Fall : 9.307 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 9.604 +Fall : 9.643 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 7.405 +Fall : 7.367 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 7.174 +Fall : 7.027 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 8.081 +Fall : 8.029 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 7.404 +Fall : 7.279 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 9.871 +Fall : 9.494 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 7.266 +Fall : 7.220 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 8.783 +Fall : 8.703 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 7.984 +Fall : 7.960 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 10.303 -Fall : 10.097 +Rise : 9.877 +Fall : 9.916 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 7.474 -Fall : 7.437 +Rise : 9.020 +Fall : 9.001 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.915 -Fall : 7.923 +Rise : 9.877 +Fall : 9.812 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.907 -Fall : 7.878 +Rise : 9.257 +Fall : 9.204 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 7.123 -Fall : 7.073 +Rise : 9.751 +Fall : 9.916 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 8.891 -Fall : 8.893 +Rise : 9.463 +Fall : 9.405 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 10.303 -Fall : 10.097 +Rise : 9.458 +Fall : 9.165 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 8.706 -Fall : 8.626 +Rise : 8.163 +Fall : 8.217 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 9.651 -Fall : 9.302 +Rise : 9.615 +Fall : 9.395 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2880,66 +3111,297 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 6.360 +Fall : 6.264 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 7.571 +Fall : 7.524 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 7.674 +Fall : 7.662 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 6.587 +Fall : 6.485 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 7.472 +Fall : 7.493 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 6.932 +Fall : 6.845 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 7.271 +Fall : 7.209 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 7.721 +Fall : 7.687 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 7.056 +Fall : 6.973 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 7.006 +Fall : 7.030 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 7.319 +Fall : 7.267 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 7.174 +Fall : 7.096 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 7.071 +Fall : 7.007 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 7.020 +Fall : 6.970 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 6.552 +Fall : 6.571 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 7.330 +Fall : 7.264 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 9.122 +Fall : 8.826 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 7.438 +Fall : 7.443 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 8.053 +Fall : 8.034 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 7.917 +Fall : 7.950 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 7.827 +Fall : 7.840 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 7.624 +Fall : 7.581 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 8.099 +Fall : 8.146 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 7.850 +Fall : 7.807 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 7.358 +Fall : 7.390 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 6.452 +Fall : 6.387 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 6.360 +Fall : 6.264 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 7.130 +Fall : 7.063 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 6.876 +Fall : 6.794 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 8.852 +Fall : 8.482 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 6.830 +Fall : 6.740 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 6.970 +Fall : 6.880 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 7.284 +Fall : 7.186 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.895 -Fall : 6.842 +Rise : 7.067 +Fall : 6.992 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 7.233 -Fall : 7.193 +Rise : 7.241 +Fall : 7.195 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.656 -Fall : 7.659 +Rise : 8.077 +Fall : 8.094 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.648 -Fall : 7.616 +Rise : 7.067 +Fall : 6.992 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.895 -Fall : 6.842 +Rise : 8.010 +Fall : 8.144 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 8.165 -Fall : 8.150 +Rise : 7.213 +Fall : 7.223 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.531 -Fall : 9.293 +Rise : 8.481 +Fall : 8.223 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 8.085 -Fall : 8.027 +Rise : 7.151 +Fall : 7.129 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 9.079 -Fall : 8.736 +Rise : 8.941 +Fall : 8.699 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2955,7 +3417,7 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 395.1 MHz +Fmax : 355.49 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -2968,8 +3430,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.531 -End Point TNS : -69.352 +Slack : -1.813 +End Point TNS : -354.793 +--------------------------------------------------------------------------------+ @@ -2978,7 +3440,7 @@ End Point TNS : -69.352 ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.299 +Slack : 0.312 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -3001,7 +3463,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -119.478 +End Point TNS : -532.816 +--------------------------------------------------------------------------------+ @@ -3009,905 +3471,905 @@ End Point TNS : -119.478 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.531 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Slack : -1.813 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.116 -Data Delay : 2.353 +Clock Skew : 0.211 +Data Delay : 3.044 -Slack : -1.531 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Slack : -1.813 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.116 -Data Delay : 2.353 +Clock Skew : 0.207 +Data Delay : 3.040 -Slack : -1.531 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Slack : -1.781 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.116 -Data Delay : 2.353 +Clock Skew : 0.229 +Data Delay : 3.030 -Slack : -1.531 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -1.780 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.116 -Data Delay : 2.353 +Clock Skew : 0.233 +Data Delay : 3.033 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Slack : -1.748 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.215 +Data Delay : 2.983 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Slack : -1.747 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.219 +Data Delay : 2.986 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Slack : -1.746 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.206 +Data Delay : 2.972 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Slack : -1.745 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.210 +Data Delay : 2.975 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Slack : -1.731 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.207 +Data Delay : 2.958 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Slack : -1.730 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.211 +Data Delay : 2.961 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Slack : -1.700 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.211 +Data Delay : 2.931 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Slack : -1.700 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 +Clock Skew : 0.207 +Data Delay : 2.927 -Slack : -1.265 -From Node : counter[15] -To Node : A[13] +Slack : -1.663 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.207 +Data Delay : 2.890 -Slack : -1.265 -From Node : counter[15] -To Node : A[12] +Slack : -1.662 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.211 +Data Delay : 2.893 -Slack : -1.265 -From Node : counter[15] -To Node : A[11] +Slack : -1.650 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : -0.115 +Data Delay : 2.555 -Slack : -1.265 -From Node : counter[15] -To Node : A[10] +Slack : -1.640 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : -0.112 +Data Delay : 2.548 -Slack : -1.265 -From Node : counter[15] -To Node : A[9] +Slack : -1.627 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : -0.111 +Data Delay : 2.536 -Slack : -1.265 -From Node : counter[15] -To Node : A[8] +Slack : -1.627 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : -0.110 +Data Delay : 2.537 -Slack : -1.265 -From Node : counter[15] -To Node : A[7] +Slack : -1.596 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.208 +Data Delay : 2.824 -Slack : -1.265 -From Node : counter[15] -To Node : A[6] +Slack : -1.596 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.204 +Data Delay : 2.820 -Slack : -1.265 -From Node : counter[15] -To Node : A[5] +Slack : -1.594 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.211 +Data Delay : 2.825 -Slack : -1.265 -From Node : counter[15] -To Node : A[4] +Slack : -1.594 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : 0.207 +Data Delay : 2.821 -Slack : -1.265 -From Node : counter[15] -To Node : A[3] +Slack : -1.592 +From Node : counter[14] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 +Clock Skew : -0.057 +Data Delay : 2.530 -Slack : -1.265 -From Node : counter[15] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 - -Slack : -1.265 -From Node : counter[15] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.522 - -Slack : -1.264 +Slack : -1.592 From Node : counter[14] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 +Clock Skew : -0.057 +Data Delay : 2.530 -Slack : -1.264 -From Node : counter[14] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 +Slack : -1.592 From Node : counter[14] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 +Clock Skew : -0.057 +Data Delay : 2.530 -Slack : -1.264 -From Node : counter[14] -To Node : A[3] +Slack : -1.585 +From Node : counter[15] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 +Clock Skew : -0.057 +Data Delay : 2.523 -Slack : -1.264 -From Node : counter[14] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.264 -From Node : counter[14] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.262 -Data Delay : 2.521 - -Slack : -1.221 -From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.132 -Data Delay : 2.109 - -Slack : -1.200 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.139 - -Slack : -1.177 -From Node : counter[1] +Slack : -1.585 +From Node : counter[15] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 +Clock Skew : -0.057 +Data Delay : 2.523 -Slack : -1.177 -From Node : counter[1] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] +Slack : -1.585 +From Node : counter[15] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 +Clock Skew : -0.057 +Data Delay : 2.523 -Slack : -1.177 -From Node : counter[1] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.177 -From Node : counter[1] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.433 - -Slack : -1.170 -From Node : counter[0] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.170 -From Node : counter[0] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.426 - -Slack : -1.169 +Slack : -1.576 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.130 -Data Delay : 2.059 +Clock Skew : 0.212 +Data Delay : 2.808 -Slack : -1.169 +Slack : -1.576 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.133 -Data Delay : 2.056 +Clock Skew : 0.216 +Data Delay : 2.812 -Slack : -1.168 +Slack : -1.576 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.131 -Data Delay : 2.057 +Clock Skew : 0.213 +Data Delay : 2.809 -Slack : -1.157 -From Node : A[0] -To Node : A[12] +Slack : -1.574 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 2.084 +Clock Skew : 0.216 +Data Delay : 2.810 -Slack : -1.145 -From Node : A[0] -To Node : A[13] +Slack : -1.570 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 2.072 +Clock Skew : 0.222 +Data Delay : 2.812 -Slack : -1.144 +Slack : -1.570 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.219 +Data Delay : 2.809 + +Slack : -1.569 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.204 +Data Delay : 2.793 + +Slack : -1.569 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.200 +Data Delay : 2.789 + +Slack : -1.569 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.218 +Data Delay : 2.807 + +Slack : -1.568 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.222 +Data Delay : 2.810 + +Slack : -1.566 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.136 -Data Delay : 2.028 +Clock Skew : 0.216 +Data Delay : 2.802 -Slack : -1.144 -From Node : counter[6] -To Node : A[13] +Slack : -1.565 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.229 +Data Delay : 2.814 -Slack : -1.144 -From Node : counter[6] -To Node : A[12] +Slack : -1.565 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.217 +Data Delay : 2.802 -Slack : -1.144 -From Node : counter[6] -To Node : A[11] +Slack : -1.564 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.233 +Data Delay : 2.817 -Slack : -1.144 -From Node : counter[6] -To Node : A[10] +Slack : -1.561 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.228 +Data Delay : 2.809 -Slack : -1.144 -From Node : counter[6] -To Node : A[9] +Slack : -1.560 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.232 +Data Delay : 2.812 -Slack : -1.144 -From Node : counter[6] -To Node : A[8] +Slack : -1.560 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : -0.115 +Data Delay : 2.465 -Slack : -1.144 -From Node : counter[6] -To Node : A[7] +Slack : -1.554 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.205 +Data Delay : 2.779 -Slack : -1.144 -From Node : counter[6] -To Node : A[6] +Slack : -1.554 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.201 +Data Delay : 2.775 -Slack : -1.144 -From Node : counter[6] -To Node : A[5] +Slack : -1.547 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.205 +Data Delay : 2.772 -Slack : -1.144 -From Node : counter[6] -To Node : A[4] +Slack : -1.547 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : 0.201 +Data Delay : 2.768 -Slack : -1.144 -From Node : counter[6] -To Node : A[3] +Slack : -1.546 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : -0.117 +Data Delay : 2.449 -Slack : -1.144 -From Node : counter[6] -To Node : A[2] +Slack : -1.546 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : -0.116 +Data Delay : 2.450 -Slack : -1.144 -From Node : counter[6] -To Node : A[1] +Slack : -1.543 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.400 +Clock Skew : -0.117 +Data Delay : 2.446 -Slack : -1.139 +Slack : -1.543 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.116 +Data Delay : 2.447 + +Slack : -1.539 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.199 +Data Delay : 2.758 + +Slack : -1.539 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.195 +Data Delay : 2.754 + +Slack : -1.538 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.231 +Data Delay : 2.789 + +Slack : -1.538 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.227 +Data Delay : 2.785 + +Slack : -1.533 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.218 +Data Delay : 2.771 + +Slack : -1.533 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.214 +Data Delay : 2.767 + +Slack : -1.533 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.119 +Data Delay : 2.434 + +Slack : -1.532 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.205 +Data Delay : 2.757 + +Slack : -1.531 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.208 +Data Delay : 2.759 + +Slack : -1.531 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.204 +Data Delay : 2.755 + +Slack : -1.531 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.209 +Data Delay : 2.760 + +Slack : -1.530 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.117 +Data Delay : 2.433 + +Slack : -1.530 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.116 +Data Delay : 2.434 + +Slack : -1.527 From Node : counter[1] -To Node : counter[19] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.078 +Clock Skew : -0.055 +Data Delay : 2.467 -Slack : -1.137 -From Node : counter[4] +Slack : -1.527 +From Node : counter[1] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 +Clock Skew : -0.055 +Data Delay : 2.467 -Slack : -1.137 -From Node : counter[4] -To Node : A[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 - -Slack : -1.137 -From Node : counter[4] +Slack : -1.527 +From Node : counter[1] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 +Clock Skew : -0.055 +Data Delay : 2.467 -Slack : -1.137 -From Node : counter[4] -To Node : A[3] +Slack : -1.526 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 +Clock Skew : 0.229 +Data Delay : 2.775 -Slack : -1.137 -From Node : counter[4] -To Node : A[2] +Slack : -1.525 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 +Clock Skew : 0.233 +Data Delay : 2.778 -Slack : -1.137 -From Node : counter[4] -To Node : A[1] +Slack : -1.521 +From Node : counter[0] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.261 -Data Delay : 2.393 +Clock Skew : -0.055 +Data Delay : 2.461 -Slack : -1.131 -From Node : counter[21] +Slack : -1.521 +From Node : counter[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.067 -Data Delay : 2.059 +Clock Skew : -0.055 +Data Delay : 2.461 + +Slack : -1.521 +From Node : counter[0] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.461 + +Slack : -1.518 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.126 +Data Delay : 2.412 + +Slack : -1.518 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.211 +Data Delay : 2.749 + +Slack : -1.518 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.207 +Data Delay : 2.745 + +Slack : -1.515 +From Node : A[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.112 +Data Delay : 2.423 + +Slack : -1.514 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.210 +Data Delay : 2.744 + +Slack : -1.514 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.206 +Data Delay : 2.740 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.068 +Data Delay : 2.381 + +Slack : -1.511 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.111 +Data Delay : 2.420 + +Slack : -1.511 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.110 +Data Delay : 2.421 + +Slack : -1.510 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.122 +Data Delay : 2.408 + +Slack : -1.509 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.113 +Data Delay : 2.416 +--------------------------------------------------------------------------------+ @@ -3915,13 +4377,13 @@ Data Delay : 2.059 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.299 +Slack : 0.312 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.320 @@ -3933,59 +4395,68 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.519 -Slack : 0.334 +Slack : 0.324 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.830 + +Slack : 0.338 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.537 + +Slack : 0.348 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.069 +Clock Skew : 0.055 Data Delay : 0.547 -Slack : 0.340 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - Slack : 0.352 -From Node : A[13] -To Node : A[13] +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.564 +Clock Skew : 0.333 +Data Delay : 0.854 -Slack : 0.425 -From Node : counter[19] -To Node : counter[20] +Slack : 0.365 +From Node : A[0] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 -Data Delay : 0.953 +Data Delay : 0.893 -Slack : 0.432 -From Node : counter[19] -To Node : counter[21] +Slack : 0.399 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 -Data Delay : 0.960 +Data Delay : 0.927 -Slack : 0.498 +Slack : 0.426 From Node : A[4] -To Node : A[4] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.710 +Clock Skew : 0.384 +Data Delay : 0.954 Slack : 0.499 From Node : A[12] @@ -3996,15 +4467,6 @@ Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.711 -Slack : 0.499 -From Node : A[6] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.711 - Slack : 0.499 From Node : A[2] To Node : A[2] @@ -4014,14 +4476,14 @@ Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.711 -Slack : 0.500 -From Node : A[7] -To Node : A[7] +Slack : 0.499 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.712 +Clock Skew : 0.055 +Data Delay : 0.698 Slack : 0.500 From Node : counter[14] @@ -4032,6 +4494,15 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.699 +Slack : 0.500 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.699 + Slack : 0.500 From Node : counter[6] To Node : counter[6] @@ -4050,24 +4521,6 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.700 -Slack : 0.501 -From Node : counter[12] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.700 - -Slack : 0.501 -From Node : counter[20] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.714 - Slack : 0.502 From Node : A[10] To Node : A[10] @@ -4086,27 +4539,36 @@ Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.714 -Slack : 0.502 -From Node : counter[4] -To Node : counter[4] +Slack : 0.503 +From Node : counter[17] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.701 +Data Delay : 0.702 Slack : 0.503 -From Node : A[5] -To Node : A[5] +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.715 +Clock Skew : 0.055 +Data Delay : 0.702 Slack : 0.503 -From Node : counter[17] -To Node : counter[17] +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : counter[4] +To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4123,8 +4585,8 @@ Clock Skew : 0.055 Data Delay : 0.702 Slack : 0.504 -From Node : A[11] -To Node : A[11] +From Node : A[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4140,6 +4602,15 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.703 +Slack : 0.504 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + Slack : 0.505 From Node : counter[19] To Node : counter[19] @@ -4149,15 +4620,6 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 -Slack : 0.505 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.704 - Slack : 0.505 From Node : counter[3] To Node : counter[3] @@ -4167,32 +4629,14 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 -Slack : 0.509 -From Node : counter[18] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.037 - -Slack : 0.510 -From Node : counter[10] -To Node : counter[10] +Slack : 0.511 +From Node : A[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.709 - -Slack : 0.510 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.709 +Data Delay : 0.710 Slack : 0.514 From Node : counter[11] @@ -4213,17 +4657,17 @@ Clock Skew : 0.055 Data Delay : 0.713 Slack : 0.515 -From Node : counter[9] -To Node : counter[9] +From Node : A[4] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.714 +Clock Skew : 0.384 +Data Delay : 1.043 Slack : 0.515 -From Node : counter[7] -To Node : counter[7] +From Node : counter[20] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4231,13 +4675,22 @@ Clock Skew : 0.055 Data Delay : 0.714 Slack : 0.516 -From Node : counter[18] -To Node : counter[21] +From Node : A[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.044 +Clock Skew : 0.068 +Data Delay : 0.728 + +Slack : 0.516 +From Node : counter[5] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.715 Slack : 0.516 From Node : counter[1] @@ -4248,104 +4701,239 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.715 -Slack : 0.519 -From Node : counter[17] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.047 - -Slack : 0.521 -From Node : A[9] -To Node : A[9] +Slack : 0.517 +From Node : A[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.733 +Data Delay : 0.729 -Slack : 0.526 -From Node : counter[17] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.054 - -Slack : 0.562 -From Node : A[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.021 -Data Delay : 0.752 - -Slack : 0.563 -From Node : A[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.021 -Data Delay : 0.753 - -Slack : 0.601 -From Node : counter[16] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.129 - -Slack : 0.608 -From Node : counter[16] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.136 - -Slack : 0.625 +Slack : 0.519 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.837 +Data Delay : 0.731 -Slack : 0.639 -From Node : A[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Slack : 0.520 +From Node : A[5] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.769 +Clock Skew : 0.068 +Data Delay : 0.732 -Slack : 0.642 +Slack : 0.521 +From Node : A[11] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.733 + +Slack : 0.522 From Node : A[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.772 +Clock Skew : 0.384 +Data Delay : 1.050 -Slack : 0.644 -From Node : counter[15] -To Node : counter[15] +Slack : 0.529 +From Node : A[14] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.843 +Data Delay : 0.728 + +Slack : 0.534 +From Node : A[13] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.733 + +Slack : 0.579 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.344 +Data Delay : 1.092 + +Slack : 0.579 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.339 +Data Delay : 1.087 + +Slack : 0.587 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.099 + +Slack : 0.595 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.107 + +Slack : 0.598 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.104 + +Slack : 0.600 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.106 + +Slack : 0.603 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.342 +Data Delay : 1.114 + +Slack : 0.604 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.342 +Data Delay : 1.115 + +Slack : 0.604 +From Node : A[0] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.132 + +Slack : 0.606 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.339 +Data Delay : 1.114 + +Slack : 0.608 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.339 +Data Delay : 1.116 + +Slack : 0.608 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.342 +Data Delay : 1.119 + +Slack : 0.611 +From Node : A[0] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.139 + +Slack : 0.611 +From Node : A[4] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.139 + +Slack : 0.612 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.124 + +Slack : 0.614 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.342 +Data Delay : 1.125 + +Slack : 0.618 +From Node : A[4] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.146 + +Slack : 0.627 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.333 +Data Delay : 1.129 + +Slack : 0.638 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.021 +Data Delay : 0.828 Slack : 0.645 From Node : counter[13] @@ -4356,140 +4944,149 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.844 -Slack : 0.666 -From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 0.649 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.017 +Data Delay : 0.835 + +Slack : 0.650 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.849 + +Slack : 0.656 +From Node : A[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 -Data Delay : 0.856 +Data Delay : 0.846 -Slack : 0.670 -From Node : A[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Slack : 0.657 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.540 + +Slack : 0.660 +From Node : A[7] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 -Data Delay : 0.860 +Data Delay : 0.850 -Slack : 0.678 +Slack : 0.660 +From Node : A[8] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.021 +Data Delay : 0.850 + +Slack : 0.675 +From Node : A[9] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.021 +Data Delay : 0.865 + +Slack : 0.683 +From Node : A[10] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.021 +Data Delay : 0.873 + +Slack : 0.684 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.890 +Data Delay : 0.896 -Slack : 0.695 -From Node : A[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Slack : 0.701 +From Node : A[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.825 +Clock Skew : 0.021 +Data Delay : 0.891 -Slack : 0.696 -From Node : counter[14] -To Node : counter[20] +Slack : 0.701 +From Node : A[11] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.224 - -Slack : 0.702 -From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.832 - -Slack : 0.703 -From Node : counter[14] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.231 +Clock Skew : 0.021 +Data Delay : 0.891 Slack : 0.707 -From Node : A[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.837 - -Slack : 0.718 -From Node : A[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.848 - -Slack : 0.731 -From Node : A[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.861 - -Slack : 0.735 -From Node : A[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.039 -Data Delay : 0.865 - -Slack : 0.742 -From Node : A[4] +From Node : A[0] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.954 +Clock Skew : 0.384 +Data Delay : 1.235 -Slack : 0.743 -From Node : A[12] -To Node : A[13] +Slack : 0.707 +From Node : A[4] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.955 +Clock Skew : 0.384 +Data Delay : 1.235 -Slack : 0.743 -From Node : A[6] -To Node : A[7] +Slack : 0.714 +From Node : A[4] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.955 +Clock Skew : 0.384 +Data Delay : 1.242 + +Slack : 0.741 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 0.942 Slack : 0.744 -From Node : A[2] -To Node : A[3] +From Node : counter[8] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.956 +Clock Skew : 0.055 +Data Delay : 0.943 Slack : 0.744 From Node : counter[6] @@ -4509,6 +5106,15 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.943 +Slack : 0.744 +From Node : A[2] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.956 + Slack : 0.745 From Node : counter[16] To Node : counter[17] @@ -4518,24 +5124,6 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.944 -Slack : 0.746 -From Node : counter[20] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.959 - -Slack : 0.746 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.945 - Slack : 0.747 From Node : A[10] To Node : A[11] @@ -4545,18 +5133,18 @@ Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.959 -Slack : 0.747 -From Node : counter[4] -To Node : counter[5] +Slack : 0.748 +From Node : counter[2] +To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.946 +Data Delay : 0.947 Slack : 0.748 -From Node : counter[2] -To Node : counter[3] +From Node : counter[4] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4572,23 +5160,14 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.948 -Slack : 0.749 -From Node : A[7] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.961 - Slack : 0.751 -From Node : A[3] -To Node : A[4] +From Node : A[5] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.963 +Clock Skew : 0.021 +Data Delay : 0.941 Slack : 0.751 From Node : counter[1] @@ -4600,13 +5179,22 @@ Clock Skew : 0.055 Data Delay : 0.950 Slack : 0.752 -From Node : A[5] -To Node : A[6] +From Node : counter[9] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.964 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.752 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 Slack : 0.752 From Node : counter[17] @@ -4618,8 +5206,17 @@ Clock Skew : 0.055 Data Delay : 0.951 Slack : 0.753 -From Node : A[11] -To Node : A[12] +From Node : counter[15] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.753 +From Node : A[9] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4635,24 +5232,6 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.952 -Slack : 0.754 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.953 - -Slack : 0.754 -From Node : counter[5] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.953 - Slack : 0.754 From Node : counter[3] To Node : counter[4] @@ -4662,32 +5241,23 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.953 -Slack : 0.755 -From Node : counter[10] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.953 - -Slack : 0.756 -From Node : A[7] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.968 - -Slack : 0.756 -From Node : counter[15] +Slack : 0.754 +From Node : counter[19] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.284 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.757 +From Node : counter[9] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 0.958 Slack : 0.758 From Node : A[3] @@ -4706,114 +5276,6 @@ Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.957 - -Slack : 0.759 -From Node : A[5] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.971 - -Slack : 0.759 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.958 - -Slack : 0.760 -From Node : A[11] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.972 - -Slack : 0.760 -From Node : counter[0] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.959 - -Slack : 0.761 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.960 - -Slack : 0.761 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.960 - -Slack : 0.763 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.962 - -Slack : 0.763 -From Node : counter[15] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.291 - -Slack : 0.764 -From Node : counter[9] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.963 - -Slack : 0.764 -From Node : counter[7] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.963 - -Slack : 0.770 -From Node : A[9] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.982 - -Slack : 0.770 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.969 +--------------------------------------------------------------------------------+ @@ -4837,6 +5299,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -4877,6 +5347,302 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -4917,6 +5683,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -4957,6 +5731,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0 + Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -4995,7 +5777,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4 Slack : -2.174 Actual Width : 1.000 @@ -5003,7 +5785,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -5011,7 +5793,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5019,7 +5801,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5027,7 +5809,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5035,7 +5817,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5043,7 +5825,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5 Slack : -2.174 Actual Width : 1.000 @@ -5051,7 +5833,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -5059,7 +5841,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5067,7 +5849,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5075,7 +5857,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5083,7 +5865,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5091,7 +5873,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6 Slack : -2.174 Actual Width : 1.000 @@ -5099,7 +5881,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0 Slack : -2.174 Actual Width : 1.000 @@ -5107,7 +5889,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -5115,511 +5897,191 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[0] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[10] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[11] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[12] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[13] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[1] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[2] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[3] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[4] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[5] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[6] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[7] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[8] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : A[9] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[0] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[10] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[11] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[12] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[14] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_datain_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[15] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[16] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : -0.009 -Actual Width : 0.221 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : -0.009 -Actual Width : 0.221 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -0.008 -Actual Width : 0.222 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : -0.008 -Actual Width : 0.222 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : -0.002 -Actual Width : 0.228 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +--------------------------------------------------------------------------------+ @@ -5627,66 +6089,297 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 9.137 +Fall : 9.069 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 8.429 +Fall : 8.365 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 8.542 +Fall : 8.421 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 7.890 +Fall : 7.771 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 8.302 +Fall : 8.265 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 8.357 +Fall : 8.233 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 8.299 +Fall : 8.154 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 8.033 +Fall : 7.897 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 8.543 +Fall : 8.355 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 7.417 +Fall : 7.301 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 7.041 +Fall : 6.908 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 7.794 +Fall : 7.668 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 6.828 +Fall : 6.706 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 8.327 +Fall : 8.170 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 6.829 +Fall : 6.733 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 7.582 +Fall : 7.472 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 8.811 +Fall : 8.378 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 9.137 +Fall : 9.009 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 9.135 +Fall : 9.069 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 9.006 +Fall : 8.944 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 8.525 +Fall : 8.432 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 8.503 +Fall : 8.432 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 8.406 +Fall : 8.301 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 8.512 +Fall : 8.360 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 8.655 +Fall : 8.593 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 6.693 +Fall : 6.594 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 6.481 +Fall : 6.347 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 7.334 +Fall : 7.229 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 6.690 +Fall : 6.530 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 8.878 +Fall : 8.400 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 6.560 +Fall : 6.444 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 7.920 +Fall : 7.797 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 7.220 +Fall : 7.099 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 9.271 -Fall : 8.853 +Rise : 8.923 +Fall : 8.865 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.755 -Fall : 6.657 +Rise : 8.116 +Fall : 8.045 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.164 -Fall : 7.086 +Rise : 8.923 +Fall : 8.813 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.155 -Fall : 7.038 +Rise : 8.364 +Fall : 8.245 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.435 -Fall : 6.313 +Rise : 8.832 +Fall : 8.865 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 8.039 -Fall : 7.928 +Rise : 8.480 +Fall : 8.355 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.271 -Fall : 8.853 +Rise : 8.508 +Fall : 8.062 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.923 -Fall : 7.721 +Rise : 7.411 +Fall : 7.341 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.704 -Fall : 8.167 +Rise : 8.646 +Fall : 8.260 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5696,66 +6389,297 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 5.719 +Fall : 5.621 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 6.832 +Fall : 6.743 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 6.935 +Fall : 6.848 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 5.936 +Fall : 5.782 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 6.753 +Fall : 6.676 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 6.256 +Fall : 6.096 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 6.560 +Fall : 6.429 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 6.992 +Fall : 6.854 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 6.370 +Fall : 6.221 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 6.339 +Fall : 6.296 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 6.622 +Fall : 6.528 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 6.478 +Fall : 6.327 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 6.408 +Fall : 6.287 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 6.322 +Fall : 6.213 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 5.924 +Fall : 5.871 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 6.649 +Fall : 6.505 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 8.181 +Fall : 7.735 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 6.743 +Fall : 6.618 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 7.307 +Fall : 7.199 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 7.163 +Fall : 7.142 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 7.087 +Fall : 6.997 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 6.904 +Fall : 6.791 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 7.347 +Fall : 7.286 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 7.119 +Fall : 6.970 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 6.640 +Fall : 6.575 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 5.830 +Fall : 5.723 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 5.719 +Fall : 5.621 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 6.441 +Fall : 6.356 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 6.186 +Fall : 6.052 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 7.918 +Fall : 7.455 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 6.144 +Fall : 6.018 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 6.282 +Fall : 6.137 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 6.586 +Fall : 6.436 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.217 -Fall : 6.097 +Rise : 6.391 +Fall : 6.237 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.524 -Fall : 6.427 +Rise : 6.532 +Fall : 6.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.917 -Fall : 6.838 +Rise : 7.301 +Fall : 7.224 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 6.908 -Fall : 6.793 +Rise : 6.391 +Fall : 6.237 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.217 -Fall : 6.097 +Rise : 7.262 +Fall : 7.252 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.382 -Fall : 7.269 +Rise : 6.470 +Fall : 6.392 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.568 -Fall : 8.173 +Rise : 7.605 +Fall : 7.202 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.330 -Fall : 7.173 +Rise : 6.484 +Fall : 6.378 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.145 -Fall : 7.660 +Rise : 8.022 +Fall : 7.620 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5772,8 +6696,8 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.444 -End Point TNS : -17.149 +Slack : -0.824 +End Point TNS : -117.237 +--------------------------------------------------------------------------------+ @@ -5782,7 +6706,7 @@ End Point TNS : -17.149 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.178 +Slack : 0.169 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -5805,7 +6729,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -99.404 +End Point TNS : -347.907 +--------------------------------------------------------------------------------+ @@ -5813,905 +6737,905 @@ End Point TNS : -99.404 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.444 +Slack : -0.824 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.145 +Data Delay : 1.978 + +Slack : -0.822 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.148 +Data Delay : 1.979 + +Slack : -0.811 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.129 +Data Delay : 1.949 + +Slack : -0.809 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.134 +Data Delay : 1.952 + +Slack : -0.809 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.132 +Data Delay : 1.950 + +Slack : -0.807 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.137 +Data Delay : 1.953 + +Slack : -0.807 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 1.753 + +Slack : -0.797 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.060 +Data Delay : 1.746 + +Slack : -0.795 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.060 +Data Delay : 1.744 + +Slack : -0.793 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.058 +Data Delay : 1.744 + +Slack : -0.779 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.130 +Data Delay : 1.918 + +Slack : -0.777 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.133 +Data Delay : 1.919 + +Slack : -0.775 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.129 +Data Delay : 1.913 + +Slack : -0.773 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.132 +Data Delay : 1.914 + +Slack : -0.735 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.130 +Data Delay : 1.874 + +Slack : -0.733 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.133 +Data Delay : 1.875 + +Slack : -0.733 +From Node : A[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.060 +Data Delay : 1.682 + +Slack : -0.733 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 1.679 + +Slack : -0.726 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 1.376 +Clock Skew : 0.133 +Data Delay : 1.868 -Slack : -0.424 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.374 - -Slack : -0.423 -From Node : A[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.075 -Data Delay : 1.357 - -Slack : -0.411 -From Node : A[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.075 -Data Delay : 1.345 - -Slack : -0.411 +Slack : -0.725 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.076 -Data Delay : 1.344 +Clock Skew : 0.136 +Data Delay : 1.870 -Slack : -0.407 +Slack : -0.725 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.079 -Data Delay : 1.337 +Clock Skew : 0.137 +Data Delay : 1.871 -Slack : -0.401 +Slack : -0.725 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.135 +Data Delay : 1.869 + +Slack : -0.724 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.065 +Data Delay : 1.668 + +Slack : -0.722 +From Node : A[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 1.668 + +Slack : -0.719 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.065 +Data Delay : 1.663 + +Slack : -0.718 +From Node : A[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 1.664 + +Slack : -0.717 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.138 +Data Delay : 1.864 + +Slack : -0.717 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.081 -Data Delay : 1.329 +Clock Skew : 0.137 +Data Delay : 1.863 -Slack : -0.394 +Slack : -0.717 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.065 +Data Delay : 1.661 + +Slack : -0.717 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 1.663 + +Slack : -0.716 From Node : A[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.075 -Data Delay : 1.328 +Clock Skew : 0.140 +Data Delay : 1.865 -Slack : -0.385 -From Node : A[0] -To Node : A[13] +Slack : -0.715 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.327 +Clock Skew : 0.141 +Data Delay : 1.865 -Slack : -0.380 -From Node : counter[15] -To Node : A[13] +Slack : -0.715 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.067 +Data Delay : 1.657 -Slack : -0.380 -From Node : counter[15] -To Node : A[12] +Slack : -0.715 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.063 +Data Delay : 1.661 -Slack : -0.380 -From Node : counter[15] -To Node : A[11] +Slack : -0.714 +From Node : A[13] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : 0.142 +Data Delay : 1.865 -Slack : -0.380 -From Node : counter[15] -To Node : A[10] +Slack : -0.711 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : 0.138 +Data Delay : 1.858 -Slack : -0.380 -From Node : counter[15] -To Node : A[9] +Slack : -0.707 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.073 +Data Delay : 1.643 -Slack : -0.380 -From Node : counter[15] -To Node : A[8] +Slack : -0.705 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.061 +Data Delay : 1.653 -Slack : -0.380 -From Node : counter[15] -To Node : A[7] +Slack : -0.702 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.074 +Data Delay : 1.637 -Slack : -0.380 -From Node : counter[15] -To Node : A[6] +Slack : -0.702 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.070 +Data Delay : 1.641 -Slack : -0.380 -From Node : counter[15] -To Node : A[5] +Slack : -0.700 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.057 +Data Delay : 1.652 -Slack : -0.380 -From Node : counter[15] -To Node : A[4] +Slack : -0.698 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.055 +Data Delay : 1.652 -Slack : -0.380 -From Node : counter[15] -To Node : A[3] +Slack : -0.698 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.067 +Data Delay : 1.640 -Slack : -0.380 -From Node : counter[15] -To Node : A[2] +Slack : -0.697 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.065 +Data Delay : 1.641 -Slack : -0.380 -From Node : counter[15] -To Node : A[1] +Slack : -0.696 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.521 +Clock Skew : -0.054 +Data Delay : 1.651 -Slack : -0.377 -From Node : counter[0] -To Node : counter[19] +Slack : -0.695 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.327 +Clock Skew : -0.063 +Data Delay : 1.641 -Slack : -0.375 -From Node : counter[1] -To Node : counter[19] +Slack : -0.695 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.325 +Clock Skew : -0.061 +Data Delay : 1.643 -Slack : -0.374 -From Node : counter[14] -To Node : A[13] +Slack : -0.694 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 +Clock Skew : -0.052 +Data Delay : 1.651 -Slack : -0.374 -From Node : counter[14] -To Node : A[12] +Slack : -0.694 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 +Clock Skew : -0.064 +Data Delay : 1.639 -Slack : -0.374 -From Node : counter[14] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.374 -From Node : counter[14] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.154 -Data Delay : 1.515 - -Slack : -0.360 -From Node : counter[2] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.310 - -Slack : -0.356 -From Node : counter[2] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.306 - -Slack : -0.356 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.306 - -Slack : -0.355 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.078 -Data Delay : 1.232 - -Slack : -0.355 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.078 -Data Delay : 1.232 - -Slack : -0.355 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.078 -Data Delay : 1.232 - -Slack : -0.354 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -0.693 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.077 -Data Delay : 1.232 +Data Delay : 1.625 -Slack : -0.350 -From Node : counter[21] -To Node : A[13] +Slack : -0.693 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.059 +Data Delay : 1.643 -Slack : -0.350 -From Node : counter[21] -To Node : A[12] +Slack : -0.692 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.062 +Data Delay : 1.639 -Slack : -0.350 -From Node : counter[21] -To Node : A[11] +Slack : -0.692 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.063 +Data Delay : 1.638 -Slack : -0.350 -From Node : counter[21] -To Node : A[10] +Slack : -0.689 +From Node : A[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.061 +Data Delay : 1.637 -Slack : -0.350 -From Node : counter[21] -To Node : A[9] +Slack : -0.686 +From Node : A[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.069 +Data Delay : 1.626 -Slack : -0.350 -From Node : counter[21] -To Node : A[8] +Slack : -0.686 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.070 +Data Delay : 1.625 -Slack : -0.350 -From Node : counter[21] -To Node : A[7] +Slack : -0.685 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.067 +Data Delay : 1.627 -Slack : -0.350 -From Node : counter[21] -To Node : A[6] +Slack : -0.684 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.074 +Data Delay : 1.619 -Slack : -0.350 -From Node : counter[21] -To Node : A[5] +Slack : -0.682 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.060 +Data Delay : 1.631 -Slack : -0.350 -From Node : counter[21] -To Node : A[4] +Slack : -0.682 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.070 +Data Delay : 1.621 -Slack : -0.350 -From Node : counter[21] -To Node : A[3] +Slack : -0.681 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.056 +Data Delay : 1.634 -Slack : -0.350 -From Node : counter[21] -To Node : A[2] +Slack : -0.680 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.058 +Data Delay : 1.631 -Slack : -0.350 -From Node : counter[21] -To Node : A[1] +Slack : -0.680 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.293 +Clock Skew : -0.060 +Data Delay : 1.629 -Slack : -0.345 -From Node : counter[1] -To Node : counter[18] +Slack : -0.680 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.295 +Clock Skew : -0.063 +Data Delay : 1.626 -Slack : -0.345 -From Node : counter[0] -To Node : counter[18] +Slack : -0.679 +From Node : A[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.295 +Clock Skew : -0.054 +Data Delay : 1.634 -Slack : -0.336 -From Node : counter[20] -To Node : A[13] +Slack : -0.678 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.072 +Data Delay : 1.615 -Slack : -0.336 -From Node : counter[20] -To Node : A[12] +Slack : -0.677 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.067 +Data Delay : 1.619 -Slack : -0.336 -From Node : counter[20] -To Node : A[11] +Slack : -0.674 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : 0.129 +Data Delay : 1.812 -Slack : -0.336 -From Node : counter[20] -To Node : A[10] +Slack : -0.673 +From Node : A[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.070 +Data Delay : 1.612 -Slack : -0.336 -From Node : counter[20] -To Node : A[9] +Slack : -0.672 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : 0.132 +Data Delay : 1.813 -Slack : -0.336 -From Node : counter[20] -To Node : A[8] +Slack : -0.672 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.072 +Data Delay : 1.609 -Slack : -0.336 -From Node : counter[20] -To Node : A[7] +Slack : -0.672 +From Node : A[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.060 +Data Delay : 1.621 -Slack : -0.336 -From Node : counter[20] -To Node : A[6] +Slack : -0.672 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.070 +Data Delay : 1.611 -Slack : -0.336 -From Node : counter[20] -To Node : A[5] +Slack : -0.670 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.069 +Data Delay : 1.610 -Slack : -0.336 -From Node : counter[20] -To Node : A[4] +Slack : -0.669 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : -0.074 +Data Delay : 1.604 -Slack : -0.336 -From Node : counter[20] -To Node : A[3] +Slack : -0.668 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : 0.135 +Data Delay : 1.812 -Slack : -0.336 -From Node : counter[20] -To Node : A[2] +Slack : -0.667 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : 0.145 +Data Delay : 1.821 -Slack : -0.336 -From Node : counter[20] -To Node : A[1] +Slack : -0.665 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.044 -Data Delay : 1.279 +Clock Skew : 0.148 +Data Delay : 1.822 -Slack : -0.334 -From Node : A[0] -To Node : A[12] +Slack : -0.665 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.276 +Clock Skew : 0.145 +Data Delay : 1.819 -Slack : -0.326 -From Node : counter[1] -To Node : A[13] +Slack : -0.663 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : 0.148 +Data Delay : 1.820 -Slack : -0.326 -From Node : counter[1] -To Node : A[12] +Slack : -0.662 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : 0.144 +Data Delay : 1.815 -Slack : -0.326 -From Node : counter[1] -To Node : A[11] +Slack : -0.661 +From Node : A[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.071 +Data Delay : 1.599 -Slack : -0.326 -From Node : counter[1] -To Node : A[10] +Slack : -0.660 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : 0.147 +Data Delay : 1.816 -Slack : -0.326 -From Node : counter[1] -To Node : A[9] +Slack : -0.660 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.055 +Data Delay : 1.614 -Slack : -0.326 -From Node : counter[1] -To Node : A[8] +Slack : -0.658 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.053 +Data Delay : 1.614 -Slack : -0.326 -From Node : counter[1] -To Node : A[7] +Slack : -0.658 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.061 +Data Delay : 1.606 -Slack : -0.326 -From Node : counter[1] -To Node : A[6] +Slack : -0.654 +From Node : A[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.061 +Data Delay : 1.602 -Slack : -0.326 -From Node : counter[1] -To Node : A[5] +Slack : -0.653 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.073 +Data Delay : 1.589 -Slack : -0.326 -From Node : counter[1] -To Node : A[4] +Slack : -0.652 +From Node : A[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.070 +Data Delay : 1.591 -Slack : -0.326 -From Node : counter[1] -To Node : A[3] +Slack : -0.651 +From Node : A[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.060 +Data Delay : 1.600 -Slack : -0.326 -From Node : counter[1] -To Node : A[2] +Slack : -0.650 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : 0.134 +Data Delay : 1.793 -Slack : -0.326 -From Node : counter[1] -To Node : A[1] +Slack : -0.649 +From Node : A[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.466 +Clock Skew : -0.058 +Data Delay : 1.600 -Slack : -0.325 -From Node : counter[0] -To Node : A[13] +Slack : -0.648 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : -0.060 +Data Delay : 1.597 -Slack : -0.325 -From Node : counter[0] -To Node : A[12] +Slack : -0.648 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : -0.071 +Data Delay : 1.586 -Slack : -0.325 -From Node : counter[0] -To Node : A[11] +Slack : -0.648 +From Node : A[13] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : 0.137 +Data Delay : 1.794 -Slack : -0.325 -From Node : counter[0] -To Node : A[10] +Slack : -0.646 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : 0.128 +Data Delay : 1.783 -Slack : -0.325 -From Node : counter[0] -To Node : A[9] +Slack : -0.646 +From Node : A[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : -0.058 +Data Delay : 1.597 -Slack : -0.325 -From Node : counter[0] -To Node : A[8] +Slack : -0.645 +From Node : A[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : -0.070 +Data Delay : 1.584 -Slack : -0.325 -From Node : counter[0] -To Node : A[7] +Slack : -0.644 +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 +Clock Skew : 0.131 +Data Delay : 1.784 -Slack : -0.325 -From Node : counter[0] -To Node : A[6] +Slack : -0.644 +From Node : A[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.325 -From Node : counter[0] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.325 -From Node : counter[0] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.325 -From Node : counter[0] -To Node : A[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.325 -From Node : counter[0] -To Node : A[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.325 -From Node : counter[0] -To Node : A[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.465 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 +Clock Skew : -0.067 +Data Delay : 1.586 +--------------------------------------------------------------------------------+ @@ -6719,15 +7643,42 @@ Data Delay : 1.232 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.178 +Slack : 0.169 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.492 + +Slack : 0.185 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.216 +Data Delay : 0.505 + +Slack : 0.186 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.192 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.313 + Slack : 0.193 From Node : counter[0] To Node : counter[0] @@ -6737,50 +7688,50 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.195 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] +Slack : 0.199 +From Node : A[0] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.315 +Clock Skew : 0.235 +Data Delay : 0.518 -Slack : 0.196 +Slack : 0.204 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.037 Data Delay : 0.325 Slack : 0.208 -From Node : A[13] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.337 - -Slack : 0.261 -From Node : counter[19] -To Node : counter[20] +From Node : A[14] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 -Data Delay : 0.579 +Data Delay : 0.526 -Slack : 0.264 -From Node : counter[19] -To Node : counter[21] +Slack : 0.256 +From Node : A[4] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 -Data Delay : 0.582 +Data Delay : 0.574 + +Slack : 0.295 +From Node : counter[10] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 Slack : 0.296 From Node : A[12] @@ -6791,24 +7742,6 @@ Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 -Slack : 0.296 -From Node : A[6] -To Node : A[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.425 - -Slack : 0.296 -From Node : A[4] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.425 - Slack : 0.296 From Node : A[2] To Node : A[2] @@ -6818,23 +7751,32 @@ Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 -Slack : 0.297 -From Node : A[7] -To Node : A[7] +Slack : 0.296 +From Node : counter[8] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.426 +Clock Skew : 0.037 +Data Delay : 0.417 Slack : 0.297 -From Node : counter[12] -To Node : counter[12] +From Node : counter[16] +To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.417 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : counter[14] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 Slack : 0.297 From Node : counter[6] @@ -6855,8 +7797,8 @@ Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.298 -From Node : A[5] -To Node : A[5] +From Node : A[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -6873,22 +7815,13 @@ Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.298 -From Node : counter[16] -To Node : counter[16] +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.418 - -Slack : 0.298 -From Node : counter[14] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.418 +Clock Skew : 0.037 +Data Delay : 0.419 Slack : 0.298 From Node : counter[4] @@ -6917,78 +7850,51 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 -Slack : 0.298 -From Node : counter[20] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.427 - Slack : 0.299 -From Node : A[11] -To Node : A[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.428 - -Slack : 0.299 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.300 From Node : counter[18] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.420 -Slack : 0.300 +Slack : 0.299 From Node : counter[17] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.420 -Slack : 0.301 +Slack : 0.299 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.300 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.421 -Slack : 0.303 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 - -Slack : 0.303 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 - Slack : 0.304 From Node : counter[1] To Node : counter[1] @@ -6999,8 +7905,17 @@ Clock Skew : 0.037 Data Delay : 0.425 Slack : 0.305 -From Node : counter[9] -To Node : counter[9] +From Node : A[4] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 +From Node : counter[11] +To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -7017,17 +7932,17 @@ Clock Skew : 0.037 Data Delay : 0.426 Slack : 0.306 -From Node : counter[11] -To Node : counter[11] +From Node : counter[20] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.426 +Clock Skew : 0.037 +Data Delay : 0.427 Slack : 0.306 -From Node : counter[7] -To Node : counter[7] +From Node : counter[5] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -7035,247 +7950,409 @@ Clock Skew : 0.037 Data Delay : 0.427 Slack : 0.308 -From Node : A[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.030 -Data Delay : 0.442 - -Slack : 0.309 -From Node : A[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.029 -Data Delay : 0.442 - -Slack : 0.310 -From Node : A[9] -To Node : A[9] +From Node : A[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 -Data Delay : 0.439 +Data Delay : 0.437 -Slack : 0.314 -From Node : counter[18] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.632 - -Slack : 0.317 -From Node : counter[18] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.635 - -Slack : 0.326 -From Node : counter[17] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.644 - -Slack : 0.329 -From Node : counter[17] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.647 - -Slack : 0.359 -From Node : A[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.451 - -Slack : 0.361 +Slack : 0.309 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 -Data Delay : 0.490 +Data Delay : 0.438 -Slack : 0.362 -From Node : A[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Slack : 0.309 +From Node : A[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.454 +Clock Skew : 0.045 +Data Delay : 0.438 -Slack : 0.372 -From Node : counter[15] -To Node : counter[15] +Slack : 0.310 +From Node : A[11] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.439 + +Slack : 0.310 +From Node : A[5] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.439 + +Slack : 0.317 +From Node : A[14] +To Node : A[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 +Data Delay : 0.437 + +Slack : 0.319 +From Node : A[13] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.439 + +Slack : 0.319 +From Node : A[4] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.637 + +Slack : 0.322 +From Node : A[4] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.640 + +Slack : 0.327 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.650 + +Slack : 0.332 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.225 +Data Delay : 0.661 + +Slack : 0.332 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.657 + +Slack : 0.336 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.226 +Data Delay : 0.666 + +Slack : 0.341 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.666 + +Slack : 0.341 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.225 +Data Delay : 0.670 + +Slack : 0.344 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.671 + +Slack : 0.345 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.218 +Data Delay : 0.667 + +Slack : 0.346 +From Node : A[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.673 + +Slack : 0.346 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.222 +Data Delay : 0.672 + +Slack : 0.350 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.224 +Data Delay : 0.678 + +Slack : 0.350 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.222 +Data Delay : 0.676 + +Slack : 0.352 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.220 +Data Delay : 0.676 + +Slack : 0.352 +From Node : A[0] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.671 + +Slack : 0.354 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.215 +Data Delay : 0.673 + +Slack : 0.355 +From Node : A[0] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.674 + +Slack : 0.359 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 Data Delay : 0.492 -Slack : 0.372 +Slack : 0.368 +From Node : A[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.026 +Data Delay : 0.498 + +Slack : 0.368 +From Node : A[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.501 + +Slack : 0.371 From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.492 -Slack : 0.373 -From Node : A[0] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Slack : 0.372 +From Node : A[8] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.030 -Data Delay : 0.507 +Clock Skew : 0.029 +Data Delay : 0.505 + +Slack : 0.373 +From Node : A[7] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.506 + +Slack : 0.373 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.494 Slack : 0.376 -From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +From Node : A[9] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.029 Data Delay : 0.509 -Slack : 0.378 -From Node : counter[16] -To Node : counter[20] +Slack : 0.385 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.696 +Clock Skew : -0.153 +Data Delay : 0.316 -Slack : 0.381 -From Node : counter[16] -To Node : counter[21] +Slack : 0.385 +From Node : A[4] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 -Data Delay : 0.699 +Data Delay : 0.703 + +Slack : 0.387 +From Node : A[10] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.520 + +Slack : 0.388 +From Node : A[4] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.706 Slack : 0.390 +From Node : A[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.523 + +Slack : 0.394 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 -Data Delay : 0.519 +Data Delay : 0.523 -Slack : 0.395 -From Node : A[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.487 - -Slack : 0.404 +Slack : 0.398 From Node : A[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.496 +Clock Skew : 0.029 +Data Delay : 0.531 -Slack : 0.405 +Slack : 0.421 From Node : A[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.497 - -Slack : 0.413 -From Node : A[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.505 - -Slack : 0.414 -From Node : A[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.506 - -Slack : 0.419 -From Node : A[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : -0.012 -Data Delay : 0.511 - -Slack : 0.444 -From Node : counter[14] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.762 - -Slack : 0.445 -From Node : A[12] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.574 - -Slack : 0.445 -From Node : A[6] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.574 - -Slack : 0.445 -From Node : A[4] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.574 +Clock Skew : 0.235 +Data Delay : 0.740 + +Slack : 0.431 +From Node : A[5] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.564 + +Slack : 0.433 +From Node : A[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.222 +Data Delay : 0.759 + +Slack : 0.442 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.565 + +Slack : 0.445 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.566 Slack : 0.445 From Node : A[2] @@ -7286,6 +8363,24 @@ Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.574 +Slack : 0.446 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.446 +From Node : counter[14] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + Slack : 0.446 From Node : counter[6] To Node : counter[7] @@ -7295,24 +8390,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.567 -Slack : 0.446 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.566 - -Slack : 0.447 -From Node : counter[20] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.576 - Slack : 0.447 From Node : counter[2] To Node : counter[3] @@ -7322,6 +8399,15 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.568 +Slack : 0.447 +From Node : counter[4] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + Slack : 0.447 From Node : A[10] To Node : A[11] @@ -7331,95 +8417,50 @@ Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.576 -Slack : 0.447 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.568 - -Slack : 0.447 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.567 - -Slack : 0.447 -From Node : counter[14] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.567 - -Slack : 0.447 -From Node : counter[14] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.765 - -Slack : 0.449 +Slack : 0.448 From Node : counter[18] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.569 -Slack : 0.452 -From Node : counter[8] -To Node : counter[9] +Slack : 0.451 +From Node : A[4] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.769 + +Slack : 0.454 +From Node : A[4] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.772 + +Slack : 0.455 +From Node : counter[20] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.453 -From Node : counter[10] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.573 - -Slack : 0.455 -From Node : A[7] -To Node : A[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.584 +Data Delay : 0.576 Slack : 0.456 -From Node : A[5] -To Node : A[6] +From Node : counter[9] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.585 - -Slack : 0.456 -From Node : A[3] -To Node : A[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.585 +Clock Skew : 0.037 +Data Delay : 0.577 Slack : 0.456 From Node : counter[3] @@ -7439,9 +8480,45 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.577 +Slack : 0.456 +From Node : A[9] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.585 + Slack : 0.457 -From Node : A[11] -To Node : A[12] +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.457 +From Node : counter[15] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.457 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.457 +From Node : A[6] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -7449,175 +8526,22 @@ Clock Skew : 0.045 Data Delay : 0.586 Slack : 0.457 -From Node : counter[5] -To Node : counter[6] +From Node : counter[9] +To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.578 +Clock Skew : 0.039 +Data Delay : 0.580 Slack : 0.458 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.578 - -Slack : 0.458 -From Node : A[7] -To Node : A[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.587 - -Slack : 0.458 -From Node : counter[0] -To Node : counter[2] +From Node : counter[19] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.579 - -Slack : 0.459 -From Node : A[5] -To Node : A[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.588 - -Slack : 0.459 -From Node : A[3] -To Node : A[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.588 - -Slack : 0.459 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.580 - -Slack : 0.459 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.580 - -Slack : 0.460 -From Node : A[11] -To Node : A[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.589 - -Slack : 0.460 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.581 - -Slack : 0.461 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.581 - -Slack : 0.461 -From Node : counter[0] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.582 - -Slack : 0.463 -From Node : A[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.029 -Data Delay : 0.596 - -Slack : 0.463 -From Node : counter[9] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.584 - -Slack : 0.464 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.584 - -Slack : 0.464 -From Node : counter[7] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.585 - -Slack : 0.464 -From Node : counter[15] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.782 - -Slack : 0.465 -From Node : A[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.034 -Data Delay : 0.603 - -Slack : 0.467 -From Node : A[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.034 -Data Delay : 0.605 +--------------------------------------------------------------------------------+ @@ -7673,6 +8597,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : A[13] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : A[14] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7929,6 +8861,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0 + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7969,6 +8909,302 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0 + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -8009,6 +9245,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0 + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -8049,6 +9293,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0 + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -8087,7 +9339,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4 Slack : -1.000 Actual Width : 1.000 @@ -8095,335 +9347,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : -0.292 -Actual Width : -0.062 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -0.292 -Actual Width : -0.062 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : -0.289 -Actual Width : -0.059 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 - -Slack : -0.289 -Actual Width : -0.059 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : -0.289 -Actual Width : -0.059 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : -0.288 -Actual Width : -0.058 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 - -Slack : -0.287 -Actual Width : -0.057 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0 +--------------------------------------------------------------------------------+ @@ -8431,66 +9355,297 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 6.082 +Fall : 6.081 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 5.573 +Fall : 5.638 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 5.626 +Fall : 5.669 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 5.194 +Fall : 5.221 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 5.475 +Fall : 5.590 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 5.464 +Fall : 5.517 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 5.468 +Fall : 5.485 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 5.212 +Fall : 5.287 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 5.640 +Fall : 5.626 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 4.757 +Fall : 4.916 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 4.513 +Fall : 4.647 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 5.130 +Fall : 5.141 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 4.369 +Fall : 4.467 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 5.513 +Fall : 5.499 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 4.376 +Fall : 4.495 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 4.860 +Fall : 5.016 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 6.070 +Fall : 5.956 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 5.968 +Fall : 6.081 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 5.937 +Fall : 6.072 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 5.814 +Fall : 5.988 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 5.581 +Fall : 5.665 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 5.531 +Fall : 5.631 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 5.463 +Fall : 5.580 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 5.534 +Fall : 5.586 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 5.710 +Fall : 5.809 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 4.299 +Fall : 4.392 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 4.239 +Fall : 4.202 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 4.707 +Fall : 4.867 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 4.365 +Fall : 4.344 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 6.082 +Fall : 5.937 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 4.227 +Fall : 4.292 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 5.180 +Fall : 5.215 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 4.627 +Fall : 4.744 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.337 -Fall : 6.302 +Rise : 5.942 +Fall : 6.003 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.384 -Fall : 4.484 +Rise : 5.367 +Fall : 5.404 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.664 -Fall : 4.798 +Rise : 5.883 +Fall : 5.967 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.639 -Fall : 4.768 +Rise : 5.479 +Fall : 5.535 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.160 -Fall : 4.243 +Rise : 5.807 +Fall : 6.003 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 5.127 -Fall : 5.334 +Rise : 5.652 +Fall : 5.660 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 6.337 -Fall : 6.302 +Rise : 5.818 +Fall : 5.728 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 5.006 -Fall : 5.199 +Rise : 4.735 +Fall : 4.914 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.916 -Fall : 5.799 +Rise : 5.942 +Fall : 5.866 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8500,66 +9655,297 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 3.706 +Fall : 3.729 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 4.396 +Fall : 4.507 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 4.455 +Fall : 4.582 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 3.819 +Fall : 3.860 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 4.372 +Fall : 4.496 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 3.988 +Fall : 4.055 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 4.203 +Fall : 4.287 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 4.444 +Fall : 4.573 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 4.090 +Fall : 4.150 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 4.085 +Fall : 4.185 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 4.238 +Fall : 4.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 4.152 +Fall : 4.224 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 4.092 +Fall : 4.126 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 4.067 +Fall : 4.130 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 3.816 +Fall : 3.889 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 4.256 +Fall : 4.298 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 5.667 +Fall : 5.519 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 4.353 +Fall : 4.463 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 4.650 +Fall : 4.762 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 4.587 +Fall : 4.766 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 4.544 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 4.413 +Fall : 4.491 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 4.703 +Fall : 4.828 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 4.504 +Fall : 4.604 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 4.319 +Fall : 4.415 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 3.761 +Fall : 3.760 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 3.706 +Fall : 3.729 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 4.126 +Fall : 4.166 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 3.985 +Fall : 4.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 5.493 +Fall : 5.301 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 3.962 +Fall : 3.977 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 4.032 +Fall : 4.088 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 4.207 +Fall : 4.225 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 4.024 -Fall : 4.101 +Rise : 4.093 +Fall : 4.161 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.238 -Fall : 4.332 +Rise : 4.198 +Fall : 4.283 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.506 -Fall : 4.633 +Rise : 4.701 +Fall : 4.868 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.483 -Fall : 4.604 +Rise : 4.093 +Fall : 4.161 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.024 -Fall : 4.101 +Rise : 4.690 +Fall : 4.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.709 -Fall : 4.829 +Rise : 4.204 +Fall : 4.288 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.876 -Fall : 5.767 +Rise : 5.262 +Fall : 5.126 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 4.659 -Fall : 4.810 +Rise : 4.137 +Fall : 4.202 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.589 -Fall : 5.444 +Rise : 5.544 +Fall : 5.435 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8576,32 +9962,32 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -1.812 -Hold : 0.178 +Setup : -2.088 +Hold : 0.169 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : CLOCK_50 -Setup : -1.812 -Hold : 0.178 +Setup : -2.088 +Hold : 0.169 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : Design-wide TNS -Setup : -85.179 +Setup : -422.664 Hold : 0.0 Recovery : 0.0 Removal : 0.0 -Minimum Pulse Width : -119.48 +Minimum Pulse Width : -532.995 Clock : CLOCK_50 -Setup : -85.179 +Setup : -422.664 Hold : 0.000 Recovery : N/A Removal : N/A -Minimum Pulse Width : -119.480 +Minimum Pulse Width : -532.995 +--------------------------------------------------------------------------------+ @@ -8609,66 +9995,297 @@ Minimum Pulse Width : -119.480 +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 10.136 +Fall : 10.163 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 9.364 +Fall : 9.344 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 9.457 +Fall : 9.363 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 8.758 +Fall : 8.675 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 9.190 +Fall : 9.237 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 9.262 +Fall : 9.197 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 9.193 +Fall : 9.075 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 8.870 +Fall : 8.811 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 9.462 +Fall : 9.314 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 8.169 +Fall : 8.165 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 7.769 +Fall : 7.723 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 8.654 +Fall : 8.577 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 7.536 +Fall : 7.508 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 9.266 +Fall : 9.145 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 7.532 +Fall : 7.515 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 8.347 +Fall : 8.356 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 9.800 +Fall : 9.526 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 10.073 +Fall : 10.080 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 10.136 +Fall : 10.163 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 9.933 +Fall : 9.935 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 9.469 +Fall : 9.489 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 9.418 +Fall : 9.420 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 9.271 +Fall : 9.281 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 9.411 +Fall : 9.307 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 9.604 +Fall : 9.643 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 7.405 +Fall : 7.367 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 7.174 +Fall : 7.027 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 8.081 +Fall : 8.029 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 7.404 +Fall : 7.279 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 9.871 +Fall : 9.494 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 7.266 +Fall : 7.220 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 8.783 +Fall : 8.703 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 7.984 +Fall : 7.960 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 10.303 -Fall : 10.097 +Rise : 9.877 +Fall : 9.916 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 7.474 -Fall : 7.437 +Rise : 9.020 +Fall : 9.001 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.915 -Fall : 7.923 +Rise : 9.877 +Fall : 9.812 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.907 -Fall : 7.878 +Rise : 9.257 +Fall : 9.204 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 7.123 -Fall : 7.073 +Rise : 9.751 +Fall : 9.916 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 8.891 -Fall : 8.893 +Rise : 9.463 +Fall : 9.405 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 10.303 -Fall : 10.097 +Rise : 9.458 +Fall : 9.165 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 8.706 -Fall : 8.626 +Rise : 8.163 +Fall : 8.217 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 9.651 -Fall : 9.302 +Rise : 9.615 +Fall : 9.395 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8678,66 +10295,297 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : GPIO_0[*] +Clock Port : CLOCK_50 +Rise : 3.706 +Fall : 3.729 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[0] +Clock Port : CLOCK_50 +Rise : 4.396 +Fall : 4.507 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[1] +Clock Port : CLOCK_50 +Rise : 4.455 +Fall : 4.582 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[2] +Clock Port : CLOCK_50 +Rise : 3.819 +Fall : 3.860 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[3] +Clock Port : CLOCK_50 +Rise : 4.372 +Fall : 4.496 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[4] +Clock Port : CLOCK_50 +Rise : 3.988 +Fall : 4.055 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[5] +Clock Port : CLOCK_50 +Rise : 4.203 +Fall : 4.287 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[6] +Clock Port : CLOCK_50 +Rise : 4.444 +Fall : 4.573 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[7] +Clock Port : CLOCK_50 +Rise : 4.090 +Fall : 4.150 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[8] +Clock Port : CLOCK_50 +Rise : 4.085 +Fall : 4.185 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[9] +Clock Port : CLOCK_50 +Rise : 4.238 +Fall : 4.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[10] +Clock Port : CLOCK_50 +Rise : 4.152 +Fall : 4.224 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[11] +Clock Port : CLOCK_50 +Rise : 4.092 +Fall : 4.126 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[12] +Clock Port : CLOCK_50 +Rise : 4.067 +Fall : 4.130 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[13] +Clock Port : CLOCK_50 +Rise : 3.816 +Fall : 3.889 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[14] +Clock Port : CLOCK_50 +Rise : 4.256 +Fall : 4.298 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[15] +Clock Port : CLOCK_50 +Rise : 5.667 +Fall : 5.519 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[16] +Clock Port : CLOCK_50 +Rise : 4.353 +Fall : 4.463 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[17] +Clock Port : CLOCK_50 +Rise : 4.650 +Fall : 4.762 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[18] +Clock Port : CLOCK_50 +Rise : 4.587 +Fall : 4.766 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[19] +Clock Port : CLOCK_50 +Rise : 4.544 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[20] +Clock Port : CLOCK_50 +Rise : 4.413 +Fall : 4.491 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[21] +Clock Port : CLOCK_50 +Rise : 4.703 +Fall : 4.828 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[22] +Clock Port : CLOCK_50 +Rise : 4.504 +Fall : 4.604 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[23] +Clock Port : CLOCK_50 +Rise : 4.319 +Fall : 4.415 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[24] +Clock Port : CLOCK_50 +Rise : 3.761 +Fall : 3.760 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[25] +Clock Port : CLOCK_50 +Rise : 3.706 +Fall : 3.729 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[26] +Clock Port : CLOCK_50 +Rise : 4.126 +Fall : 4.166 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[27] +Clock Port : CLOCK_50 +Rise : 3.985 +Fall : 4.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[28] +Clock Port : CLOCK_50 +Rise : 5.493 +Fall : 5.301 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[29] +Clock Port : CLOCK_50 +Rise : 3.962 +Fall : 3.977 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[30] +Clock Port : CLOCK_50 +Rise : 4.032 +Fall : 4.088 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_0[31] +Clock Port : CLOCK_50 +Rise : 4.207 +Fall : 4.225 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 4.024 -Fall : 4.101 +Rise : 4.093 +Fall : 4.161 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.238 -Fall : 4.332 +Rise : 4.198 +Fall : 4.283 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.506 -Fall : 4.633 +Rise : 4.701 +Fall : 4.868 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.483 -Fall : 4.604 +Rise : 4.093 +Fall : 4.161 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.024 -Fall : 4.101 +Rise : 4.690 +Fall : 4.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.709 -Fall : 4.829 +Rise : 4.204 +Fall : 4.288 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.876 -Fall : 5.767 +Rise : 5.262 +Fall : 5.126 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 4.659 -Fall : 4.810 +Rise : 4.137 +Fall : 4.202 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.589 -Fall : 5.444 +Rise : 5.544 +Fall : 5.435 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8931,6 +10779,788 @@ EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a +Pin : GPIO_0[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[13] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[14] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[15] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[16] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[17] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[18] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[19] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[20] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[21] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[22] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[23] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[24] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[25] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[26] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[27] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[28] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[29] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[30] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[31] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[32] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_0[33] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in @@ -9209,6 +11839,856 @@ Ringback Voltage on Fall at Far-end : 0.297 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : GPIO_0[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -9465,6 +12945,856 @@ Ringback Voltage on Fall at Far-end : 0.277 V Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No +Pin : GPIO_0[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_0[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -9721,6 +14051,856 @@ Ringback Voltage on Fall at Far-end : 0.317 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : GPIO_0[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_0[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -9779,7 +14959,7 @@ Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 864 +RR Paths : 2035 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9793,7 +14973,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 864 +RR Paths : 2035 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9834,12 +15014,12 @@ Setup : 0 Hold : 0 Property : Unconstrained Output Ports -Setup : 8 -Hold : 8 +Setup : 40 +Hold : 40 Property : Unconstrained Output Port Paths -Setup : 16 -Hold : 16 +Setup : 144 +Hold : 144 +--------------------------------------------------------------------------------+ @@ -9850,7 +15030,7 @@ Hold : 16 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:47:20 2022 + Info: Processing started: Wed Mar 30 14:56:15 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -9867,63 +15047,63 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.812 +Info (332146): Worst-case setup slack is -2.088 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.812 -85.179 CLOCK_50 -Info (332146): Worst-case hold slack is 0.343 + Info (332119): -2.088 -422.664 CLOCK_50 +Info (332146): Worst-case hold slack is 0.337 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.343 0.000 CLOCK_50 + Info (332119): 0.337 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -119.480 CLOCK_50 + Info (332119): -3.000 -532.995 CLOCK_50 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.531 +Info (332146): Worst-case setup slack is -1.813 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.531 -69.352 CLOCK_50 -Info (332146): Worst-case hold slack is 0.299 + Info (332119): -1.813 -354.793 CLOCK_50 +Info (332146): Worst-case hold slack is 0.312 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.299 0.000 CLOCK_50 + Info (332119): 0.312 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -119.478 CLOCK_50 + Info (332119): -3.000 -532.816 CLOCK_50 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -0.444 +Info (332146): Worst-case setup slack is -0.824 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.444 -17.149 CLOCK_50 -Info (332146): Worst-case hold slack is 0.178 + Info (332119): -0.824 -117.237 CLOCK_50 +Info (332146): Worst-case hold slack is 0.169 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.178 0.000 CLOCK_50 + Info (332119): 0.169 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -99.404 CLOCK_50 + Info (332119): -3.000 -347.907 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 419 megabytes - Info: Processing ended: Wed Mar 30 13:47:22 2022 + Info: Peak virtual memory: 420 megabytes + Info: Processing ended: Wed Mar 30 14:56:17 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 354a22c..3daef11 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -1.812 -TNS : -85.179 +Slack : -2.088 +TNS : -422.664 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.343 +Slack : 0.337 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -119.480 +TNS : -532.995 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -1.531 -TNS : -69.352 +Slack : -1.813 +TNS : -354.793 Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.299 +Slack : 0.312 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -119.478 +TNS : -532.816 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -0.444 -TNS : -17.149 +Slack : -0.824 +TNS : -117.237 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.178 +Slack : 0.169 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -99.404 +TNS : -347.907 ------------------------------------------------------------ diff --git a/ram32.qip b/ram32.qip new file mode 100644 index 0000000..a91a201 --- /dev/null +++ b/ram32.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram32.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram32_bb.v"] diff --git a/ram32.v b/ram32.v new file mode 100644 index 0000000..633cc39 --- /dev/null +++ b/ram32.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram32.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram32 ( + address, + clock, + data, + wren, + q); + + input [14:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "led_patterns.mif", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 32768, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 15, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "15" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/ram32_bb.v b/ram32_bb.v new file mode 100644 index 0000000..95bbbf9 --- /dev/null +++ b/ram32_bb.v @@ -0,0 +1,124 @@ +// megafunction wizard: %RAM: 1-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram32.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module ram32 ( + address, + clock, + data, + wren, + q); + + input [14:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "15" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram32_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index 8137f5d..3a1d7c1 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:47:24" +// DATE "03/30/2022 14:56:19" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -30,9 +30,11 @@ module spectrum ( CLOCK_50, - LED); + LED, + GPIO_0); input CLOCK_50; output [7:0] LED; +output [33:0] GPIO_0; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -43,6 +45,40 @@ output [7:0] LED; // LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[0] => Location: PIN_D3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[1] => Location: PIN_C3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[2] => Location: PIN_A2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[3] => Location: PIN_A3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[4] => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[5] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[6] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[7] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[8] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[9] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[10] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[11] => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[12] => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[13] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[14] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[15] => Location: PIN_C6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[16] => Location: PIN_C8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[17] => Location: PIN_E6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[18] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[19] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[20] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[21] => Location: PIN_F8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[22] => Location: PIN_F9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[23] => Location: PIN_E9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[24] => Location: PIN_C9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[25] => Location: PIN_D9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[26] => Location: PIN_E11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[27] => Location: PIN_E10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[28] => Location: PIN_C11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[29] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[30] => Location: PIN_A12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[31] => Location: PIN_D11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[32] => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[33] => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -69,6 +105,40 @@ wire \LED[4]~output_o ; wire \LED[5]~output_o ; wire \LED[6]~output_o ; wire \LED[7]~output_o ; +wire \GPIO_0[0]~output_o ; +wire \GPIO_0[1]~output_o ; +wire \GPIO_0[2]~output_o ; +wire \GPIO_0[3]~output_o ; +wire \GPIO_0[4]~output_o ; +wire \GPIO_0[5]~output_o ; +wire \GPIO_0[6]~output_o ; +wire \GPIO_0[7]~output_o ; +wire \GPIO_0[8]~output_o ; +wire \GPIO_0[9]~output_o ; +wire \GPIO_0[10]~output_o ; +wire \GPIO_0[11]~output_o ; +wire \GPIO_0[12]~output_o ; +wire \GPIO_0[13]~output_o ; +wire \GPIO_0[14]~output_o ; +wire \GPIO_0[15]~output_o ; +wire \GPIO_0[16]~output_o ; +wire \GPIO_0[17]~output_o ; +wire \GPIO_0[18]~output_o ; +wire \GPIO_0[19]~output_o ; +wire \GPIO_0[20]~output_o ; +wire \GPIO_0[21]~output_o ; +wire \GPIO_0[22]~output_o ; +wire \GPIO_0[23]~output_o ; +wire \GPIO_0[24]~output_o ; +wire \GPIO_0[25]~output_o ; +wire \GPIO_0[26]~output_o ; +wire \GPIO_0[27]~output_o ; +wire \GPIO_0[28]~output_o ; +wire \GPIO_0[29]~output_o ; +wire \GPIO_0[30]~output_o ; +wire \GPIO_0[31]~output_o ; +wire \GPIO_0[32]~output_o ; +wire \GPIO_0[33]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; wire \counter[0]~63_combout ; @@ -113,67 +183,200 @@ wire \counter[19]~58 ; wire \counter[20]~59_combout ; wire \counter[20]~60 ; wire \counter[21]~61_combout ; +wire \Equal0~7_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; +wire \A[0]~40_combout ; +wire \A[1]~14_combout ; wire \Equal0~6_combout ; -wire \A[0]~39_combout ; -wire \A[1]~13_combout ; -wire \A[1]~14 ; -wire \A[2]~15_combout ; -wire \A[2]~16 ; -wire \A[3]~17_combout ; -wire \A[3]~18 ; -wire \A[4]~19_combout ; -wire \A[4]~20 ; -wire \A[5]~21_combout ; -wire \A[5]~22 ; -wire \A[6]~23_combout ; -wire \A[6]~24 ; -wire \A[7]~25_combout ; -wire \A[7]~26 ; -wire \A[8]~27_combout ; -wire \A[8]~28 ; -wire \A[9]~29_combout ; -wire \A[9]~30 ; -wire \A[10]~31_combout ; -wire \A[10]~32 ; -wire \A[11]~33_combout ; -wire \A[11]~34 ; -wire \A[12]~35_combout ; -wire \A[12]~36 ; -wire \A[13]~37_combout ; +wire \A[1]~15 ; +wire \A[2]~16_combout ; +wire \A[2]~17 ; +wire \A[3]~18_combout ; +wire \A[3]~19 ; +wire \A[4]~20_combout ; +wire \A[4]~21 ; +wire \A[5]~22_combout ; +wire \A[5]~23 ; +wire \A[6]~24_combout ; +wire \A[6]~25 ; +wire \A[7]~26_combout ; +wire \A[7]~27 ; +wire \A[8]~28_combout ; +wire \A[8]~29 ; +wire \A[9]~30_combout ; +wire \A[9]~31 ; +wire \A[10]~32_combout ; +wire \A[10]~33 ; +wire \A[11]~34_combout ; +wire \A[11]~35 ; +wire \A[12]~36_combout ; +wire \A[12]~37 ; +wire \A[13]~38_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; wire \~GND~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ; +wire \A[13]~39 ; +wire \A[14]~41_combout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ; wire [21:0] counter; wire [15:0] A; -wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -182,14 +385,102 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_b wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -207,9 +498,105 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +609,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +622,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -248,7 +635,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -261,7 +648,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -274,7 +661,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -287,7 +674,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -300,7 +687,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -311,6 +698,448 @@ defparam \LED[7]~output .bus_hold = "false"; defparam \LED[7]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X1_Y34_N9 +cycloneive_io_obuf \GPIO_0[0]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[0]~output .bus_hold = "false"; +defparam \GPIO_0[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y34_N2 +cycloneive_io_obuf \GPIO_0[1]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[1]~output .bus_hold = "false"; +defparam \GPIO_0[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N9 +cycloneive_io_obuf \GPIO_0[2]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[2]~output .bus_hold = "false"; +defparam \GPIO_0[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N16 +cycloneive_io_obuf \GPIO_0[3]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[3]~output .bus_hold = "false"; +defparam \GPIO_0[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \GPIO_0[4]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[4]~output .bus_hold = "false"; +defparam \GPIO_0[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N2 +cycloneive_io_obuf \GPIO_0[5]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[5]~output .bus_hold = "false"; +defparam \GPIO_0[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N23 +cycloneive_io_obuf \GPIO_0[6]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[6]~output .bus_hold = "false"; +defparam \GPIO_0[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y34_N2 +cycloneive_io_obuf \GPIO_0[7]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[7]~output .bus_hold = "false"; +defparam \GPIO_0[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N23 +cycloneive_io_obuf \GPIO_0[8]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[8]~output .bus_hold = "false"; +defparam \GPIO_0[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y34_N16 +cycloneive_io_obuf \GPIO_0[9]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[9]~output .bus_hold = "false"; +defparam \GPIO_0[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N9 +cycloneive_io_obuf \GPIO_0[10]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[10]~output .bus_hold = "false"; +defparam \GPIO_0[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N2 +cycloneive_io_obuf \GPIO_0[11]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[11]~output .bus_hold = "false"; +defparam \GPIO_0[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N2 +cycloneive_io_obuf \GPIO_0[12]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[12]~output .bus_hold = "false"; +defparam \GPIO_0[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N9 +cycloneive_io_obuf \GPIO_0[13]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[13]~output .bus_hold = "false"; +defparam \GPIO_0[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N23 +cycloneive_io_obuf \GPIO_0[14]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[14]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[14]~output .bus_hold = "false"; +defparam \GPIO_0[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N23 +cycloneive_io_obuf \GPIO_0[15]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[15]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[15]~output .bus_hold = "false"; +defparam \GPIO_0[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N16 +cycloneive_io_obuf \GPIO_0[16]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[16]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[16]~output .bus_hold = "false"; +defparam \GPIO_0[16]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N16 +cycloneive_io_obuf \GPIO_0[17]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[17]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[17]~output .bus_hold = "false"; +defparam \GPIO_0[17]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N16 +cycloneive_io_obuf \GPIO_0[18]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[18]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[18]~output .bus_hold = "false"; +defparam \GPIO_0[18]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N23 +cycloneive_io_obuf \GPIO_0[19]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[19]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[19]~output .bus_hold = "false"; +defparam \GPIO_0[19]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N9 +cycloneive_io_obuf \GPIO_0[20]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[20]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[20]~output .bus_hold = "false"; +defparam \GPIO_0[20]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N16 +cycloneive_io_obuf \GPIO_0[21]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[21]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[21]~output .bus_hold = "false"; +defparam \GPIO_0[21]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y34_N2 +cycloneive_io_obuf \GPIO_0[22]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[22]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[22]~output .bus_hold = "false"; +defparam \GPIO_0[22]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X29_Y34_N16 +cycloneive_io_obuf \GPIO_0[23]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[23]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[23]~output .bus_hold = "false"; +defparam \GPIO_0[23]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N2 +cycloneive_io_obuf \GPIO_0[24]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[24]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[24]~output .bus_hold = "false"; +defparam \GPIO_0[24]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N9 +cycloneive_io_obuf \GPIO_0[25]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[25]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[25]~output .bus_hold = "false"; +defparam \GPIO_0[25]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N9 +cycloneive_io_obuf \GPIO_0[26]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[26]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[26]~output .bus_hold = "false"; +defparam \GPIO_0[26]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N16 +cycloneive_io_obuf \GPIO_0[27]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[27]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[27]~output .bus_hold = "false"; +defparam \GPIO_0[27]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X38_Y34_N2 +cycloneive_io_obuf \GPIO_0[28]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[28]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[28]~output .bus_hold = "false"; +defparam \GPIO_0[28]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X40_Y34_N9 +cycloneive_io_obuf \GPIO_0[29]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[29]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[29]~output .bus_hold = "false"; +defparam \GPIO_0[29]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N16 +cycloneive_io_obuf \GPIO_0[30]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[30]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[30]~output .bus_hold = "false"; +defparam \GPIO_0[30]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N16 +cycloneive_io_obuf \GPIO_0[31]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[31]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[31]~output .bus_hold = "false"; +defparam \GPIO_0[31]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N23 +cycloneive_io_obuf \GPIO_0[32]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[32]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[32]~output .bus_hold = "false"; +defparam \GPIO_0[32]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N23 +cycloneive_io_obuf \GPIO_0[33]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[33]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[33]~output .bus_hold = "false"; +defparam \GPIO_0[33]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -334,7 +1163,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 +// Location: LCCOMB_X31_Y7_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -351,7 +1180,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X31_Y7_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -370,7 +1199,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 +// Location: LCCOMB_X31_Y7_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -388,7 +1217,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N13 +// Location: FF_X31_Y7_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -407,7 +1236,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N14 +// Location: LCCOMB_X31_Y7_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -425,7 +1254,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N15 +// Location: FF_X31_Y7_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -444,7 +1273,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 +// Location: LCCOMB_X31_Y7_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -462,7 +1291,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N17 +// Location: FF_X31_Y7_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -481,7 +1310,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N18 +// Location: LCCOMB_X31_Y7_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -499,7 +1328,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N19 +// Location: FF_X31_Y7_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -518,7 +1347,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N20 +// Location: LCCOMB_X31_Y7_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -536,7 +1365,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N21 +// Location: FF_X31_Y7_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -555,7 +1384,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N22 +// Location: LCCOMB_X31_Y7_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -573,7 +1402,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N23 +// Location: FF_X31_Y7_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -592,7 +1421,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 +// Location: LCCOMB_X31_Y7_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -610,7 +1439,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N25 +// Location: FF_X31_Y7_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -629,7 +1458,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 +// Location: LCCOMB_X31_Y7_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -647,7 +1476,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N27 +// Location: FF_X31_Y7_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -666,7 +1495,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N28 +// Location: LCCOMB_X31_Y7_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -684,7 +1513,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N29 +// Location: FF_X31_Y7_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -703,7 +1532,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 +// Location: LCCOMB_X31_Y7_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -721,7 +1550,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N31 +// Location: FF_X31_Y7_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -740,7 +1569,7 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N0 +// Location: LCCOMB_X31_Y6_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) @@ -758,7 +1587,7 @@ defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N1 +// Location: FF_X31_Y6_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[11]~41_combout ), @@ -777,7 +1606,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N2 +// Location: LCCOMB_X31_Y6_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -795,7 +1624,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N3 +// Location: FF_X31_Y6_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -814,7 +1643,7 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N4 +// Location: LCCOMB_X31_Y6_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) @@ -832,7 +1661,7 @@ defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N5 +// Location: FF_X31_Y6_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -851,7 +1680,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N6 +// Location: LCCOMB_X31_Y6_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -869,7 +1698,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N7 +// Location: FF_X31_Y6_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -888,25 +1717,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N8 +// Location: LCCOMB_X31_Y6_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(counter[15]), - .datab(gnd), + .dataa(gnd), + .datab(counter[15]), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hA50A; +defparam \counter[15]~49 .lut_mask = 16'hC30C; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N9 +// Location: FF_X31_Y6_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -925,7 +1754,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N10 +// Location: LCCOMB_X31_Y6_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -943,7 +1772,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N11 +// Location: FF_X31_Y6_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -962,7 +1791,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N12 +// Location: LCCOMB_X31_Y6_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -980,7 +1809,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N13 +// Location: FF_X31_Y6_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -999,7 +1828,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N14 +// Location: LCCOMB_X31_Y6_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1017,7 +1846,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N15 +// Location: FF_X31_Y6_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1036,7 +1865,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 +// Location: LCCOMB_X31_Y6_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1054,7 +1883,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N17 +// Location: FF_X31_Y6_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1073,7 +1902,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N18 +// Location: LCCOMB_X31_Y6_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1091,7 +1920,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N19 +// Location: FF_X31_Y6_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1110,7 +1939,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N20 +// Location: LCCOMB_X31_Y6_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1127,7 +1956,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N21 +// Location: FF_X31_Y6_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1146,7 +1975,24 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N24 +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[20] & !counter[21]) + + .dataa(counter[20]), + .datab(gnd), + .datac(counter[21]), + .datad(gnd), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0505; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N24 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): // \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) @@ -1163,7 +2009,7 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N4 +// Location: LCCOMB_X31_Y7_N4 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): // \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) @@ -1180,15 +2026,15 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 +// Location: LCCOMB_X31_Y7_N10 cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) .dataa(counter[6]), - .datab(counter[4]), - .datac(counter[7]), - .datad(counter[5]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), .cin(gnd), .combout(\Equal0~1_combout ), .cout()); @@ -1197,14 +2043,14 @@ defparam \Equal0~1 .lut_mask = 16'h0001; defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N26 +// Location: LCCOMB_X31_Y7_N8 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) +// \Equal0~2_combout = (!counter[8] & (!counter[9] & (!counter[10] & !counter[11]))) - .dataa(counter[10]), + .dataa(counter[8]), .datab(counter[9]), - .datac(counter[8]), + .datac(counter[10]), .datad(counter[11]), .cin(gnd), .combout(\Equal0~2_combout ), @@ -1214,7 +2060,7 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N30 +// Location: LCCOMB_X31_Y6_N30 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): // \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) @@ -1231,7 +2077,7 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N28 +// Location: LCCOMB_X30_Y7_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): // \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) @@ -1248,44 +2094,27 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \Equal0~6 ( +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \A[0]~40 ( // Equation(s): -// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) +// \A[0]~40_combout = A[0] $ (((\Equal0~7_combout & (\Equal0~5_combout & \Equal0~4_combout )))) - .dataa(counter[20]), - .datab(counter[21]), - .datac(\Equal0~5_combout ), + .dataa(\Equal0~7_combout ), + .datab(\Equal0~5_combout ), + .datac(A[0]), .datad(\Equal0~4_combout ), .cin(gnd), - .combout(\Equal0~6_combout ), + .combout(\A[0]~40_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h1000; -defparam \Equal0~6 .sum_lutc_input = "datac"; +defparam \A[0]~40 .lut_mask = 16'h78F0; +defparam \A[0]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \A[0]~39 ( -// Equation(s): -// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(A[0]), - .datad(\Equal0~6_combout ), - .cin(gnd), - .combout(\A[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \A[0]~39 .lut_mask = 16'h0FF0; -defparam \A[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 +// Location: FF_X31_Y7_N1 dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[0]~39_combout ), + .d(\A[0]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1301,28 +2130,45 @@ defparam \A[0] .is_wysiwyg = "true"; defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \A[1]~13 ( +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \A[1]~14 ( // Equation(s): -// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) -// \A[1]~14 = CARRY((A[1] & A[0])) +// \A[1]~14_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~15 = CARRY((A[1] & A[0])) .dataa(A[1]), .datab(A[0]), .datac(gnd), .datad(vcc), .cin(gnd), - .combout(\A[1]~13_combout ), - .cout(\A[1]~14 )); + .combout(\A[1]~14_combout ), + .cout(\A[1]~15 )); // synopsys translate_off -defparam \A[1]~13 .lut_mask = 16'h6688; -defparam \A[1]~13 .sum_lutc_input = "datac"; +defparam \A[1]~14 .lut_mask = 16'h6688; +defparam \A[1]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y14_N1 +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \Equal0~6 ( +// Equation(s): +// \Equal0~6_combout = (!counter[21] & (!counter[20] & (\Equal0~5_combout & \Equal0~4_combout ))) + + .dataa(counter[21]), + .datab(counter[20]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~6 .lut_mask = 16'h1000; +defparam \Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N1 dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[1]~13_combout ), + .d(\A[1]~14_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1338,28 +2184,28 @@ defparam \A[1] .is_wysiwyg = "true"; defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \A[2]~15 ( +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \A[2]~16 ( // Equation(s): -// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) -// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) +// \A[2]~16_combout = (A[2] & (!\A[1]~15 )) # (!A[2] & ((\A[1]~15 ) # (GND))) +// \A[2]~17 = CARRY((!\A[1]~15 ) # (!A[2])) .dataa(gnd), .datab(A[2]), .datac(gnd), .datad(vcc), - .cin(\A[1]~14 ), - .combout(\A[2]~15_combout ), - .cout(\A[2]~16 )); + .cin(\A[1]~15 ), + .combout(\A[2]~16_combout ), + .cout(\A[2]~17 )); // synopsys translate_off -defparam \A[2]~15 .lut_mask = 16'h3C3F; -defparam \A[2]~15 .sum_lutc_input = "cin"; +defparam \A[2]~16 .lut_mask = 16'h3C3F; +defparam \A[2]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N3 +// Location: FF_X30_Y7_N3 dffeas \A[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[2]~15_combout ), + .d(\A[2]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1375,28 +2221,28 @@ defparam \A[2] .is_wysiwyg = "true"; defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \A[3]~17 ( +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \A[3]~18 ( // Equation(s): -// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) -// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) +// \A[3]~18_combout = (A[3] & (\A[2]~17 $ (GND))) # (!A[3] & (!\A[2]~17 & VCC)) +// \A[3]~19 = CARRY((A[3] & !\A[2]~17 )) .dataa(gnd), .datab(A[3]), .datac(gnd), .datad(vcc), - .cin(\A[2]~16 ), - .combout(\A[3]~17_combout ), - .cout(\A[3]~18 )); + .cin(\A[2]~17 ), + .combout(\A[3]~18_combout ), + .cout(\A[3]~19 )); // synopsys translate_off -defparam \A[3]~17 .lut_mask = 16'hC30C; -defparam \A[3]~17 .sum_lutc_input = "cin"; +defparam \A[3]~18 .lut_mask = 16'hC30C; +defparam \A[3]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N5 +// Location: FF_X30_Y7_N5 dffeas \A[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[3]~17_combout ), + .d(\A[3]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1412,28 +2258,28 @@ defparam \A[3] .is_wysiwyg = "true"; defparam \A[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \A[4]~19 ( +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \A[4]~20 ( // Equation(s): -// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) -// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) +// \A[4]~20_combout = (A[4] & (!\A[3]~19 )) # (!A[4] & ((\A[3]~19 ) # (GND))) +// \A[4]~21 = CARRY((!\A[3]~19 ) # (!A[4])) .dataa(A[4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[3]~18 ), - .combout(\A[4]~19_combout ), - .cout(\A[4]~20 )); + .cin(\A[3]~19 ), + .combout(\A[4]~20_combout ), + .cout(\A[4]~21 )); // synopsys translate_off -defparam \A[4]~19 .lut_mask = 16'h5A5F; -defparam \A[4]~19 .sum_lutc_input = "cin"; +defparam \A[4]~20 .lut_mask = 16'h5A5F; +defparam \A[4]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N7 +// Location: FF_X30_Y7_N7 dffeas \A[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[4]~19_combout ), + .d(\A[4]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1449,28 +2295,28 @@ defparam \A[4] .is_wysiwyg = "true"; defparam \A[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \A[5]~21 ( +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \A[5]~22 ( // Equation(s): -// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) -// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) +// \A[5]~22_combout = (A[5] & (\A[4]~21 $ (GND))) # (!A[5] & (!\A[4]~21 & VCC)) +// \A[5]~23 = CARRY((A[5] & !\A[4]~21 )) .dataa(gnd), .datab(A[5]), .datac(gnd), .datad(vcc), - .cin(\A[4]~20 ), - .combout(\A[5]~21_combout ), - .cout(\A[5]~22 )); + .cin(\A[4]~21 ), + .combout(\A[5]~22_combout ), + .cout(\A[5]~23 )); // synopsys translate_off -defparam \A[5]~21 .lut_mask = 16'hC30C; -defparam \A[5]~21 .sum_lutc_input = "cin"; +defparam \A[5]~22 .lut_mask = 16'hC30C; +defparam \A[5]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N9 +// Location: FF_X30_Y7_N9 dffeas \A[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[5]~21_combout ), + .d(\A[5]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1486,28 +2332,28 @@ defparam \A[5] .is_wysiwyg = "true"; defparam \A[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \A[6]~23 ( +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \A[6]~24 ( // Equation(s): -// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) -// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) +// \A[6]~24_combout = (A[6] & (!\A[5]~23 )) # (!A[6] & ((\A[5]~23 ) # (GND))) +// \A[6]~25 = CARRY((!\A[5]~23 ) # (!A[6])) .dataa(A[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[5]~22 ), - .combout(\A[6]~23_combout ), - .cout(\A[6]~24 )); + .cin(\A[5]~23 ), + .combout(\A[6]~24_combout ), + .cout(\A[6]~25 )); // synopsys translate_off -defparam \A[6]~23 .lut_mask = 16'h5A5F; -defparam \A[6]~23 .sum_lutc_input = "cin"; +defparam \A[6]~24 .lut_mask = 16'h5A5F; +defparam \A[6]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N11 +// Location: FF_X30_Y7_N11 dffeas \A[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[6]~23_combout ), + .d(\A[6]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1523,28 +2369,28 @@ defparam \A[6] .is_wysiwyg = "true"; defparam \A[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \A[7]~25 ( +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \A[7]~26 ( // Equation(s): -// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) -// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) +// \A[7]~26_combout = (A[7] & (\A[6]~25 $ (GND))) # (!A[7] & (!\A[6]~25 & VCC)) +// \A[7]~27 = CARRY((A[7] & !\A[6]~25 )) .dataa(A[7]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[6]~24 ), - .combout(\A[7]~25_combout ), - .cout(\A[7]~26 )); + .cin(\A[6]~25 ), + .combout(\A[7]~26_combout ), + .cout(\A[7]~27 )); // synopsys translate_off -defparam \A[7]~25 .lut_mask = 16'hA50A; -defparam \A[7]~25 .sum_lutc_input = "cin"; +defparam \A[7]~26 .lut_mask = 16'hA50A; +defparam \A[7]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N13 +// Location: FF_X30_Y7_N13 dffeas \A[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[7]~25_combout ), + .d(\A[7]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1560,28 +2406,28 @@ defparam \A[7] .is_wysiwyg = "true"; defparam \A[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \A[8]~27 ( +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \A[8]~28 ( // Equation(s): -// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) -// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) +// \A[8]~28_combout = (A[8] & (!\A[7]~27 )) # (!A[8] & ((\A[7]~27 ) # (GND))) +// \A[8]~29 = CARRY((!\A[7]~27 ) # (!A[8])) - .dataa(A[8]), - .datab(gnd), + .dataa(gnd), + .datab(A[8]), .datac(gnd), .datad(vcc), - .cin(\A[7]~26 ), - .combout(\A[8]~27_combout ), - .cout(\A[8]~28 )); + .cin(\A[7]~27 ), + .combout(\A[8]~28_combout ), + .cout(\A[8]~29 )); // synopsys translate_off -defparam \A[8]~27 .lut_mask = 16'h5A5F; -defparam \A[8]~27 .sum_lutc_input = "cin"; +defparam \A[8]~28 .lut_mask = 16'h3C3F; +defparam \A[8]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N15 +// Location: FF_X30_Y7_N15 dffeas \A[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[8]~27_combout ), + .d(\A[8]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1597,28 +2443,28 @@ defparam \A[8] .is_wysiwyg = "true"; defparam \A[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \A[9]~29 ( +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \A[9]~30 ( // Equation(s): -// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) -// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) +// \A[9]~30_combout = (A[9] & (\A[8]~29 $ (GND))) # (!A[9] & (!\A[8]~29 & VCC)) +// \A[9]~31 = CARRY((A[9] & !\A[8]~29 )) .dataa(gnd), .datab(A[9]), .datac(gnd), .datad(vcc), - .cin(\A[8]~28 ), - .combout(\A[9]~29_combout ), - .cout(\A[9]~30 )); + .cin(\A[8]~29 ), + .combout(\A[9]~30_combout ), + .cout(\A[9]~31 )); // synopsys translate_off -defparam \A[9]~29 .lut_mask = 16'hC30C; -defparam \A[9]~29 .sum_lutc_input = "cin"; +defparam \A[9]~30 .lut_mask = 16'hC30C; +defparam \A[9]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N17 +// Location: FF_X30_Y7_N17 dffeas \A[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[9]~29_combout ), + .d(\A[9]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1634,28 +2480,28 @@ defparam \A[9] .is_wysiwyg = "true"; defparam \A[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \A[10]~31 ( +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \A[10]~32 ( // Equation(s): -// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) -// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) +// \A[10]~32_combout = (A[10] & (!\A[9]~31 )) # (!A[10] & ((\A[9]~31 ) # (GND))) +// \A[10]~33 = CARRY((!\A[9]~31 ) # (!A[10])) .dataa(gnd), .datab(A[10]), .datac(gnd), .datad(vcc), - .cin(\A[9]~30 ), - .combout(\A[10]~31_combout ), - .cout(\A[10]~32 )); + .cin(\A[9]~31 ), + .combout(\A[10]~32_combout ), + .cout(\A[10]~33 )); // synopsys translate_off -defparam \A[10]~31 .lut_mask = 16'h3C3F; -defparam \A[10]~31 .sum_lutc_input = "cin"; +defparam \A[10]~32 .lut_mask = 16'h3C3F; +defparam \A[10]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N19 +// Location: FF_X30_Y7_N19 dffeas \A[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[10]~31_combout ), + .d(\A[10]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1671,28 +2517,28 @@ defparam \A[10] .is_wysiwyg = "true"; defparam \A[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \A[11]~33 ( +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \A[11]~34 ( // Equation(s): -// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) -// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) +// \A[11]~34_combout = (A[11] & (\A[10]~33 $ (GND))) # (!A[11] & (!\A[10]~33 & VCC)) +// \A[11]~35 = CARRY((A[11] & !\A[10]~33 )) .dataa(gnd), .datab(A[11]), .datac(gnd), .datad(vcc), - .cin(\A[10]~32 ), - .combout(\A[11]~33_combout ), - .cout(\A[11]~34 )); + .cin(\A[10]~33 ), + .combout(\A[11]~34_combout ), + .cout(\A[11]~35 )); // synopsys translate_off -defparam \A[11]~33 .lut_mask = 16'hC30C; -defparam \A[11]~33 .sum_lutc_input = "cin"; +defparam \A[11]~34 .lut_mask = 16'hC30C; +defparam \A[11]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N21 +// Location: FF_X30_Y7_N21 dffeas \A[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[11]~33_combout ), + .d(\A[11]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1708,28 +2554,28 @@ defparam \A[11] .is_wysiwyg = "true"; defparam \A[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \A[12]~35 ( +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \A[12]~36 ( // Equation(s): -// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) -// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) +// \A[12]~36_combout = (A[12] & (!\A[11]~35 )) # (!A[12] & ((\A[11]~35 ) # (GND))) +// \A[12]~37 = CARRY((!\A[11]~35 ) # (!A[12])) .dataa(A[12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[11]~34 ), - .combout(\A[12]~35_combout ), - .cout(\A[12]~36 )); + .cin(\A[11]~35 ), + .combout(\A[12]~36_combout ), + .cout(\A[12]~37 )); // synopsys translate_off -defparam \A[12]~35 .lut_mask = 16'h5A5F; -defparam \A[12]~35 .sum_lutc_input = "cin"; +defparam \A[12]~36 .lut_mask = 16'h5A5F; +defparam \A[12]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N23 +// Location: FF_X30_Y7_N23 dffeas \A[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[12]~35_combout ), + .d(\A[12]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1745,27 +2591,28 @@ defparam \A[12] .is_wysiwyg = "true"; defparam \A[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \A[13]~37 ( +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \A[13]~38 ( // Equation(s): -// \A[13]~37_combout = \A[12]~36 $ (!A[13]) +// \A[13]~38_combout = (A[13] & (\A[12]~37 $ (GND))) # (!A[13] & (!\A[12]~37 & VCC)) +// \A[13]~39 = CARRY((A[13] & !\A[12]~37 )) .dataa(gnd), - .datab(gnd), + .datab(A[13]), .datac(gnd), - .datad(A[13]), - .cin(\A[12]~36 ), - .combout(\A[13]~37_combout ), - .cout()); + .datad(vcc), + .cin(\A[12]~37 ), + .combout(\A[13]~38_combout ), + .cout(\A[13]~39 )); // synopsys translate_off -defparam \A[13]~37 .lut_mask = 16'hF00F; -defparam \A[13]~37 .sum_lutc_input = "cin"; +defparam \A[13]~38 .lut_mask = 16'hC30C; +defparam \A[13]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N25 +// Location: FF_X30_Y7_N25 dffeas \A[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[13]~37_combout ), + .d(\A[13]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1781,301 +2628,8 @@ defparam \A[13] .is_wysiwyg = "true"; defparam \A[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2098,39 +2652,1216 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X32_Y26_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N3 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N5 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y28_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X21_Y31_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y28_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .lut_mask = 16'hFA50; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N18 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .lut_mask = 16'hFC0C; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N26 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -2186,97 +3917,81 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] - - .dataa(gnd), - .datab(gnd), - .datac(A[13]), - .datad(gnd), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N16 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - .dataa(gnd), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datab(gnd), - .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y14_N17 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2332,7 +4047,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y21_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2388,25 +4103,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X21_Y28_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hAAF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2462,7 +4177,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y15_N0 +// Location: M9K_X22_Y12_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -2518,81 +4233,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(A[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 +// Location: M9K_X22_Y27_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(vcc), .portare(vcc), @@ -2648,22 +4307,3086 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N30 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y29_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .lut_mask = 16'hF5A0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \A[14]~41 ( +// Equation(s): +// \A[14]~41_combout = A[14] $ (\A[13]~39 ) + + .dataa(A[14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\A[13]~39 ), + .combout(\A[14]~41_combout ), + .cout()); +// synopsys translate_off +defparam \A[14]~41 .lut_mask = 16'h5A5A; +defparam \A[14]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X30_Y7_N27 +dffeas \A[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[14]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[14]), + .prn(vcc)); +// synopsys translate_off +defparam \A[14] .is_wysiwyg = "true"; +defparam \A[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00F0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout = (A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .lut_mask = 16'hF000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2] = (!A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .lut_mask = 16'h000F; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout = (!A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .lut_mask = 16'h0F00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout = A[14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N1 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hAAE4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .lut_mask = 16'hF2C2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hB9A8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hEE50; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .lut_mask = 16'hEE22; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N14 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .lut_mask = 16'hF3C0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .lut_mask = 16'hFA0A; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; @@ -2682,4 +7405,72 @@ assign LED[6] = \LED[6]~output_o ; assign LED[7] = \LED[7]~output_o ; +assign GPIO_0[0] = \GPIO_0[0]~output_o ; + +assign GPIO_0[1] = \GPIO_0[1]~output_o ; + +assign GPIO_0[2] = \GPIO_0[2]~output_o ; + +assign GPIO_0[3] = \GPIO_0[3]~output_o ; + +assign GPIO_0[4] = \GPIO_0[4]~output_o ; + +assign GPIO_0[5] = \GPIO_0[5]~output_o ; + +assign GPIO_0[6] = \GPIO_0[6]~output_o ; + +assign GPIO_0[7] = \GPIO_0[7]~output_o ; + +assign GPIO_0[8] = \GPIO_0[8]~output_o ; + +assign GPIO_0[9] = \GPIO_0[9]~output_o ; + +assign GPIO_0[10] = \GPIO_0[10]~output_o ; + +assign GPIO_0[11] = \GPIO_0[11]~output_o ; + +assign GPIO_0[12] = \GPIO_0[12]~output_o ; + +assign GPIO_0[13] = \GPIO_0[13]~output_o ; + +assign GPIO_0[14] = \GPIO_0[14]~output_o ; + +assign GPIO_0[15] = \GPIO_0[15]~output_o ; + +assign GPIO_0[16] = \GPIO_0[16]~output_o ; + +assign GPIO_0[17] = \GPIO_0[17]~output_o ; + +assign GPIO_0[18] = \GPIO_0[18]~output_o ; + +assign GPIO_0[19] = \GPIO_0[19]~output_o ; + +assign GPIO_0[20] = \GPIO_0[20]~output_o ; + +assign GPIO_0[21] = \GPIO_0[21]~output_o ; + +assign GPIO_0[22] = \GPIO_0[22]~output_o ; + +assign GPIO_0[23] = \GPIO_0[23]~output_o ; + +assign GPIO_0[24] = \GPIO_0[24]~output_o ; + +assign GPIO_0[25] = \GPIO_0[25]~output_o ; + +assign GPIO_0[26] = \GPIO_0[26]~output_o ; + +assign GPIO_0[27] = \GPIO_0[27]~output_o ; + +assign GPIO_0[28] = \GPIO_0[28]~output_o ; + +assign GPIO_0[29] = \GPIO_0[29]~output_o ; + +assign GPIO_0[30] = \GPIO_0[30]~output_o ; + +assign GPIO_0[31] = \GPIO_0[31]~output_o ; + +assign GPIO_0[32] = \GPIO_0[32]~output_o ; + +assign GPIO_0[33] = \GPIO_0[33]~output_o ; + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index 859d091..93c01b3 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:47:24" +// DATE "03/30/2022 14:56:19" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -30,9 +30,11 @@ module spectrum ( CLOCK_50, - LED); + LED, + GPIO_0); input CLOCK_50; output [7:0] LED; +output [33:0] GPIO_0; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -43,6 +45,40 @@ output [7:0] LED; // LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[0] => Location: PIN_D3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[1] => Location: PIN_C3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[2] => Location: PIN_A2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[3] => Location: PIN_A3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[4] => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[5] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[6] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[7] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[8] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[9] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[10] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[11] => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[12] => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[13] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[14] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[15] => Location: PIN_C6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[16] => Location: PIN_C8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[17] => Location: PIN_E6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[18] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[19] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[20] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[21] => Location: PIN_F8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[22] => Location: PIN_F9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[23] => Location: PIN_E9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[24] => Location: PIN_C9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[25] => Location: PIN_D9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[26] => Location: PIN_E11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[27] => Location: PIN_E10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[28] => Location: PIN_C11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[29] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[30] => Location: PIN_A12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[31] => Location: PIN_D11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[32] => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[33] => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -69,6 +105,40 @@ wire \LED[4]~output_o ; wire \LED[5]~output_o ; wire \LED[6]~output_o ; wire \LED[7]~output_o ; +wire \GPIO_0[0]~output_o ; +wire \GPIO_0[1]~output_o ; +wire \GPIO_0[2]~output_o ; +wire \GPIO_0[3]~output_o ; +wire \GPIO_0[4]~output_o ; +wire \GPIO_0[5]~output_o ; +wire \GPIO_0[6]~output_o ; +wire \GPIO_0[7]~output_o ; +wire \GPIO_0[8]~output_o ; +wire \GPIO_0[9]~output_o ; +wire \GPIO_0[10]~output_o ; +wire \GPIO_0[11]~output_o ; +wire \GPIO_0[12]~output_o ; +wire \GPIO_0[13]~output_o ; +wire \GPIO_0[14]~output_o ; +wire \GPIO_0[15]~output_o ; +wire \GPIO_0[16]~output_o ; +wire \GPIO_0[17]~output_o ; +wire \GPIO_0[18]~output_o ; +wire \GPIO_0[19]~output_o ; +wire \GPIO_0[20]~output_o ; +wire \GPIO_0[21]~output_o ; +wire \GPIO_0[22]~output_o ; +wire \GPIO_0[23]~output_o ; +wire \GPIO_0[24]~output_o ; +wire \GPIO_0[25]~output_o ; +wire \GPIO_0[26]~output_o ; +wire \GPIO_0[27]~output_o ; +wire \GPIO_0[28]~output_o ; +wire \GPIO_0[29]~output_o ; +wire \GPIO_0[30]~output_o ; +wire \GPIO_0[31]~output_o ; +wire \GPIO_0[32]~output_o ; +wire \GPIO_0[33]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; wire \counter[0]~63_combout ; @@ -113,67 +183,200 @@ wire \counter[19]~58 ; wire \counter[20]~59_combout ; wire \counter[20]~60 ; wire \counter[21]~61_combout ; +wire \Equal0~7_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; +wire \A[0]~40_combout ; +wire \A[1]~14_combout ; wire \Equal0~6_combout ; -wire \A[0]~39_combout ; -wire \A[1]~13_combout ; -wire \A[1]~14 ; -wire \A[2]~15_combout ; -wire \A[2]~16 ; -wire \A[3]~17_combout ; -wire \A[3]~18 ; -wire \A[4]~19_combout ; -wire \A[4]~20 ; -wire \A[5]~21_combout ; -wire \A[5]~22 ; -wire \A[6]~23_combout ; -wire \A[6]~24 ; -wire \A[7]~25_combout ; -wire \A[7]~26 ; -wire \A[8]~27_combout ; -wire \A[8]~28 ; -wire \A[9]~29_combout ; -wire \A[9]~30 ; -wire \A[10]~31_combout ; -wire \A[10]~32 ; -wire \A[11]~33_combout ; -wire \A[11]~34 ; -wire \A[12]~35_combout ; -wire \A[12]~36 ; -wire \A[13]~37_combout ; +wire \A[1]~15 ; +wire \A[2]~16_combout ; +wire \A[2]~17 ; +wire \A[3]~18_combout ; +wire \A[3]~19 ; +wire \A[4]~20_combout ; +wire \A[4]~21 ; +wire \A[5]~22_combout ; +wire \A[5]~23 ; +wire \A[6]~24_combout ; +wire \A[6]~25 ; +wire \A[7]~26_combout ; +wire \A[7]~27 ; +wire \A[8]~28_combout ; +wire \A[8]~29 ; +wire \A[9]~30_combout ; +wire \A[9]~31 ; +wire \A[10]~32_combout ; +wire \A[10]~33 ; +wire \A[11]~34_combout ; +wire \A[11]~35 ; +wire \A[12]~36_combout ; +wire \A[12]~37 ; +wire \A[13]~38_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; wire \~GND~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ; +wire \A[13]~39 ; +wire \A[14]~41_combout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ; wire [21:0] counter; wire [15:0] A; -wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -182,14 +385,102 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_b wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -207,9 +498,105 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +609,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +622,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -248,7 +635,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -261,7 +648,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -274,7 +661,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -287,7 +674,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -300,7 +687,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -311,6 +698,448 @@ defparam \LED[7]~output .bus_hold = "false"; defparam \LED[7]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X1_Y34_N9 +cycloneive_io_obuf \GPIO_0[0]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[0]~output .bus_hold = "false"; +defparam \GPIO_0[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y34_N2 +cycloneive_io_obuf \GPIO_0[1]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[1]~output .bus_hold = "false"; +defparam \GPIO_0[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N9 +cycloneive_io_obuf \GPIO_0[2]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[2]~output .bus_hold = "false"; +defparam \GPIO_0[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N16 +cycloneive_io_obuf \GPIO_0[3]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[3]~output .bus_hold = "false"; +defparam \GPIO_0[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \GPIO_0[4]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[4]~output .bus_hold = "false"; +defparam \GPIO_0[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N2 +cycloneive_io_obuf \GPIO_0[5]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[5]~output .bus_hold = "false"; +defparam \GPIO_0[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N23 +cycloneive_io_obuf \GPIO_0[6]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[6]~output .bus_hold = "false"; +defparam \GPIO_0[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y34_N2 +cycloneive_io_obuf \GPIO_0[7]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[7]~output .bus_hold = "false"; +defparam \GPIO_0[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N23 +cycloneive_io_obuf \GPIO_0[8]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[8]~output .bus_hold = "false"; +defparam \GPIO_0[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y34_N16 +cycloneive_io_obuf \GPIO_0[9]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[9]~output .bus_hold = "false"; +defparam \GPIO_0[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N9 +cycloneive_io_obuf \GPIO_0[10]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[10]~output .bus_hold = "false"; +defparam \GPIO_0[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N2 +cycloneive_io_obuf \GPIO_0[11]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[11]~output .bus_hold = "false"; +defparam \GPIO_0[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N2 +cycloneive_io_obuf \GPIO_0[12]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[12]~output .bus_hold = "false"; +defparam \GPIO_0[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N9 +cycloneive_io_obuf \GPIO_0[13]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[13]~output .bus_hold = "false"; +defparam \GPIO_0[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N23 +cycloneive_io_obuf \GPIO_0[14]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[14]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[14]~output .bus_hold = "false"; +defparam \GPIO_0[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N23 +cycloneive_io_obuf \GPIO_0[15]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[15]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[15]~output .bus_hold = "false"; +defparam \GPIO_0[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N16 +cycloneive_io_obuf \GPIO_0[16]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[16]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[16]~output .bus_hold = "false"; +defparam \GPIO_0[16]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N16 +cycloneive_io_obuf \GPIO_0[17]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[17]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[17]~output .bus_hold = "false"; +defparam \GPIO_0[17]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N16 +cycloneive_io_obuf \GPIO_0[18]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[18]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[18]~output .bus_hold = "false"; +defparam \GPIO_0[18]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N23 +cycloneive_io_obuf \GPIO_0[19]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[19]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[19]~output .bus_hold = "false"; +defparam \GPIO_0[19]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N9 +cycloneive_io_obuf \GPIO_0[20]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[20]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[20]~output .bus_hold = "false"; +defparam \GPIO_0[20]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N16 +cycloneive_io_obuf \GPIO_0[21]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[21]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[21]~output .bus_hold = "false"; +defparam \GPIO_0[21]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y34_N2 +cycloneive_io_obuf \GPIO_0[22]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[22]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[22]~output .bus_hold = "false"; +defparam \GPIO_0[22]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X29_Y34_N16 +cycloneive_io_obuf \GPIO_0[23]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[23]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[23]~output .bus_hold = "false"; +defparam \GPIO_0[23]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N2 +cycloneive_io_obuf \GPIO_0[24]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[24]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[24]~output .bus_hold = "false"; +defparam \GPIO_0[24]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N9 +cycloneive_io_obuf \GPIO_0[25]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[25]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[25]~output .bus_hold = "false"; +defparam \GPIO_0[25]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N9 +cycloneive_io_obuf \GPIO_0[26]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[26]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[26]~output .bus_hold = "false"; +defparam \GPIO_0[26]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N16 +cycloneive_io_obuf \GPIO_0[27]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[27]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[27]~output .bus_hold = "false"; +defparam \GPIO_0[27]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X38_Y34_N2 +cycloneive_io_obuf \GPIO_0[28]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[28]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[28]~output .bus_hold = "false"; +defparam \GPIO_0[28]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X40_Y34_N9 +cycloneive_io_obuf \GPIO_0[29]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[29]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[29]~output .bus_hold = "false"; +defparam \GPIO_0[29]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N16 +cycloneive_io_obuf \GPIO_0[30]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[30]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[30]~output .bus_hold = "false"; +defparam \GPIO_0[30]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N16 +cycloneive_io_obuf \GPIO_0[31]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[31]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[31]~output .bus_hold = "false"; +defparam \GPIO_0[31]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N23 +cycloneive_io_obuf \GPIO_0[32]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[32]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[32]~output .bus_hold = "false"; +defparam \GPIO_0[32]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N23 +cycloneive_io_obuf \GPIO_0[33]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[33]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[33]~output .bus_hold = "false"; +defparam \GPIO_0[33]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -334,7 +1163,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 +// Location: LCCOMB_X31_Y7_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -351,7 +1180,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X31_Y7_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -370,7 +1199,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 +// Location: LCCOMB_X31_Y7_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -388,7 +1217,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N13 +// Location: FF_X31_Y7_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -407,7 +1236,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N14 +// Location: LCCOMB_X31_Y7_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -425,7 +1254,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N15 +// Location: FF_X31_Y7_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -444,7 +1273,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 +// Location: LCCOMB_X31_Y7_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -462,7 +1291,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N17 +// Location: FF_X31_Y7_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -481,7 +1310,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N18 +// Location: LCCOMB_X31_Y7_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -499,7 +1328,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N19 +// Location: FF_X31_Y7_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -518,7 +1347,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N20 +// Location: LCCOMB_X31_Y7_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -536,7 +1365,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N21 +// Location: FF_X31_Y7_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -555,7 +1384,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N22 +// Location: LCCOMB_X31_Y7_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -573,7 +1402,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N23 +// Location: FF_X31_Y7_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -592,7 +1421,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 +// Location: LCCOMB_X31_Y7_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -610,7 +1439,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N25 +// Location: FF_X31_Y7_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -629,7 +1458,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 +// Location: LCCOMB_X31_Y7_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -647,7 +1476,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N27 +// Location: FF_X31_Y7_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -666,7 +1495,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N28 +// Location: LCCOMB_X31_Y7_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -684,7 +1513,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N29 +// Location: FF_X31_Y7_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -703,7 +1532,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 +// Location: LCCOMB_X31_Y7_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -721,7 +1550,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N31 +// Location: FF_X31_Y7_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -740,7 +1569,7 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N0 +// Location: LCCOMB_X31_Y6_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) @@ -758,7 +1587,7 @@ defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N1 +// Location: FF_X31_Y6_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[11]~41_combout ), @@ -777,7 +1606,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N2 +// Location: LCCOMB_X31_Y6_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -795,7 +1624,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N3 +// Location: FF_X31_Y6_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -814,7 +1643,7 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N4 +// Location: LCCOMB_X31_Y6_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) @@ -832,7 +1661,7 @@ defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N5 +// Location: FF_X31_Y6_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -851,7 +1680,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N6 +// Location: LCCOMB_X31_Y6_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -869,7 +1698,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N7 +// Location: FF_X31_Y6_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -888,25 +1717,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N8 +// Location: LCCOMB_X31_Y6_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(counter[15]), - .datab(gnd), + .dataa(gnd), + .datab(counter[15]), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hA50A; +defparam \counter[15]~49 .lut_mask = 16'hC30C; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N9 +// Location: FF_X31_Y6_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -925,7 +1754,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N10 +// Location: LCCOMB_X31_Y6_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -943,7 +1772,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N11 +// Location: FF_X31_Y6_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -962,7 +1791,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N12 +// Location: LCCOMB_X31_Y6_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -980,7 +1809,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N13 +// Location: FF_X31_Y6_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -999,7 +1828,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N14 +// Location: LCCOMB_X31_Y6_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1017,7 +1846,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N15 +// Location: FF_X31_Y6_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1036,7 +1865,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 +// Location: LCCOMB_X31_Y6_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1054,7 +1883,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N17 +// Location: FF_X31_Y6_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1073,7 +1902,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N18 +// Location: LCCOMB_X31_Y6_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1091,7 +1920,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N19 +// Location: FF_X31_Y6_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1110,7 +1939,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N20 +// Location: LCCOMB_X31_Y6_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1127,7 +1956,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N21 +// Location: FF_X31_Y6_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1146,7 +1975,24 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N24 +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[20] & !counter[21]) + + .dataa(counter[20]), + .datab(gnd), + .datac(counter[21]), + .datad(gnd), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0505; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N24 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): // \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) @@ -1163,7 +2009,7 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N4 +// Location: LCCOMB_X31_Y7_N4 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): // \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) @@ -1180,15 +2026,15 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 +// Location: LCCOMB_X31_Y7_N10 cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) .dataa(counter[6]), - .datab(counter[4]), - .datac(counter[7]), - .datad(counter[5]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), .cin(gnd), .combout(\Equal0~1_combout ), .cout()); @@ -1197,14 +2043,14 @@ defparam \Equal0~1 .lut_mask = 16'h0001; defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N26 +// Location: LCCOMB_X31_Y7_N8 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) +// \Equal0~2_combout = (!counter[8] & (!counter[9] & (!counter[10] & !counter[11]))) - .dataa(counter[10]), + .dataa(counter[8]), .datab(counter[9]), - .datac(counter[8]), + .datac(counter[10]), .datad(counter[11]), .cin(gnd), .combout(\Equal0~2_combout ), @@ -1214,7 +2060,7 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N30 +// Location: LCCOMB_X31_Y6_N30 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): // \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) @@ -1231,7 +2077,7 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N28 +// Location: LCCOMB_X30_Y7_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): // \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) @@ -1248,44 +2094,27 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \Equal0~6 ( +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \A[0]~40 ( // Equation(s): -// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) +// \A[0]~40_combout = A[0] $ (((\Equal0~7_combout & (\Equal0~5_combout & \Equal0~4_combout )))) - .dataa(counter[20]), - .datab(counter[21]), - .datac(\Equal0~5_combout ), + .dataa(\Equal0~7_combout ), + .datab(\Equal0~5_combout ), + .datac(A[0]), .datad(\Equal0~4_combout ), .cin(gnd), - .combout(\Equal0~6_combout ), + .combout(\A[0]~40_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h1000; -defparam \Equal0~6 .sum_lutc_input = "datac"; +defparam \A[0]~40 .lut_mask = 16'h78F0; +defparam \A[0]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \A[0]~39 ( -// Equation(s): -// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(A[0]), - .datad(\Equal0~6_combout ), - .cin(gnd), - .combout(\A[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \A[0]~39 .lut_mask = 16'h0FF0; -defparam \A[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 +// Location: FF_X31_Y7_N1 dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[0]~39_combout ), + .d(\A[0]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1301,28 +2130,45 @@ defparam \A[0] .is_wysiwyg = "true"; defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \A[1]~13 ( +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \A[1]~14 ( // Equation(s): -// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) -// \A[1]~14 = CARRY((A[1] & A[0])) +// \A[1]~14_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~15 = CARRY((A[1] & A[0])) .dataa(A[1]), .datab(A[0]), .datac(gnd), .datad(vcc), .cin(gnd), - .combout(\A[1]~13_combout ), - .cout(\A[1]~14 )); + .combout(\A[1]~14_combout ), + .cout(\A[1]~15 )); // synopsys translate_off -defparam \A[1]~13 .lut_mask = 16'h6688; -defparam \A[1]~13 .sum_lutc_input = "datac"; +defparam \A[1]~14 .lut_mask = 16'h6688; +defparam \A[1]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y14_N1 +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \Equal0~6 ( +// Equation(s): +// \Equal0~6_combout = (!counter[21] & (!counter[20] & (\Equal0~5_combout & \Equal0~4_combout ))) + + .dataa(counter[21]), + .datab(counter[20]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~6 .lut_mask = 16'h1000; +defparam \Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N1 dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[1]~13_combout ), + .d(\A[1]~14_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1338,28 +2184,28 @@ defparam \A[1] .is_wysiwyg = "true"; defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \A[2]~15 ( +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \A[2]~16 ( // Equation(s): -// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) -// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) +// \A[2]~16_combout = (A[2] & (!\A[1]~15 )) # (!A[2] & ((\A[1]~15 ) # (GND))) +// \A[2]~17 = CARRY((!\A[1]~15 ) # (!A[2])) .dataa(gnd), .datab(A[2]), .datac(gnd), .datad(vcc), - .cin(\A[1]~14 ), - .combout(\A[2]~15_combout ), - .cout(\A[2]~16 )); + .cin(\A[1]~15 ), + .combout(\A[2]~16_combout ), + .cout(\A[2]~17 )); // synopsys translate_off -defparam \A[2]~15 .lut_mask = 16'h3C3F; -defparam \A[2]~15 .sum_lutc_input = "cin"; +defparam \A[2]~16 .lut_mask = 16'h3C3F; +defparam \A[2]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N3 +// Location: FF_X30_Y7_N3 dffeas \A[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[2]~15_combout ), + .d(\A[2]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1375,28 +2221,28 @@ defparam \A[2] .is_wysiwyg = "true"; defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \A[3]~17 ( +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \A[3]~18 ( // Equation(s): -// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) -// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) +// \A[3]~18_combout = (A[3] & (\A[2]~17 $ (GND))) # (!A[3] & (!\A[2]~17 & VCC)) +// \A[3]~19 = CARRY((A[3] & !\A[2]~17 )) .dataa(gnd), .datab(A[3]), .datac(gnd), .datad(vcc), - .cin(\A[2]~16 ), - .combout(\A[3]~17_combout ), - .cout(\A[3]~18 )); + .cin(\A[2]~17 ), + .combout(\A[3]~18_combout ), + .cout(\A[3]~19 )); // synopsys translate_off -defparam \A[3]~17 .lut_mask = 16'hC30C; -defparam \A[3]~17 .sum_lutc_input = "cin"; +defparam \A[3]~18 .lut_mask = 16'hC30C; +defparam \A[3]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N5 +// Location: FF_X30_Y7_N5 dffeas \A[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[3]~17_combout ), + .d(\A[3]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1412,28 +2258,28 @@ defparam \A[3] .is_wysiwyg = "true"; defparam \A[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \A[4]~19 ( +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \A[4]~20 ( // Equation(s): -// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) -// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) +// \A[4]~20_combout = (A[4] & (!\A[3]~19 )) # (!A[4] & ((\A[3]~19 ) # (GND))) +// \A[4]~21 = CARRY((!\A[3]~19 ) # (!A[4])) .dataa(A[4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[3]~18 ), - .combout(\A[4]~19_combout ), - .cout(\A[4]~20 )); + .cin(\A[3]~19 ), + .combout(\A[4]~20_combout ), + .cout(\A[4]~21 )); // synopsys translate_off -defparam \A[4]~19 .lut_mask = 16'h5A5F; -defparam \A[4]~19 .sum_lutc_input = "cin"; +defparam \A[4]~20 .lut_mask = 16'h5A5F; +defparam \A[4]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N7 +// Location: FF_X30_Y7_N7 dffeas \A[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[4]~19_combout ), + .d(\A[4]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1449,28 +2295,28 @@ defparam \A[4] .is_wysiwyg = "true"; defparam \A[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \A[5]~21 ( +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \A[5]~22 ( // Equation(s): -// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) -// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) +// \A[5]~22_combout = (A[5] & (\A[4]~21 $ (GND))) # (!A[5] & (!\A[4]~21 & VCC)) +// \A[5]~23 = CARRY((A[5] & !\A[4]~21 )) .dataa(gnd), .datab(A[5]), .datac(gnd), .datad(vcc), - .cin(\A[4]~20 ), - .combout(\A[5]~21_combout ), - .cout(\A[5]~22 )); + .cin(\A[4]~21 ), + .combout(\A[5]~22_combout ), + .cout(\A[5]~23 )); // synopsys translate_off -defparam \A[5]~21 .lut_mask = 16'hC30C; -defparam \A[5]~21 .sum_lutc_input = "cin"; +defparam \A[5]~22 .lut_mask = 16'hC30C; +defparam \A[5]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N9 +// Location: FF_X30_Y7_N9 dffeas \A[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[5]~21_combout ), + .d(\A[5]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1486,28 +2332,28 @@ defparam \A[5] .is_wysiwyg = "true"; defparam \A[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \A[6]~23 ( +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \A[6]~24 ( // Equation(s): -// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) -// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) +// \A[6]~24_combout = (A[6] & (!\A[5]~23 )) # (!A[6] & ((\A[5]~23 ) # (GND))) +// \A[6]~25 = CARRY((!\A[5]~23 ) # (!A[6])) .dataa(A[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[5]~22 ), - .combout(\A[6]~23_combout ), - .cout(\A[6]~24 )); + .cin(\A[5]~23 ), + .combout(\A[6]~24_combout ), + .cout(\A[6]~25 )); // synopsys translate_off -defparam \A[6]~23 .lut_mask = 16'h5A5F; -defparam \A[6]~23 .sum_lutc_input = "cin"; +defparam \A[6]~24 .lut_mask = 16'h5A5F; +defparam \A[6]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N11 +// Location: FF_X30_Y7_N11 dffeas \A[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[6]~23_combout ), + .d(\A[6]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1523,28 +2369,28 @@ defparam \A[6] .is_wysiwyg = "true"; defparam \A[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \A[7]~25 ( +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \A[7]~26 ( // Equation(s): -// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) -// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) +// \A[7]~26_combout = (A[7] & (\A[6]~25 $ (GND))) # (!A[7] & (!\A[6]~25 & VCC)) +// \A[7]~27 = CARRY((A[7] & !\A[6]~25 )) .dataa(A[7]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[6]~24 ), - .combout(\A[7]~25_combout ), - .cout(\A[7]~26 )); + .cin(\A[6]~25 ), + .combout(\A[7]~26_combout ), + .cout(\A[7]~27 )); // synopsys translate_off -defparam \A[7]~25 .lut_mask = 16'hA50A; -defparam \A[7]~25 .sum_lutc_input = "cin"; +defparam \A[7]~26 .lut_mask = 16'hA50A; +defparam \A[7]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N13 +// Location: FF_X30_Y7_N13 dffeas \A[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[7]~25_combout ), + .d(\A[7]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1560,28 +2406,28 @@ defparam \A[7] .is_wysiwyg = "true"; defparam \A[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \A[8]~27 ( +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \A[8]~28 ( // Equation(s): -// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) -// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) +// \A[8]~28_combout = (A[8] & (!\A[7]~27 )) # (!A[8] & ((\A[7]~27 ) # (GND))) +// \A[8]~29 = CARRY((!\A[7]~27 ) # (!A[8])) - .dataa(A[8]), - .datab(gnd), + .dataa(gnd), + .datab(A[8]), .datac(gnd), .datad(vcc), - .cin(\A[7]~26 ), - .combout(\A[8]~27_combout ), - .cout(\A[8]~28 )); + .cin(\A[7]~27 ), + .combout(\A[8]~28_combout ), + .cout(\A[8]~29 )); // synopsys translate_off -defparam \A[8]~27 .lut_mask = 16'h5A5F; -defparam \A[8]~27 .sum_lutc_input = "cin"; +defparam \A[8]~28 .lut_mask = 16'h3C3F; +defparam \A[8]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N15 +// Location: FF_X30_Y7_N15 dffeas \A[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[8]~27_combout ), + .d(\A[8]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1597,28 +2443,28 @@ defparam \A[8] .is_wysiwyg = "true"; defparam \A[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \A[9]~29 ( +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \A[9]~30 ( // Equation(s): -// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) -// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) +// \A[9]~30_combout = (A[9] & (\A[8]~29 $ (GND))) # (!A[9] & (!\A[8]~29 & VCC)) +// \A[9]~31 = CARRY((A[9] & !\A[8]~29 )) .dataa(gnd), .datab(A[9]), .datac(gnd), .datad(vcc), - .cin(\A[8]~28 ), - .combout(\A[9]~29_combout ), - .cout(\A[9]~30 )); + .cin(\A[8]~29 ), + .combout(\A[9]~30_combout ), + .cout(\A[9]~31 )); // synopsys translate_off -defparam \A[9]~29 .lut_mask = 16'hC30C; -defparam \A[9]~29 .sum_lutc_input = "cin"; +defparam \A[9]~30 .lut_mask = 16'hC30C; +defparam \A[9]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N17 +// Location: FF_X30_Y7_N17 dffeas \A[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[9]~29_combout ), + .d(\A[9]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1634,28 +2480,28 @@ defparam \A[9] .is_wysiwyg = "true"; defparam \A[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \A[10]~31 ( +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \A[10]~32 ( // Equation(s): -// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) -// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) +// \A[10]~32_combout = (A[10] & (!\A[9]~31 )) # (!A[10] & ((\A[9]~31 ) # (GND))) +// \A[10]~33 = CARRY((!\A[9]~31 ) # (!A[10])) .dataa(gnd), .datab(A[10]), .datac(gnd), .datad(vcc), - .cin(\A[9]~30 ), - .combout(\A[10]~31_combout ), - .cout(\A[10]~32 )); + .cin(\A[9]~31 ), + .combout(\A[10]~32_combout ), + .cout(\A[10]~33 )); // synopsys translate_off -defparam \A[10]~31 .lut_mask = 16'h3C3F; -defparam \A[10]~31 .sum_lutc_input = "cin"; +defparam \A[10]~32 .lut_mask = 16'h3C3F; +defparam \A[10]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N19 +// Location: FF_X30_Y7_N19 dffeas \A[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[10]~31_combout ), + .d(\A[10]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1671,28 +2517,28 @@ defparam \A[10] .is_wysiwyg = "true"; defparam \A[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \A[11]~33 ( +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \A[11]~34 ( // Equation(s): -// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) -// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) +// \A[11]~34_combout = (A[11] & (\A[10]~33 $ (GND))) # (!A[11] & (!\A[10]~33 & VCC)) +// \A[11]~35 = CARRY((A[11] & !\A[10]~33 )) .dataa(gnd), .datab(A[11]), .datac(gnd), .datad(vcc), - .cin(\A[10]~32 ), - .combout(\A[11]~33_combout ), - .cout(\A[11]~34 )); + .cin(\A[10]~33 ), + .combout(\A[11]~34_combout ), + .cout(\A[11]~35 )); // synopsys translate_off -defparam \A[11]~33 .lut_mask = 16'hC30C; -defparam \A[11]~33 .sum_lutc_input = "cin"; +defparam \A[11]~34 .lut_mask = 16'hC30C; +defparam \A[11]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N21 +// Location: FF_X30_Y7_N21 dffeas \A[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[11]~33_combout ), + .d(\A[11]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1708,28 +2554,28 @@ defparam \A[11] .is_wysiwyg = "true"; defparam \A[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \A[12]~35 ( +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \A[12]~36 ( // Equation(s): -// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) -// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) +// \A[12]~36_combout = (A[12] & (!\A[11]~35 )) # (!A[12] & ((\A[11]~35 ) # (GND))) +// \A[12]~37 = CARRY((!\A[11]~35 ) # (!A[12])) .dataa(A[12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[11]~34 ), - .combout(\A[12]~35_combout ), - .cout(\A[12]~36 )); + .cin(\A[11]~35 ), + .combout(\A[12]~36_combout ), + .cout(\A[12]~37 )); // synopsys translate_off -defparam \A[12]~35 .lut_mask = 16'h5A5F; -defparam \A[12]~35 .sum_lutc_input = "cin"; +defparam \A[12]~36 .lut_mask = 16'h5A5F; +defparam \A[12]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N23 +// Location: FF_X30_Y7_N23 dffeas \A[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[12]~35_combout ), + .d(\A[12]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1745,27 +2591,28 @@ defparam \A[12] .is_wysiwyg = "true"; defparam \A[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \A[13]~37 ( +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \A[13]~38 ( // Equation(s): -// \A[13]~37_combout = \A[12]~36 $ (!A[13]) +// \A[13]~38_combout = (A[13] & (\A[12]~37 $ (GND))) # (!A[13] & (!\A[12]~37 & VCC)) +// \A[13]~39 = CARRY((A[13] & !\A[12]~37 )) .dataa(gnd), - .datab(gnd), + .datab(A[13]), .datac(gnd), - .datad(A[13]), - .cin(\A[12]~36 ), - .combout(\A[13]~37_combout ), - .cout()); + .datad(vcc), + .cin(\A[12]~37 ), + .combout(\A[13]~38_combout ), + .cout(\A[13]~39 )); // synopsys translate_off -defparam \A[13]~37 .lut_mask = 16'hF00F; -defparam \A[13]~37 .sum_lutc_input = "cin"; +defparam \A[13]~38 .lut_mask = 16'hC30C; +defparam \A[13]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N25 +// Location: FF_X30_Y7_N25 dffeas \A[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[13]~37_combout ), + .d(\A[13]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1781,301 +2628,8 @@ defparam \A[13] .is_wysiwyg = "true"; defparam \A[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2098,39 +2652,1216 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X32_Y26_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N3 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N5 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y28_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X21_Y31_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y28_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .lut_mask = 16'hFA50; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N18 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .lut_mask = 16'hFC0C; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N26 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -2186,97 +3917,81 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] - - .dataa(gnd), - .datab(gnd), - .datac(A[13]), - .datad(gnd), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N16 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - .dataa(gnd), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datab(gnd), - .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y14_N17 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2332,7 +4047,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y21_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2388,25 +4103,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X21_Y28_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hAAF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2462,7 +4177,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y15_N0 +// Location: M9K_X22_Y12_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -2518,81 +4233,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(A[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 +// Location: M9K_X22_Y27_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(vcc), .portare(vcc), @@ -2648,22 +4307,3086 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N30 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y29_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .lut_mask = 16'hF5A0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \A[14]~41 ( +// Equation(s): +// \A[14]~41_combout = A[14] $ (\A[13]~39 ) + + .dataa(A[14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\A[13]~39 ), + .combout(\A[14]~41_combout ), + .cout()); +// synopsys translate_off +defparam \A[14]~41 .lut_mask = 16'h5A5A; +defparam \A[14]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X30_Y7_N27 +dffeas \A[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[14]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[14]), + .prn(vcc)); +// synopsys translate_off +defparam \A[14] .is_wysiwyg = "true"; +defparam \A[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00F0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout = (A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .lut_mask = 16'hF000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2] = (!A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .lut_mask = 16'h000F; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout = (!A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .lut_mask = 16'h0F00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout = A[14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N1 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hAAE4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .lut_mask = 16'hF2C2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hB9A8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hEE50; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .lut_mask = 16'hEE22; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N14 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .lut_mask = 16'hF3C0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .lut_mask = 16'hFA0A; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; @@ -2682,4 +7405,72 @@ assign LED[6] = \LED[6]~output_o ; assign LED[7] = \LED[7]~output_o ; +assign GPIO_0[0] = \GPIO_0[0]~output_o ; + +assign GPIO_0[1] = \GPIO_0[1]~output_o ; + +assign GPIO_0[2] = \GPIO_0[2]~output_o ; + +assign GPIO_0[3] = \GPIO_0[3]~output_o ; + +assign GPIO_0[4] = \GPIO_0[4]~output_o ; + +assign GPIO_0[5] = \GPIO_0[5]~output_o ; + +assign GPIO_0[6] = \GPIO_0[6]~output_o ; + +assign GPIO_0[7] = \GPIO_0[7]~output_o ; + +assign GPIO_0[8] = \GPIO_0[8]~output_o ; + +assign GPIO_0[9] = \GPIO_0[9]~output_o ; + +assign GPIO_0[10] = \GPIO_0[10]~output_o ; + +assign GPIO_0[11] = \GPIO_0[11]~output_o ; + +assign GPIO_0[12] = \GPIO_0[12]~output_o ; + +assign GPIO_0[13] = \GPIO_0[13]~output_o ; + +assign GPIO_0[14] = \GPIO_0[14]~output_o ; + +assign GPIO_0[15] = \GPIO_0[15]~output_o ; + +assign GPIO_0[16] = \GPIO_0[16]~output_o ; + +assign GPIO_0[17] = \GPIO_0[17]~output_o ; + +assign GPIO_0[18] = \GPIO_0[18]~output_o ; + +assign GPIO_0[19] = \GPIO_0[19]~output_o ; + +assign GPIO_0[20] = \GPIO_0[20]~output_o ; + +assign GPIO_0[21] = \GPIO_0[21]~output_o ; + +assign GPIO_0[22] = \GPIO_0[22]~output_o ; + +assign GPIO_0[23] = \GPIO_0[23]~output_o ; + +assign GPIO_0[24] = \GPIO_0[24]~output_o ; + +assign GPIO_0[25] = \GPIO_0[25]~output_o ; + +assign GPIO_0[26] = \GPIO_0[26]~output_o ; + +assign GPIO_0[27] = \GPIO_0[27]~output_o ; + +assign GPIO_0[28] = \GPIO_0[28]~output_o ; + +assign GPIO_0[29] = \GPIO_0[29]~output_o ; + +assign GPIO_0[30] = \GPIO_0[30]~output_o ; + +assign GPIO_0[31] = \GPIO_0[31]~output_o ; + +assign GPIO_0[32] = \GPIO_0[32]~output_o ; + +assign GPIO_0[33] = \GPIO_0[33]~output_o ; + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index bc38df0..01c0119 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:47:24") + (DATE "03/30/2022 14:56:19") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2068:2068:2068) (2050:2050:2050)) + (PORT i (1004:1004:1004) (994:994:994)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2478:2478:2478) (2480:2480:2480)) + (PORT i (1778:1778:1778) (1774:1774:1774)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2467:2467:2467) (2430:2430:2430)) + (PORT i (1450:1450:1450) (1402:1402:1402)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1746:1746:1746) (1704:1704:1704)) + (PORT i (2368:2368:2368) (2471:2471:2471)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2240:2240:2240) (2238:2238:2238)) + (PORT i (1162:1162:1162) (1183:1183:1183)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1807:1807:1807) (1820:1820:1820)) + (PORT i (1234:1234:1234) (1203:1203:1203)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2185:2185:2185) (2116:2116:2116)) + (PORT i (1516:1516:1516) (1500:1500:1500)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) ) ) @@ -111,11 +111,331 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1193:1193:1193) (1143:1143:1143)) + (PORT i (1389:1389:1389) (1434:1434:1434)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1317:1317:1317) (1314:1314:1314)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1397:1397:1397) (1382:1382:1382)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (976:976:976) (928:928:928)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1838:1838:1838) (1871:1871:1871)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1325:1325:1325) (1272:1272:1272)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1187:1187:1187) (1148:1148:1148)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1602:1602:1602) (1537:1537:1537)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1159:1159:1159) (1110:1110:1110)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1685:1685:1685) (1678:1678:1678)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1352:1352:1352) (1358:1358:1358)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (925:925:925) (865:865:865)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1235:1235:1235) (1213:1213:1213)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1021:1021:1021) (998:998:998)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1251:1251:1251) (1233:1233:1233)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1616:1616:1616) (1570:1570:1570)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1482:1482:1482) (1481:1481:1481)) + (IOPATH i o (4033:4033:4033) (3610:3610:3610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[16\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2255:2255:2255) (2227:2227:2227)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[17\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2180:2180:2180) (2170:2170:2170)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[18\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2525:2525:2525) (2541:2541:2541)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[19\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1758:1758:1758) (1740:1740:1740)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[20\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1756:1756:1756) (1741:1741:1741)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[21\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2041:2041:2041) (2016:2016:2016)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[22\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1862:1862:1862) (1800:1800:1800)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[23\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1967:1967:1967) (1975:1975:1975)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[24\]\~output) + (DELAY + (ABSOLUTE + (PORT i (785:785:785) (779:779:779)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[25\]\~output) + (DELAY + (ABSOLUTE + (PORT i (753:753:753) (758:758:758)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[26\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1086:1086:1086) (1040:1040:1040)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[27\]\~output) + (DELAY + (ABSOLUTE + (PORT i (962:962:962) (941:941:941)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[28\]\~output) + (DELAY + (ABSOLUTE + (PORT i (945:945:945) (920:920:920)) + (IOPATH i o (4033:4033:4033) (3610:3610:3610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[29\]\~output) + (DELAY + (ABSOLUTE + (PORT i (912:912:912) (884:884:884)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[30\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1348:1348:1348) (1305:1305:1305)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[31\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1321:1321:1321) (1269:1269:1269)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -148,7 +468,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -177,7 +497,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -205,7 +525,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -233,7 +553,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -247,7 +567,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (301:301:301)) + (PORT datab (228:228:228) (299:299:299)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -261,7 +581,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -275,7 +595,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (300:300:300)) + (PORT datab (240:240:240) (309:309:309)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -289,7 +609,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -317,7 +637,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -331,7 +651,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (239:239:239) (308:308:308)) + (PORT datab (226:226:226) (299:299:299)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -345,7 +665,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -359,7 +679,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (312:312:312)) + (PORT dataa (229:229:229) (305:305:305)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -373,7 +693,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -387,7 +707,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (238:238:238) (307:307:307)) + (PORT datab (226:226:226) (298:298:298)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -401,7 +721,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -415,7 +735,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (312:312:312)) + (PORT dataa (228:228:228) (302:302:302)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -429,7 +749,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -457,7 +777,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -471,7 +791,7 @@ (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (297:297:297)) + (PORT datab (381:381:381) (418:418:418)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -485,7 +805,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -513,7 +833,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -541,7 +861,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -555,9 +875,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (426:426:426)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (227:227:227) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -569,7 +889,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -597,7 +917,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -625,7 +945,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -653,7 +973,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -681,7 +1001,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -709,7 +1029,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1699:1699:1699)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -734,7 +1054,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1699:1699:1699)) + (PORT clk (1346:1346:1346) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -743,6 +1063,18 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (684:684:684)) + (PORT datac (646:646:646) (673:673:673)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) @@ -750,7 +1082,7 @@ (ABSOLUTE (PORT dataa (230:230:230) (307:307:307)) (PORT datab (227:227:227) (299:299:299)) - (PORT datac (201:201:201) (271:271:271)) + (PORT datac (201:201:201) (272:272:272)) (PORT datad (205:205:205) (267:267:267)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) @@ -765,7 +1097,7 @@ (DELAY (ABSOLUTE (PORT dataa (229:229:229) (305:305:305)) - (PORT datab (226:226:226) (298:298:298)) + (PORT datab (226:226:226) (299:299:299)) (PORT datac (200:200:200) (270:270:270)) (PORT datad (203:203:203) (265:265:265)) (IOPATH dataa combout (309:309:309) (326:326:326)) @@ -781,8 +1113,8 @@ (DELAY (ABSOLUTE (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datac (353:353:353) (392:392:392)) + (PORT datab (229:229:229) (302:302:302)) + (PORT datac (352:352:352) (391:391:391)) (PORT datad (205:205:205) (267:267:267)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) @@ -796,10 +1128,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (419:419:419) (453:453:453)) - (PORT datab (379:379:379) (422:422:422)) - (PORT datac (533:533:533) (544:544:544)) - (PORT datad (537:537:537) (553:553:553)) + (PORT dataa (231:231:231) (308:308:308)) + (PORT datab (228:228:228) (301:301:301)) + (PORT datac (203:203:203) (275:275:275)) + (PORT datad (353:353:353) (388:388:388)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -813,9 +1145,9 @@ (DELAY (ABSOLUTE (PORT dataa (232:232:232) (310:310:310)) - (PORT datab (241:241:241) (311:311:311)) + (PORT datab (229:229:229) (303:303:303)) (PORT datac (216:216:216) (283:283:283)) - (PORT datad (206:206:206) (268:268:268)) + (PORT datad (219:219:219) (277:277:277)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -828,10 +1160,10 @@ (INSTANCE Equal0\~4) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (368:368:368)) - (PORT datab (323:323:323) (337:337:337)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (586:586:586) (583:583:583)) + (PORT dataa (366:366:366) (368:368:368)) + (PORT datab (326:326:326) (341:341:341)) + (PORT datac (326:326:326) (330:330:330)) + (PORT datad (562:562:562) (556:556:556)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -841,26 +1173,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~6) + (INSTANCE A\[0\]\~40) (DELAY (ABSOLUTE - (PORT dataa (826:826:826) (842:842:842)) - (PORT datab (861:861:861) (867:867:867)) - (PORT datac (571:571:571) (562:562:562)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT datad (308:308:308) (313:313:313)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (585:585:585) (577:577:577)) + (PORT datad (331:331:331) (338:338:338)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -871,7 +1191,7 @@ (INSTANCE A\[0\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -882,11 +1202,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[1\]\~13) + (INSTANCE A\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (463:463:463)) - (PORT datab (575:575:575) (602:602:602)) + (PORT dataa (418:418:418) (472:472:472)) + (PORT datab (414:414:414) (460:460:460)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -895,14 +1215,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (847:847:847)) + (PORT datab (623:623:623) (657:657:657)) + (PORT datac (532:532:532) (528:528:528)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE A\[1\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -913,7 +1249,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[2\]\~15) + (INSTANCE A\[2\]\~16) (DELAY (ABSOLUTE (PORT datab (238:238:238) (307:307:307)) @@ -930,9 +1266,9 @@ (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -943,7 +1279,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[3\]\~17) + (INSTANCE A\[3\]\~18) (DELAY (ABSOLUTE (PORT datab (239:239:239) (307:307:307)) @@ -960,9 +1296,9 @@ (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -973,7 +1309,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[4\]\~19) + (INSTANCE A\[4\]\~20) (DELAY (ABSOLUTE (PORT dataa (241:241:241) (313:313:313)) @@ -990,9 +1326,9 @@ (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (754:754:754) (770:770:770)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1003,10 +1339,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[5\]\~21) + (INSTANCE A\[5\]\~22) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (308:308:308)) + (PORT datab (258:258:258) (327:327:327)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1020,9 +1356,9 @@ (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1033,10 +1369,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[6\]\~23) + (INSTANCE A\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) + (PORT dataa (259:259:259) (334:334:334)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1050,9 +1386,9 @@ (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1063,10 +1399,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[7\]\~25) + (INSTANCE A\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) + (PORT dataa (259:259:259) (334:334:334)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1080,9 +1416,9 @@ (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1093,12 +1429,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[8\]\~27) + (INSTANCE A\[8\]\~28) (DELAY (ABSOLUTE - (PORT dataa (373:373:373) (423:423:423)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (259:259:259) (329:329:329)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -1110,9 +1446,9 @@ (INSTANCE A\[8\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1123,10 +1459,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[9\]\~29) + (INSTANCE A\[9\]\~30) (DELAY (ABSOLUTE - (PORT datab (259:259:259) (329:329:329)) + (PORT datab (241:241:241) (310:310:310)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1140,9 +1476,9 @@ (INSTANCE A\[9\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1153,7 +1489,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[10\]\~31) + (INSTANCE A\[10\]\~32) (DELAY (ABSOLUTE (PORT datab (241:241:241) (310:310:310)) @@ -1170,9 +1506,9 @@ (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1183,10 +1519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[11\]\~33) + (INSTANCE A\[11\]\~34) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (311:311:311)) + (PORT datab (259:259:259) (329:329:329)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1200,9 +1536,9 @@ (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1213,7 +1549,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[12\]\~35) + (INSTANCE A\[12\]\~36) (DELAY (ABSOLUTE (PORT dataa (242:242:242) (314:314:314)) @@ -1230,9 +1566,9 @@ (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1673:1673:1673) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (728:728:728) (735:735:735)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1243,12 +1579,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[13\]\~37) + (INSTANCE A\[13\]\~38) (DELAY (ABSOLUTE - (PORT datad (235:235:235) (292:292:292)) + (PORT datab (258:258:258) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) @@ -1257,9 +1596,9 @@ (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) + (PORT ena (754:754:754) (770:770:770)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1270,11 +1609,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (965:965:965) (986:986:986)) - (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (1889:1889:1889) (2031:2031:2031)) + (PORT d[1] (1875:1875:1875) (1962:1962:1962)) + (PORT d[2] (1726:1726:1726) (1801:1801:1801)) + (PORT d[3] (2301:2301:2301) (2375:2375:2375)) + (PORT d[4] (2031:2031:2031) (2119:2119:2119)) + (PORT d[5] (2026:2026:2026) (2091:2091:2091)) + (PORT d[6] (1989:1989:1989) (2041:2041:2041)) + (PORT d[7] (1895:1895:1895) (2026:2026:2026)) + (PORT d[8] (2179:2179:2179) (2233:2233:2233)) + (PORT d[9] (2010:2010:2010) (2105:2105:2105)) + (PORT d[10] (2114:2114:2114) (2221:2221:2221)) + (PORT d[11] (2121:2121:2121) (2200:2200:2200)) + (PORT d[12] (2184:2184:2184) (2285:2285:2285)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -1283,84 +1634,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (967:967:967) (1018:1018:1018)) - (PORT d[1] (1372:1372:1372) (1392:1392:1392)) - (PORT d[2] (884:884:884) (921:921:921)) - (PORT d[3] (941:941:941) (967:967:967)) - (PORT d[4] (941:941:941) (967:967:967)) - (PORT d[5] (720:720:720) (753:753:753)) - (PORT d[6] (720:720:720) (753:753:753)) - (PORT d[7] (720:720:720) (753:753:753)) - (PORT d[8] (720:720:720) (753:753:753)) - (PORT d[9] (720:720:720) (753:753:753)) - (PORT d[10] (720:720:720) (753:753:753)) - (PORT d[11] (720:720:720) (753:753:753)) - (PORT d[12] (720:720:720) (753:753:753)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + (PORT d[0] (1682:1682:1682) (1734:1734:1734)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) + (PORT clk (1609:1609:1609) (1637:1637:1637)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -1371,865 +1668,58 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (969:969:969) (990:990:990)) - (PORT clk (1611:1611:1611) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (949:949:949) (1000:1000:1000)) - (PORT d[1] (1373:1373:1373) (1393:1393:1393)) - (PORT d[2] (907:907:907) (939:939:939)) - (PORT d[3] (1154:1154:1154) (1170:1170:1170)) - (PORT d[4] (893:893:893) (932:932:932)) - (PORT d[5] (1441:1441:1441) (1466:1466:1466)) - (PORT d[6] (1147:1147:1147) (1174:1174:1174)) - (PORT d[7] (1183:1183:1183) (1221:1221:1221)) - (PORT d[8] (1128:1128:1128) (1149:1149:1149)) - (PORT d[9] (1143:1143:1143) (1180:1180:1180)) - (PORT d[10] (1158:1158:1158) (1183:1183:1183)) - (PORT d[11] (1143:1143:1143) (1170:1170:1170)) - (PORT d[12] (1190:1190:1190) (1223:1223:1223)) - (PORT clk (1608:1608:1608) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1607:1607:1607)) - (PORT d[0] (817:817:817) (818:818:818)) + (PORT clk (880:880:880) (884:884:884)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + (PORT clk (881:881:881) (885:885:885)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1608:1608:1608)) + (PORT clk (881:881:881) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (936:936:936) (951:951:951)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (952:952:952) (1005:1005:1005)) - (PORT d[1] (1106:1106:1106) (1134:1134:1134)) - (PORT d[2] (886:886:886) (926:926:926)) - (PORT d[3] (953:953:953) (973:973:973)) - (PORT d[4] (953:953:953) (973:973:973)) - (PORT d[5] (749:749:749) (791:791:791)) - (PORT d[6] (749:749:749) (791:791:791)) - (PORT d[7] (749:749:749) (791:791:791)) - (PORT d[8] (749:749:749) (791:791:791)) - (PORT d[9] (749:749:749) (791:791:791)) - (PORT d[10] (749:749:749) (791:791:791)) - (PORT d[11] (749:749:749) (791:791:791)) - (PORT d[12] (749:749:749) (791:791:791)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (940:940:940) (955:955:955)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (974:974:974) (1028:1028:1028)) - (PORT d[1] (886:886:886) (928:928:928)) - (PORT d[2] (1182:1182:1182) (1202:1202:1202)) - (PORT d[3] (1153:1153:1153) (1160:1160:1160)) - (PORT d[4] (870:870:870) (911:911:911)) - (PORT d[5] (1436:1436:1436) (1446:1446:1446)) - (PORT d[6] (1183:1183:1183) (1208:1208:1208)) - (PORT d[7] (1185:1185:1185) (1223:1223:1223)) - (PORT d[8] (1334:1334:1334) (1340:1340:1340)) - (PORT d[9] (1147:1147:1147) (1186:1186:1186)) - (PORT d[10] (1167:1167:1167) (1196:1196:1196)) - (PORT d[11] (1154:1154:1154) (1177:1177:1177)) - (PORT d[12] (1176:1176:1176) (1203:1203:1203)) - (PORT clk (1607:1607:1607) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (PORT d[0] (823:823:823) (821:821:821)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1246:1246:1246) (1257:1257:1257)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (985:985:985) (1031:1031:1031)) - (PORT d[1] (862:862:862) (901:901:901)) - (PORT d[2] (1411:1411:1411) (1436:1436:1436)) - (PORT d[3] (1243:1243:1243) (1258:1258:1258)) - (PORT d[4] (1243:1243:1243) (1258:1258:1258)) - (PORT d[5] (710:710:710) (733:733:733)) - (PORT d[6] (710:710:710) (733:733:733)) - (PORT d[7] (710:710:710) (733:733:733)) - (PORT d[8] (710:710:710) (733:733:733)) - (PORT d[9] (710:710:710) (733:733:733)) - (PORT d[10] (710:710:710) (733:733:733)) - (PORT d[11] (710:710:710) (733:733:733)) - (PORT d[12] (710:710:710) (733:733:733)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1250:1250:1250) (1261:1261:1261)) - (PORT clk (1612:1612:1612) (1609:1609:1609)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (965:965:965) (1011:1011:1011)) - (PORT d[1] (1384:1384:1384) (1415:1415:1415)) - (PORT d[2] (851:851:851) (879:879:879)) - (PORT d[3] (1359:1359:1359) (1362:1362:1362)) - (PORT d[4] (865:865:865) (893:893:893)) - (PORT d[5] (979:979:979) (1019:1019:1019)) - (PORT d[6] (1158:1158:1158) (1174:1174:1174)) - (PORT d[7] (970:970:970) (994:994:994)) - (PORT d[8] (1375:1375:1375) (1392:1392:1392)) - (PORT d[9] (1161:1161:1161) (1191:1191:1191)) - (PORT d[10] (1150:1150:1150) (1166:1166:1166)) - (PORT d[11] (1157:1157:1157) (1177:1177:1177)) - (PORT d[12] (1155:1155:1155) (1174:1174:1174)) - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (PORT d[0] (800:800:800) (809:809:809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1257:1257:1257) (1262:1262:1262)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (704:704:704) (733:733:733)) - (PORT d[1] (597:597:597) (634:634:634)) - (PORT d[2] (1424:1424:1424) (1449:1449:1449)) - (PORT d[3] (623:623:623) (627:627:627)) - (PORT d[4] (623:623:623) (627:627:627)) - (PORT d[5] (447:447:447) (472:472:472)) - (PORT d[6] (447:447:447) (472:472:472)) - (PORT d[7] (447:447:447) (472:472:472)) - (PORT d[8] (447:447:447) (472:472:472)) - (PORT d[9] (447:447:447) (472:472:472)) - (PORT d[10] (447:447:447) (472:472:472)) - (PORT d[11] (447:447:447) (472:472:472)) - (PORT d[12] (447:447:447) (472:472:472)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1603:1603:1603)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1261:1261:1261) (1266:1266:1266)) - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (679:679:679) (718:718:718)) - (PORT d[1] (1414:1414:1414) (1440:1440:1440)) - (PORT d[2] (1426:1426:1426) (1449:1449:1449)) - (PORT d[3] (613:613:613) (642:642:642)) - (PORT d[4] (616:616:616) (651:651:651)) - (PORT d[5] (671:671:671) (707:707:707)) - (PORT d[6] (713:713:713) (745:745:745)) - (PORT d[7] (696:696:696) (738:738:738)) - (PORT d[8] (1404:1404:1404) (1432:1432:1432)) - (PORT d[9] (709:709:709) (732:732:732)) - (PORT d[10] (910:910:910) (932:932:932)) - (PORT d[11] (684:684:684) (714:714:714)) - (PORT d[12] (872:872:872) (895:895:895)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - (PORT d[0] (557:557:557) (569:569:569)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1520:1520:1520)) - (PORT d[1] (1184:1184:1184) (1215:1215:1215)) - (PORT d[2] (1162:1162:1162) (1194:1194:1194)) - (PORT d[3] (1176:1176:1176) (1202:1202:1202)) - (PORT d[4] (1194:1194:1194) (1236:1236:1236)) - (PORT d[5] (1453:1453:1453) (1530:1530:1530)) - (PORT d[6] (1157:1157:1157) (1196:1196:1196)) - (PORT d[7] (1142:1142:1142) (1184:1184:1184)) - (PORT d[8] (1171:1171:1171) (1208:1208:1208)) - (PORT d[9] (1184:1184:1184) (1214:1214:1214)) - (PORT d[10] (1181:1181:1181) (1207:1207:1207)) - (PORT d[11] (1171:1171:1171) (1210:1210:1210)) - (PORT d[12] (1425:1425:1425) (1468:1468:1468)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (1080:1080:1080) (1047:1047:1047)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1225:1225:1225) (1295:1295:1295)) - (PORT d[1] (1172:1172:1172) (1212:1212:1212)) - (PORT d[2] (1177:1177:1177) (1223:1223:1223)) - (PORT d[3] (1234:1234:1234) (1269:1269:1269)) - (PORT d[4] (1224:1224:1224) (1277:1277:1277)) - (PORT d[5] (1448:1448:1448) (1523:1523:1523)) - (PORT d[6] (1144:1144:1144) (1190:1190:1190)) - (PORT d[7] (1151:1151:1151) (1201:1201:1201)) - (PORT d[8] (1184:1184:1184) (1233:1233:1233)) - (PORT d[9] (1167:1167:1167) (1202:1202:1202)) - (PORT d[10] (1166:1166:1166) (1196:1196:1196)) - (PORT d[11] (1181:1181:1181) (1219:1219:1219)) - (PORT d[12] (1176:1176:1176) (1246:1246:1246)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1660:1660:1660)) - (PORT d[0] (1083:1083:1083) (1109:1109:1109)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (881:881:881) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (597:597:597) (621:621:621)) + (PORT datac (1499:1499:1499) (1573:1573:1573)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -2240,20 +1730,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (200:200:200) (258:258:258)) + (PORT datad (198:198:198) (255:255:255)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -2263,37 +1753,550 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT datab (586:586:586) (570:570:570)) - (PORT datac (853:853:853) (841:841:841)) - (PORT datad (901:901:901) (939:939:939)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT d[0] (1934:1934:1934) (2067:2067:2067)) + (PORT d[1] (1839:1839:1839) (1927:1927:1927)) + (PORT d[2] (2024:2024:2024) (2095:2095:2095)) + (PORT d[3] (2074:2074:2074) (2161:2161:2161)) + (PORT d[4] (1995:1995:1995) (2072:2072:2072)) + (PORT d[5] (2000:2000:2000) (2056:2056:2056)) + (PORT d[6] (2003:2003:2003) (2061:2061:2061)) + (PORT d[7] (1918:1918:1918) (2045:2045:2045)) + (PORT d[8] (2168:2168:2168) (2228:2228:2228)) + (PORT d[9] (1971:1971:1971) (2048:2048:2048)) + (PORT d[10] (1839:1839:1839) (1960:1960:1960)) + (PORT d[11] (2109:2109:2109) (2197:2197:2197)) + (PORT d[12] (2116:2116:2116) (2206:2206:2206)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1600:1600:1600) (1591:1591:1591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (834:834:834)) + (PORT datab (2309:2309:2309) (2424:2424:2424)) + (PORT datac (833:833:833) (830:830:830)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1903:1903:1903) (2034:2034:2034)) + (PORT d[1] (1791:1791:1791) (1873:1873:1873)) + (PORT d[2] (1932:1932:1932) (1990:1990:1990)) + (PORT d[3] (2057:2057:2057) (2132:2132:2132)) + (PORT d[4] (2010:2010:2010) (2111:2111:2111)) + (PORT d[5] (1757:1757:1757) (1820:1820:1820)) + (PORT d[6] (1729:1729:1729) (1778:1778:1778)) + (PORT d[7] (2039:2039:2039) (2130:2130:2130)) + (PORT d[8] (1634:1634:1634) (1673:1673:1673)) + (PORT d[9] (2000:2000:2000) (2095:2095:2095)) + (PORT d[10] (1516:1516:1516) (1619:1619:1619)) + (PORT d[11] (2137:2137:2137) (2232:2232:2232)) + (PORT d[12] (1833:1833:1833) (1919:1919:1919)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (1600:1600:1600) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1866:1866:1866) (2004:2004:2004)) + (PORT d[1] (1807:1807:1807) (1895:1895:1895)) + (PORT d[2] (2017:2017:2017) (2097:2097:2097)) + (PORT d[3] (2064:2064:2064) (2131:2131:2131)) + (PORT d[4] (2001:2001:2001) (2097:2097:2097)) + (PORT d[5] (1520:1520:1520) (1579:1579:1579)) + (PORT d[6] (1949:1949:1949) (2003:2003:2003)) + (PORT d[7] (1985:1985:1985) (2052:2052:2052)) + (PORT d[8] (1996:1996:1996) (2041:2041:2041)) + (PORT d[9] (2060:2060:2060) (2159:2159:2159)) + (PORT d[10] (1531:1531:1531) (1645:1645:1645)) + (PORT d[11] (2020:2020:2020) (2097:2097:2097)) + (PORT d[12] (1981:1981:1981) (2109:2109:2109)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (1564:1564:1564) (1561:1561:1561)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (880:880:880) (884:884:884)) + (PORT datac (862:862:862) (870:870:870)) + (PORT datad (2519:2519:2519) (2641:2641:2641)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1471:1471:1471) (1536:1536:1536)) - (PORT d[1] (917:917:917) (958:958:958)) - (PORT d[2] (929:929:929) (984:984:984)) - (PORT d[3] (974:974:974) (991:991:991)) - (PORT d[4] (912:912:912) (955:955:955)) - (PORT d[5] (1454:1454:1454) (1531:1531:1531)) - (PORT d[6] (910:910:910) (947:947:947)) - (PORT d[7] (884:884:884) (927:927:927)) - (PORT d[8] (938:938:938) (983:983:983)) - (PORT d[9] (1410:1410:1410) (1416:1416:1416)) - (PORT d[10] (1372:1372:1372) (1359:1359:1359)) - (PORT d[11] (886:886:886) (923:923:923)) - (PORT d[12] (926:926:926) (969:969:969)) + (PORT d[0] (1953:1953:1953) (2093:2093:2093)) + (PORT d[1] (1570:1570:1570) (1658:1658:1658)) + (PORT d[2] (2010:2010:2010) (2081:2081:2081)) + (PORT d[3] (2096:2096:2096) (2175:2175:2175)) + (PORT d[4] (1985:1985:1985) (2057:2057:2057)) + (PORT d[5] (1791:1791:1791) (1856:1856:1856)) + (PORT d[6] (1933:1933:1933) (2007:2007:2007)) + (PORT d[7] (1908:1908:1908) (2042:2042:2042)) + (PORT d[8] (1980:1980:1980) (2044:2044:2044)) + (PORT d[9] (1982:1982:1982) (2045:2045:2045)) + (PORT d[10] (1601:1601:1601) (1716:1716:1716)) + (PORT d[11] (2128:2128:2128) (2214:2214:2214)) + (PORT d[12] (2026:2026:2026) (2164:2164:2164)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1628:1628:1628) (1658:1658:1658)) + (PORT d[0] (1623:1623:1623) (1611:1611:1611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1595:1595:1595) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1895:1895:1895) (2031:2031:2031)) + (PORT d[1] (1884:1884:1884) (1967:1967:1967)) + (PORT d[2] (1831:1831:1831) (1898:1898:1898)) + (PORT d[3] (2297:2297:2297) (2368:2368:2368)) + (PORT d[4] (2030:2030:2030) (2137:2137:2137)) + (PORT d[5] (1833:1833:1833) (1886:1886:1886)) + (PORT d[6] (2031:2031:2031) (2090:2090:2090)) + (PORT d[7] (1899:1899:1899) (2032:2032:2032)) + (PORT d[8] (2167:2167:2167) (2198:2198:2198)) + (PORT d[9] (2021:2021:2021) (2119:2119:2119)) + (PORT d[10] (2138:2138:2138) (2243:2243:2243)) + (PORT d[11] (2135:2135:2135) (2198:2198:2198)) + (PORT d[12] (2072:2072:2072) (2143:2143:2143)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (1744:1744:1744) (1801:1801:1801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1639:1639:1639)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (905:905:905)) + (PORT datac (2220:2220:2220) (2324:2324:2324)) + (PORT datad (329:329:329) (323:323:323)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1602:1602:1602) (1731:1731:1731)) + (PORT d[1] (1816:1816:1816) (1922:1922:1922)) + (PORT d[2] (2006:2006:2006) (2073:2073:2073)) + (PORT d[3] (2062:2062:2062) (2127:2127:2127)) + (PORT d[4] (1931:1931:1931) (1992:1992:1992)) + (PORT d[5] (1757:1757:1757) (1818:1818:1818)) + (PORT d[6] (1698:1698:1698) (1745:1745:1745)) + (PORT d[7] (1718:1718:1718) (1774:1774:1774)) + (PORT d[8] (1736:1736:1736) (1779:1779:1779)) + (PORT d[9] (1773:1773:1773) (1862:1862:1862)) + (PORT d[10] (1634:1634:1634) (1748:1748:1748)) + (PORT d[11] (1729:1729:1729) (1781:1781:1781)) + (PORT d[12] (1897:1897:1897) (1934:1934:1934)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -2303,17 +2306,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (829:829:829) (809:809:809)) + (PORT d[0] (1570:1570:1570) (1575:1575:1575)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1636:1636:1636) (1665:1665:1665)) @@ -2323,7 +2326,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1602:1602:1602) (1630:1630:1630)) @@ -2337,7 +2340,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (877:877:877)) @@ -2346,7 +2349,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -2355,7 +2358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -2365,7 +2368,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -2375,22 +2378,1918 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1166:1166:1166) (1209:1209:1209)) - (PORT d[1] (1176:1176:1176) (1219:1219:1219)) - (PORT d[2] (1148:1148:1148) (1195:1195:1195)) - (PORT d[3] (1218:1218:1218) (1252:1252:1252)) - (PORT d[4] (1181:1181:1181) (1236:1236:1236)) - (PORT d[5] (1446:1446:1446) (1481:1481:1481)) - (PORT d[6] (1170:1170:1170) (1218:1218:1218)) - (PORT d[7] (1154:1154:1154) (1206:1206:1206)) - (PORT d[8] (1188:1188:1188) (1239:1239:1239)) - (PORT d[9] (1170:1170:1170) (1208:1208:1208)) - (PORT d[10] (1169:1169:1169) (1201:1201:1201)) - (PORT d[11] (1159:1159:1159) (1204:1204:1204)) - (PORT d[12] (1405:1405:1405) (1441:1441:1441)) + (PORT d[0] (1837:1837:1837) (1958:1958:1958)) + (PORT d[1] (1794:1794:1794) (1867:1867:1867)) + (PORT d[2] (2014:2014:2014) (2091:2091:2091)) + (PORT d[3] (2055:2055:2055) (2132:2132:2132)) + (PORT d[4] (1972:1972:1972) (2034:2034:2034)) + (PORT d[5] (1740:1740:1740) (1796:1796:1796)) + (PORT d[6] (1669:1669:1669) (1735:1735:1735)) + (PORT d[7] (1768:1768:1768) (1868:1868:1868)) + (PORT d[8] (1731:1731:1731) (1791:1791:1791)) + (PORT d[9] (2027:2027:2027) (2128:2128:2128)) + (PORT d[10] (1960:1960:1960) (2059:2059:2059)) + (PORT d[11] (1721:1721:1721) (1787:1787:1787)) + (PORT d[12] (1954:1954:1954) (2083:2083:2083)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1602:1602:1602) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (691:691:691)) + (PORT datac (1755:1755:1755) (1876:1876:1876)) + (PORT datad (329:329:329) (322:322:322)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2024:2024:2024) (2066:2066:2066)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1907:1907:1907) (2040:2040:2040)) + (PORT d[1] (2033:2033:2033) (2088:2088:2088)) + (PORT d[2] (2056:2056:2056) (2145:2145:2145)) + (PORT d[3] (2117:2117:2117) (2201:2201:2201)) + (PORT d[4] (2012:2012:2012) (2113:2113:2113)) + (PORT d[5] (2062:2062:2062) (2132:2132:2132)) + (PORT d[6] (1999:1999:1999) (2053:2053:2053)) + (PORT d[7] (1924:1924:1924) (2049:2049:2049)) + (PORT d[8] (2199:2199:2199) (2253:2253:2253)) + (PORT d[9] (1991:1991:1991) (2077:2077:2077)) + (PORT d[10] (1874:1874:1874) (1999:1999:1999)) + (PORT d[11] (2165:2165:2165) (2266:2266:2266)) + (PORT d[12] (2168:2168:2168) (2269:2269:2269)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (1803:1803:1803) (1759:1759:1759)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1635:1635:1635)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2028:2028:2028) (2070:2070:2070)) + (PORT clk (1643:1643:1643) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1887:1887:1887) (2020:2020:2020)) + (PORT d[1] (2076:2076:2076) (2132:2132:2132)) + (PORT d[2] (2013:2013:2013) (2083:2083:2083)) + (PORT d[3] (2118:2118:2118) (2202:2202:2202)) + (PORT d[4] (2031:2031:2031) (2119:2119:2119)) + (PORT d[5] (2063:2063:2063) (2133:2133:2133)) + (PORT d[6] (2000:2000:2000) (2054:2054:2054)) + (PORT d[7] (1925:1925:1925) (2050:2050:2050)) + (PORT d[8] (2200:2200:2200) (2254:2254:2254)) + (PORT d[9] (1992:1992:1992) (2078:2078:2078)) + (PORT d[10] (1875:1875:1875) (2000:2000:2000)) + (PORT d[11] (2166:2166:2166) (2267:2267:2267)) + (PORT d[12] (2169:2169:2169) (2270:2270:2270)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1673:1673:1673)) + (PORT d[0] (1803:1803:1803) (1759:1759:1759)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2933:2933:2933) (2922:2922:2922)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1815:1815:1815) (1883:1883:1883)) + (PORT d[1] (2131:2131:2131) (2240:2240:2240)) + (PORT d[2] (1805:1805:1805) (1878:1878:1878)) + (PORT d[3] (1609:1609:1609) (1704:1704:1704)) + (PORT d[4] (2018:2018:2018) (2119:2119:2119)) + (PORT d[5] (1456:1456:1456) (1543:1543:1543)) + (PORT d[6] (1653:1653:1653) (1759:1759:1759)) + (PORT d[7] (1620:1620:1620) (1717:1717:1717)) + (PORT d[8] (1802:1802:1802) (1867:1867:1867)) + (PORT d[9] (1645:1645:1645) (1680:1680:1680)) + (PORT d[10] (1560:1560:1560) (1647:1647:1647)) + (PORT d[11] (1861:1861:1861) (1918:1918:1918)) + (PORT d[12] (1917:1917:1917) (2011:2011:2011)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT d[0] (1177:1177:1177) (1205:1205:1205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1641:1641:1641)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2937:2937:2937) (2926:2926:2926)) + (PORT clk (1649:1649:1649) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1822:1822:1822) (1882:1882:1882)) + (PORT d[1] (2132:2132:2132) (2241:2241:2241)) + (PORT d[2] (1764:1764:1764) (1838:1838:1838)) + (PORT d[3] (1610:1610:1610) (1705:1705:1705)) + (PORT d[4] (2053:2053:2053) (2170:2170:2170)) + (PORT d[5] (1457:1457:1457) (1544:1544:1544)) + (PORT d[6] (1654:1654:1654) (1760:1760:1760)) + (PORT d[7] (1621:1621:1621) (1718:1718:1718)) + (PORT d[8] (1803:1803:1803) (1868:1868:1868)) + (PORT d[9] (1646:1646:1646) (1681:1681:1681)) + (PORT d[10] (1561:1561:1561) (1648:1648:1648)) + (PORT d[11] (1862:1862:1862) (1919:1919:1919)) + (PORT d[12] (1918:1918:1918) (2012:2012:2012)) + (PORT clk (1648:1648:1648) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1679:1679:1679)) + (PORT d[0] (1177:1177:1177) (1205:1205:1205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1643:1643:1643)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2490:2490:2490) (2600:2600:2600)) + (PORT datac (592:592:592) (588:588:588)) + (PORT datad (1013:1013:1013) (999:999:999)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2917:2917:2917) (2901:2901:2901)) + (PORT clk (1652:1652:1652) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1552:1552:1552) (1631:1631:1631)) + (PORT d[1] (1766:1766:1766) (1854:1854:1854)) + (PORT d[2] (1805:1805:1805) (1879:1879:1879)) + (PORT d[3] (1635:1635:1635) (1722:1722:1722)) + (PORT d[4] (1851:1851:1851) (1935:1935:1935)) + (PORT d[5] (1741:1741:1741) (1837:1837:1837)) + (PORT d[6] (1811:1811:1811) (1890:1890:1890)) + (PORT d[7] (1873:1873:1873) (1972:1972:1972)) + (PORT d[8] (1828:1828:1828) (1897:1897:1897)) + (PORT d[9] (1890:1890:1890) (1981:1981:1981)) + (PORT d[10] (1611:1611:1611) (1704:1704:1704)) + (PORT d[11] (1813:1813:1813) (1880:1880:1880)) + (PORT d[12] (1903:1903:1903) (1997:1997:1997)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT d[0] (1443:1443:1443) (1423:1423:1423)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1616:1616:1616) (1643:1643:1643)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2921:2921:2921) (2905:2905:2905)) + (PORT clk (1652:1652:1652) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1624:1624:1624)) + (PORT d[1] (1776:1776:1776) (1869:1869:1869)) + (PORT d[2] (1764:1764:1764) (1838:1838:1838)) + (PORT d[3] (1636:1636:1636) (1723:1723:1723)) + (PORT d[4] (1831:1831:1831) (1921:1921:1921)) + (PORT d[5] (1742:1742:1742) (1838:1838:1838)) + (PORT d[6] (1812:1812:1812) (1891:1891:1891)) + (PORT d[7] (1874:1874:1874) (1973:1973:1973)) + (PORT d[8] (1829:1829:1829) (1898:1898:1898)) + (PORT d[9] (1891:1891:1891) (1982:1982:1982)) + (PORT d[10] (1612:1612:1612) (1705:1705:1705)) + (PORT d[11] (1814:1814:1814) (1881:1881:1881)) + (PORT d[12] (1904:1904:1904) (1998:1998:1998)) + (PORT clk (1651:1651:1651) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1681:1681:1681)) + (PORT d[0] (1443:1443:1443) (1423:1423:1423)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1645:1645:1645)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2942:2942:2942) (2938:2938:2938)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1570:1570:1570) (1650:1650:1650)) + (PORT d[1] (1816:1816:1816) (1894:1894:1894)) + (PORT d[2] (1527:1527:1527) (1577:1577:1577)) + (PORT d[3] (1592:1592:1592) (1687:1687:1687)) + (PORT d[4] (1794:1794:1794) (1909:1909:1909)) + (PORT d[5] (1430:1430:1430) (1514:1514:1514)) + (PORT d[6] (1895:1895:1895) (1995:1995:1995)) + (PORT d[7] (1613:1613:1613) (1714:1714:1714)) + (PORT d[8] (1789:1789:1789) (1855:1855:1855)) + (PORT d[9] (1882:1882:1882) (1971:1971:1971)) + (PORT d[10] (2027:2027:2027) (2172:2172:2172)) + (PORT d[11] (1855:1855:1855) (1905:1905:1905)) + (PORT d[12] (1895:1895:1895) (1997:1997:1997)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (1177:1177:1177) (1205:1205:1205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2946:2946:2946) (2942:2942:2942)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1550:1550:1550) (1629:1629:1629)) + (PORT d[1] (1817:1817:1817) (1896:1896:1896)) + (PORT d[2] (1541:1541:1541) (1606:1606:1606)) + (PORT d[3] (1593:1593:1593) (1688:1688:1688)) + (PORT d[4] (1801:1801:1801) (1898:1898:1898)) + (PORT d[5] (1431:1431:1431) (1515:1515:1515)) + (PORT d[6] (1896:1896:1896) (1996:1996:1996)) + (PORT d[7] (1614:1614:1614) (1715:1715:1715)) + (PORT d[8] (1790:1790:1790) (1856:1856:1856)) + (PORT d[9] (1883:1883:1883) (1972:1972:1972)) + (PORT d[10] (2028:2028:2028) (2173:2173:2173)) + (PORT d[11] (1856:1856:1856) (1906:1906:1906)) + (PORT d[12] (1896:1896:1896) (1998:1998:1998)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1675:1675:1675)) + (PORT d[0] (1177:1177:1177) (1205:1205:1205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1676:1676:1676)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1676:1676:1676)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1676:1676:1676)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1676:1676:1676)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1639:1639:1639)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (319:319:319)) + (PORT datac (628:628:628) (634:634:634)) + (PORT datad (329:329:329) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (865:865:865) (874:874:874)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1472:1472:1472) (1537:1537:1537)) + (PORT d[1] (1564:1564:1564) (1641:1641:1641)) + (PORT d[2] (1474:1474:1474) (1544:1544:1544)) + (PORT d[3] (1579:1579:1579) (1647:1647:1647)) + (PORT d[4] (1543:1543:1543) (1633:1633:1633)) + (PORT d[5] (1370:1370:1370) (1449:1449:1449)) + (PORT d[6] (1510:1510:1510) (1570:1570:1570)) + (PORT d[7] (1787:1787:1787) (1854:1854:1854)) + (PORT d[8] (1553:1553:1553) (1630:1630:1630)) + (PORT d[9] (1606:1606:1606) (1687:1687:1687)) + (PORT d[10] (1349:1349:1349) (1445:1445:1445)) + (PORT d[11] (1744:1744:1744) (1801:1801:1801)) + (PORT d[12] (1615:1615:1615) (1699:1699:1699)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1167:1167:1167) (1141:1141:1141)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (869:869:869) (878:878:878)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1494:1494:1494) (1558:1558:1558)) + (PORT d[1] (1551:1551:1551) (1613:1613:1613)) + (PORT d[2] (1486:1486:1486) (1547:1547:1547)) + (PORT d[3] (1580:1580:1580) (1648:1648:1648)) + (PORT d[4] (1545:1545:1545) (1635:1635:1635)) + (PORT d[5] (1371:1371:1371) (1450:1450:1450)) + (PORT d[6] (1511:1511:1511) (1571:1571:1571)) + (PORT d[7] (1788:1788:1788) (1855:1855:1855)) + (PORT d[8] (1554:1554:1554) (1631:1631:1631)) + (PORT d[9] (1607:1607:1607) (1688:1688:1688)) + (PORT d[10] (1350:1350:1350) (1446:1446:1446)) + (PORT d[11] (1745:1745:1745) (1802:1802:1802)) + (PORT d[12] (1616:1616:1616) (1700:1700:1700)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1167:1167:1167) (1141:1141:1141)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (840:840:840) (855:855:855)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1801:1801:1801) (1896:1896:1896)) + (PORT d[1] (1570:1570:1570) (1656:1656:1656)) + (PORT d[2] (1748:1748:1748) (1810:1810:1810)) + (PORT d[3] (1571:1571:1571) (1637:1637:1637)) + (PORT d[4] (1553:1553:1553) (1645:1645:1645)) + (PORT d[5] (1374:1374:1374) (1452:1452:1452)) + (PORT d[6] (1738:1738:1738) (1790:1790:1790)) + (PORT d[7] (1554:1554:1554) (1641:1641:1641)) + (PORT d[8] (1586:1586:1586) (1668:1668:1668)) + (PORT d[9] (1591:1591:1591) (1672:1672:1672)) + (PORT d[10] (1611:1611:1611) (1699:1699:1699)) + (PORT d[11] (1737:1737:1737) (1788:1788:1788)) + (PORT d[12] (1626:1626:1626) (1712:1712:1712)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1129:1129:1129) (1156:1156:1156)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (844:844:844) (859:859:859)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1802:1802:1802) (1897:1897:1897)) + (PORT d[1] (1550:1550:1550) (1635:1635:1635)) + (PORT d[2] (1491:1491:1491) (1553:1553:1553)) + (PORT d[3] (1572:1572:1572) (1638:1638:1638)) + (PORT d[4] (1541:1541:1541) (1617:1617:1617)) + (PORT d[5] (1375:1375:1375) (1453:1453:1453)) + (PORT d[6] (1739:1739:1739) (1791:1791:1791)) + (PORT d[7] (1555:1555:1555) (1642:1642:1642)) + (PORT d[8] (1587:1587:1587) (1669:1669:1669)) + (PORT d[9] (1592:1592:1592) (1673:1673:1673)) + (PORT d[10] (1612:1612:1612) (1700:1700:1700)) + (PORT d[11] (1738:1738:1738) (1789:1789:1789)) + (PORT d[12] (1627:1627:1627) (1713:1713:1713)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1129:1129:1129) (1156:1156:1156)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (923:923:923) (934:934:934)) + (PORT datac (679:679:679) (740:740:740)) + (PORT datad (897:897:897) (894:894:894)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3190:3190:3190) (3193:3193:3193)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1551:1551:1551) (1637:1637:1637)) + (PORT d[1] (1802:1802:1802) (1873:1873:1873)) + (PORT d[2] (1508:1508:1508) (1576:1576:1576)) + (PORT d[3] (1554:1554:1554) (1642:1642:1642)) + (PORT d[4] (1809:1809:1809) (1905:1905:1905)) + (PORT d[5] (1408:1408:1408) (1478:1478:1478)) + (PORT d[6] (1930:1930:1930) (2041:2041:2041)) + (PORT d[7] (1820:1820:1820) (1911:1911:1911)) + (PORT d[8] (1845:1845:1845) (1930:1930:1930)) + (PORT d[9] (1903:1903:1903) (2003:2003:2003)) + (PORT d[10] (1826:1826:1826) (1902:1902:1902)) + (PORT d[11] (1612:1612:1612) (1657:1657:1657)) + (PORT d[12] (1650:1650:1650) (1745:1745:1745)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (1154:1154:1154) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1631:1631:1631)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3194:3194:3194) (3197:3197:3197)) + (PORT clk (1639:1639:1639) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1631:1631:1631)) + (PORT d[1] (1782:1782:1782) (1852:1852:1852)) + (PORT d[2] (1549:1549:1549) (1615:1615:1615)) + (PORT d[3] (1555:1555:1555) (1643:1643:1643)) + (PORT d[4] (1797:1797:1797) (1877:1877:1877)) + (PORT d[5] (1409:1409:1409) (1479:1479:1479)) + (PORT d[6] (1931:1931:1931) (2042:2042:2042)) + (PORT d[7] (1821:1821:1821) (1912:1912:1912)) + (PORT d[8] (1846:1846:1846) (1931:1931:1931)) + (PORT d[9] (1904:1904:1904) (2004:2004:2004)) + (PORT d[10] (1827:1827:1827) (1903:1903:1903)) + (PORT d[11] (1613:1613:1613) (1658:1658:1658)) + (PORT d[12] (1651:1651:1651) (1746:1746:1746)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1669:1669:1669)) + (PORT d[0] (1154:1154:1154) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1633:1633:1633)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3173:3173:3173) (3171:3171:3171)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1779:1779:1779) (1860:1860:1860)) + (PORT d[1] (1739:1739:1739) (1832:1832:1832)) + (PORT d[2] (1547:1547:1547) (1613:1613:1613)) + (PORT d[3] (1588:1588:1588) (1675:1675:1675)) + (PORT d[4] (1857:1857:1857) (1949:1949:1949)) + (PORT d[5] (1419:1419:1419) (1493:1493:1493)) + (PORT d[6] (1933:1933:1933) (2046:2046:2046)) + (PORT d[7] (1586:1586:1586) (1682:1682:1682)) + (PORT d[8] (1501:1501:1501) (1560:1560:1560)) + (PORT d[9] (1885:1885:1885) (1979:1979:1979)) + (PORT d[10] (1609:1609:1609) (1694:1694:1694)) + (PORT d[11] (1837:1837:1837) (1907:1907:1907)) + (PORT d[12] (1895:1895:1895) (1975:1975:1975)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (PORT d[0] (1183:1183:1183) (1199:1199:1199)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3177:3177:3177) (3175:3175:3175)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1824:1824:1824) (1898:1898:1898)) + (PORT d[1] (1806:1806:1806) (1887:1887:1887)) + (PORT d[2] (1548:1548:1548) (1614:1614:1614)) + (PORT d[3] (1589:1589:1589) (1676:1676:1676)) + (PORT d[4] (1858:1858:1858) (1950:1950:1950)) + (PORT d[5] (1420:1420:1420) (1494:1494:1494)) + (PORT d[6] (1934:1934:1934) (2047:2047:2047)) + (PORT d[7] (1587:1587:1587) (1683:1683:1683)) + (PORT d[8] (1502:1502:1502) (1561:1561:1561)) + (PORT d[9] (1886:1886:1886) (1980:1980:1980)) + (PORT d[10] (1610:1610:1610) (1695:1695:1695)) + (PORT d[11] (1838:1838:1838) (1908:1908:1908)) + (PORT d[12] (1896:1896:1896) (1976:1976:1976)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (1183:1183:1183) (1199:1199:1199)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1631:1631:1631)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (708:708:708) (769:769:769)) + (PORT datac (624:624:624) (614:614:614)) + (PORT datad (330:330:330) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1626:1626:1626) (1760:1760:1760)) + (PORT d[1] (1783:1783:1783) (1854:1854:1854)) + (PORT d[2] (1969:1969:1969) (2036:2036:2036)) + (PORT d[3] (2048:2048:2048) (2096:2096:2096)) + (PORT d[4] (1982:1982:1982) (2064:2064:2064)) + (PORT d[5] (1784:1784:1784) (1853:1853:1853)) + (PORT d[6] (1651:1651:1651) (1696:1696:1696)) + (PORT d[7] (1739:1739:1739) (1813:1813:1813)) + (PORT d[8] (1750:1750:1750) (1811:1811:1811)) + (PORT d[9] (1758:1758:1758) (1850:1850:1850)) + (PORT d[10] (1620:1620:1620) (1745:1745:1745)) + (PORT d[11] (1714:1714:1714) (1779:1779:1779)) + (PORT d[12] (2036:2036:2036) (2161:2161:2161)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1581:1581:1581) (1574:1574:1574)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1944:1944:1944) (2072:2072:2072)) + (PORT d[1] (1807:1807:1807) (1884:1884:1884)) + (PORT d[2] (2016:2016:2016) (2089:2089:2089)) + (PORT d[3] (2086:2086:2086) (2163:2163:2163)) + (PORT d[4] (2022:2022:2022) (2116:2116:2116)) + (PORT d[5] (1816:1816:1816) (1892:1892:1892)) + (PORT d[6] (1968:1968:1968) (2013:2013:2013)) + (PORT d[7] (1903:1903:1903) (2035:2035:2035)) + (PORT d[8] (1907:1907:1907) (1957:1957:1957)) + (PORT d[9] (2005:2005:2005) (2088:2088:2088)) + (PORT d[10] (1828:1828:1828) (1940:1940:1940)) + (PORT d[11] (2103:2103:2103) (2185:2185:2185)) + (PORT d[12] (1886:1886:1886) (1965:1965:1965)) (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) @@ -2400,17 +4299,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (1034:1034:1034) (1056:1056:1056)) + (PORT d[0] (1587:1587:1587) (1594:1594:1594)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1633:1633:1633) (1661:1661:1661)) @@ -2420,7 +4319,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1599:1599:1599) (1626:1626:1626)) @@ -2434,7 +4333,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (870:870:870) (873:873:873)) @@ -2443,7 +4342,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) (DELAY (ABSOLUTE (PORT clk (871:871:871) (874:874:874)) @@ -2452,7 +4351,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (871:871:871) (874:874:874)) @@ -2462,7 +4361,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (871:871:871) (874:874:874)) @@ -2472,15 +4371,223 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (581:581:581) (581:581:581)) - (PORT datab (675:675:675) (722:722:722)) - (PORT datac (835:835:835) (825:825:825)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1086:1086:1086) (1089:1089:1089)) + (PORT datac (2311:2311:2311) (2442:2442:2442)) + (PORT datad (327:327:327) (320:320:320)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1893:1893:1893) (2038:2038:2038)) + (PORT d[1] (1845:1845:1845) (1924:1924:1924)) + (PORT d[2] (1979:1979:1979) (2052:2052:2052)) + (PORT d[3] (2031:2031:2031) (2090:2090:2090)) + (PORT d[4] (2013:2013:2013) (2095:2095:2095)) + (PORT d[5] (1790:1790:1790) (1864:1864:1864)) + (PORT d[6] (2001:2001:2001) (2035:2035:2035)) + (PORT d[7] (1928:1928:1928) (2062:2062:2062)) + (PORT d[8] (1681:1681:1681) (1739:1739:1739)) + (PORT d[9] (2006:2006:2006) (2093:2093:2093)) + (PORT d[10] (1586:1586:1586) (1705:1705:1705)) + (PORT d[11] (2118:2118:2118) (2204:2204:2204)) + (PORT d[12] (1873:1873:1873) (1958:1958:1958)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1628:1628:1628) (1655:1655:1655)) + (PORT d[0] (1579:1579:1579) (1579:1579:1579)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1595:1595:1595) (1621:1621:1621)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (868:868:868)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (869:869:869)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (869:869:869)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1888:1888:1888) (2021:2021:2021)) + (PORT d[1] (1603:1603:1603) (1686:1686:1686)) + (PORT d[2] (2038:2038:2038) (2119:2119:2119)) + (PORT d[3] (2058:2058:2058) (2137:2137:2137)) + (PORT d[4] (2005:2005:2005) (2088:2088:2088)) + (PORT d[5] (1532:1532:1532) (1591:1591:1591)) + (PORT d[6] (1930:1930:1930) (2000:2000:2000)) + (PORT d[7] (1802:1802:1802) (1899:1899:1899)) + (PORT d[8] (1663:1663:1663) (1710:1710:1710)) + (PORT d[9] (2040:2040:2040) (2138:2138:2138)) + (PORT d[10] (1567:1567:1567) (1688:1688:1688)) + (PORT d[11] (2009:2009:2009) (2081:2081:2081)) + (PORT d[12] (1990:1990:1990) (2129:2129:2129)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT d[0] (1579:1579:1579) (1579:1579:1579)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1627:1627:1627)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (646:646:646)) + (PORT datac (866:866:866) (870:870:870)) + (PORT datad (2488:2488:2488) (2608:2608:2608)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -2489,19 +4596,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1730:1730:1730) (1788:1788:1788)) - (PORT d[1] (1138:1138:1138) (1162:1162:1162)) - (PORT d[2] (1178:1178:1178) (1212:1212:1212)) - (PORT d[3] (1221:1221:1221) (1226:1226:1226)) - (PORT d[4] (1174:1174:1174) (1190:1190:1190)) - (PORT d[5] (1739:1739:1739) (1812:1812:1812)) - (PORT d[6] (1161:1161:1161) (1174:1174:1174)) - (PORT d[7] (1257:1257:1257) (1318:1318:1318)) - (PORT d[8] (1125:1125:1125) (1155:1155:1155)) - (PORT d[9] (1167:1167:1167) (1188:1188:1188)) - (PORT d[10] (1178:1178:1178) (1194:1194:1194)) - (PORT d[11] (1131:1131:1131) (1145:1145:1145)) - (PORT d[12] (1172:1172:1172) (1230:1230:1230)) + (PORT d[0] (1809:1809:1809) (1908:1908:1908)) + (PORT d[1] (1513:1513:1513) (1564:1564:1564)) + (PORT d[2] (1741:1741:1741) (1796:1796:1796)) + (PORT d[3] (1755:1755:1755) (1805:1805:1805)) + (PORT d[4] (1675:1675:1675) (1746:1746:1746)) + (PORT d[5] (1550:1550:1550) (1612:1612:1612)) + (PORT d[6] (1740:1740:1740) (1788:1788:1788)) + (PORT d[7] (1452:1452:1452) (1507:1507:1507)) + (PORT d[8] (1471:1471:1471) (1518:1518:1518)) + (PORT d[9] (1437:1437:1437) (1507:1507:1507)) + (PORT d[10] (1640:1640:1640) (1762:1762:1762)) + (PORT d[11] (1496:1496:1496) (1539:1539:1539)) + (PORT d[12] (1648:1648:1648) (1698:1698:1698)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -2515,7 +4622,7 @@ (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (1039:1039:1039) (1059:1059:1059)) + (PORT d[0] (1552:1552:1552) (1562:1562:1562)) ) ) ) @@ -2586,20 +4693,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (709:709:709) (744:744:744)) - (PORT d[1] (597:597:597) (635:635:635)) - (PORT d[2] (1405:1405:1405) (1428:1428:1428)) - (PORT d[3] (1136:1136:1136) (1139:1139:1139)) - (PORT d[4] (876:876:876) (905:905:905)) - (PORT d[5] (977:977:977) (1007:1007:1007)) - (PORT d[6] (1112:1112:1112) (1125:1125:1125)) - (PORT d[7] (1159:1159:1159) (1172:1172:1172)) - (PORT d[8] (1381:1381:1381) (1409:1409:1409)) - (PORT d[9] (1161:1161:1161) (1186:1186:1186)) - (PORT d[10] (1148:1148:1148) (1158:1158:1158)) - (PORT d[11] (1125:1125:1125) (1135:1135:1135)) - (PORT d[12] (1149:1149:1149) (1159:1159:1159)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (1568:1568:1568) (1668:1668:1668)) + (PORT d[1] (1510:1510:1510) (1559:1559:1559)) + (PORT d[2] (1702:1702:1702) (1746:1746:1746)) + (PORT d[3] (1672:1672:1672) (1689:1689:1689)) + (PORT d[4] (1662:1662:1662) (1717:1717:1717)) + (PORT d[5] (1491:1491:1491) (1548:1548:1548)) + (PORT d[6] (1422:1422:1422) (1461:1461:1461)) + (PORT d[7] (1422:1422:1422) (1494:1494:1494)) + (PORT d[8] (1453:1453:1453) (1487:1487:1487)) + (PORT d[9] (1404:1404:1404) (1458:1458:1458)) + (PORT d[10] (1652:1652:1652) (1786:1786:1786)) + (PORT d[11] (1447:1447:1447) (1481:1481:1481)) + (PORT d[12] (1637:1637:1637) (1661:1661:1661)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -2611,8 +4718,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (817:817:817) (799:799:799)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1512:1512:1512) (1483:1483:1483)) ) ) ) @@ -2621,7 +4728,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) + (PORT clk (1634:1634:1634) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -2631,7 +4738,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) + (PORT clk (1600:1600:1600) (1626:1626:1626)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2645,7 +4752,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) + (PORT clk (871:871:871) (873:873:873)) ) ) ) @@ -2654,7 +4761,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (872:872:872) (874:874:874)) ) ) ) @@ -2663,7 +4770,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (872:872:872) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2673,141 +4780,44 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (872:872:872) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) (DELAY (ABSOLUTE - (PORT datab (876:876:876) (918:918:918)) - (PORT datac (557:557:557) (538:538:538)) - (PORT datad (966:966:966) (927:927:927)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (676:676:676) (688:688:688)) + (PORT datac (1719:1719:1719) (1841:1841:1841)) + (PORT datad (884:884:884) (886:886:886)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1429:1429:1429) (1476:1476:1476)) - (PORT d[1] (1197:1197:1197) (1241:1241:1241)) - (PORT d[2] (1171:1171:1171) (1217:1217:1217)) - (PORT d[3] (1268:1268:1268) (1305:1305:1305)) - (PORT d[4] (1457:1457:1457) (1497:1497:1497)) - (PORT d[5] (1204:1204:1204) (1268:1268:1268)) - (PORT d[6] (1196:1196:1196) (1238:1238:1238)) - (PORT d[7] (1155:1155:1155) (1207:1207:1207)) - (PORT d[8] (1164:1164:1164) (1212:1212:1212)) - (PORT d[9] (1196:1196:1196) (1237:1237:1237)) - (PORT d[10] (1195:1195:1195) (1230:1230:1230)) - (PORT d[11] (1159:1159:1159) (1205:1205:1205)) - (PORT d[12] (1156:1156:1156) (1197:1197:1197)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1629:1629:1629) (1658:1658:1658)) - (PORT d[0] (1051:1051:1051) (1017:1017:1017)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (942:942:942) (994:994:994)) - (PORT d[1] (857:857:857) (902:902:902)) - (PORT d[2] (859:859:859) (895:895:895)) - (PORT d[3] (1152:1152:1152) (1160:1160:1160)) - (PORT d[4] (1403:1403:1403) (1451:1451:1451)) - (PORT d[5] (1209:1209:1209) (1238:1238:1238)) - (PORT d[6] (1157:1157:1157) (1180:1180:1180)) - (PORT d[7] (1218:1218:1218) (1253:1253:1253)) - (PORT d[8] (1362:1362:1362) (1381:1381:1381)) - (PORT d[9] (1172:1172:1172) (1214:1214:1214)) - (PORT d[10] (1167:1167:1167) (1196:1196:1196)) - (PORT d[11] (1179:1179:1179) (1206:1206:1206)) - (PORT d[12] (1176:1176:1176) (1203:1203:1203)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (1880:1880:1880) (2006:2006:2006)) + (PORT d[1] (1828:1828:1828) (1902:1902:1902)) + (PORT d[2] (2053:2053:2053) (2134:2134:2134)) + (PORT d[3] (2079:2079:2079) (2168:2168:2168)) + (PORT d[4] (2023:2023:2023) (2125:2125:2125)) + (PORT d[5] (2057:2057:2057) (2126:2126:2126)) + (PORT d[6] (2013:2013:2013) (2069:2069:2069)) + (PORT d[7] (1942:1942:1942) (2060:2060:2060)) + (PORT d[8] (2167:2167:2167) (2227:2227:2227)) + (PORT d[9] (1746:1746:1746) (1831:1831:1831)) + (PORT d[10] (1878:1878:1878) (1994:1994:1994)) + (PORT d[11] (2115:2115:2115) (2196:2196:2196)) + (PORT d[12] (2151:2151:2151) (2254:2254:2254)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) ) ) (TIMINGCHECK @@ -2819,8 +4829,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1666:1666:1666)) - (PORT d[0] (824:824:824) (822:822:822)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + (PORT d[0] (1617:1617:1617) (1612:1612:1612)) ) ) ) @@ -2829,7 +4839,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1667:1667:1667)) + (PORT clk (1639:1639:1639) (1668:1668:1668)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -2839,7 +4849,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) + (PORT clk (1605:1605:1605) (1633:1633:1633)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2853,7 +4863,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) + (PORT clk (876:876:876) (880:880:880)) ) ) ) @@ -2862,7 +4872,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (877:877:877) (881:881:881)) ) ) ) @@ -2871,7 +4881,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (877:877:877) (881:881:881)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2879,6 +4889,2940 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1886:1886:1886) (2013:2013:2013)) + (PORT d[1] (2054:2054:2054) (2118:2118:2118)) + (PORT d[2] (2118:2118:2118) (2216:2216:2216)) + (PORT d[3] (2074:2074:2074) (2156:2156:2156)) + (PORT d[4] (2031:2031:2031) (2119:2119:2119)) + (PORT d[5] (2018:2018:2018) (2074:2074:2074)) + (PORT d[6] (1803:1803:1803) (1897:1897:1897)) + (PORT d[7] (1899:1899:1899) (2031:2031:2031)) + (PORT d[8] (1896:1896:1896) (1946:1946:1946)) + (PORT d[9] (1994:1994:1994) (2090:2090:2090)) + (PORT d[10] (1861:1861:1861) (1978:1978:1978)) + (PORT d[11] (2159:2159:2159) (2236:2236:2236)) + (PORT d[12] (2096:2096:2096) (2186:2186:2186)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT d[0] (1757:1757:1757) (1801:1801:1801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (2541:2541:2541) (2671:2671:2671)) + (PORT datac (519:519:519) (497:497:497)) + (PORT datad (599:599:599) (600:600:600)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3214:3214:3214) (3222:3222:3222)) + (PORT clk (1642:1642:1642) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1852:1852:1852) (1928:1928:1928)) + (PORT d[1] (1600:1600:1600) (1676:1676:1676)) + (PORT d[2] (1605:1605:1605) (1646:1646:1646)) + (PORT d[3] (1599:1599:1599) (1679:1679:1679)) + (PORT d[4] (1809:1809:1809) (1905:1905:1905)) + (PORT d[5] (1362:1362:1362) (1421:1421:1421)) + (PORT d[6] (1588:1588:1588) (1675:1675:1675)) + (PORT d[7] (2070:2070:2070) (2138:2138:2138)) + (PORT d[8] (1820:1820:1820) (1904:1904:1904)) + (PORT d[9] (1648:1648:1648) (1681:1681:1681)) + (PORT d[10] (1332:1332:1332) (1436:1436:1436)) + (PORT d[11] (1997:1997:1997) (2058:2058:2058)) + (PORT d[12] (1619:1619:1619) (1692:1692:1692)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (PORT d[0] (1177:1177:1177) (1142:1142:1142)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1633:1633:1633)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3218:3218:3218) (3226:3226:3226)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1866:1866:1866) (1952:1952:1952)) + (PORT d[1] (1580:1580:1580) (1656:1656:1656)) + (PORT d[2] (1628:1628:1628) (1665:1665:1665)) + (PORT d[3] (1600:1600:1600) (1680:1680:1680)) + (PORT d[4] (1797:1797:1797) (1877:1877:1877)) + (PORT d[5] (1363:1363:1363) (1422:1422:1422)) + (PORT d[6] (1589:1589:1589) (1676:1676:1676)) + (PORT d[7] (2071:2071:2071) (2139:2139:2139)) + (PORT d[8] (1821:1821:1821) (1905:1905:1905)) + (PORT d[9] (1649:1649:1649) (1682:1682:1682)) + (PORT d[10] (1333:1333:1333) (1437:1437:1437)) + (PORT d[11] (1998:1998:1998) (2059:2059:2059)) + (PORT d[12] (1620:1620:1620) (1693:1693:1693)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1671:1671:1671)) + (PORT d[0] (1177:1177:1177) (1142:1142:1142)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1635:1635:1635)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3215:3215:3215) (3223:3223:3223)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (1867:1867:1867)) + (PORT d[1] (1829:1829:1829) (1901:1901:1901)) + (PORT d[2] (1758:1758:1758) (1837:1837:1837)) + (PORT d[3] (1648:1648:1648) (1743:1743:1743)) + (PORT d[4] (1800:1800:1800) (1893:1893:1893)) + (PORT d[5] (1360:1360:1360) (1442:1442:1442)) + (PORT d[6] (1898:1898:1898) (1971:1971:1971)) + (PORT d[7] (1609:1609:1609) (1702:1702:1702)) + (PORT d[8] (1513:1513:1513) (1575:1575:1575)) + (PORT d[9] (1870:1870:1870) (1963:1963:1963)) + (PORT d[10] (1828:1828:1828) (1908:1908:1908)) + (PORT d[11] (2022:2022:2022) (2084:2084:2084)) + (PORT d[12] (1617:1617:1617) (1713:1713:1713)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT d[0] (1142:1142:1142) (1176:1176:1176)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1635:1635:1635)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3219:3219:3219) (3227:3227:3227)) + (PORT clk (1644:1644:1644) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1818:1818:1818) (1905:1905:1905)) + (PORT d[1] (1837:1837:1837) (1900:1900:1900)) + (PORT d[2] (1794:1794:1794) (1859:1859:1859)) + (PORT d[3] (1649:1649:1649) (1744:1744:1744)) + (PORT d[4] (1802:1802:1802) (1896:1896:1896)) + (PORT d[5] (1361:1361:1361) (1443:1443:1443)) + (PORT d[6] (1899:1899:1899) (1972:1972:1972)) + (PORT d[7] (1610:1610:1610) (1703:1703:1703)) + (PORT d[8] (1514:1514:1514) (1576:1576:1576)) + (PORT d[9] (1871:1871:1871) (1964:1964:1964)) + (PORT d[10] (1829:1829:1829) (1909:1909:1909)) + (PORT d[11] (2023:2023:2023) (2085:2085:2085)) + (PORT d[12] (1618:1618:1618) (1714:1714:1714)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (PORT d[0] (1142:1142:1142) (1176:1176:1176)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (318:318:318)) + (PORT datac (608:608:608) (615:615:615)) + (PORT datad (891:891:891) (886:886:886)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2588:2588:2588) (2564:2564:2564)) + (PORT clk (1655:1655:1655) (1682:1682:1682)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1831:1831:1831) (1908:1908:1908)) + (PORT d[1] (1783:1783:1783) (1877:1877:1877)) + (PORT d[2] (1808:1808:1808) (1871:1871:1871)) + (PORT d[3] (1607:1607:1607) (1704:1704:1704)) + (PORT d[4] (2013:2013:2013) (2095:2095:2095)) + (PORT d[5] (1706:1706:1706) (1798:1798:1798)) + (PORT d[6] (1895:1895:1895) (2001:2001:2001)) + (PORT d[7] (1885:1885:1885) (1979:1979:1979)) + (PORT d[8] (1770:1770:1770) (1821:1821:1821)) + (PORT d[9] (1875:1875:1875) (1975:1975:1975)) + (PORT d[10] (2011:2011:2011) (2161:2161:2161)) + (PORT d[11] (1864:1864:1864) (1935:1935:1935)) + (PORT d[12] (1922:1922:1922) (2022:2022:2022)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (PORT d[0] (1402:1402:1402) (1421:1421:1421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1646:1646:1646)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2592:2592:2592) (2568:2568:2568)) + (PORT clk (1655:1655:1655) (1684:1684:1684)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1833:1833:1833) (1915:1915:1915)) + (PORT d[1] (1804:1804:1804) (1899:1899:1899)) + (PORT d[2] (1809:1809:1809) (1872:1872:1872)) + (PORT d[3] (1608:1608:1608) (1705:1705:1705)) + (PORT d[4] (2056:2056:2056) (2137:2137:2137)) + (PORT d[5] (1707:1707:1707) (1799:1799:1799)) + (PORT d[6] (1896:1896:1896) (2002:2002:2002)) + (PORT d[7] (1886:1886:1886) (1980:1980:1980)) + (PORT d[8] (1771:1771:1771) (1822:1822:1822)) + (PORT d[9] (1876:1876:1876) (1976:1976:1976)) + (PORT d[10] (2012:2012:2012) (2162:2162:2162)) + (PORT d[11] (1865:1865:1865) (1936:1936:1936)) + (PORT d[12] (1923:1923:1923) (2023:2023:2023)) + (PORT clk (1654:1654:1654) (1682:1682:1682)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1684:1684:1684)) + (PORT d[0] (1402:1402:1402) (1421:1421:1421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1685:1685:1685)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1685:1685:1685)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1685:1685:1685)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1685:1685:1685)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1648:1648:1648)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2578:2578:2578) (2553:2553:2553)) + (PORT clk (1656:1656:1656) (1683:1683:1683)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1802:1802:1802) (1856:1856:1856)) + (PORT d[1] (1798:1798:1798) (1899:1899:1899)) + (PORT d[2] (1858:1858:1858) (1885:1885:1885)) + (PORT d[3] (1630:1630:1630) (1727:1727:1727)) + (PORT d[4] (2012:2012:2012) (2112:2112:2112)) + (PORT d[5] (1616:1616:1616) (1694:1694:1694)) + (PORT d[6] (1863:1863:1863) (1938:1938:1938)) + (PORT d[7] (1884:1884:1884) (1983:1983:1983)) + (PORT d[8] (2108:2108:2108) (2174:2174:2174)) + (PORT d[9] (1901:1901:1901) (1995:1995:1995)) + (PORT d[10] (1545:1545:1545) (1626:1626:1626)) + (PORT d[11] (1843:1843:1843) (1914:1914:1914)) + (PORT d[12] (1939:1939:1939) (2044:2044:2044)) + (PORT clk (1653:1653:1653) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (PORT d[0] (1418:1418:1418) (1410:1410:1410)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2582:2582:2582) (2557:2557:2557)) + (PORT clk (1656:1656:1656) (1685:1685:1685)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1816:1816:1816) (1885:1885:1885)) + (PORT d[1] (1779:1779:1779) (1879:1879:1879)) + (PORT d[2] (2152:2152:2152) (2153:2153:2153)) + (PORT d[3] (1631:1631:1631) (1728:1728:1728)) + (PORT d[4] (1814:1814:1814) (1913:1913:1913)) + (PORT d[5] (1617:1617:1617) (1695:1695:1695)) + (PORT d[6] (1864:1864:1864) (1939:1939:1939)) + (PORT d[7] (1885:1885:1885) (1984:1984:1984)) + (PORT d[8] (2109:2109:2109) (2175:2175:2175)) + (PORT d[9] (1902:1902:1902) (1996:1996:1996)) + (PORT d[10] (1546:1546:1546) (1627:1627:1627)) + (PORT d[11] (1844:1844:1844) (1915:1915:1915)) + (PORT d[12] (1940:1940:1940) (2045:2045:2045)) + (PORT clk (1655:1655:1655) (1683:1683:1683)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1685:1685:1685)) + (PORT d[0] (1418:1418:1418) (1410:1410:1410)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1649:1649:1649)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (592:592:592) (577:577:577)) + (PORT datac (912:912:912) (984:984:984)) + (PORT datad (836:836:836) (801:801:801)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1976:1976:1976) (1978:1978:1978)) + (PORT clk (1649:1649:1649) (1676:1676:1676)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1927:1927:1927) (2057:2057:2057)) + (PORT d[1] (1848:1848:1848) (1935:1935:1935)) + (PORT d[2] (1742:1742:1742) (1794:1794:1794)) + (PORT d[3] (2299:2299:2299) (2356:2356:2356)) + (PORT d[4] (2323:2323:2323) (2419:2419:2419)) + (PORT d[5] (2012:2012:2012) (2052:2052:2052)) + (PORT d[6] (2084:2084:2084) (2172:2172:2172)) + (PORT d[7] (2042:2042:2042) (2129:2129:2129)) + (PORT d[8] (2074:2074:2074) (2160:2160:2160)) + (PORT d[9] (2067:2067:2067) (2132:2132:2132)) + (PORT d[10] (1880:1880:1880) (1983:1983:1983)) + (PORT d[11] (2124:2124:2124) (2205:2205:2205)) + (PORT d[12] (2072:2072:2072) (2153:2153:2153)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT d[0] (1746:1746:1746) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1677:1677:1677)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1677:1677:1677)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1677:1677:1677)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1677:1677:1677)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1640:1640:1640)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1980:1980:1980) (1982:1982:1982)) + (PORT clk (1649:1649:1649) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1920:1920:1920) (2060:2060:2060)) + (PORT d[1] (1870:1870:1870) (1958:1958:1958)) + (PORT d[2] (1737:1737:1737) (1806:1806:1806)) + (PORT d[3] (2300:2300:2300) (2357:2357:2357)) + (PORT d[4] (2178:2178:2178) (2246:2246:2246)) + (PORT d[5] (2013:2013:2013) (2053:2053:2053)) + (PORT d[6] (2085:2085:2085) (2173:2173:2173)) + (PORT d[7] (2043:2043:2043) (2130:2130:2130)) + (PORT d[8] (2075:2075:2075) (2161:2161:2161)) + (PORT d[9] (2068:2068:2068) (2133:2133:2133)) + (PORT d[10] (1881:1881:1881) (1984:1984:1984)) + (PORT d[11] (2125:2125:2125) (2206:2206:2206)) + (PORT d[12] (2073:2073:2073) (2154:2154:2154)) + (PORT clk (1648:1648:1648) (1676:1676:1676)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1678:1678:1678)) + (PORT d[0] (1746:1746:1746) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1679:1679:1679)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1679:1679:1679)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1679:1679:1679)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1679:1679:1679)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1642:1642:1642)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2943:2943:2943) (2939:2939:2939)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1581:1581:1581) (1660:1660:1660)) + (PORT d[1] (1840:1840:1840) (1925:1925:1925)) + (PORT d[2] (1624:1624:1624) (1665:1665:1665)) + (PORT d[3] (1599:1599:1599) (1691:1691:1691)) + (PORT d[4] (1841:1841:1841) (1935:1935:1935)) + (PORT d[5] (1403:1403:1403) (1484:1484:1484)) + (PORT d[6] (1929:1929:1929) (2040:2040:2040)) + (PORT d[7] (1873:1873:1873) (1970:1970:1970)) + (PORT d[8] (1769:1769:1769) (1820:1820:1820)) + (PORT d[9] (1856:1856:1856) (1929:1929:1929)) + (PORT d[10] (1566:1566:1566) (1643:1643:1643)) + (PORT d[11] (1835:1835:1835) (1901:1901:1901)) + (PORT d[12] (1874:1874:1874) (1971:1971:1971)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1218:1218:1218) (1192:1192:1192)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2947:2947:2947) (2943:2943:2943)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1639:1639:1639)) + (PORT d[1] (1828:1828:1828) (1897:1897:1897)) + (PORT d[2] (1798:1798:1798) (1859:1859:1859)) + (PORT d[3] (1600:1600:1600) (1692:1692:1692)) + (PORT d[4] (1842:1842:1842) (1936:1936:1936)) + (PORT d[5] (1404:1404:1404) (1485:1485:1485)) + (PORT d[6] (1930:1930:1930) (2041:2041:2041)) + (PORT d[7] (1874:1874:1874) (1971:1971:1971)) + (PORT d[8] (1770:1770:1770) (1821:1821:1821)) + (PORT d[9] (1857:1857:1857) (1930:1930:1930)) + (PORT d[10] (1567:1567:1567) (1644:1644:1644)) + (PORT d[11] (1836:1836:1836) (1902:1902:1902)) + (PORT d[12] (1875:1875:1875) (1972:1972:1972)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (1218:1218:1218) (1192:1192:1192)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2061:2061:2061) (2194:2194:2194)) + (PORT datac (845:845:845) (835:835:835)) + (PORT datad (1215:1215:1215) (1172:1172:1172)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2670:2670:2670) (2660:2660:2660)) + (PORT clk (1653:1653:1653) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1801:1801:1801) (1882:1882:1882)) + (PORT d[1] (1803:1803:1803) (1897:1897:1897)) + (PORT d[2] (1823:1823:1823) (1887:1887:1887)) + (PORT d[3] (1633:1633:1633) (1731:1731:1731)) + (PORT d[4] (1800:1800:1800) (1895:1895:1895)) + (PORT d[5] (1727:1727:1727) (1819:1819:1819)) + (PORT d[6] (1911:1911:1911) (1984:1984:1984)) + (PORT d[7] (1813:1813:1813) (1886:1886:1886)) + (PORT d[8] (2072:2072:2072) (2147:2147:2147)) + (PORT d[9] (1871:1871:1871) (1969:1969:1969)) + (PORT d[10] (2034:2034:2034) (2187:2187:2187)) + (PORT d[11] (2081:2081:2081) (2128:2128:2128)) + (PORT d[12] (1913:1913:1913) (2017:2017:2017)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (PORT d[0] (1417:1417:1417) (1433:1433:1433)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1644:1644:1644)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2674:2674:2674) (2664:2664:2664)) + (PORT clk (1653:1653:1653) (1682:1682:1682)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1782:1782:1782) (1861:1861:1861)) + (PORT d[1] (1790:1790:1790) (1876:1876:1876)) + (PORT d[2] (1778:1778:1778) (1844:1844:1844)) + (PORT d[3] (1634:1634:1634) (1732:1732:1732)) + (PORT d[4] (1781:1781:1781) (1875:1875:1875)) + (PORT d[5] (1728:1728:1728) (1820:1820:1820)) + (PORT d[6] (1912:1912:1912) (1985:1985:1985)) + (PORT d[7] (1814:1814:1814) (1887:1887:1887)) + (PORT d[8] (2073:2073:2073) (2148:2148:2148)) + (PORT d[9] (1872:1872:1872) (1970:1970:1970)) + (PORT d[10] (2035:2035:2035) (2188:2188:2188)) + (PORT d[11] (2082:2082:2082) (2129:2129:2129)) + (PORT d[12] (1914:1914:1914) (2018:2018:2018)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1682:1682:1682)) + (PORT d[0] (1417:1417:1417) (1433:1433:1433)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1618:1618:1618) (1646:1646:1646)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2136:2136:2136) (2135:2135:2135)) + (PORT clk (1657:1657:1657) (1683:1683:1683)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1816:1816:1816) (1907:1907:1907)) + (PORT d[1] (1779:1779:1779) (1879:1879:1879)) + (PORT d[2] (1754:1754:1754) (1812:1812:1812)) + (PORT d[3] (1869:1869:1869) (1959:1959:1959)) + (PORT d[4] (2052:2052:2052) (2146:2146:2146)) + (PORT d[5] (1646:1646:1646) (1724:1724:1724)) + (PORT d[6] (1869:1869:1869) (1956:1956:1956)) + (PORT d[7] (1872:1872:1872) (1961:1961:1961)) + (PORT d[8] (1741:1741:1741) (1799:1799:1799)) + (PORT d[9] (1869:1869:1869) (1964:1964:1964)) + (PORT d[10] (2133:2133:2133) (2201:2201:2201)) + (PORT d[11] (1866:1866:1866) (1911:1911:1911)) + (PORT d[12] (1919:1919:1919) (2023:2023:2023)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1683:1683:1683)) + (PORT d[0] (1446:1446:1446) (1411:1411:1411)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2140:2140:2140) (2139:2139:2139)) + (PORT clk (1657:1657:1657) (1685:1685:1685)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1796:1796:1796) (1887:1887:1887)) + (PORT d[1] (1780:1780:1780) (1880:1880:1880)) + (PORT d[2] (1768:1768:1768) (1842:1842:1842)) + (PORT d[3] (1870:1870:1870) (1960:1960:1960)) + (PORT d[4] (2074:2074:2074) (2167:2167:2167)) + (PORT d[5] (1647:1647:1647) (1725:1725:1725)) + (PORT d[6] (1870:1870:1870) (1957:1957:1957)) + (PORT d[7] (1873:1873:1873) (1962:1962:1962)) + (PORT d[8] (1742:1742:1742) (1800:1800:1800)) + (PORT d[9] (1870:1870:1870) (1965:1965:1965)) + (PORT d[10] (2134:2134:2134) (2202:2202:2202)) + (PORT d[11] (1867:1867:1867) (1912:1912:1912)) + (PORT d[12] (1920:1920:1920) (2024:2024:2024)) + (PORT clk (1656:1656:1656) (1683:1683:1683)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1685:1685:1685)) + (PORT d[0] (1446:1446:1446) (1411:1411:1411)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1686:1686:1686)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1622:1622:1622) (1649:1649:1649)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (536:536:536)) + (PORT datac (806:806:806) (852:852:852)) + (PORT datad (604:604:604) (607:607:607)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[14\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (333:333:333)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (754:754:754) (770:770:770)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (597:597:597)) + (PORT datad (420:420:420) (464:464:464)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2019:2019:2019) (1994:1994:1994)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1284:1284:1284)) + (PORT d[1] (1224:1224:1224) (1272:1272:1272)) + (PORT d[2] (1260:1260:1260) (1298:1298:1298)) + (PORT d[3] (1251:1251:1251) (1298:1298:1298)) + (PORT d[4] (1204:1204:1204) (1261:1261:1261)) + (PORT d[5] (1179:1179:1179) (1186:1186:1186)) + (PORT d[6] (1198:1198:1198) (1239:1239:1239)) + (PORT d[7] (1389:1389:1389) (1412:1412:1412)) + (PORT d[8] (1257:1257:1257) (1306:1306:1306)) + (PORT d[9] (1238:1238:1238) (1282:1282:1282)) + (PORT d[10] (1234:1234:1234) (1284:1284:1284)) + (PORT d[11] (1247:1247:1247) (1278:1278:1278)) + (PORT d[12] (1290:1290:1290) (1333:1333:1333)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (905:905:905) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datac (571:571:571) (597:597:597)) + (PORT datad (422:422:422) (463:463:463)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (842:842:842) (835:835:835)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1456:1456:1456) (1510:1510:1510)) + (PORT d[1] (1200:1200:1200) (1268:1268:1268)) + (PORT d[2] (1487:1487:1487) (1553:1553:1553)) + (PORT d[3] (1604:1604:1604) (1681:1681:1681)) + (PORT d[4] (1552:1552:1552) (1632:1632:1632)) + (PORT d[5] (1382:1382:1382) (1461:1461:1461)) + (PORT d[6] (1548:1548:1548) (1600:1600:1600)) + (PORT d[7] (1747:1747:1747) (1806:1806:1806)) + (PORT d[8] (1532:1532:1532) (1590:1590:1590)) + (PORT d[9] (1564:1564:1564) (1627:1627:1627)) + (PORT d[10] (1611:1611:1611) (1718:1718:1718)) + (PORT d[11] (1756:1756:1756) (1813:1813:1813)) + (PORT d[12] (1634:1634:1634) (1728:1728:1728)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1243:1243:1243) (1216:1216:1216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (596:596:596)) + (PORT datad (421:421:421) (463:463:463)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2401:2401:2401) (2407:2407:2407)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1653:1653:1653) (1699:1699:1699)) + (PORT d[1] (1711:1711:1711) (1773:1773:1773)) + (PORT d[2] (1396:1396:1396) (1415:1415:1415)) + (PORT d[3] (1383:1383:1383) (1382:1382:1382)) + (PORT d[4] (1433:1433:1433) (1449:1449:1449)) + (PORT d[5] (1225:1225:1225) (1263:1263:1263)) + (PORT d[6] (1442:1442:1442) (1494:1494:1494)) + (PORT d[7] (1640:1640:1640) (1687:1687:1687)) + (PORT d[8] (1194:1194:1194) (1236:1236:1236)) + (PORT d[9] (1159:1159:1159) (1202:1202:1202)) + (PORT d[10] (1170:1170:1170) (1220:1220:1220)) + (PORT d[11] (1222:1222:1222) (1249:1249:1249)) + (PORT d[12] (1114:1114:1114) (1145:1145:1145)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (993:993:993) (931:931:931)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (571:571:571) (594:594:594)) + (PORT datad (418:418:418) (460:460:460)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2248:2248:2248) (2259:2259:2259)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (950:950:950) (991:991:991)) + (PORT d[1] (970:970:970) (1028:1028:1028)) + (PORT d[2] (1002:1002:1002) (1049:1049:1049)) + (PORT d[3] (983:983:983) (1032:1032:1032)) + (PORT d[4] (1440:1440:1440) (1486:1486:1486)) + (PORT d[5] (977:977:977) (1014:1014:1014)) + (PORT d[6] (1025:1025:1025) (1073:1073:1073)) + (PORT d[7] (1175:1175:1175) (1213:1213:1213)) + (PORT d[8] (1228:1228:1228) (1263:1263:1263)) + (PORT d[9] (1023:1023:1023) (1076:1076:1076)) + (PORT d[10] (1241:1241:1241) (1287:1287:1287)) + (PORT d[11] (1046:1046:1046) (1093:1093:1093)) + (PORT d[12] (1190:1190:1190) (1219:1219:1219)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (779:779:779) (745:745:745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (606:606:606) (623:623:623)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1692:1692:1692)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (201:201:201) (259:259:259)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1716:1716:1716) (1790:1790:1790)) + (PORT datab (1053:1053:1053) (1028:1028:1028)) + (PORT datac (789:789:789) (789:789:789)) + (PORT datad (244:244:244) (318:318:318)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1087:1087:1087)) + (PORT datab (1322:1322:1322) (1323:1323:1323)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (244:244:244) (318:318:318)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1789:1789:1789) (1783:1783:1783)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2013:2013:2013) (2090:2090:2090)) + (PORT d[1] (1451:1451:1451) (1512:1512:1512)) + (PORT d[2] (1614:1614:1614) (1636:1636:1636)) + (PORT d[3] (1631:1631:1631) (1629:1629:1629)) + (PORT d[4] (1630:1630:1630) (1655:1655:1655)) + (PORT d[5] (1439:1439:1439) (1473:1473:1473)) + (PORT d[6] (1414:1414:1414) (1458:1458:1458)) + (PORT d[7] (1361:1361:1361) (1383:1383:1383)) + (PORT d[8] (1431:1431:1431) (1467:1467:1467)) + (PORT d[9] (1374:1374:1374) (1424:1424:1424)) + (PORT d[10] (1381:1381:1381) (1442:1442:1442)) + (PORT d[11] (1446:1446:1446) (1468:1468:1468)) + (PORT d[12] (1644:1644:1644) (1670:1670:1670)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1188:1188:1188) (1145:1145:1145)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2098:2098:2098) (2086:2086:2086)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1834:1834:1834) (1918:1918:1918)) + (PORT d[1] (1412:1412:1412) (1473:1473:1473)) + (PORT d[2] (1624:1624:1624) (1649:1649:1649)) + (PORT d[3] (1631:1631:1631) (1634:1634:1634)) + (PORT d[4] (1626:1626:1626) (1646:1646:1646)) + (PORT d[5] (1463:1463:1463) (1501:1501:1501)) + (PORT d[6] (1438:1438:1438) (1485:1485:1485)) + (PORT d[7] (1344:1344:1344) (1378:1378:1378)) + (PORT d[8] (1429:1429:1429) (1471:1471:1471)) + (PORT d[9] (1393:1393:1393) (1438:1438:1438)) + (PORT d[10] (1401:1401:1401) (1455:1455:1455)) + (PORT d[11] (1470:1470:1470) (1496:1496:1496)) + (PORT d[12] (1616:1616:1616) (1638:1638:1638)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1156:1156:1156) (1085:1085:1085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2516:2516:2516) (2536:2536:2536)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (976:976:976) (1028:1028:1028)) + (PORT d[1] (1004:1004:1004) (1051:1051:1051)) + (PORT d[2] (976:976:976) (1009:1009:1009)) + (PORT d[3] (1237:1237:1237) (1260:1260:1260)) + (PORT d[4] (1205:1205:1205) (1263:1263:1263)) + (PORT d[5] (968:968:968) (1005:1005:1005)) + (PORT d[6] (952:952:952) (988:988:988)) + (PORT d[7] (1139:1139:1139) (1163:1163:1163)) + (PORT d[8] (985:985:985) (1018:1018:1018)) + (PORT d[9] (1029:1029:1029) (1070:1070:1070)) + (PORT d[10] (1007:1007:1007) (1056:1056:1056)) + (PORT d[11] (1022:1022:1022) (1058:1058:1058)) + (PORT d[12] (1000:1000:1000) (1056:1056:1056)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (763:763:763) (705:705:705)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (876:876:876) (880:880:880)) @@ -2888,16 +7832,3838 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (927:927:927) (979:979:979)) - (PORT datac (562:562:562) (545:545:545)) - (PORT datad (978:978:978) (932:932:932)) + (PORT dataa (1419:1419:1419) (1526:1526:1526)) + (PORT datab (1396:1396:1396) (1399:1399:1399)) + (PORT datac (1222:1222:1222) (1181:1181:1181)) + (PORT datad (906:906:906) (957:957:957)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (846:846:846) (833:833:833)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1578:1578:1578) (1701:1701:1701)) + (PORT d[1] (1611:1611:1611) (1701:1701:1701)) + (PORT d[2] (2020:2020:2020) (2087:2087:2087)) + (PORT d[3] (1708:1708:1708) (1741:1741:1741)) + (PORT d[4] (1902:1902:1902) (1974:1974:1974)) + (PORT d[5] (1505:1505:1505) (1554:1554:1554)) + (PORT d[6] (1697:1697:1697) (1744:1744:1744)) + (PORT d[7] (2016:2016:2016) (2081:2081:2081)) + (PORT d[8] (1447:1447:1447) (1491:1491:1491)) + (PORT d[9] (1416:1416:1416) (1481:1481:1481)) + (PORT d[10] (1661:1661:1661) (1776:1776:1776)) + (PORT d[11] (1497:1497:1497) (1540:1540:1540)) + (PORT d[12] (1669:1669:1669) (1721:1721:1721)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1083:1083:1083) (1076:1076:1076)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1398:1398:1398)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1011:1011:1011) (986:986:986)) + (PORT datad (906:906:906) (964:964:964)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2274:2274:2274) (2288:2288:2288)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (958:958:958) (1000:1000:1000)) + (PORT d[1] (975:975:975) (1031:1031:1031)) + (PORT d[2] (1001:1001:1001) (1048:1048:1048)) + (PORT d[3] (1220:1220:1220) (1252:1252:1252)) + (PORT d[4] (984:984:984) (1041:1041:1041)) + (PORT d[5] (986:986:986) (1027:1027:1027)) + (PORT d[6] (988:988:988) (1041:1041:1041)) + (PORT d[7] (1175:1175:1175) (1212:1212:1212)) + (PORT d[8] (1010:1010:1010) (1057:1057:1057)) + (PORT d[9] (1022:1022:1022) (1075:1075:1075)) + (PORT d[10] (999:999:999) (1058:1058:1058)) + (PORT d[11] (1045:1045:1045) (1092:1092:1092)) + (PORT d[12] (1043:1043:1043) (1091:1091:1091)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (706:706:706) (665:665:665)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2122:2122:2122) (2118:2118:2118)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1381:1381:1381) (1424:1424:1424)) + (PORT d[1] (1710:1710:1710) (1772:1772:1772)) + (PORT d[2] (1429:1429:1429) (1475:1475:1475)) + (PORT d[3] (1394:1394:1394) (1403:1403:1403)) + (PORT d[4] (1405:1405:1405) (1433:1433:1433)) + (PORT d[5] (1209:1209:1209) (1255:1255:1255)) + (PORT d[6] (1455:1455:1455) (1494:1494:1494)) + (PORT d[7] (1640:1640:1640) (1686:1686:1686)) + (PORT d[8] (1202:1202:1202) (1255:1255:1255)) + (PORT d[9] (1148:1148:1148) (1200:1200:1200)) + (PORT d[10] (1158:1158:1158) (1217:1217:1217)) + (PORT d[11] (1206:1206:1206) (1241:1241:1241)) + (PORT d[12] (1415:1415:1415) (1450:1450:1450)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (980:980:980) (930:930:930)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2109:2109:2109) (2107:2107:2107)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1618:1618:1618) (1658:1658:1658)) + (PORT d[1] (1718:1718:1718) (1770:1770:1770)) + (PORT d[2] (1441:1441:1441) (1485:1485:1485)) + (PORT d[3] (1421:1421:1421) (1448:1448:1448)) + (PORT d[4] (1436:1436:1436) (1459:1459:1459)) + (PORT d[5] (1216:1216:1216) (1264:1264:1264)) + (PORT d[6] (1452:1452:1452) (1490:1490:1490)) + (PORT d[7] (1602:1602:1602) (1636:1636:1636)) + (PORT d[8] (1183:1183:1183) (1235:1235:1235)) + (PORT d[9] (1188:1188:1188) (1244:1244:1244)) + (PORT d[10] (1164:1164:1164) (1225:1225:1225)) + (PORT d[11] (1245:1245:1245) (1283:1283:1283)) + (PORT d[12] (1127:1127:1127) (1167:1167:1167)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (969:969:969) (940:940:940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1062:1062:1062)) + (PORT datab (270:270:270) (353:353:353)) + (PORT datac (1398:1398:1398) (1471:1471:1471)) + (PORT datad (1053:1053:1053) (1034:1034:1034)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2546:2546:2546) (2573:2573:2573)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (703:703:703) (745:745:745)) + (PORT d[1] (683:683:683) (727:727:727)) + (PORT d[2] (931:931:931) (960:960:960)) + (PORT d[3] (1223:1223:1223) (1251:1251:1251)) + (PORT d[4] (989:989:989) (1040:1040:1040)) + (PORT d[5] (1198:1198:1198) (1238:1238:1238)) + (PORT d[6] (940:940:940) (972:972:972)) + (PORT d[7] (1158:1158:1158) (1181:1181:1181)) + (PORT d[8] (968:968:968) (1004:1004:1004)) + (PORT d[9] (988:988:988) (1028:1028:1028)) + (PORT d[10] (1164:1164:1164) (1196:1196:1196)) + (PORT d[11] (1191:1191:1191) (1213:1213:1213)) + (PORT d[12] (1145:1145:1145) (1154:1154:1154)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (754:754:754) (706:706:706)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1627:1627:1627)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (762:762:762)) + (PORT datab (269:269:269) (353:353:353)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (760:760:760) (734:734:734)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1772:1772:1772) (1804:1804:1804)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1843:1843:1843) (1977:1977:1977)) + (PORT d[1] (1580:1580:1580) (1677:1677:1677)) + (PORT d[2] (1983:1983:1983) (2051:2051:2051)) + (PORT d[3] (2103:2103:2103) (2192:2192:2192)) + (PORT d[4] (1951:1951:1951) (2012:2012:2012)) + (PORT d[5] (1809:1809:1809) (1880:1880:1880)) + (PORT d[6] (1659:1659:1659) (1706:1706:1706)) + (PORT d[7] (1982:1982:1982) (2042:2042:2042)) + (PORT d[8] (1755:1755:1755) (1818:1818:1818)) + (PORT d[9] (1738:1738:1738) (1830:1830:1830)) + (PORT d[10] (1622:1622:1622) (1754:1754:1754)) + (PORT d[11] (1720:1720:1720) (1786:1786:1786)) + (PORT d[12] (1917:1917:1917) (1977:1977:1977)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (1265:1265:1265) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2806:2806:2806) (2845:2845:2845)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (966:966:966) (1011:1011:1011)) + (PORT d[1] (938:938:938) (997:997:997)) + (PORT d[2] (1198:1198:1198) (1237:1237:1237)) + (PORT d[3] (1257:1257:1257) (1319:1319:1319)) + (PORT d[4] (1270:1270:1270) (1336:1336:1336)) + (PORT d[5] (1372:1372:1372) (1448:1448:1448)) + (PORT d[6] (1256:1256:1256) (1310:1310:1310)) + (PORT d[7] (1464:1464:1464) (1511:1511:1511)) + (PORT d[8] (1242:1242:1242) (1290:1290:1290)) + (PORT d[9] (1275:1275:1275) (1328:1328:1328)) + (PORT d[10] (1258:1258:1258) (1332:1332:1332)) + (PORT d[11] (1470:1470:1470) (1503:1503:1503)) + (PORT d[12] (1229:1229:1229) (1258:1258:1258)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (1014:1014:1014) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1524:1524:1524)) + (PORT datab (949:949:949) (999:999:999)) + (PORT datac (1329:1329:1329) (1312:1312:1312)) + (PORT datad (997:997:997) (964:964:964)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2411:2411:2411) (2414:2414:2414)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1663:1663:1663) (1721:1721:1721)) + (PORT d[1] (959:959:959) (1001:1001:1001)) + (PORT d[2] (1143:1143:1143) (1186:1186:1186)) + (PORT d[3] (1087:1087:1087) (1109:1109:1109)) + (PORT d[4] (1150:1150:1150) (1174:1174:1174)) + (PORT d[5] (971:971:971) (1020:1020:1020)) + (PORT d[6] (1466:1466:1466) (1521:1521:1521)) + (PORT d[7] (1437:1437:1437) (1466:1466:1466)) + (PORT d[8] (930:930:930) (967:967:967)) + (PORT d[9] (877:877:877) (919:919:919)) + (PORT d[10] (977:977:977) (1016:1016:1016)) + (PORT d[11] (906:906:906) (944:944:944)) + (PORT d[12] (883:883:883) (915:915:915)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (735:735:735) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2801:2801:2801) (2820:2820:2820)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (998:998:998)) + (PORT d[1] (924:924:924) (970:970:970)) + (PORT d[2] (941:941:941) (970:970:970)) + (PORT d[3] (994:994:994) (1036:1036:1036)) + (PORT d[4] (965:965:965) (1016:1016:1016)) + (PORT d[5] (1412:1412:1412) (1493:1493:1493)) + (PORT d[6] (984:984:984) (1029:1029:1029)) + (PORT d[7] (1193:1193:1193) (1229:1229:1229)) + (PORT d[8] (977:977:977) (1024:1024:1024)) + (PORT d[9] (1019:1019:1019) (1071:1071:1071)) + (PORT d[10] (1176:1176:1176) (1216:1216:1216)) + (PORT d[11] (1237:1237:1237) (1265:1265:1265)) + (PORT d[12] (972:972:972) (1015:1015:1015)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (757:757:757) (716:716:716)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (945:945:945) (993:993:993)) + (PORT datac (1023:1023:1023) (1023:1023:1023)) + (PORT datad (969:969:969) (939:939:939)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2120:2120:2120) (2118:2118:2118)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1345:1345:1345) (1396:1396:1396)) + (PORT d[1] (1168:1168:1168) (1224:1224:1224)) + (PORT d[2] (1440:1440:1440) (1484:1484:1484)) + (PORT d[3] (1421:1421:1421) (1445:1445:1445)) + (PORT d[4] (1435:1435:1435) (1458:1458:1458)) + (PORT d[5] (1240:1240:1240) (1292:1292:1292)) + (PORT d[6] (1163:1163:1163) (1216:1216:1216)) + (PORT d[7] (1131:1131:1131) (1148:1148:1148)) + (PORT d[8] (1182:1182:1182) (1234:1234:1234)) + (PORT d[9] (1187:1187:1187) (1243:1243:1243)) + (PORT d[10] (1163:1163:1163) (1224:1224:1224)) + (PORT d[11] (1219:1219:1219) (1253:1253:1253)) + (PORT d[12] (1151:1151:1151) (1186:1186:1186)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (975:975:975) (944:944:944)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1129:1129:1129) (1138:1138:1138)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1576:1576:1576) (1690:1690:1690)) + (PORT d[1] (1257:1257:1257) (1308:1308:1308)) + (PORT d[2] (1422:1422:1422) (1464:1464:1464)) + (PORT d[3] (1497:1497:1497) (1539:1539:1539)) + (PORT d[4] (1679:1679:1679) (1737:1737:1737)) + (PORT d[5] (1256:1256:1256) (1305:1305:1305)) + (PORT d[6] (1421:1421:1421) (1460:1460:1460)) + (PORT d[7] (1724:1724:1724) (1778:1778:1778)) + (PORT d[8] (1174:1174:1174) (1207:1207:1207)) + (PORT d[9] (1143:1143:1143) (1200:1200:1200)) + (PORT d[10] (1628:1628:1628) (1759:1759:1759)) + (PORT d[11] (1171:1171:1171) (1220:1220:1220)) + (PORT d[12] (1390:1390:1390) (1431:1431:1431)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1049:1049:1049) (984:984:984)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3048:3048:3048) (3087:3087:3087)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1288:1288:1288) (1341:1341:1341)) + (PORT d[1] (1198:1198:1198) (1262:1262:1262)) + (PORT d[2] (1259:1259:1259) (1316:1316:1316)) + (PORT d[3] (1261:1261:1261) (1319:1319:1319)) + (PORT d[4] (1257:1257:1257) (1328:1328:1328)) + (PORT d[5] (1381:1381:1381) (1446:1446:1446)) + (PORT d[6] (1518:1518:1518) (1575:1575:1575)) + (PORT d[7] (1523:1523:1523) (1576:1576:1576)) + (PORT d[8] (1290:1290:1290) (1340:1340:1340)) + (PORT d[9] (1310:1310:1310) (1377:1377:1377)) + (PORT d[10] (1248:1248:1248) (1314:1314:1314)) + (PORT d[11] (1722:1722:1722) (1758:1758:1758)) + (PORT d[12] (1602:1602:1602) (1688:1688:1688)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (974:974:974) (928:928:928)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1526:1526:1526)) + (PORT datab (946:946:946) (1000:1000:1000)) + (PORT datac (788:788:788) (766:766:766)) + (PORT datad (1141:1141:1141) (1132:1132:1132)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (849:849:849) (867:867:867)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1474:1474:1474) (1535:1535:1535)) + (PORT d[1] (1851:1851:1851) (1928:1928:1928)) + (PORT d[2] (1496:1496:1496) (1566:1566:1566)) + (PORT d[3] (1593:1593:1593) (1669:1669:1669)) + (PORT d[4] (1739:1739:1739) (1818:1818:1818)) + (PORT d[5] (1363:1363:1363) (1439:1439:1439)) + (PORT d[6] (1536:1536:1536) (1596:1596:1596)) + (PORT d[7] (1756:1756:1756) (1820:1820:1820)) + (PORT d[8] (1550:1550:1550) (1628:1628:1628)) + (PORT d[9] (1605:1605:1605) (1688:1688:1688)) + (PORT d[10] (1577:1577:1577) (1685:1685:1685)) + (PORT d[11] (1447:1447:1447) (1488:1488:1488)) + (PORT d[12] (1633:1633:1633) (1720:1720:1720)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1200:1200:1200) (1169:1169:1169)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1312:1312:1312)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1270:1270:1270) (1243:1243:1243)) + (PORT datad (910:910:910) (957:957:957)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2810:2810:2810) (2848:2848:2848)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (985:985:985) (1032:1032:1032)) + (PORT d[1] (1166:1166:1166) (1199:1199:1199)) + (PORT d[2] (943:943:943) (974:974:974)) + (PORT d[3] (1000:1000:1000) (1058:1058:1058)) + (PORT d[4] (974:974:974) (1029:1029:1029)) + (PORT d[5] (1398:1398:1398) (1477:1477:1477)) + (PORT d[6] (980:980:980) (1019:1019:1019)) + (PORT d[7] (1228:1228:1228) (1268:1268:1268)) + (PORT d[8] (1010:1010:1010) (1062:1062:1062)) + (PORT d[9] (1005:1005:1005) (1059:1059:1059)) + (PORT d[10] (1187:1187:1187) (1225:1225:1225)) + (PORT d[11] (1191:1191:1191) (1224:1224:1224)) + (PORT d[12] (1009:1009:1009) (1055:1055:1055)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (727:727:727) (696:696:696)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1416:1416:1416) (1433:1433:1433)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1558:1558:1558) (1674:1674:1674)) + (PORT d[1] (1236:1236:1236) (1286:1286:1286)) + (PORT d[2] (1486:1486:1486) (1541:1541:1541)) + (PORT d[3] (1384:1384:1384) (1412:1412:1412)) + (PORT d[4] (1366:1366:1366) (1419:1419:1419)) + (PORT d[5] (1230:1230:1230) (1276:1276:1276)) + (PORT d[6] (1416:1416:1416) (1452:1452:1452)) + (PORT d[7] (1733:1733:1733) (1798:1798:1798)) + (PORT d[8] (1199:1199:1199) (1234:1234:1234)) + (PORT d[9] (1163:1163:1163) (1221:1221:1221)) + (PORT d[10] (1220:1220:1220) (1287:1287:1287)) + (PORT d[11] (1237:1237:1237) (1277:1277:1277)) + (PORT d[12] (1369:1369:1369) (1408:1408:1408)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1000:1000:1000) (964:964:964)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2788:2788:2788) (2821:2821:2821)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (946:946:946) (982:982:982)) + (PORT d[1] (933:933:933) (988:988:988)) + (PORT d[2] (1013:1013:1013) (1049:1049:1049)) + (PORT d[3] (976:976:976) (1031:1031:1031)) + (PORT d[4] (974:974:974) (1029:1029:1029)) + (PORT d[5] (1386:1386:1386) (1464:1464:1464)) + (PORT d[6] (1256:1256:1256) (1301:1301:1301)) + (PORT d[7] (1207:1207:1207) (1246:1246:1246)) + (PORT d[8] (983:983:983) (1032:1032:1032)) + (PORT d[9] (1025:1025:1025) (1080:1080:1080)) + (PORT d[10] (1161:1161:1161) (1196:1196:1196)) + (PORT d[11] (1264:1264:1264) (1292:1292:1292)) + (PORT d[12] (1160:1160:1160) (1184:1184:1184)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (785:785:785) (747:747:747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (872:872:872)) + (PORT datab (950:950:950) (994:994:994)) + (PORT datac (978:978:978) (949:949:949)) + (PORT datad (1392:1392:1392) (1484:1484:1484)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3061:3061:3061) (3086:3086:3086)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1256:1256:1256) (1311:1311:1311)) + (PORT d[1] (1190:1190:1190) (1241:1241:1241)) + (PORT d[2] (1217:1217:1217) (1258:1258:1258)) + (PORT d[3] (1261:1261:1261) (1324:1324:1324)) + (PORT d[4] (1247:1247:1247) (1314:1314:1314)) + (PORT d[5] (1394:1394:1394) (1470:1470:1470)) + (PORT d[6] (1282:1282:1282) (1339:1339:1339)) + (PORT d[7] (1502:1502:1502) (1554:1554:1554)) + (PORT d[8] (1251:1251:1251) (1307:1307:1307)) + (PORT d[9] (1304:1304:1304) (1369:1369:1369)) + (PORT d[10] (1484:1484:1484) (1542:1542:1542)) + (PORT d[11] (1484:1484:1484) (1531:1531:1531)) + (PORT d[12] (1233:1233:1233) (1278:1278:1278)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (1033:1033:1033) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (721:721:721)) + (PORT datab (944:944:944) (994:994:994)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (1009:1009:1009) (972:972:972)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1388:1388:1388) (1408:1408:1408)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1697:1697:1697) (1753:1753:1753)) + (PORT d[1] (1250:1250:1250) (1299:1299:1299)) + (PORT d[2] (1380:1380:1380) (1426:1426:1426)) + (PORT d[3] (1380:1380:1380) (1410:1410:1410)) + (PORT d[4] (1363:1363:1363) (1407:1407:1407)) + (PORT d[5] (1225:1225:1225) (1269:1269:1269)) + (PORT d[6] (1433:1433:1433) (1461:1461:1461)) + (PORT d[7] (1163:1163:1163) (1202:1202:1202)) + (PORT d[8] (1439:1439:1439) (1464:1464:1464)) + (PORT d[9] (1161:1161:1161) (1219:1219:1219)) + (PORT d[10] (1441:1441:1441) (1495:1495:1495)) + (PORT d[11] (1166:1166:1166) (1213:1213:1213)) + (PORT d[12] (1393:1393:1393) (1412:1412:1412)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (1018:1018:1018) (944:944:944)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2391:2391:2391) (2394:2394:2394)) + (PORT clk (1626:1626:1626) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1675:1675:1675) (1730:1730:1730)) + (PORT d[1] (1437:1437:1437) (1460:1460:1460)) + (PORT d[2] (1414:1414:1414) (1447:1447:1447)) + (PORT d[3] (1400:1400:1400) (1420:1420:1420)) + (PORT d[4] (1359:1359:1359) (1382:1382:1382)) + (PORT d[5] (1195:1195:1195) (1228:1228:1228)) + (PORT d[6] (1165:1165:1165) (1188:1188:1188)) + (PORT d[7] (1430:1430:1430) (1454:1454:1454)) + (PORT d[8] (1181:1181:1181) (1204:1204:1204)) + (PORT d[9] (1126:1126:1126) (1168:1168:1168)) + (PORT d[10] (1495:1495:1495) (1563:1563:1563)) + (PORT d[11] (1191:1191:1191) (1216:1216:1216)) + (PORT d[12] (1354:1354:1354) (1383:1383:1383)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1626:1626:1626) (1655:1655:1655)) + (PORT d[0] (979:979:979) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1619:1619:1619)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (861:861:861) (866:866:866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (900:900:900)) + (PORT datab (816:816:816) (796:796:796)) + (PORT datac (1044:1044:1044) (1008:1008:1008)) + (PORT datad (1584:1584:1584) (1626:1626:1626)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1124:1124:1124) (1131:1131:1131)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1491:1491:1491) (1582:1582:1582)) + (PORT d[1] (1507:1507:1507) (1554:1554:1554)) + (PORT d[2] (1712:1712:1712) (1756:1756:1756)) + (PORT d[3] (1651:1651:1651) (1679:1679:1679)) + (PORT d[4] (1674:1674:1674) (1745:1745:1745)) + (PORT d[5] (1524:1524:1524) (1583:1583:1583)) + (PORT d[6] (1711:1711:1711) (1749:1749:1749)) + (PORT d[7] (1451:1451:1451) (1515:1515:1515)) + (PORT d[8] (1467:1467:1467) (1511:1511:1511)) + (PORT d[9] (1438:1438:1438) (1495:1495:1495)) + (PORT d[10] (1623:1623:1623) (1752:1752:1752)) + (PORT d[11] (1556:1556:1556) (1610:1610:1610)) + (PORT d[12] (1662:1662:1662) (1712:1712:1712)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (1143:1143:1143) (1159:1159:1159)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2539:2539:2539) (2563:2563:2563)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (677:677:677) (719:719:719)) + (PORT d[1] (676:676:676) (718:718:718)) + (PORT d[2] (694:694:694) (717:717:717)) + (PORT d[3] (742:742:742) (767:767:767)) + (PORT d[4] (1205:1205:1205) (1258:1258:1258)) + (PORT d[5] (793:793:793) (834:834:834)) + (PORT d[6] (1236:1236:1236) (1255:1255:1255)) + (PORT d[7] (698:698:698) (730:730:730)) + (PORT d[8] (699:699:699) (737:737:737)) + (PORT d[9] (714:714:714) (751:751:751)) + (PORT d[10] (723:723:723) (763:763:763)) + (PORT d[11] (741:741:741) (774:774:774)) + (PORT d[12] (1635:1635:1635) (1718:1718:1718)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (662:662:662) (590:590:590)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (898:898:898)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1068:1068:1068) (1024:1024:1024)) + (PORT datad (973:973:973) (922:922:922)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2529:2529:2529) (2535:2535:2535)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (978:978:978) (1036:1036:1036)) + (PORT d[1] (984:984:984) (1046:1046:1046)) + (PORT d[2] (1008:1008:1008) (1053:1053:1053)) + (PORT d[3] (1014:1014:1014) (1059:1059:1059)) + (PORT d[4] (974:974:974) (1025:1025:1025)) + (PORT d[5] (1671:1671:1671) (1757:1757:1757)) + (PORT d[6] (1223:1223:1223) (1259:1259:1259)) + (PORT d[7] (1148:1148:1148) (1182:1182:1182)) + (PORT d[8] (992:992:992) (1032:1032:1032)) + (PORT d[9] (1017:1017:1017) (1067:1067:1067)) + (PORT d[10] (970:970:970) (1025:1025:1025)) + (PORT d[11] (1007:1007:1007) (1050:1050:1050)) + (PORT d[12] (1055:1055:1055) (1109:1109:1109)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (755:755:755) (724:724:724)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1125:1125:1125)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1511:1511:1511) (1566:1566:1566)) + (PORT d[1] (1563:1563:1563) (1645:1645:1645)) + (PORT d[2] (1756:1756:1756) (1832:1832:1832)) + (PORT d[3] (1563:1563:1563) (1654:1654:1654)) + (PORT d[4] (1748:1748:1748) (1829:1829:1829)) + (PORT d[5] (1347:1347:1347) (1425:1425:1425)) + (PORT d[6] (1570:1570:1570) (1654:1654:1654)) + (PORT d[7] (2007:2007:2007) (2072:2072:2072)) + (PORT d[8] (1848:1848:1848) (1916:1916:1916)) + (PORT d[9] (1861:1861:1861) (1952:1952:1952)) + (PORT d[10] (1317:1317:1317) (1412:1412:1412)) + (PORT d[11] (1983:1983:1983) (2040:2040:2040)) + (PORT d[12] (1654:1654:1654) (1743:1743:1743)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (992:992:992) (964:964:964)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (814:814:814)) + (PORT datab (270:270:270) (353:353:353)) + (PORT datac (1396:1396:1396) (1469:1469:1469)) + (PORT datad (1345:1345:1345) (1353:1353:1353)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3071:3071:3071) (3114:3114:3114)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1268:1268:1268) (1320:1320:1320)) + (PORT d[1] (1217:1217:1217) (1285:1285:1285)) + (PORT d[2] (1440:1440:1440) (1483:1483:1483)) + (PORT d[3] (1589:1589:1589) (1675:1675:1675)) + (PORT d[4] (1257:1257:1257) (1328:1328:1328)) + (PORT d[5] (1355:1355:1355) (1427:1427:1427)) + (PORT d[6] (1522:1522:1522) (1581:1581:1581)) + (PORT d[7] (1484:1484:1484) (1521:1521:1521)) + (PORT d[8] (1280:1280:1280) (1341:1341:1341)) + (PORT d[9] (1290:1290:1290) (1357:1357:1357)) + (PORT d[10] (1282:1282:1282) (1367:1367:1367)) + (PORT d[11] (1462:1462:1462) (1504:1504:1504)) + (PORT d[12] (1654:1654:1654) (1743:1743:1743)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1035:1035:1035) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2260:2260:2260) (2262:2262:2262)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1223:1223:1223) (1262:1262:1262)) + (PORT d[1] (1223:1223:1223) (1276:1276:1276)) + (PORT d[2] (1236:1236:1236) (1281:1281:1281)) + (PORT d[3] (1314:1314:1314) (1349:1349:1349)) + (PORT d[4] (1450:1450:1450) (1495:1495:1495)) + (PORT d[5] (1199:1199:1199) (1232:1232:1232)) + (PORT d[6] (1196:1196:1196) (1242:1242:1242)) + (PORT d[7] (1387:1387:1387) (1415:1415:1415)) + (PORT d[8] (1235:1235:1235) (1279:1279:1279)) + (PORT d[9] (1257:1257:1257) (1296:1296:1296)) + (PORT d[10] (1230:1230:1230) (1275:1275:1275)) + (PORT d[11] (1271:1271:1271) (1306:1306:1306)) + (PORT d[12] (1240:1240:1240) (1279:1279:1279)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (925:925:925) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (271:271:271) (357:357:357)) + (PORT datac (1078:1078:1078) (1062:1062:1062)) + (PORT datad (998:998:998) (968:968:968)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (865:865:865)) + (PORT datac (654:654:654) (711:711:711)) + (PORT datad (598:598:598) (588:588:588)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (1015:1015:1015)) + (PORT datac (570:570:570) (553:553:553)) + (PORT datad (318:318:318) (317:317:317)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (902:902:902)) + (PORT datab (938:938:938) (1009:1009:1009)) + (PORT datad (1400:1400:1400) (1445:1445:1445)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (1015:1015:1015)) + (PORT datac (594:594:594) (599:599:599)) + (PORT datad (597:597:597) (586:586:586)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (940:940:940) (1012:1012:1012)) + (PORT datac (1222:1222:1222) (1191:1191:1191)) + (PORT datad (581:581:581) (581:581:581)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (614:614:614)) + (PORT datac (913:913:913) (984:984:984)) + (PORT datad (605:605:605) (608:608:608)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1846:1846:1846) (1889:1889:1889)) + (PORT datac (589:589:589) (596:596:596)) + (PORT datad (319:319:319) (318:318:318)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (868:868:868)) + (PORT datac (908:908:908) (977:977:977)) + (PORT datad (1020:1020:1020) (1011:1011:1011)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index e44946c..7f22f9c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:47:24" +// DATE "03/30/2022 14:56:19" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -30,9 +30,11 @@ module spectrum ( CLOCK_50, - LED); + LED, + GPIO_0); input CLOCK_50; output [7:0] LED; +output [33:0] GPIO_0; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -43,6 +45,40 @@ output [7:0] LED; // LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[0] => Location: PIN_D3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[1] => Location: PIN_C3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[2] => Location: PIN_A2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[3] => Location: PIN_A3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[4] => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[5] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[6] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[7] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[8] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[9] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[10] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[11] => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[12] => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[13] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[14] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[15] => Location: PIN_C6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[16] => Location: PIN_C8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[17] => Location: PIN_E6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[18] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[19] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[20] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[21] => Location: PIN_F8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[22] => Location: PIN_F9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[23] => Location: PIN_E9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[24] => Location: PIN_C9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[25] => Location: PIN_D9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[26] => Location: PIN_E11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[27] => Location: PIN_E10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[28] => Location: PIN_C11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[29] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[30] => Location: PIN_A12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[31] => Location: PIN_D11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[32] => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[33] => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -69,6 +105,40 @@ wire \LED[4]~output_o ; wire \LED[5]~output_o ; wire \LED[6]~output_o ; wire \LED[7]~output_o ; +wire \GPIO_0[0]~output_o ; +wire \GPIO_0[1]~output_o ; +wire \GPIO_0[2]~output_o ; +wire \GPIO_0[3]~output_o ; +wire \GPIO_0[4]~output_o ; +wire \GPIO_0[5]~output_o ; +wire \GPIO_0[6]~output_o ; +wire \GPIO_0[7]~output_o ; +wire \GPIO_0[8]~output_o ; +wire \GPIO_0[9]~output_o ; +wire \GPIO_0[10]~output_o ; +wire \GPIO_0[11]~output_o ; +wire \GPIO_0[12]~output_o ; +wire \GPIO_0[13]~output_o ; +wire \GPIO_0[14]~output_o ; +wire \GPIO_0[15]~output_o ; +wire \GPIO_0[16]~output_o ; +wire \GPIO_0[17]~output_o ; +wire \GPIO_0[18]~output_o ; +wire \GPIO_0[19]~output_o ; +wire \GPIO_0[20]~output_o ; +wire \GPIO_0[21]~output_o ; +wire \GPIO_0[22]~output_o ; +wire \GPIO_0[23]~output_o ; +wire \GPIO_0[24]~output_o ; +wire \GPIO_0[25]~output_o ; +wire \GPIO_0[26]~output_o ; +wire \GPIO_0[27]~output_o ; +wire \GPIO_0[28]~output_o ; +wire \GPIO_0[29]~output_o ; +wire \GPIO_0[30]~output_o ; +wire \GPIO_0[31]~output_o ; +wire \GPIO_0[32]~output_o ; +wire \GPIO_0[33]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; wire \counter[0]~63_combout ; @@ -113,67 +183,200 @@ wire \counter[19]~58 ; wire \counter[20]~59_combout ; wire \counter[20]~60 ; wire \counter[21]~61_combout ; +wire \Equal0~7_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; +wire \A[0]~40_combout ; +wire \A[1]~14_combout ; wire \Equal0~6_combout ; -wire \A[0]~39_combout ; -wire \A[1]~13_combout ; -wire \A[1]~14 ; -wire \A[2]~15_combout ; -wire \A[2]~16 ; -wire \A[3]~17_combout ; -wire \A[3]~18 ; -wire \A[4]~19_combout ; -wire \A[4]~20 ; -wire \A[5]~21_combout ; -wire \A[5]~22 ; -wire \A[6]~23_combout ; -wire \A[6]~24 ; -wire \A[7]~25_combout ; -wire \A[7]~26 ; -wire \A[8]~27_combout ; -wire \A[8]~28 ; -wire \A[9]~29_combout ; -wire \A[9]~30 ; -wire \A[10]~31_combout ; -wire \A[10]~32 ; -wire \A[11]~33_combout ; -wire \A[11]~34 ; -wire \A[12]~35_combout ; -wire \A[12]~36 ; -wire \A[13]~37_combout ; +wire \A[1]~15 ; +wire \A[2]~16_combout ; +wire \A[2]~17 ; +wire \A[3]~18_combout ; +wire \A[3]~19 ; +wire \A[4]~20_combout ; +wire \A[4]~21 ; +wire \A[5]~22_combout ; +wire \A[5]~23 ; +wire \A[6]~24_combout ; +wire \A[6]~25 ; +wire \A[7]~26_combout ; +wire \A[7]~27 ; +wire \A[8]~28_combout ; +wire \A[8]~29 ; +wire \A[9]~30_combout ; +wire \A[9]~31 ; +wire \A[10]~32_combout ; +wire \A[10]~33 ; +wire \A[11]~34_combout ; +wire \A[11]~35 ; +wire \A[12]~36_combout ; +wire \A[12]~37 ; +wire \A[13]~38_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; wire \~GND~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ; +wire \A[13]~39 ; +wire \A[14]~41_combout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ; wire [21:0] counter; wire [15:0] A; -wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -182,14 +385,102 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_b wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -207,9 +498,105 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +609,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +622,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -248,7 +635,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -261,7 +648,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -274,7 +661,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -287,7 +674,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -300,7 +687,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -311,6 +698,448 @@ defparam \LED[7]~output .bus_hold = "false"; defparam \LED[7]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X1_Y34_N9 +cycloneive_io_obuf \GPIO_0[0]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[0]~output .bus_hold = "false"; +defparam \GPIO_0[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y34_N2 +cycloneive_io_obuf \GPIO_0[1]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[1]~output .bus_hold = "false"; +defparam \GPIO_0[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N9 +cycloneive_io_obuf \GPIO_0[2]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[2]~output .bus_hold = "false"; +defparam \GPIO_0[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N16 +cycloneive_io_obuf \GPIO_0[3]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[3]~output .bus_hold = "false"; +defparam \GPIO_0[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \GPIO_0[4]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[4]~output .bus_hold = "false"; +defparam \GPIO_0[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N2 +cycloneive_io_obuf \GPIO_0[5]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[5]~output .bus_hold = "false"; +defparam \GPIO_0[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N23 +cycloneive_io_obuf \GPIO_0[6]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[6]~output .bus_hold = "false"; +defparam \GPIO_0[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y34_N2 +cycloneive_io_obuf \GPIO_0[7]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[7]~output .bus_hold = "false"; +defparam \GPIO_0[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N23 +cycloneive_io_obuf \GPIO_0[8]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[8]~output .bus_hold = "false"; +defparam \GPIO_0[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y34_N16 +cycloneive_io_obuf \GPIO_0[9]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[9]~output .bus_hold = "false"; +defparam \GPIO_0[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N9 +cycloneive_io_obuf \GPIO_0[10]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[10]~output .bus_hold = "false"; +defparam \GPIO_0[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N2 +cycloneive_io_obuf \GPIO_0[11]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[11]~output .bus_hold = "false"; +defparam \GPIO_0[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N2 +cycloneive_io_obuf \GPIO_0[12]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[12]~output .bus_hold = "false"; +defparam \GPIO_0[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N9 +cycloneive_io_obuf \GPIO_0[13]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[13]~output .bus_hold = "false"; +defparam \GPIO_0[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N23 +cycloneive_io_obuf \GPIO_0[14]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[14]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[14]~output .bus_hold = "false"; +defparam \GPIO_0[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N23 +cycloneive_io_obuf \GPIO_0[15]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[15]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[15]~output .bus_hold = "false"; +defparam \GPIO_0[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N16 +cycloneive_io_obuf \GPIO_0[16]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[16]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[16]~output .bus_hold = "false"; +defparam \GPIO_0[16]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N16 +cycloneive_io_obuf \GPIO_0[17]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[17]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[17]~output .bus_hold = "false"; +defparam \GPIO_0[17]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N16 +cycloneive_io_obuf \GPIO_0[18]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[18]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[18]~output .bus_hold = "false"; +defparam \GPIO_0[18]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N23 +cycloneive_io_obuf \GPIO_0[19]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[19]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[19]~output .bus_hold = "false"; +defparam \GPIO_0[19]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N9 +cycloneive_io_obuf \GPIO_0[20]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[20]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[20]~output .bus_hold = "false"; +defparam \GPIO_0[20]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N16 +cycloneive_io_obuf \GPIO_0[21]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[21]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[21]~output .bus_hold = "false"; +defparam \GPIO_0[21]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y34_N2 +cycloneive_io_obuf \GPIO_0[22]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[22]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[22]~output .bus_hold = "false"; +defparam \GPIO_0[22]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X29_Y34_N16 +cycloneive_io_obuf \GPIO_0[23]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[23]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[23]~output .bus_hold = "false"; +defparam \GPIO_0[23]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N2 +cycloneive_io_obuf \GPIO_0[24]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[24]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[24]~output .bus_hold = "false"; +defparam \GPIO_0[24]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N9 +cycloneive_io_obuf \GPIO_0[25]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[25]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[25]~output .bus_hold = "false"; +defparam \GPIO_0[25]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N9 +cycloneive_io_obuf \GPIO_0[26]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[26]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[26]~output .bus_hold = "false"; +defparam \GPIO_0[26]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N16 +cycloneive_io_obuf \GPIO_0[27]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[27]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[27]~output .bus_hold = "false"; +defparam \GPIO_0[27]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X38_Y34_N2 +cycloneive_io_obuf \GPIO_0[28]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[28]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[28]~output .bus_hold = "false"; +defparam \GPIO_0[28]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X40_Y34_N9 +cycloneive_io_obuf \GPIO_0[29]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[29]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[29]~output .bus_hold = "false"; +defparam \GPIO_0[29]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N16 +cycloneive_io_obuf \GPIO_0[30]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[30]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[30]~output .bus_hold = "false"; +defparam \GPIO_0[30]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N16 +cycloneive_io_obuf \GPIO_0[31]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[31]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[31]~output .bus_hold = "false"; +defparam \GPIO_0[31]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N23 +cycloneive_io_obuf \GPIO_0[32]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[32]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[32]~output .bus_hold = "false"; +defparam \GPIO_0[32]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N23 +cycloneive_io_obuf \GPIO_0[33]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[33]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[33]~output .bus_hold = "false"; +defparam \GPIO_0[33]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -334,7 +1163,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 +// Location: LCCOMB_X31_Y7_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -351,7 +1180,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X31_Y7_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -370,7 +1199,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 +// Location: LCCOMB_X31_Y7_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -388,7 +1217,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N13 +// Location: FF_X31_Y7_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -407,7 +1236,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N14 +// Location: LCCOMB_X31_Y7_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -425,7 +1254,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N15 +// Location: FF_X31_Y7_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -444,7 +1273,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 +// Location: LCCOMB_X31_Y7_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -462,7 +1291,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N17 +// Location: FF_X31_Y7_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -481,7 +1310,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N18 +// Location: LCCOMB_X31_Y7_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -499,7 +1328,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N19 +// Location: FF_X31_Y7_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -518,7 +1347,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N20 +// Location: LCCOMB_X31_Y7_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -536,7 +1365,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N21 +// Location: FF_X31_Y7_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -555,7 +1384,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N22 +// Location: LCCOMB_X31_Y7_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -573,7 +1402,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N23 +// Location: FF_X31_Y7_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -592,7 +1421,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 +// Location: LCCOMB_X31_Y7_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -610,7 +1439,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N25 +// Location: FF_X31_Y7_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -629,7 +1458,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 +// Location: LCCOMB_X31_Y7_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -647,7 +1476,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N27 +// Location: FF_X31_Y7_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -666,7 +1495,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N28 +// Location: LCCOMB_X31_Y7_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -684,7 +1513,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N29 +// Location: FF_X31_Y7_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -703,7 +1532,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 +// Location: LCCOMB_X31_Y7_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -721,7 +1550,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N31 +// Location: FF_X31_Y7_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -740,7 +1569,7 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N0 +// Location: LCCOMB_X31_Y6_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) @@ -758,7 +1587,7 @@ defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N1 +// Location: FF_X31_Y6_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[11]~41_combout ), @@ -777,7 +1606,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N2 +// Location: LCCOMB_X31_Y6_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -795,7 +1624,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N3 +// Location: FF_X31_Y6_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -814,7 +1643,7 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N4 +// Location: LCCOMB_X31_Y6_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) @@ -832,7 +1661,7 @@ defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N5 +// Location: FF_X31_Y6_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -851,7 +1680,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N6 +// Location: LCCOMB_X31_Y6_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -869,7 +1698,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N7 +// Location: FF_X31_Y6_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -888,25 +1717,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N8 +// Location: LCCOMB_X31_Y6_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(counter[15]), - .datab(gnd), + .dataa(gnd), + .datab(counter[15]), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hA50A; +defparam \counter[15]~49 .lut_mask = 16'hC30C; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N9 +// Location: FF_X31_Y6_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -925,7 +1754,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N10 +// Location: LCCOMB_X31_Y6_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -943,7 +1772,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N11 +// Location: FF_X31_Y6_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -962,7 +1791,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N12 +// Location: LCCOMB_X31_Y6_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -980,7 +1809,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N13 +// Location: FF_X31_Y6_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -999,7 +1828,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N14 +// Location: LCCOMB_X31_Y6_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1017,7 +1846,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N15 +// Location: FF_X31_Y6_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1036,7 +1865,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 +// Location: LCCOMB_X31_Y6_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1054,7 +1883,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N17 +// Location: FF_X31_Y6_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1073,7 +1902,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N18 +// Location: LCCOMB_X31_Y6_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1091,7 +1920,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N19 +// Location: FF_X31_Y6_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1110,7 +1939,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N20 +// Location: LCCOMB_X31_Y6_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1127,7 +1956,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N21 +// Location: FF_X31_Y6_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1146,7 +1975,24 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N24 +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[20] & !counter[21]) + + .dataa(counter[20]), + .datab(gnd), + .datac(counter[21]), + .datad(gnd), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0505; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N24 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): // \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) @@ -1163,7 +2009,7 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N4 +// Location: LCCOMB_X31_Y7_N4 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): // \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) @@ -1180,15 +2026,15 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 +// Location: LCCOMB_X31_Y7_N10 cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) .dataa(counter[6]), - .datab(counter[4]), - .datac(counter[7]), - .datad(counter[5]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), .cin(gnd), .combout(\Equal0~1_combout ), .cout()); @@ -1197,14 +2043,14 @@ defparam \Equal0~1 .lut_mask = 16'h0001; defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N26 +// Location: LCCOMB_X31_Y7_N8 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) +// \Equal0~2_combout = (!counter[8] & (!counter[9] & (!counter[10] & !counter[11]))) - .dataa(counter[10]), + .dataa(counter[8]), .datab(counter[9]), - .datac(counter[8]), + .datac(counter[10]), .datad(counter[11]), .cin(gnd), .combout(\Equal0~2_combout ), @@ -1214,7 +2060,7 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N30 +// Location: LCCOMB_X31_Y6_N30 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): // \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) @@ -1231,7 +2077,7 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N28 +// Location: LCCOMB_X30_Y7_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): // \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) @@ -1248,44 +2094,27 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \Equal0~6 ( +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \A[0]~40 ( // Equation(s): -// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) +// \A[0]~40_combout = A[0] $ (((\Equal0~7_combout & (\Equal0~5_combout & \Equal0~4_combout )))) - .dataa(counter[20]), - .datab(counter[21]), - .datac(\Equal0~5_combout ), + .dataa(\Equal0~7_combout ), + .datab(\Equal0~5_combout ), + .datac(A[0]), .datad(\Equal0~4_combout ), .cin(gnd), - .combout(\Equal0~6_combout ), + .combout(\A[0]~40_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h1000; -defparam \Equal0~6 .sum_lutc_input = "datac"; +defparam \A[0]~40 .lut_mask = 16'h78F0; +defparam \A[0]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \A[0]~39 ( -// Equation(s): -// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(A[0]), - .datad(\Equal0~6_combout ), - .cin(gnd), - .combout(\A[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \A[0]~39 .lut_mask = 16'h0FF0; -defparam \A[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 +// Location: FF_X31_Y7_N1 dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[0]~39_combout ), + .d(\A[0]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1301,28 +2130,45 @@ defparam \A[0] .is_wysiwyg = "true"; defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \A[1]~13 ( +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \A[1]~14 ( // Equation(s): -// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) -// \A[1]~14 = CARRY((A[1] & A[0])) +// \A[1]~14_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~15 = CARRY((A[1] & A[0])) .dataa(A[1]), .datab(A[0]), .datac(gnd), .datad(vcc), .cin(gnd), - .combout(\A[1]~13_combout ), - .cout(\A[1]~14 )); + .combout(\A[1]~14_combout ), + .cout(\A[1]~15 )); // synopsys translate_off -defparam \A[1]~13 .lut_mask = 16'h6688; -defparam \A[1]~13 .sum_lutc_input = "datac"; +defparam \A[1]~14 .lut_mask = 16'h6688; +defparam \A[1]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y14_N1 +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \Equal0~6 ( +// Equation(s): +// \Equal0~6_combout = (!counter[21] & (!counter[20] & (\Equal0~5_combout & \Equal0~4_combout ))) + + .dataa(counter[21]), + .datab(counter[20]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~6 .lut_mask = 16'h1000; +defparam \Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N1 dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[1]~13_combout ), + .d(\A[1]~14_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1338,28 +2184,28 @@ defparam \A[1] .is_wysiwyg = "true"; defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \A[2]~15 ( +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \A[2]~16 ( // Equation(s): -// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) -// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) +// \A[2]~16_combout = (A[2] & (!\A[1]~15 )) # (!A[2] & ((\A[1]~15 ) # (GND))) +// \A[2]~17 = CARRY((!\A[1]~15 ) # (!A[2])) .dataa(gnd), .datab(A[2]), .datac(gnd), .datad(vcc), - .cin(\A[1]~14 ), - .combout(\A[2]~15_combout ), - .cout(\A[2]~16 )); + .cin(\A[1]~15 ), + .combout(\A[2]~16_combout ), + .cout(\A[2]~17 )); // synopsys translate_off -defparam \A[2]~15 .lut_mask = 16'h3C3F; -defparam \A[2]~15 .sum_lutc_input = "cin"; +defparam \A[2]~16 .lut_mask = 16'h3C3F; +defparam \A[2]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N3 +// Location: FF_X30_Y7_N3 dffeas \A[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[2]~15_combout ), + .d(\A[2]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1375,28 +2221,28 @@ defparam \A[2] .is_wysiwyg = "true"; defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \A[3]~17 ( +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \A[3]~18 ( // Equation(s): -// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) -// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) +// \A[3]~18_combout = (A[3] & (\A[2]~17 $ (GND))) # (!A[3] & (!\A[2]~17 & VCC)) +// \A[3]~19 = CARRY((A[3] & !\A[2]~17 )) .dataa(gnd), .datab(A[3]), .datac(gnd), .datad(vcc), - .cin(\A[2]~16 ), - .combout(\A[3]~17_combout ), - .cout(\A[3]~18 )); + .cin(\A[2]~17 ), + .combout(\A[3]~18_combout ), + .cout(\A[3]~19 )); // synopsys translate_off -defparam \A[3]~17 .lut_mask = 16'hC30C; -defparam \A[3]~17 .sum_lutc_input = "cin"; +defparam \A[3]~18 .lut_mask = 16'hC30C; +defparam \A[3]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N5 +// Location: FF_X30_Y7_N5 dffeas \A[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[3]~17_combout ), + .d(\A[3]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1412,28 +2258,28 @@ defparam \A[3] .is_wysiwyg = "true"; defparam \A[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \A[4]~19 ( +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \A[4]~20 ( // Equation(s): -// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) -// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) +// \A[4]~20_combout = (A[4] & (!\A[3]~19 )) # (!A[4] & ((\A[3]~19 ) # (GND))) +// \A[4]~21 = CARRY((!\A[3]~19 ) # (!A[4])) .dataa(A[4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[3]~18 ), - .combout(\A[4]~19_combout ), - .cout(\A[4]~20 )); + .cin(\A[3]~19 ), + .combout(\A[4]~20_combout ), + .cout(\A[4]~21 )); // synopsys translate_off -defparam \A[4]~19 .lut_mask = 16'h5A5F; -defparam \A[4]~19 .sum_lutc_input = "cin"; +defparam \A[4]~20 .lut_mask = 16'h5A5F; +defparam \A[4]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N7 +// Location: FF_X30_Y7_N7 dffeas \A[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[4]~19_combout ), + .d(\A[4]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1449,28 +2295,28 @@ defparam \A[4] .is_wysiwyg = "true"; defparam \A[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \A[5]~21 ( +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \A[5]~22 ( // Equation(s): -// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) -// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) +// \A[5]~22_combout = (A[5] & (\A[4]~21 $ (GND))) # (!A[5] & (!\A[4]~21 & VCC)) +// \A[5]~23 = CARRY((A[5] & !\A[4]~21 )) .dataa(gnd), .datab(A[5]), .datac(gnd), .datad(vcc), - .cin(\A[4]~20 ), - .combout(\A[5]~21_combout ), - .cout(\A[5]~22 )); + .cin(\A[4]~21 ), + .combout(\A[5]~22_combout ), + .cout(\A[5]~23 )); // synopsys translate_off -defparam \A[5]~21 .lut_mask = 16'hC30C; -defparam \A[5]~21 .sum_lutc_input = "cin"; +defparam \A[5]~22 .lut_mask = 16'hC30C; +defparam \A[5]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N9 +// Location: FF_X30_Y7_N9 dffeas \A[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[5]~21_combout ), + .d(\A[5]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1486,28 +2332,28 @@ defparam \A[5] .is_wysiwyg = "true"; defparam \A[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \A[6]~23 ( +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \A[6]~24 ( // Equation(s): -// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) -// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) +// \A[6]~24_combout = (A[6] & (!\A[5]~23 )) # (!A[6] & ((\A[5]~23 ) # (GND))) +// \A[6]~25 = CARRY((!\A[5]~23 ) # (!A[6])) .dataa(A[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[5]~22 ), - .combout(\A[6]~23_combout ), - .cout(\A[6]~24 )); + .cin(\A[5]~23 ), + .combout(\A[6]~24_combout ), + .cout(\A[6]~25 )); // synopsys translate_off -defparam \A[6]~23 .lut_mask = 16'h5A5F; -defparam \A[6]~23 .sum_lutc_input = "cin"; +defparam \A[6]~24 .lut_mask = 16'h5A5F; +defparam \A[6]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N11 +// Location: FF_X30_Y7_N11 dffeas \A[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[6]~23_combout ), + .d(\A[6]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1523,28 +2369,28 @@ defparam \A[6] .is_wysiwyg = "true"; defparam \A[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \A[7]~25 ( +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \A[7]~26 ( // Equation(s): -// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) -// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) +// \A[7]~26_combout = (A[7] & (\A[6]~25 $ (GND))) # (!A[7] & (!\A[6]~25 & VCC)) +// \A[7]~27 = CARRY((A[7] & !\A[6]~25 )) .dataa(A[7]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[6]~24 ), - .combout(\A[7]~25_combout ), - .cout(\A[7]~26 )); + .cin(\A[6]~25 ), + .combout(\A[7]~26_combout ), + .cout(\A[7]~27 )); // synopsys translate_off -defparam \A[7]~25 .lut_mask = 16'hA50A; -defparam \A[7]~25 .sum_lutc_input = "cin"; +defparam \A[7]~26 .lut_mask = 16'hA50A; +defparam \A[7]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N13 +// Location: FF_X30_Y7_N13 dffeas \A[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[7]~25_combout ), + .d(\A[7]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1560,28 +2406,28 @@ defparam \A[7] .is_wysiwyg = "true"; defparam \A[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \A[8]~27 ( +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \A[8]~28 ( // Equation(s): -// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) -// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) +// \A[8]~28_combout = (A[8] & (!\A[7]~27 )) # (!A[8] & ((\A[7]~27 ) # (GND))) +// \A[8]~29 = CARRY((!\A[7]~27 ) # (!A[8])) - .dataa(A[8]), - .datab(gnd), + .dataa(gnd), + .datab(A[8]), .datac(gnd), .datad(vcc), - .cin(\A[7]~26 ), - .combout(\A[8]~27_combout ), - .cout(\A[8]~28 )); + .cin(\A[7]~27 ), + .combout(\A[8]~28_combout ), + .cout(\A[8]~29 )); // synopsys translate_off -defparam \A[8]~27 .lut_mask = 16'h5A5F; -defparam \A[8]~27 .sum_lutc_input = "cin"; +defparam \A[8]~28 .lut_mask = 16'h3C3F; +defparam \A[8]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N15 +// Location: FF_X30_Y7_N15 dffeas \A[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[8]~27_combout ), + .d(\A[8]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1597,28 +2443,28 @@ defparam \A[8] .is_wysiwyg = "true"; defparam \A[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \A[9]~29 ( +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \A[9]~30 ( // Equation(s): -// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) -// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) +// \A[9]~30_combout = (A[9] & (\A[8]~29 $ (GND))) # (!A[9] & (!\A[8]~29 & VCC)) +// \A[9]~31 = CARRY((A[9] & !\A[8]~29 )) .dataa(gnd), .datab(A[9]), .datac(gnd), .datad(vcc), - .cin(\A[8]~28 ), - .combout(\A[9]~29_combout ), - .cout(\A[9]~30 )); + .cin(\A[8]~29 ), + .combout(\A[9]~30_combout ), + .cout(\A[9]~31 )); // synopsys translate_off -defparam \A[9]~29 .lut_mask = 16'hC30C; -defparam \A[9]~29 .sum_lutc_input = "cin"; +defparam \A[9]~30 .lut_mask = 16'hC30C; +defparam \A[9]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N17 +// Location: FF_X30_Y7_N17 dffeas \A[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[9]~29_combout ), + .d(\A[9]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1634,28 +2480,28 @@ defparam \A[9] .is_wysiwyg = "true"; defparam \A[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \A[10]~31 ( +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \A[10]~32 ( // Equation(s): -// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) -// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) +// \A[10]~32_combout = (A[10] & (!\A[9]~31 )) # (!A[10] & ((\A[9]~31 ) # (GND))) +// \A[10]~33 = CARRY((!\A[9]~31 ) # (!A[10])) .dataa(gnd), .datab(A[10]), .datac(gnd), .datad(vcc), - .cin(\A[9]~30 ), - .combout(\A[10]~31_combout ), - .cout(\A[10]~32 )); + .cin(\A[9]~31 ), + .combout(\A[10]~32_combout ), + .cout(\A[10]~33 )); // synopsys translate_off -defparam \A[10]~31 .lut_mask = 16'h3C3F; -defparam \A[10]~31 .sum_lutc_input = "cin"; +defparam \A[10]~32 .lut_mask = 16'h3C3F; +defparam \A[10]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N19 +// Location: FF_X30_Y7_N19 dffeas \A[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[10]~31_combout ), + .d(\A[10]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1671,28 +2517,28 @@ defparam \A[10] .is_wysiwyg = "true"; defparam \A[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \A[11]~33 ( +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \A[11]~34 ( // Equation(s): -// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) -// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) +// \A[11]~34_combout = (A[11] & (\A[10]~33 $ (GND))) # (!A[11] & (!\A[10]~33 & VCC)) +// \A[11]~35 = CARRY((A[11] & !\A[10]~33 )) .dataa(gnd), .datab(A[11]), .datac(gnd), .datad(vcc), - .cin(\A[10]~32 ), - .combout(\A[11]~33_combout ), - .cout(\A[11]~34 )); + .cin(\A[10]~33 ), + .combout(\A[11]~34_combout ), + .cout(\A[11]~35 )); // synopsys translate_off -defparam \A[11]~33 .lut_mask = 16'hC30C; -defparam \A[11]~33 .sum_lutc_input = "cin"; +defparam \A[11]~34 .lut_mask = 16'hC30C; +defparam \A[11]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N21 +// Location: FF_X30_Y7_N21 dffeas \A[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[11]~33_combout ), + .d(\A[11]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1708,28 +2554,28 @@ defparam \A[11] .is_wysiwyg = "true"; defparam \A[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \A[12]~35 ( +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \A[12]~36 ( // Equation(s): -// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) -// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) +// \A[12]~36_combout = (A[12] & (!\A[11]~35 )) # (!A[12] & ((\A[11]~35 ) # (GND))) +// \A[12]~37 = CARRY((!\A[11]~35 ) # (!A[12])) .dataa(A[12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[11]~34 ), - .combout(\A[12]~35_combout ), - .cout(\A[12]~36 )); + .cin(\A[11]~35 ), + .combout(\A[12]~36_combout ), + .cout(\A[12]~37 )); // synopsys translate_off -defparam \A[12]~35 .lut_mask = 16'h5A5F; -defparam \A[12]~35 .sum_lutc_input = "cin"; +defparam \A[12]~36 .lut_mask = 16'h5A5F; +defparam \A[12]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N23 +// Location: FF_X30_Y7_N23 dffeas \A[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[12]~35_combout ), + .d(\A[12]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1745,27 +2591,28 @@ defparam \A[12] .is_wysiwyg = "true"; defparam \A[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \A[13]~37 ( +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \A[13]~38 ( // Equation(s): -// \A[13]~37_combout = \A[12]~36 $ (!A[13]) +// \A[13]~38_combout = (A[13] & (\A[12]~37 $ (GND))) # (!A[13] & (!\A[12]~37 & VCC)) +// \A[13]~39 = CARRY((A[13] & !\A[12]~37 )) .dataa(gnd), - .datab(gnd), + .datab(A[13]), .datac(gnd), - .datad(A[13]), - .cin(\A[12]~36 ), - .combout(\A[13]~37_combout ), - .cout()); + .datad(vcc), + .cin(\A[12]~37 ), + .combout(\A[13]~38_combout ), + .cout(\A[13]~39 )); // synopsys translate_off -defparam \A[13]~37 .lut_mask = 16'hF00F; -defparam \A[13]~37 .sum_lutc_input = "cin"; +defparam \A[13]~38 .lut_mask = 16'hC30C; +defparam \A[13]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N25 +// Location: FF_X30_Y7_N25 dffeas \A[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[13]~37_combout ), + .d(\A[13]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1781,301 +2628,8 @@ defparam \A[13] .is_wysiwyg = "true"; defparam \A[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2098,39 +2652,1216 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X32_Y26_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N3 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N5 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y28_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X21_Y31_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y28_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .lut_mask = 16'hFA50; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N18 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .lut_mask = 16'hFC0C; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N26 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -2186,97 +3917,81 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] - - .dataa(gnd), - .datab(gnd), - .datac(A[13]), - .datad(gnd), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N16 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - .dataa(gnd), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datab(gnd), - .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y14_N17 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2332,7 +4047,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y21_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2388,25 +4103,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X21_Y28_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hAAF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2462,7 +4177,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y15_N0 +// Location: M9K_X22_Y12_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -2518,81 +4233,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(A[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 +// Location: M9K_X22_Y27_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(vcc), .portare(vcc), @@ -2648,22 +4307,3086 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N30 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y29_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .lut_mask = 16'hF5A0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \A[14]~41 ( +// Equation(s): +// \A[14]~41_combout = A[14] $ (\A[13]~39 ) + + .dataa(A[14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\A[13]~39 ), + .combout(\A[14]~41_combout ), + .cout()); +// synopsys translate_off +defparam \A[14]~41 .lut_mask = 16'h5A5A; +defparam \A[14]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X30_Y7_N27 +dffeas \A[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[14]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[14]), + .prn(vcc)); +// synopsys translate_off +defparam \A[14] .is_wysiwyg = "true"; +defparam \A[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00F0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout = (A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .lut_mask = 16'hF000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2] = (!A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .lut_mask = 16'h000F; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout = (!A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .lut_mask = 16'h0F00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout = A[14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N1 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hAAE4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .lut_mask = 16'hF2C2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hB9A8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hEE50; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .lut_mask = 16'hEE22; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N14 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .lut_mask = 16'hF3C0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .lut_mask = 16'hFA0A; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; @@ -2682,4 +7405,72 @@ assign LED[6] = \LED[6]~output_o ; assign LED[7] = \LED[7]~output_o ; +assign GPIO_0[0] = \GPIO_0[0]~output_o ; + +assign GPIO_0[1] = \GPIO_0[1]~output_o ; + +assign GPIO_0[2] = \GPIO_0[2]~output_o ; + +assign GPIO_0[3] = \GPIO_0[3]~output_o ; + +assign GPIO_0[4] = \GPIO_0[4]~output_o ; + +assign GPIO_0[5] = \GPIO_0[5]~output_o ; + +assign GPIO_0[6] = \GPIO_0[6]~output_o ; + +assign GPIO_0[7] = \GPIO_0[7]~output_o ; + +assign GPIO_0[8] = \GPIO_0[8]~output_o ; + +assign GPIO_0[9] = \GPIO_0[9]~output_o ; + +assign GPIO_0[10] = \GPIO_0[10]~output_o ; + +assign GPIO_0[11] = \GPIO_0[11]~output_o ; + +assign GPIO_0[12] = \GPIO_0[12]~output_o ; + +assign GPIO_0[13] = \GPIO_0[13]~output_o ; + +assign GPIO_0[14] = \GPIO_0[14]~output_o ; + +assign GPIO_0[15] = \GPIO_0[15]~output_o ; + +assign GPIO_0[16] = \GPIO_0[16]~output_o ; + +assign GPIO_0[17] = \GPIO_0[17]~output_o ; + +assign GPIO_0[18] = \GPIO_0[18]~output_o ; + +assign GPIO_0[19] = \GPIO_0[19]~output_o ; + +assign GPIO_0[20] = \GPIO_0[20]~output_o ; + +assign GPIO_0[21] = \GPIO_0[21]~output_o ; + +assign GPIO_0[22] = \GPIO_0[22]~output_o ; + +assign GPIO_0[23] = \GPIO_0[23]~output_o ; + +assign GPIO_0[24] = \GPIO_0[24]~output_o ; + +assign GPIO_0[25] = \GPIO_0[25]~output_o ; + +assign GPIO_0[26] = \GPIO_0[26]~output_o ; + +assign GPIO_0[27] = \GPIO_0[27]~output_o ; + +assign GPIO_0[28] = \GPIO_0[28]~output_o ; + +assign GPIO_0[29] = \GPIO_0[29]~output_o ; + +assign GPIO_0[30] = \GPIO_0[30]~output_o ; + +assign GPIO_0[31] = \GPIO_0[31]~output_o ; + +assign GPIO_0[32] = \GPIO_0[32]~output_o ; + +assign GPIO_0[33] = \GPIO_0[33]~output_o ; + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 074a56c..75d2580 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:47:24") + (DATE "03/30/2022 14:56:19") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2240:2240:2240) (2288:2288:2288)) + (PORT i (1079:1079:1079) (1118:1118:1118)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2683:2683:2683) (2776:2776:2776)) + (PORT i (1927:1927:1927) (1971:1971:1971)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2672:2672:2672) (2728:2728:2728)) + (PORT i (1553:1553:1553) (1570:1570:1570)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1887:1887:1887) (1922:1922:1922)) + (PORT i (2547:2547:2547) (2782:2782:2782)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2419:2419:2419) (2498:2498:2498)) + (PORT i (1256:1256:1256) (1326:1326:1326)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1958:1958:1958) (2059:2059:2059)) + (PORT i (1315:1315:1315) (1355:1355:1355)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2348:2348:2348) (2361:2361:2361)) + (PORT i (1625:1625:1625) (1695:1695:1695)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,11 +111,331 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1275:1275:1275) (1275:1275:1275)) + (PORT i (1490:1490:1490) (1603:1603:1603)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1423:1423:1423) (1461:1461:1461)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1507:1507:1507) (1522:1522:1522)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1054:1054:1054) (1041:1041:1041)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1986:1986:1986) (2103:2103:2103)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1427:1427:1427) (1432:1432:1432)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1282:1282:1282) (1273:1273:1273)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1710:1710:1710) (1721:1721:1721)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1242:1242:1242) (1238:1238:1238)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1805:1805:1805) (1868:1868:1868)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1456:1456:1456) (1507:1507:1507)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (985:985:985) (976:976:976)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1324:1324:1324) (1362:1362:1362)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1106:1106:1106) (1123:1123:1123)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1331:1331:1331) (1387:1387:1387)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1729:1729:1729) (1767:1767:1767)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1595:1595:1595) (1671:1671:1671)) + (IOPATH i o (4557:4557:4557) (4190:4190:4190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[16\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2420:2420:2420) (2529:2529:2529)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[17\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2351:2351:2351) (2435:2435:2435)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[18\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2730:2730:2730) (2802:2802:2802)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[19\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1903:1903:1903) (1989:1989:1989)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[20\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1900:1900:1900) (1959:1959:1959)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[21\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2199:2199:2199) (2286:2286:2286)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[22\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2004:2004:2004) (2002:2002:2002)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[23\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2135:2135:2135) (2240:2240:2240)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[24\]\~output) + (DELAY + (ABSOLUTE + (PORT i (845:845:845) (883:883:883)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[25\]\~output) + (DELAY + (ABSOLUTE + (PORT i (812:812:812) (809:809:809)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[26\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1171:1171:1171) (1139:1139:1139)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[27\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1042:1042:1042) (1061:1061:1061)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[28\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1020:1020:1020) (1007:1007:1007)) + (IOPATH i o (4557:4557:4557) (4190:4190:4190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[29\]\~output) + (DELAY + (ABSOLUTE + (PORT i (988:988:988) (994:994:994)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[30\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1458:1458:1458) (1462:1462:1462)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[31\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1426:1426:1426) (1430:1430:1430)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -148,7 +468,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -177,7 +497,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -205,7 +525,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -233,7 +553,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -247,7 +567,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -261,7 +581,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -275,7 +595,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (263:263:263) (346:346:346)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -289,7 +609,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -317,7 +637,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -331,7 +651,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (262:262:262) (344:344:344)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -345,7 +665,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -359,7 +679,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (350:350:350)) + (PORT dataa (251:251:251) (341:341:341)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -373,7 +693,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -387,7 +707,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (262:262:262) (344:344:344)) + (PORT datab (250:250:250) (334:334:334)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -401,7 +721,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -415,7 +735,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (350:350:350)) + (PORT dataa (252:252:252) (340:340:340)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -429,7 +749,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -457,7 +777,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -471,7 +791,7 @@ (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) + (PORT datab (409:409:409) (473:473:473)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -485,7 +805,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -513,7 +833,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -541,7 +861,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -555,9 +875,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (479:479:479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -569,7 +889,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -597,7 +917,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -625,7 +945,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -653,7 +973,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -681,7 +1001,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -709,7 +1029,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -734,7 +1054,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -743,14 +1063,26 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (771:771:771)) + (PORT datac (699:699:699) (751:751:751)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (253:253:253) (343:343:343)) (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (302:302:302)) + (PORT datac (224:224:224) (303:303:303)) (PORT datad (225:225:225) (298:298:298)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -764,10 +1096,10 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datab (249:249:249) (334:334:334)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (250:250:250) (335:335:335)) (PORT datac (223:223:223) (301:301:301)) - (PORT datad (224:224:224) (296:296:296)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -780,9 +1112,9 @@ (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (381:381:381) (442:442:442)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (380:380:380) (441:441:441)) (PORT datad (226:226:226) (299:299:299)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -796,10 +1128,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (406:406:406) (480:480:480)) - (PORT datac (566:566:566) (611:611:611)) - (PORT datad (576:576:576) (620:620:620)) + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (306:306:306)) + (PORT datad (382:382:382) (438:438:438)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -812,10 +1144,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (238:238:238) (315:315:315)) - (PORT datad (228:228:228) (300:300:300)) + (PORT dataa (255:255:255) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (239:239:239) (316:316:316)) + (PORT datad (240:240:240) (310:310:310)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -829,9 +1161,9 @@ (DELAY (ABSOLUTE (PORT dataa (388:388:388) (416:416:416)) - (PORT datab (345:345:345) (380:380:380)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (640:640:640) (652:652:652)) + (PORT datab (348:348:348) (385:385:385)) + (PORT datac (348:348:348) (372:372:372)) + (PORT datad (612:612:612) (622:622:622)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -841,26 +1173,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~6) + (INSTANCE A\[0\]\~40) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (955:955:955)) - (PORT datab (926:926:926) (973:973:973)) - (PORT datac (615:615:615) (635:635:635)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT datad (330:330:330) (344:344:344)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (634:634:634) (650:650:650)) + (PORT datad (356:356:356) (373:373:373)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -871,7 +1191,7 @@ (INSTANCE A\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -882,11 +1202,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[1\]\~13) + (INSTANCE A\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (449:449:449) (522:522:522)) - (PORT datab (618:618:618) (683:683:683)) + (PORT dataa (454:454:454) (533:533:533)) + (PORT datab (446:446:446) (522:522:522)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -895,14 +1215,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (951:951:951)) + (PORT datab (672:672:672) (743:743:743)) + (PORT datac (574:574:574) (595:595:595)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE A\[1\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -913,7 +1249,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[2\]\~15) + (INSTANCE A\[2\]\~16) (DELAY (ABSOLUTE (PORT datab (261:261:261) (343:343:343)) @@ -930,9 +1266,9 @@ (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -943,7 +1279,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[3\]\~17) + (INSTANCE A\[3\]\~18) (DELAY (ABSOLUTE (PORT datab (262:262:262) (344:344:344)) @@ -960,9 +1296,9 @@ (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -973,10 +1309,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[4\]\~19) + (INSTANCE A\[4\]\~20) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (351:351:351)) + (PORT dataa (264:264:264) (351:351:351)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -990,9 +1326,9 @@ (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (830:830:830) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1003,10 +1339,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[5\]\~21) + (INSTANCE A\[5\]\~22) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (345:345:345)) + (PORT datab (283:283:283) (365:365:365)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1020,9 +1356,9 @@ (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1033,10 +1369,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[6\]\~23) + (INSTANCE A\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) + (PORT dataa (285:285:285) (373:373:373)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1050,9 +1386,9 @@ (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1063,10 +1399,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[7\]\~25) + (INSTANCE A\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) + (PORT dataa (285:285:285) (373:373:373)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1080,9 +1416,9 @@ (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1093,12 +1429,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[8\]\~27) + (INSTANCE A\[8\]\~28) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (480:480:480)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1110,9 +1446,9 @@ (INSTANCE A\[8\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1123,10 +1459,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[9\]\~29) + (INSTANCE A\[9\]\~30) (DELAY (ABSOLUTE - (PORT datab (284:284:284) (367:367:367)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1140,9 +1476,9 @@ (INSTANCE A\[9\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1153,7 +1489,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[10\]\~31) + (INSTANCE A\[10\]\~32) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1170,9 +1506,9 @@ (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1183,10 +1519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[11\]\~33) + (INSTANCE A\[11\]\~34) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) + (PORT datab (284:284:284) (368:368:368)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1200,9 +1536,9 @@ (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1213,7 +1549,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[12\]\~35) + (INSTANCE A\[12\]\~36) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (352:352:352)) @@ -1230,9 +1566,9 @@ (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1243,12 +1579,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[13\]\~37) + (INSTANCE A\[13\]\~38) (DELAY (ABSOLUTE - (PORT datad (258:258:258) (327:327:327)) + (PORT datab (283:283:283) (366:366:366)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -1257,9 +1596,9 @@ (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (830:830:830) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1270,11 +1609,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1043:1043:1043) (1097:1097:1097)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (2043:2043:2043) (2263:2263:2263)) + (PORT d[1] (2019:2019:2019) (2202:2202:2202)) + (PORT d[2] (1854:1854:1854) (2009:2009:2009)) + (PORT d[3] (2468:2468:2468) (2633:2633:2633)) + (PORT d[4] (2187:2187:2187) (2357:2357:2357)) + (PORT d[5] (2172:2172:2172) (2317:2317:2317)) + (PORT d[6] (2138:2138:2138) (2285:2285:2285)) + (PORT d[7] (2050:2050:2050) (2279:2279:2279)) + (PORT d[8] (2347:2347:2347) (2486:2486:2486)) + (PORT d[9] (2169:2169:2169) (2346:2346:2346)) + (PORT d[10] (2278:2278:2278) (2456:2456:2456)) + (PORT d[11] (2295:2295:2295) (2429:2429:2429)) + (PORT d[12] (2349:2349:2349) (2504:2504:2504)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -1283,84 +1634,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1047:1047:1047) (1146:1146:1146)) - (PORT d[1] (1492:1492:1492) (1562:1562:1562)) - (PORT d[2] (954:954:954) (1036:1036:1036)) - (PORT d[3] (1018:1018:1018) (1075:1075:1075)) - (PORT d[4] (1018:1018:1018) (1075:1075:1075)) - (PORT d[5] (783:783:783) (838:838:838)) - (PORT d[6] (783:783:783) (838:838:838)) - (PORT d[7] (783:783:783) (838:838:838)) - (PORT d[8] (783:783:783) (838:838:838)) - (PORT d[9] (783:783:783) (838:838:838)) - (PORT d[10] (783:783:783) (838:838:838)) - (PORT d[11] (783:783:783) (838:838:838)) - (PORT d[12] (783:783:783) (838:838:838)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (1825:1825:1825) (1943:1943:1943)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT clk (1858:1858:1858) (1883:1883:1883)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1813:1813:1813) (1809:1809:1809)) + (PORT clk (1820:1820:1820) (1845:1845:1845)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1371,98 +1668,109 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1102:1102:1102)) - (PORT clk (1823:1823:1823) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1028:1028:1028) (1127:1127:1127)) - (PORT d[1] (1493:1493:1493) (1562:1562:1562)) - (PORT d[2] (979:979:979) (1058:1058:1058)) - (PORT d[3] (1250:1250:1250) (1312:1312:1312)) - (PORT d[4] (967:967:967) (1025:1025:1025)) - (PORT d[5] (1558:1558:1558) (1643:1643:1643)) - (PORT d[6] (1237:1237:1237) (1323:1323:1323)) - (PORT d[7] (1284:1284:1284) (1363:1363:1363)) - (PORT d[8] (1214:1214:1214) (1273:1273:1273)) - (PORT d[9] (1235:1235:1235) (1302:1302:1302)) - (PORT d[10] (1250:1250:1250) (1318:1318:1318)) - (PORT d[11] (1232:1232:1232) (1314:1314:1314)) - (PORT d[12] (1287:1287:1287) (1358:1358:1358)) - (PORT clk (1819:1819:1819) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1815:1815:1815)) - (PORT d[0] (903:903:903) (890:890:890)) + (PORT clk (1005:1005:1005) (1008:1008:1008)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT d[0] (1006:1006:1006) (1061:1061:1061)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT datac (1619:1619:1619) (1769:1769:1769)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2095:2095:2095) (2299:2299:2299)) + (PORT d[1] (1981:1981:1981) (2171:2171:2171)) + (PORT d[2] (2178:2178:2178) (2333:2333:2333)) + (PORT d[3] (2235:2235:2235) (2394:2394:2394)) + (PORT d[4] (2150:2150:2150) (2298:2298:2298)) + (PORT d[5] (2138:2138:2138) (2260:2260:2260)) + (PORT d[6] (2153:2153:2153) (2309:2309:2309)) + (PORT d[7] (2077:2077:2077) (2297:2297:2297)) + (PORT d[8] (2333:2333:2333) (2484:2484:2484)) + (PORT d[9] (2128:2128:2128) (2284:2284:2284)) + (PORT d[10] (1989:1989:1989) (2169:2169:2169)) + (PORT d[11] (2292:2292:2292) (2429:2429:2429)) + (PORT d[12] (2279:2279:2279) (2438:2438:2438)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -1471,84 +1779,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1030:1030:1030) (1132:1132:1132)) - (PORT d[1] (1194:1194:1194) (1270:1270:1270)) - (PORT d[2] (957:957:957) (1039:1039:1039)) - (PORT d[3] (1025:1025:1025) (1086:1086:1086)) - (PORT d[4] (1025:1025:1025) (1086:1086:1086)) - (PORT d[5] (813:813:813) (881:881:881)) - (PORT d[6] (813:813:813) (881:881:881)) - (PORT d[7] (813:813:813) (881:881:881)) - (PORT d[8] (813:813:813) (881:881:881)) - (PORT d[9] (813:813:813) (881:881:881)) - (PORT d[10] (813:813:813) (881:881:881)) - (PORT d[11] (813:813:813) (881:881:881)) - (PORT d[12] (813:813:813) (881:881:881)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1788:1788:1788) (1705:1705:1705)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1811:1811:1811) (1808:1808:1808)) + (PORT clk (1812:1812:1812) (1839:1839:1839)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1559,98 +1813,75 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1011:1011:1011) (1066:1066:1066)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1054:1054:1054) (1156:1156:1156)) - (PORT d[1] (960:960:960) (1039:1039:1039)) - (PORT d[2] (1276:1276:1276) (1350:1350:1350)) - (PORT d[3] (1249:1249:1249) (1279:1279:1279)) - (PORT d[4] (941:941:941) (1014:1014:1014)) - (PORT d[5] (1553:1553:1553) (1633:1633:1633)) - (PORT d[6] (1275:1275:1275) (1334:1334:1334)) - (PORT d[7] (1286:1286:1286) (1364:1364:1364)) - (PORT d[8] (1442:1442:1442) (1487:1487:1487)) - (PORT d[9] (1239:1239:1239) (1309:1309:1309)) - (PORT d[10] (1259:1259:1259) (1333:1333:1333)) - (PORT d[11] (1243:1243:1243) (1305:1305:1305)) - (PORT d[12] (1271:1271:1271) (1318:1318:1318)) - (PORT clk (1817:1817:1817) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1814:1814:1814)) - (PORT d[0] (908:908:908) (894:894:894)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (998:998:998) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (998:998:998) (1003:1003:1003)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (998:998:998) (1003:1003:1003)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (1352:1352:1352) (1400:1400:1400)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT dataa (925:925:925) (930:930:930)) + (PORT datab (2498:2498:2498) (2712:2712:2712)) + (PORT datac (903:903:903) (906:906:906)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2065:2065:2065) (2268:2268:2268)) + (PORT d[1] (1940:1940:1940) (2074:2074:2074)) + (PORT d[2] (2079:2079:2079) (2206:2206:2206)) + (PORT d[3] (2222:2222:2222) (2377:2377:2377)) + (PORT d[4] (2175:2175:2175) (2348:2348:2348)) + (PORT d[5] (1890:1890:1890) (2010:2010:2010)) + (PORT d[6] (1854:1854:1854) (1985:1985:1985)) + (PORT d[7] (2198:2198:2198) (2368:2368:2368)) + (PORT d[8] (1757:1757:1757) (1867:1867:1867)) + (PORT d[9] (2154:2154:2154) (2298:2298:2298)) + (PORT d[10] (1641:1641:1641) (1806:1806:1806)) + (PORT d[11] (2317:2317:2317) (2449:2449:2449)) + (PORT d[12] (1976:1976:1976) (2131:2131:2131)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) ) ) (TIMINGCHECK @@ -1659,84 +1890,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1071:1071:1071) (1146:1146:1146)) - (PORT d[1] (935:935:935) (1004:1004:1004)) - (PORT d[2] (1531:1531:1531) (1621:1621:1621)) - (PORT d[3] (1349:1349:1349) (1401:1401:1401)) - (PORT d[4] (1349:1349:1349) (1401:1401:1401)) - (PORT d[5] (773:773:773) (814:814:814)) - (PORT d[6] (773:773:773) (814:814:814)) - (PORT d[7] (773:773:773) (814:814:814)) - (PORT d[8] (773:773:773) (814:814:814)) - (PORT d[9] (773:773:773) (814:814:814)) - (PORT d[10] (773:773:773) (814:814:814)) - (PORT d[11] (773:773:773) (814:814:814)) - (PORT d[12] (773:773:773) (814:814:814)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT d[0] (1789:1789:1789) (1707:1707:1707)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) + (PORT clk (1808:1808:1808) (1835:1835:1835)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1747,297 +1924,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1357:1357:1357) (1405:1405:1405)) - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1049:1049:1049) (1122:1122:1122)) - (PORT d[1] (1503:1503:1503) (1591:1591:1591)) - (PORT d[2] (917:917:917) (979:979:979)) - (PORT d[3] (1464:1464:1464) (1521:1521:1521)) - (PORT d[4] (935:935:935) (996:996:996)) - (PORT d[5] (1058:1058:1058) (1128:1128:1128)) - (PORT d[6] (1250:1250:1250) (1319:1319:1319)) - (PORT d[7] (1047:1047:1047) (1105:1105:1105)) - (PORT d[8] (1486:1486:1486) (1542:1542:1542)) - (PORT d[9] (1254:1254:1254) (1312:1312:1312)) - (PORT d[10] (1242:1242:1242) (1297:1297:1297)) - (PORT d[11] (1250:1250:1250) (1319:1319:1319)) - (PORT d[12] (1251:1251:1251) (1299:1299:1299)) - (PORT clk (1820:1820:1820) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1817:1817:1817)) - (PORT d[0] (880:880:880) (882:882:882)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (994:994:994) (999:999:999)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT clk (994:994:994) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT clk (994:994:994) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1362:1362:1362) (1429:1429:1429)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (762:762:762) (824:824:824)) - (PORT d[1] (644:644:644) (706:706:706)) - (PORT d[2] (1543:1543:1543) (1614:1614:1614)) - (PORT d[3] (664:664:664) (693:693:693)) - (PORT d[4] (664:664:664) (693:693:693)) - (PORT d[5] (484:484:484) (522:522:522)) - (PORT d[6] (484:484:484) (522:522:522)) - (PORT d[7] (484:484:484) (522:522:522)) - (PORT d[8] (484:484:484) (522:522:522)) - (PORT d[9] (484:484:484) (522:522:522)) - (PORT d[10] (484:484:484) (522:522:522)) - (PORT d[11] (484:484:484) (522:522:522)) - (PORT d[12] (484:484:484) (522:522:522)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1367:1367:1367) (1434:1434:1434)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (735:735:735) (812:812:812)) - (PORT d[1] (1534:1534:1534) (1599:1599:1599)) - (PORT d[2] (1545:1545:1545) (1615:1615:1615)) - (PORT d[3] (659:659:659) (709:709:709)) - (PORT d[4] (664:664:664) (725:725:725)) - (PORT d[5] (722:722:722) (794:794:794)) - (PORT d[6] (766:766:766) (839:839:839)) - (PORT d[7] (749:749:749) (827:827:827)) - (PORT d[8] (1517:1517:1517) (1590:1590:1590)) - (PORT d[9] (761:761:761) (822:822:822)) - (PORT d[10] (979:979:979) (1037:1037:1037)) - (PORT d[11] (734:734:734) (803:803:803)) - (PORT d[12] (940:940:940) (991:991:991)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (PORT d[0] (628:628:628) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1580:1580:1580) (1693:1693:1693)) - (PORT d[1] (1272:1272:1272) (1354:1354:1354)) - (PORT d[2] (1245:1245:1245) (1308:1308:1308)) - (PORT d[3] (1263:1263:1263) (1339:1339:1339)) - (PORT d[4] (1283:1283:1283) (1370:1370:1370)) - (PORT d[5] (1569:1569:1569) (1701:1701:1701)) - (PORT d[6] (1243:1243:1243) (1329:1329:1329)) - (PORT d[7] (1231:1231:1231) (1310:1310:1310)) - (PORT d[8] (1267:1267:1267) (1363:1363:1363)) - (PORT d[9] (1273:1273:1273) (1361:1361:1361)) - (PORT d[10] (1275:1275:1275) (1366:1366:1366)) - (PORT d[11] (1259:1259:1259) (1344:1344:1344)) - (PORT d[12] (1532:1532:1532) (1614:1614:1614)) + (PORT d[0] (2019:2019:2019) (2227:2227:2227)) + (PORT d[1] (1947:1947:1947) (2115:2115:2115)) + (PORT d[2] (2170:2170:2170) (2334:2334:2334)) + (PORT d[3] (2218:2218:2218) (2359:2359:2359)) + (PORT d[4] (2158:2158:2158) (2329:2329:2329)) + (PORT d[5] (1630:1630:1630) (1742:1742:1742)) + (PORT d[6] (2095:2095:2095) (2239:2239:2239)) + (PORT d[7] (2150:2150:2150) (2292:2292:2292)) + (PORT d[8] (2149:2149:2149) (2291:2291:2291)) + (PORT d[9] (2220:2220:2220) (2350:2350:2350)) + (PORT d[10] (1655:1655:1655) (1834:1834:1834)) + (PORT d[11] (2184:2184:2184) (2353:2353:2353)) + (PORT d[12] (2144:2144:2144) (2362:2362:2362)) (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) @@ -2047,17 +1987,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1172:1172:1172) (1188:1188:1188)) + (PORT d[0] (1680:1680:1680) (1746:1746:1746)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) @@ -2067,7 +2007,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1837:1837:1837)) @@ -2081,7 +2021,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (1000:1000:1000)) @@ -2090,7 +2030,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2099,7 +2039,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2109,7 +2049,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2117,25 +2057,39 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (993:993:993)) + (PORT datac (927:927:927) (988:988:988)) + (PORT datad (2737:2737:2737) (2929:2929:2929)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1320:1320:1320) (1440:1440:1440)) - (PORT d[1] (1259:1259:1259) (1353:1353:1353)) - (PORT d[2] (1264:1264:1264) (1323:1323:1323)) - (PORT d[3] (1324:1324:1324) (1419:1419:1419)) - (PORT d[4] (1316:1316:1316) (1418:1418:1418)) - (PORT d[5] (1564:1564:1564) (1691:1691:1691)) - (PORT d[6] (1229:1229:1229) (1326:1326:1326)) - (PORT d[7] (1239:1239:1239) (1332:1332:1332)) - (PORT d[8] (1280:1280:1280) (1393:1393:1393)) - (PORT d[9] (1254:1254:1254) (1351:1351:1351)) - (PORT d[10] (1258:1258:1258) (1357:1357:1357)) - (PORT d[11] (1267:1267:1267) (1367:1367:1367)) - (PORT d[12] (1266:1266:1266) (1351:1351:1351)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (2114:2114:2114) (2311:2311:2311)) + (PORT d[1] (1686:1686:1686) (1848:1848:1848)) + (PORT d[2] (2168:2168:2168) (2314:2314:2314)) + (PORT d[3] (2251:2251:2251) (2410:2410:2410)) + (PORT d[4] (2142:2142:2142) (2284:2284:2284)) + (PORT d[5] (1925:1925:1925) (2063:2063:2063)) + (PORT d[6] (2081:2081:2081) (2241:2241:2241)) + (PORT d[7] (2063:2063:2063) (2296:2296:2296)) + (PORT d[8] (2131:2131:2131) (2296:2296:2296)) + (PORT d[9] (2131:2131:2131) (2289:2289:2289)) + (PORT d[10] (1732:1732:1732) (1913:1913:1913)) + (PORT d[11] (2308:2308:2308) (2449:2449:2449)) + (PORT d[12] (2190:2190:2190) (2407:2407:2407)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -2144,30 +2098,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1872:1872:1872)) - (PORT d[0] (1215:1215:1215) (1202:1202:1202)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1818:1818:1818) (1733:1733:1733)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1806:1806:1806) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2178,122 +2132,171 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (991:991:991) (997:997:997)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2045:2045:2045) (2260:2260:2260)) + (PORT d[1] (2023:2023:2023) (2209:2209:2209)) + (PORT d[2] (1962:1962:1962) (2121:2121:2121)) + (PORT d[3] (2465:2465:2465) (2628:2628:2628)) + (PORT d[4] (2184:2184:2184) (2381:2381:2381)) + (PORT d[5] (1958:1958:1958) (2089:2089:2089)) + (PORT d[6] (2196:2196:2196) (2345:2345:2345)) + (PORT d[7] (2053:2053:2053) (2286:2286:2286)) + (PORT d[8] (2335:2335:2335) (2452:2452:2452)) + (PORT d[9] (2180:2180:2180) (2364:2364:2364)) + (PORT d[10] (2313:2313:2313) (2485:2485:2485)) + (PORT d[11] (2298:2298:2298) (2430:2430:2430)) + (PORT d[12] (2225:2225:2225) (2392:2392:2392)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (1894:1894:1894) (2005:2005:2005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (643:643:643) (706:706:706)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (628:628:628) (637:637:637)) - (PORT datac (922:922:922) (922:922:922)) - (PORT datad (973:973:973) (1040:1040:1040)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (964:964:964) (1029:1029:1029)) + (PORT datac (2401:2401:2401) (2590:2590:2590)) + (PORT datad (348:348:348) (364:364:364)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1588:1588:1588) (1696:1696:1696)) - (PORT d[1] (980:980:980) (1067:1067:1067)) - (PORT d[2] (995:995:995) (1068:1068:1068)) - (PORT d[3] (1044:1044:1044) (1123:1123:1123)) - (PORT d[4] (975:975:975) (1061:1061:1061)) - (PORT d[5] (1570:1570:1570) (1702:1702:1702)) - (PORT d[6] (974:974:974) (1057:1057:1057)) - (PORT d[7] (950:950:950) (1029:1029:1029)) - (PORT d[8] (1007:1007:1007) (1107:1107:1107)) - (PORT d[9] (1511:1511:1511) (1583:1583:1583)) - (PORT d[10] (1476:1476:1476) (1552:1552:1552)) - (PORT d[11] (949:949:949) (1029:1029:1029)) - (PORT d[12] (993:993:993) (1056:1056:1056)) + (PORT d[0] (1733:1733:1733) (1922:1922:1922)) + (PORT d[1] (1970:1970:1970) (2131:2131:2131)) + (PORT d[2] (2159:2159:2159) (2306:2306:2306)) + (PORT d[3] (2219:2219:2219) (2360:2360:2360)) + (PORT d[4] (2084:2084:2084) (2195:2195:2195)) + (PORT d[5] (1896:1896:1896) (1993:1993:1993)) + (PORT d[6] (1827:1827:1827) (1951:1951:1951)) + (PORT d[7] (1862:1862:1862) (1984:1984:1984)) + (PORT d[8] (1868:1868:1868) (1994:1994:1994)) + (PORT d[9] (1908:1908:1908) (2030:2030:2030)) + (PORT d[10] (1767:1767:1767) (1972:1972:1972)) + (PORT d[11] (1868:1868:1868) (1996:1996:1996)) + (PORT d[12] (2048:2048:2048) (2130:2130:2130)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2303,17 +2306,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (897:897:897) (921:921:921)) + (PORT d[0] (1685:1685:1685) (1767:1767:1767)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1849:1849:1849) (1876:1876:1876)) @@ -2323,7 +2326,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -2337,7 +2340,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2346,7 +2349,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2355,7 +2358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2365,7 +2368,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2373,25 +2376,2129 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1982:1982:1982) (2177:2177:2177)) + (PORT d[1] (1928:1928:1928) (2063:2063:2063)) + (PORT d[2] (2166:2166:2166) (2327:2327:2327)) + (PORT d[3] (2210:2210:2210) (2351:2351:2351)) + (PORT d[4] (2129:2129:2129) (2252:2252:2252)) + (PORT d[5] (1872:1872:1872) (1985:1985:1985)) + (PORT d[6] (1796:1796:1796) (1941:1941:1941)) + (PORT d[7] (1902:1902:1902) (2083:2083:2083)) + (PORT d[8] (1861:1861:1861) (2011:2011:2011)) + (PORT d[9] (2186:2186:2186) (2333:2333:2333)) + (PORT d[10] (2118:2118:2118) (2300:2300:2300)) + (PORT d[11] (1858:1858:1858) (2006:2006:2006)) + (PORT d[12] (2105:2105:2105) (2343:2343:2343)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1792:1792:1792) (1727:1727:1727)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (773:773:773)) + (PORT datac (1897:1897:1897) (2091:2091:2091)) + (PORT datad (348:348:348) (363:363:363)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2186:2186:2186) (2285:2285:2285)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2065:2065:2065) (2268:2268:2268)) + (PORT d[1] (2187:2187:2187) (2316:2316:2316)) + (PORT d[2] (2211:2211:2211) (2384:2384:2384)) + (PORT d[3] (2281:2281:2281) (2440:2440:2440)) + (PORT d[4] (2169:2169:2169) (2344:2344:2344)) + (PORT d[5] (2210:2210:2210) (2364:2364:2364)) + (PORT d[6] (2149:2149:2149) (2283:2283:2283)) + (PORT d[7] (2077:2077:2077) (2302:2302:2302)) + (PORT d[8] (2367:2367:2367) (2522:2522:2522)) + (PORT d[9] (2150:2150:2150) (2314:2314:2314)) + (PORT d[10] (2027:2027:2027) (2231:2231:2231)) + (PORT d[11] (2348:2348:2348) (2486:2486:2486)) + (PORT d[12] (2333:2333:2333) (2496:2496:2496)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (2022:2022:2022) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2191:2191:2191) (2290:2290:2290)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (2243:2243:2243)) + (PORT d[1] (2233:2233:2233) (2365:2365:2365)) + (PORT d[2] (2159:2159:2159) (2330:2330:2330)) + (PORT d[3] (2282:2282:2282) (2440:2440:2440)) + (PORT d[4] (2187:2187:2187) (2356:2356:2356)) + (PORT d[5] (2211:2211:2211) (2364:2364:2364)) + (PORT d[6] (2150:2150:2150) (2283:2283:2283)) + (PORT d[7] (2078:2078:2078) (2302:2302:2302)) + (PORT d[8] (2368:2368:2368) (2522:2522:2522)) + (PORT d[9] (2151:2151:2151) (2314:2314:2314)) + (PORT d[10] (2028:2028:2028) (2231:2231:2231)) + (PORT d[11] (2349:2349:2349) (2486:2486:2486)) + (PORT d[12] (2334:2334:2334) (2496:2496:2496)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2022:2022:2022) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3174:3174:3174) (3285:3285:3285)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1967:1967:1967) (2086:2086:2086)) + (PORT d[1] (2293:2293:2293) (2486:2486:2486)) + (PORT d[2] (1954:1954:1954) (2112:2112:2112)) + (PORT d[3] (1742:1742:1742) (1900:1900:1900)) + (PORT d[4] (2207:2207:2207) (2364:2364:2364)) + (PORT d[5] (1570:1570:1570) (1733:1733:1733)) + (PORT d[6] (1787:1787:1787) (1945:1945:1945)) + (PORT d[7] (1752:1752:1752) (1914:1914:1914)) + (PORT d[8] (1950:1950:1950) (2065:2065:2065)) + (PORT d[9] (1769:1769:1769) (1880:1880:1880)) + (PORT d[10] (1682:1682:1682) (1838:1838:1838)) + (PORT d[11] (2015:2015:2015) (2121:2121:2121)) + (PORT d[12] (2067:2067:2067) (2250:2250:2250)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1850:1850:1850)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3179:3179:3179) (3290:3290:3290)) + (PORT clk (1866:1866:1866) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1976:1976:1976) (2082:2082:2082)) + (PORT d[1] (2294:2294:2294) (2486:2486:2486)) + (PORT d[2] (1911:1911:1911) (2064:2064:2064)) + (PORT d[3] (1743:1743:1743) (1900:1900:1900)) + (PORT d[4] (2244:2244:2244) (2421:2421:2421)) + (PORT d[5] (1571:1571:1571) (1733:1733:1733)) + (PORT d[6] (1788:1788:1788) (1945:1945:1945)) + (PORT d[7] (1753:1753:1753) (1914:1914:1914)) + (PORT d[8] (1951:1951:1951) (2065:2065:2065)) + (PORT d[9] (1770:1770:1770) (1880:1880:1880)) + (PORT d[10] (1683:1683:1683) (1838:1838:1838)) + (PORT d[11] (2016:2016:2016) (2121:2121:2121)) + (PORT d[12] (2068:2068:2068) (2250:2250:2250)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1892:1892:1892)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1851:1851:1851)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2697:2697:2697) (2912:2912:2912)) + (PORT datac (642:642:642) (662:662:662)) + (PORT datad (1091:1091:1091) (1109:1109:1109)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3157:3157:3157) (3259:3259:3259)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1684:1684:1684) (1814:1814:1814)) + (PORT d[1] (1912:1912:1912) (2072:2072:2072)) + (PORT d[2] (1954:1954:1954) (2112:2112:2112)) + (PORT d[3] (1766:1766:1766) (1915:1915:1915)) + (PORT d[4] (1998:1998:1998) (2150:2150:2150)) + (PORT d[5] (1881:1881:1881) (2064:2064:2064)) + (PORT d[6] (1954:1954:1954) (2093:2093:2093)) + (PORT d[7] (2034:2034:2034) (2198:2198:2198)) + (PORT d[8] (1978:1978:1978) (2097:2097:2097)) + (PORT d[9] (2037:2037:2037) (2220:2220:2220)) + (PORT d[10] (1742:1742:1742) (1908:1908:1908)) + (PORT d[11] (1966:1966:1966) (2088:2088:2088)) + (PORT d[12] (2052:2052:2052) (2237:2237:2237)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (1617:1617:1617) (1549:1549:1549)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1852:1852:1852)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3162:3162:3162) (3264:3264:3264)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1694:1694:1694) (1812:1812:1812)) + (PORT d[1] (1917:1917:1917) (2089:2089:2089)) + (PORT d[2] (1911:1911:1911) (2064:2064:2064)) + (PORT d[3] (1767:1767:1767) (1915:1915:1915)) + (PORT d[4] (1977:1977:1977) (2126:2126:2126)) + (PORT d[5] (1882:1882:1882) (2064:2064:2064)) + (PORT d[6] (1955:1955:1955) (2093:2093:2093)) + (PORT d[7] (2035:2035:2035) (2198:2198:2198)) + (PORT d[8] (1979:1979:1979) (2097:2097:2097)) + (PORT d[9] (2038:2038:2038) (2220:2220:2220)) + (PORT d[10] (1743:1743:1743) (1908:1908:1908)) + (PORT d[11] (1967:1967:1967) (2088:2088:2088)) + (PORT d[12] (2053:2053:2053) (2237:2237:2237)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (1617:1617:1617) (1549:1549:1549)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1853:1853:1853)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3172:3172:3172) (3285:3285:3285)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1706:1706:1706) (1842:1842:1842)) + (PORT d[1] (1974:1974:1974) (2127:2127:2127)) + (PORT d[2] (1651:1651:1651) (1764:1764:1764)) + (PORT d[3] (1724:1724:1724) (1872:1872:1872)) + (PORT d[4] (1952:1952:1952) (2127:2127:2127)) + (PORT d[5] (1542:1542:1542) (1700:1700:1700)) + (PORT d[6] (2052:2052:2052) (2207:2207:2207)) + (PORT d[7] (1747:1747:1747) (1911:1911:1911)) + (PORT d[8] (1938:1938:1938) (2069:2069:2069)) + (PORT d[9] (2028:2028:2028) (2200:2200:2200)) + (PORT d[10] (2188:2188:2188) (2417:2417:2417)) + (PORT d[11] (2008:2008:2008) (2111:2111:2111)) + (PORT d[12] (2045:2045:2045) (2242:2242:2242)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3177:3177:3177) (3290:3290:3290)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1685:1685:1685) (1817:1817:1817)) + (PORT d[1] (1975:1975:1975) (2132:2132:2132)) + (PORT d[2] (1665:1665:1665) (1796:1796:1796)) + (PORT d[3] (1725:1725:1725) (1872:1872:1872)) + (PORT d[4] (1960:1960:1960) (2115:2115:2115)) + (PORT d[5] (1543:1543:1543) (1700:1700:1700)) + (PORT d[6] (2053:2053:2053) (2207:2207:2207)) + (PORT d[7] (1748:1748:1748) (1911:1911:1911)) + (PORT d[8] (1939:1939:1939) (2069:2069:2069)) + (PORT d[9] (2029:2029:2029) (2200:2200:2200)) + (PORT d[10] (2189:2189:2189) (2417:2417:2417)) + (PORT d[11] (2009:2009:2009) (2111:2111:2111)) + (PORT d[12] (2046:2046:2046) (2242:2242:2242)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (271:271:271) (357:357:357)) + (PORT datac (681:681:681) (694:694:694)) + (PORT datad (348:348:348) (364:364:364)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (929:929:929) (968:968:968)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1594:1594:1594) (1715:1715:1715)) + (PORT d[1] (1702:1702:1702) (1831:1831:1831)) + (PORT d[2] (1596:1596:1596) (1703:1703:1703)) + (PORT d[3] (1706:1706:1706) (1830:1830:1830)) + (PORT d[4] (1670:1670:1670) (1826:1826:1826)) + (PORT d[5] (1479:1479:1479) (1627:1627:1627)) + (PORT d[6] (1631:1631:1631) (1770:1770:1770)) + (PORT d[7] (1937:1937:1937) (2048:2048:2048)) + (PORT d[8] (1681:1681:1681) (1829:1829:1829)) + (PORT d[9] (1735:1735:1735) (1889:1889:1889)) + (PORT d[10] (1456:1456:1456) (1610:1610:1610)) + (PORT d[11] (1888:1888:1888) (2010:2010:2010)) + (PORT d[12] (1744:1744:1744) (1905:1905:1905)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1312:1312:1312) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (934:934:934) (973:973:973)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1617:1617:1617) (1734:1734:1734)) + (PORT d[1] (1689:1689:1689) (1799:1799:1799)) + (PORT d[2] (1610:1610:1610) (1731:1731:1731)) + (PORT d[3] (1707:1707:1707) (1830:1830:1830)) + (PORT d[4] (1671:1671:1671) (1832:1832:1832)) + (PORT d[5] (1480:1480:1480) (1627:1627:1627)) + (PORT d[6] (1632:1632:1632) (1770:1770:1770)) + (PORT d[7] (1938:1938:1938) (2048:2048:2048)) + (PORT d[8] (1682:1682:1682) (1829:1829:1829)) + (PORT d[9] (1736:1736:1736) (1889:1889:1889)) + (PORT d[10] (1457:1457:1457) (1610:1610:1610)) + (PORT d[11] (1889:1889:1889) (2010:2010:2010)) + (PORT d[12] (1745:1745:1745) (1905:1905:1905)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1312:1312:1312) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (901:901:901) (948:948:948)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1970:1970:1970) (2104:2104:2104)) + (PORT d[1] (1716:1716:1716) (1847:1847:1847)) + (PORT d[2] (1895:1895:1895) (2002:2002:2002)) + (PORT d[3] (1692:1692:1692) (1826:1826:1826)) + (PORT d[4] (1680:1680:1680) (1846:1846:1846)) + (PORT d[5] (1484:1484:1484) (1636:1636:1636)) + (PORT d[6] (1880:1880:1880) (2002:2002:2002)) + (PORT d[7] (1679:1679:1679) (1844:1844:1844)) + (PORT d[8] (1716:1716:1716) (1877:1877:1877)) + (PORT d[9] (1718:1718:1718) (1874:1874:1874)) + (PORT d[10] (1753:1753:1753) (1899:1899:1899)) + (PORT d[11] (1880:1880:1880) (1999:1999:1999)) + (PORT d[12] (1753:1753:1753) (1919:1919:1919)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1244:1244:1244) (1290:1290:1290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (906:906:906) (953:953:953)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1971:1971:1971) (2104:2104:2104)) + (PORT d[1] (1695:1695:1695) (1822:1822:1822)) + (PORT d[2] (1615:1615:1615) (1740:1740:1740)) + (PORT d[3] (1693:1693:1693) (1826:1826:1826)) + (PORT d[4] (1667:1667:1667) (1814:1814:1814)) + (PORT d[5] (1485:1485:1485) (1636:1636:1636)) + (PORT d[6] (1881:1881:1881) (2002:2002:2002)) + (PORT d[7] (1680:1680:1680) (1844:1844:1844)) + (PORT d[8] (1717:1717:1717) (1877:1877:1877)) + (PORT d[9] (1719:1719:1719) (1874:1874:1874)) + (PORT d[10] (1754:1754:1754) (1899:1899:1899)) + (PORT d[11] (1881:1881:1881) (1999:1999:1999)) + (PORT d[12] (1754:1754:1754) (1919:1919:1919)) + (PORT clk (1858:1858:1858) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (1244:1244:1244) (1290:1290:1290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (992:992:992) (1034:1034:1034)) + (PORT datac (735:735:735) (831:831:831)) + (PORT datad (969:969:969) (1010:1010:1010)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3451:3451:3451) (3568:3568:3568)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1695:1695:1695) (1821:1821:1821)) + (PORT d[1] (1961:1961:1961) (2101:2101:2101)) + (PORT d[2] (1635:1635:1635) (1763:1763:1763)) + (PORT d[3] (1691:1691:1691) (1829:1829:1829)) + (PORT d[4] (1958:1958:1958) (2143:2143:2143)) + (PORT d[5] (1514:1514:1514) (1654:1654:1654)) + (PORT d[6] (2088:2088:2088) (2262:2262:2262)) + (PORT d[7] (1969:1969:1969) (2129:2129:2129)) + (PORT d[8] (1996:1996:1996) (2177:2177:2177)) + (PORT d[9] (2062:2062:2062) (2258:2258:2258)) + (PORT d[10] (1974:1974:1974) (2129:2129:2129)) + (PORT d[11] (1732:1732:1732) (1851:1851:1851)) + (PORT d[12] (1780:1780:1780) (1964:1964:1964)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (1309:1309:1309) (1248:1248:1248)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3456:3456:3456) (3573:3573:3573)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1705:1705:1705) (1819:1819:1819)) + (PORT d[1] (1940:1940:1940) (2077:2077:2077)) + (PORT d[2] (1677:1677:1677) (1808:1808:1808)) + (PORT d[3] (1692:1692:1692) (1829:1829:1829)) + (PORT d[4] (1945:1945:1945) (2111:2111:2111)) + (PORT d[5] (1515:1515:1515) (1654:1654:1654)) + (PORT d[6] (2089:2089:2089) (2262:2262:2262)) + (PORT d[7] (1970:1970:1970) (2129:2129:2129)) + (PORT d[8] (1997:1997:1997) (2177:2177:2177)) + (PORT d[9] (2063:2063:2063) (2258:2258:2258)) + (PORT d[10] (1975:1975:1975) (2129:2129:2129)) + (PORT d[11] (1733:1733:1733) (1851:1851:1851)) + (PORT d[12] (1781:1781:1781) (1964:1964:1964)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1309:1309:1309) (1248:1248:1248)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3433:3433:3433) (3533:3533:3533)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1935:1935:1935) (2059:2059:2059)) + (PORT d[1] (1879:1879:1879) (2055:2055:2055)) + (PORT d[2] (1673:1673:1673) (1806:1806:1806)) + (PORT d[3] (1719:1719:1719) (1862:1862:1862)) + (PORT d[4] (2011:2011:2011) (2162:2162:2162)) + (PORT d[5] (1532:1532:1532) (1674:1674:1674)) + (PORT d[6] (2091:2091:2091) (2267:2267:2267)) + (PORT d[7] (1723:1723:1723) (1889:1889:1889)) + (PORT d[8] (1623:1623:1623) (1738:1738:1738)) + (PORT d[9] (2043:2043:2043) (2237:2237:2237)) + (PORT d[10] (1745:1745:1745) (1889:1889:1889)) + (PORT d[11] (1993:1993:1993) (2111:2111:2111)) + (PORT d[12] (2047:2047:2047) (2224:2224:2224)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1291:1291:1291) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3438:3438:3438) (3538:3538:3538)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1990:1990:1990) (2109:2109:2109)) + (PORT d[1] (1965:1965:1965) (2111:2111:2111)) + (PORT d[2] (1674:1674:1674) (1806:1806:1806)) + (PORT d[3] (1720:1720:1720) (1862:1862:1862)) + (PORT d[4] (2012:2012:2012) (2162:2162:2162)) + (PORT d[5] (1533:1533:1533) (1674:1674:1674)) + (PORT d[6] (2092:2092:2092) (2267:2267:2267)) + (PORT d[7] (1724:1724:1724) (1889:1889:1889)) + (PORT d[8] (1624:1624:1624) (1738:1738:1738)) + (PORT d[9] (2044:2044:2044) (2237:2237:2237)) + (PORT d[10] (1746:1746:1746) (1889:1889:1889)) + (PORT d[11] (1994:1994:1994) (2111:2111:2111)) + (PORT d[12] (2048:2048:2048) (2224:2224:2224)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1291:1291:1291) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1841:1841:1841)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (767:767:767) (864:864:864)) + (PORT datac (674:674:674) (687:687:687)) + (PORT datad (349:349:349) (365:365:365)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1759:1759:1759) (1954:1954:1954)) + (PORT d[1] (1921:1921:1921) (2055:2055:2055)) + (PORT d[2] (2115:2115:2115) (2262:2262:2262)) + (PORT d[3] (2204:2204:2204) (2339:2339:2339)) + (PORT d[4] (2144:2144:2144) (2260:2260:2260)) + (PORT d[5] (1918:1918:1918) (2036:2036:2036)) + (PORT d[6] (1770:1770:1770) (1893:1893:1893)) + (PORT d[7] (1884:1884:1884) (2012:2012:2012)) + (PORT d[8] (1882:1882:1882) (2030:2030:2030)) + (PORT d[9] (1891:1891:1891) (2020:2020:2020)) + (PORT d[10] (1752:1752:1752) (1953:1953:1953)) + (PORT d[11] (1851:1851:1851) (1994:1994:1994)) + (PORT d[12] (2201:2201:2201) (2421:2421:2421)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1773:1773:1773) (1689:1689:1689)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2105:2105:2105) (2311:2311:2311)) + (PORT d[1] (1947:1947:1947) (2084:2084:2084)) + (PORT d[2] (2166:2166:2166) (2324:2324:2324)) + (PORT d[3] (2248:2248:2248) (2396:2396:2396)) + (PORT d[4] (2176:2176:2176) (2348:2348:2348)) + (PORT d[5] (1952:1952:1952) (2095:2095:2095)) + (PORT d[6] (2117:2117:2117) (2251:2251:2251)) + (PORT d[7] (2058:2058:2058) (2288:2288:2288)) + (PORT d[8] (2060:2060:2060) (2177:2177:2177)) + (PORT d[9] (2163:2163:2163) (2322:2322:2322)) + (PORT d[10] (1982:1982:1982) (2160:2160:2160)) + (PORT d[11] (2269:2269:2269) (2403:2403:2403)) + (PORT d[12] (2020:2020:2020) (2182:2182:2182)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (1701:1701:1701) (1783:1783:1783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1214:1214:1214)) + (PORT datac (2506:2506:2506) (2721:2721:2721)) + (PORT datad (346:346:346) (361:361:361)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2054:2054:2054) (2271:2271:2271)) + (PORT d[1] (1989:1989:1989) (2131:2131:2131)) + (PORT d[2] (2133:2133:2133) (2280:2280:2280)) + (PORT d[3] (2185:2185:2185) (2313:2313:2313)) + (PORT d[4] (2173:2173:2173) (2323:2323:2323)) + (PORT d[5] (1924:1924:1924) (2063:2063:2063)) + (PORT d[6] (2151:2151:2151) (2279:2279:2279)) + (PORT d[7] (2084:2084:2084) (2320:2320:2320)) + (PORT d[8] (1814:1814:1814) (1935:1935:1935)) + (PORT d[9] (2164:2164:2164) (2343:2343:2343)) + (PORT d[10] (1715:1715:1715) (1899:1899:1899)) + (PORT d[11] (2299:2299:2299) (2432:2432:2432)) + (PORT d[12] (2017:2017:2017) (2181:2181:2181)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1694:1694:1694) (1761:1761:1761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1251:1251:1251) (1346:1346:1346)) - (PORT d[1] (1263:1263:1263) (1359:1359:1359)) - (PORT d[2] (1230:1230:1230) (1312:1312:1312)) - (PORT d[3] (1305:1305:1305) (1378:1378:1378)) - (PORT d[4] (1268:1268:1268) (1374:1374:1374)) - (PORT d[5] (1558:1558:1558) (1661:1661:1661)) - (PORT d[6] (1255:1255:1255) (1359:1359:1359)) - (PORT d[7] (1243:1243:1243) (1338:1338:1338)) - (PORT d[8] (1284:1284:1284) (1400:1400:1400)) - (PORT d[9] (1257:1257:1257) (1358:1358:1358)) - (PORT d[10] (1261:1261:1261) (1362:1362:1362)) - (PORT d[11] (1244:1244:1244) (1341:1341:1341)) - (PORT d[12] (1513:1513:1513) (1597:1597:1597)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (2042:2042:2042) (2251:2251:2251)) + (PORT d[1] (1726:1726:1726) (1880:1880:1880)) + (PORT d[2] (2193:2193:2193) (2359:2359:2359)) + (PORT d[3] (2213:2213:2213) (2374:2374:2374)) + (PORT d[4] (2158:2158:2158) (2320:2320:2320)) + (PORT d[5] (1641:1641:1641) (1756:1756:1756)) + (PORT d[6] (2078:2078:2078) (2220:2220:2220)) + (PORT d[7] (1942:1942:1942) (2112:2112:2112)) + (PORT d[8] (1789:1789:1789) (1911:1911:1911)) + (PORT d[9] (2199:2199:2199) (2326:2326:2326)) + (PORT d[10] (1702:1702:1702) (1882:1882:1882)) + (PORT d[11] (2172:2172:2172) (2318:2318:2318)) + (PORT d[12] (2153:2153:2153) (2388:2388:2388)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -2403,8 +4510,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1844:1844:1844) (1871:1871:1871)) - (PORT d[0] (1181:1181:1181) (1146:1146:1146)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (1766:1766:1766) (1700:1700:1700)) ) ) ) @@ -2413,7 +4520,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2423,7 +4530,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) + (PORT clk (1809:1809:1809) (1836:1836:1836)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2437,7 +4544,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) + (PORT clk (994:994:994) (999:999:999)) ) ) ) @@ -2446,7 +4553,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) @@ -2455,7 +4562,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2465,22 +4572,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (648:648:648)) - (PORT datab (722:722:722) (791:791:791)) - (PORT datac (902:902:902) (941:941:941)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (693:693:693) (733:733:733)) + (PORT datac (925:925:925) (989:989:989)) + (PORT datad (2699:2699:2699) (2890:2890:2890)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -2489,19 +4596,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1869:1869:1869) (2011:2011:2011)) - (PORT d[1] (1219:1219:1219) (1293:1293:1293)) - (PORT d[2] (1262:1262:1262) (1328:1328:1328)) - (PORT d[3] (1315:1315:1315) (1385:1385:1385)) - (PORT d[4] (1268:1268:1268) (1345:1345:1345)) - (PORT d[5] (1878:1878:1878) (2013:2013:2013)) - (PORT d[6] (1241:1241:1241) (1311:1311:1311)) - (PORT d[7] (1353:1353:1353) (1455:1455:1455)) - (PORT d[8] (1215:1215:1215) (1306:1306:1306)) - (PORT d[9] (1254:1254:1254) (1335:1335:1335)) - (PORT d[10] (1270:1270:1270) (1354:1354:1354)) - (PORT d[11] (1212:1212:1212) (1279:1279:1279)) - (PORT d[12] (1262:1262:1262) (1346:1346:1346)) + (PORT d[0] (1958:1958:1958) (2119:2119:2119)) + (PORT d[1] (1627:1627:1627) (1734:1734:1734)) + (PORT d[2] (1870:1870:1870) (2003:2003:2003)) + (PORT d[3] (1889:1889:1889) (1979:1979:1979)) + (PORT d[4] (1810:1810:1810) (1926:1926:1926)) + (PORT d[5] (1669:1669:1669) (1774:1774:1774)) + (PORT d[6] (1873:1873:1873) (2001:2001:2001)) + (PORT d[7] (1570:1570:1570) (1685:1685:1685)) + (PORT d[8] (1579:1579:1579) (1703:1703:1703)) + (PORT d[9] (1542:1542:1542) (1637:1637:1637)) + (PORT d[10] (1774:1774:1774) (1984:1984:1984)) + (PORT d[11] (1616:1616:1616) (1719:1719:1719)) + (PORT d[12] (1777:1777:1777) (1896:1896:1896)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2515,7 +4622,7 @@ (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1161:1161:1161) (1144:1144:1144)) + (PORT d[0] (1741:1741:1741) (1677:1677:1677)) ) ) ) @@ -2586,20 +4693,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (767:767:767) (837:837:837)) - (PORT d[1] (644:644:644) (707:707:707)) - (PORT d[2] (1522:1522:1522) (1591:1591:1591)) - (PORT d[3] (1232:1232:1232) (1276:1276:1276)) - (PORT d[4] (948:948:948) (1009:1009:1009)) - (PORT d[5] (1053:1053:1053) (1132:1132:1132)) - (PORT d[6] (1198:1198:1198) (1268:1268:1268)) - (PORT d[7] (1251:1251:1251) (1321:1321:1321)) - (PORT d[8] (1492:1492:1492) (1563:1563:1563)) - (PORT d[9] (1256:1256:1256) (1307:1307:1307)) - (PORT d[10] (1239:1239:1239) (1292:1292:1292)) - (PORT d[11] (1213:1213:1213) (1275:1275:1275)) - (PORT d[12] (1242:1242:1242) (1308:1308:1308)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1696:1696:1696) (1855:1855:1855)) + (PORT d[1] (1624:1624:1624) (1716:1716:1716)) + (PORT d[2] (1829:1829:1829) (1941:1941:1941)) + (PORT d[3] (1799:1799:1799) (1866:1866:1866)) + (PORT d[4] (1795:1795:1795) (1904:1904:1904)) + (PORT d[5] (1607:1607:1607) (1721:1721:1721)) + (PORT d[6] (1527:1527:1527) (1632:1632:1632)) + (PORT d[7] (1539:1539:1539) (1667:1667:1667)) + (PORT d[8] (1561:1561:1561) (1665:1665:1665)) + (PORT d[9] (1507:1507:1507) (1599:1599:1599)) + (PORT d[10] (1787:1787:1787) (2014:2014:2014)) + (PORT d[11] (1560:1560:1560) (1657:1657:1657)) + (PORT d[12] (1765:1765:1765) (1857:1857:1857)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) ) ) (TIMINGCHECK @@ -2611,8 +4718,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (890:890:890) (887:887:887)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1628:1628:1628) (1667:1667:1667)) ) ) ) @@ -2621,7 +4728,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2631,7 +4738,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) + (PORT clk (1809:1809:1809) (1835:1835:1835)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2645,7 +4752,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) + (PORT clk (994:994:994) (998:998:998)) ) ) ) @@ -2654,7 +4761,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) ) ) ) @@ -2663,7 +4770,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2673,141 +4780,44 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) (DELAY (ABSOLUTE - (PORT datab (938:938:938) (1009:1009:1009)) - (PORT datac (597:597:597) (600:600:600)) - (PORT datad (1037:1037:1037) (1036:1036:1036)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (726:726:726) (771:771:771)) + (PORT datac (1862:1862:1862) (2046:2046:2046)) + (PORT datad (959:959:959) (1001:1001:1001)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1536:1536:1536) (1641:1641:1641)) - (PORT d[1] (1285:1285:1285) (1385:1385:1385)) - (PORT d[2] (1257:1257:1257) (1341:1341:1341)) - (PORT d[3] (1362:1362:1362) (1438:1438:1438)) - (PORT d[4] (1567:1567:1567) (1669:1669:1669)) - (PORT d[5] (1299:1299:1299) (1410:1410:1410)) - (PORT d[6] (1283:1283:1283) (1391:1391:1391)) - (PORT d[7] (1243:1243:1243) (1339:1339:1339)) - (PORT d[8] (1257:1257:1257) (1369:1369:1369)) - (PORT d[9] (1285:1285:1285) (1390:1390:1390)) - (PORT d[10] (1289:1289:1289) (1395:1395:1395)) - (PORT d[11] (1244:1244:1244) (1342:1342:1342)) - (PORT d[12] (1238:1238:1238) (1316:1316:1316)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1869:1869:1869)) - (PORT d[0] (1140:1140:1140) (1166:1166:1166)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1019:1019:1019) (1118:1118:1118)) - (PORT d[1] (928:928:928) (1013:1013:1013)) - (PORT d[2] (926:926:926) (1007:1007:1007)) - (PORT d[3] (1249:1249:1249) (1279:1279:1279)) - (PORT d[4] (1509:1509:1509) (1612:1612:1612)) - (PORT d[5] (1306:1306:1306) (1397:1397:1397)) - (PORT d[6] (1247:1247:1247) (1313:1313:1313)) - (PORT d[7] (1321:1321:1321) (1414:1414:1414)) - (PORT d[8] (1471:1471:1471) (1521:1521:1521)) - (PORT d[9] (1265:1265:1265) (1341:1341:1341)) - (PORT d[10] (1259:1259:1259) (1333:1333:1333)) - (PORT d[11] (1270:1270:1270) (1337:1337:1337)) - (PORT d[12] (1271:1271:1271) (1319:1319:1319)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2034:2034:2034) (2233:2233:2233)) + (PORT d[1] (1965:1965:1965) (2106:2106:2106)) + (PORT d[2] (2209:2209:2209) (2367:2367:2367)) + (PORT d[3] (2240:2240:2240) (2404:2404:2404)) + (PORT d[4] (2184:2184:2184) (2357:2357:2357)) + (PORT d[5] (2204:2204:2204) (2358:2358:2358)) + (PORT d[6] (2164:2164:2164) (2290:2290:2290)) + (PORT d[7] (2094:2094:2094) (2301:2301:2301)) + (PORT d[8] (2332:2332:2332) (2483:2483:2483)) + (PORT d[9] (1879:1879:1879) (2041:2041:2041)) + (PORT d[10] (2031:2031:2031) (2222:2222:2222)) + (PORT d[11] (2277:2277:2277) (2430:2430:2430)) + (PORT d[12] (2315:2315:2315) (2497:2497:2497)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -2819,8 +4829,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (909:909:909) (894:894:894)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1813:1813:1813) (1728:1728:1728)) ) ) ) @@ -2829,7 +4839,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2839,7 +4849,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) + (PORT clk (1815:1815:1815) (1842:1842:1842)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2853,7 +4863,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) + (PORT clk (1000:1000:1000) (1005:1005:1005)) ) ) ) @@ -2862,7 +4872,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (1001:1001:1001) (1006:1006:1006)) ) ) ) @@ -2871,7 +4881,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (1001:1001:1001) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2879,6 +4889,2940 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2036:2036:2036) (2238:2238:2238)) + (PORT d[1] (2208:2208:2208) (2355:2355:2355)) + (PORT d[2] (2290:2290:2290) (2482:2482:2482)) + (PORT d[3] (2227:2227:2227) (2392:2392:2392)) + (PORT d[4] (2188:2188:2188) (2350:2350:2350)) + (PORT d[5] (2163:2163:2163) (2296:2296:2296)) + (PORT d[6] (1938:1938:1938) (2096:2096:2096)) + (PORT d[7] (2053:2053:2053) (2285:2285:2285)) + (PORT d[8] (2038:2038:2038) (2172:2172:2172)) + (PORT d[9] (2152:2152:2152) (2331:2331:2331)) + (PORT d[10] (2012:2012:2012) (2207:2207:2207)) + (PORT d[11] (2331:2331:2331) (2476:2476:2476)) + (PORT d[12] (2240:2240:2240) (2416:2416:2416)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (1909:1909:1909) (2020:2020:2020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (2760:2760:2760) (2963:2963:2963)) + (PORT datac (556:556:556) (558:558:558)) + (PORT datad (649:649:649) (676:676:676)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3478:3478:3478) (3599:3599:3599)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2019:2019:2019) (2126:2126:2126)) + (PORT d[1] (1744:1744:1744) (1872:1872:1872)) + (PORT d[2] (1727:1727:1727) (1824:1824:1824)) + (PORT d[3] (1724:1724:1724) (1879:1879:1879)) + (PORT d[4] (1958:1958:1958) (2143:2143:2143)) + (PORT d[5] (1471:1471:1471) (1597:1597:1597)) + (PORT d[6] (1707:1707:1707) (1863:1863:1863)) + (PORT d[7] (2243:2243:2243) (2372:2372:2372)) + (PORT d[8] (1971:1971:1971) (2145:2145:2145)) + (PORT d[9] (1769:1769:1769) (1882:1882:1882)) + (PORT d[10] (1445:1445:1445) (1602:1602:1602)) + (PORT d[11] (2162:2162:2162) (2306:2306:2306)) + (PORT d[12] (1740:1740:1740) (1899:1899:1899)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1319:1319:1319) (1255:1255:1255)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3483:3483:3483) (3604:3604:3604)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2034:2034:2034) (2152:2152:2152)) + (PORT d[1] (1723:1723:1723) (1848:1848:1848)) + (PORT d[2] (1752:1752:1752) (1847:1847:1847)) + (PORT d[3] (1725:1725:1725) (1879:1879:1879)) + (PORT d[4] (1945:1945:1945) (2111:2111:2111)) + (PORT d[5] (1472:1472:1472) (1597:1597:1597)) + (PORT d[6] (1708:1708:1708) (1863:1863:1863)) + (PORT d[7] (2244:2244:2244) (2372:2372:2372)) + (PORT d[8] (1972:1972:1972) (2145:2145:2145)) + (PORT d[9] (1770:1770:1770) (1882:1882:1882)) + (PORT d[10] (1446:1446:1446) (1602:1602:1602)) + (PORT d[11] (2163:2163:2163) (2306:2306:2306)) + (PORT d[12] (1741:1741:1741) (1899:1899:1899)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (1319:1319:1319) (1255:1255:1255)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3478:3478:3478) (3600:3600:3600)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1943:1943:1943) (2073:2073:2073)) + (PORT d[1] (1998:1998:1998) (2125:2125:2125)) + (PORT d[2] (1904:1904:1904) (2028:2028:2028)) + (PORT d[3] (1782:1782:1782) (1923:1923:1923)) + (PORT d[4] (1950:1950:1950) (2124:2124:2124)) + (PORT d[5] (1477:1477:1477) (1622:1622:1622)) + (PORT d[6] (2045:2045:2045) (2181:2181:2181)) + (PORT d[7] (1737:1737:1737) (1896:1896:1896)) + (PORT d[8] (1640:1640:1640) (1754:1754:1754)) + (PORT d[9] (2015:2015:2015) (2206:2206:2206)) + (PORT d[10] (1977:1977:1977) (2149:2149:2149)) + (PORT d[11] (2188:2188:2188) (2337:2337:2337)) + (PORT d[12] (1746:1746:1746) (1924:1924:1924)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (1256:1256:1256) (1318:1318:1318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3483:3483:3483) (3605:3605:3605)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1989:1989:1989) (2122:2122:2122)) + (PORT d[1] (2007:2007:2007) (2122:2122:2122)) + (PORT d[2] (1944:1944:1944) (2065:2065:2065)) + (PORT d[3] (1783:1783:1783) (1923:1923:1923)) + (PORT d[4] (1951:1951:1951) (2130:2130:2130)) + (PORT d[5] (1478:1478:1478) (1622:1622:1622)) + (PORT d[6] (2046:2046:2046) (2181:2181:2181)) + (PORT d[7] (1738:1738:1738) (1896:1896:1896)) + (PORT d[8] (1641:1641:1641) (1754:1754:1754)) + (PORT d[9] (2016:2016:2016) (2206:2206:2206)) + (PORT d[10] (1978:1978:1978) (2149:2149:2149)) + (PORT d[11] (2189:2189:2189) (2337:2337:2337)) + (PORT d[12] (1747:1747:1747) (1924:1924:1924)) + (PORT clk (1856:1856:1856) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1256:1256:1256) (1318:1318:1318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (355:355:355)) + (PORT datac (649:649:649) (696:696:696)) + (PORT datad (965:965:965) (1003:1003:1003)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2795:2795:2795) (2881:2881:2881)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1986:1986:1986) (2096:2096:2096)) + (PORT d[1] (1924:1924:1924) (2104:2104:2104)) + (PORT d[2] (1955:1955:1955) (2104:2104:2104)) + (PORT d[3] (1736:1736:1736) (1899:1899:1899)) + (PORT d[4] (2176:2176:2176) (2350:2350:2350)) + (PORT d[5] (1843:1843:1843) (2000:2000:2000)) + (PORT d[6] (2047:2047:2047) (2218:2218:2218)) + (PORT d[7] (2035:2035:2035) (2190:2190:2190)) + (PORT d[8] (1909:1909:1909) (2029:2029:2029)) + (PORT d[9] (2025:2025:2025) (2217:2217:2217)) + (PORT d[10] (2173:2173:2173) (2412:2412:2412)) + (PORT d[11] (2021:2021:2021) (2147:2147:2147)) + (PORT d[12] (2070:2070:2070) (2251:2251:2251)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (1526:1526:1526) (1593:1593:1593)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2800:2800:2800) (2886:2886:2886)) + (PORT clk (1872:1872:1872) (1897:1897:1897)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1987:1987:1987) (2103:2103:2103)) + (PORT d[1] (1947:1947:1947) (2127:2127:2127)) + (PORT d[2] (1956:1956:1956) (2104:2104:2104)) + (PORT d[3] (1737:1737:1737) (1899:1899:1899)) + (PORT d[4] (2222:2222:2222) (2399:2399:2399)) + (PORT d[5] (1844:1844:1844) (2000:2000:2000)) + (PORT d[6] (2048:2048:2048) (2218:2218:2218)) + (PORT d[7] (2036:2036:2036) (2190:2190:2190)) + (PORT d[8] (1910:1910:1910) (2029:2029:2029)) + (PORT d[9] (2026:2026:2026) (2217:2217:2217)) + (PORT d[10] (2174:2174:2174) (2412:2412:2412)) + (PORT d[11] (2022:2022:2022) (2147:2147:2147)) + (PORT d[12] (2071:2071:2071) (2251:2251:2251)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (PORT d[0] (1526:1526:1526) (1593:1593:1593)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2785:2785:2785) (2862:2862:2862)) + (PORT clk (1870:1870:1870) (1897:1897:1897)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1953:1953:1953) (2079:2079:2079)) + (PORT d[1] (1947:1947:1947) (2130:2130:2130)) + (PORT d[2] (1994:1994:1994) (2095:2095:2095)) + (PORT d[3] (1760:1760:1760) (1926:1926:1926)) + (PORT d[4] (2185:2185:2185) (2357:2357:2357)) + (PORT d[5] (1741:1741:1741) (1881:1881:1881)) + (PORT d[6] (2007:2007:2007) (2161:2161:2161)) + (PORT d[7] (2039:2039:2039) (2194:2194:2194)) + (PORT d[8] (2281:2281:2281) (2397:2397:2397)) + (PORT d[9] (2052:2052:2052) (2249:2249:2249)) + (PORT d[10] (1662:1662:1662) (1830:1830:1830)) + (PORT d[11] (1999:1999:1999) (2122:2122:2122)) + (PORT d[12] (2091:2091:2091) (2299:2299:2299)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT d[0] (1591:1591:1591) (1526:1526:1526)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2790:2790:2790) (2867:2867:2867)) + (PORT clk (1872:1872:1872) (1898:1898:1898)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1967:1967:1967) (2105:2105:2105)) + (PORT d[1] (1926:1926:1926) (2106:2106:2106)) + (PORT d[2] (2313:2313:2313) (2399:2399:2399)) + (PORT d[3] (1761:1761:1761) (1926:1926:1926)) + (PORT d[4] (1962:1962:1962) (2131:2131:2131)) + (PORT d[5] (1742:1742:1742) (1881:1881:1881)) + (PORT d[6] (2008:2008:2008) (2161:2161:2161)) + (PORT d[7] (2040:2040:2040) (2194:2194:2194)) + (PORT d[8] (2282:2282:2282) (2397:2397:2397)) + (PORT d[9] (2053:2053:2053) (2249:2249:2249)) + (PORT d[10] (1663:1663:1663) (1830:1830:1830)) + (PORT d[11] (2000:2000:2000) (2122:2122:2122)) + (PORT d[12] (2092:2092:2092) (2299:2299:2299)) + (PORT clk (1868:1868:1868) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1898:1898:1898)) + (PORT d[0] (1591:1591:1591) (1526:1526:1526)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (645:645:645)) + (PORT datac (993:993:993) (1070:1070:1070)) + (PORT datad (902:902:902) (910:910:910)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2129:2129:2129) (2209:2209:2209)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2080:2080:2080) (2290:2290:2290)) + (PORT d[1] (1984:1984:1984) (2161:2161:2161)) + (PORT d[2] (1864:1864:1864) (2019:2019:2019)) + (PORT d[3] (2469:2469:2469) (2619:2619:2619)) + (PORT d[4] (2505:2505:2505) (2677:2677:2677)) + (PORT d[5] (2155:2155:2155) (2279:2279:2279)) + (PORT d[6] (2240:2240:2240) (2392:2392:2392)) + (PORT d[7] (2203:2203:2203) (2386:2386:2386)) + (PORT d[8] (2230:2230:2230) (2405:2405:2405)) + (PORT d[9] (2206:2206:2206) (2378:2378:2378)) + (PORT d[10] (2026:2026:2026) (2221:2221:2221)) + (PORT d[11] (2288:2288:2288) (2426:2426:2426)) + (PORT d[12] (2218:2218:2218) (2381:2381:2381)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1896:1896:1896) (2026:2026:2026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2134:2134:2134) (2214:2214:2214)) + (PORT clk (1864:1864:1864) (1890:1890:1890)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2073:2073:2073) (2293:2293:2293)) + (PORT d[1] (2007:2007:2007) (2186:2186:2186)) + (PORT d[2] (1860:1860:1860) (2030:2030:2030)) + (PORT d[3] (2470:2470:2470) (2619:2619:2619)) + (PORT d[4] (2337:2337:2337) (2481:2481:2481)) + (PORT d[5] (2156:2156:2156) (2279:2279:2279)) + (PORT d[6] (2241:2241:2241) (2392:2392:2392)) + (PORT d[7] (2204:2204:2204) (2386:2386:2386)) + (PORT d[8] (2231:2231:2231) (2405:2405:2405)) + (PORT d[9] (2207:2207:2207) (2378:2378:2378)) + (PORT d[10] (2027:2027:2027) (2221:2221:2221)) + (PORT d[11] (2289:2289:2289) (2426:2426:2426)) + (PORT d[12] (2219:2219:2219) (2381:2381:2381)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1890:1890:1890)) + (PORT d[0] (1896:1896:1896) (2026:2026:2026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1849:1849:1849)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3173:3173:3173) (3286:3286:3286)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1718:1718:1718) (1848:1848:1848)) + (PORT d[1] (2002:2002:2002) (2154:2154:2154)) + (PORT d[2] (1745:1745:1745) (1851:1851:1851)) + (PORT d[3] (1732:1732:1732) (1875:1875:1875)) + (PORT d[4] (1993:1993:1993) (2145:2145:2145)) + (PORT d[5] (1514:1514:1514) (1664:1664:1664)) + (PORT d[6] (2087:2087:2087) (2261:2261:2261)) + (PORT d[7] (2026:2026:2026) (2179:2179:2179)) + (PORT d[8] (1911:1911:1911) (2044:2044:2044)) + (PORT d[9] (2000:2000:2000) (2165:2165:2165)) + (PORT d[10] (1691:1691:1691) (1849:1849:1849)) + (PORT d[11] (1991:1991:1991) (2092:2092:2092)) + (PORT d[12] (2025:2025:2025) (2206:2206:2206)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1365:1365:1365) (1299:1299:1299)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3178:3178:3178) (3291:3291:3291)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1697:1697:1697) (1824:1824:1824)) + (PORT d[1] (1990:1990:1990) (2122:2122:2122)) + (PORT d[2] (1947:1947:1947) (2080:2080:2080)) + (PORT d[3] (1733:1733:1733) (1875:1875:1875)) + (PORT d[4] (1994:1994:1994) (2145:2145:2145)) + (PORT d[5] (1515:1515:1515) (1664:1664:1664)) + (PORT d[6] (2088:2088:2088) (2261:2261:2261)) + (PORT d[7] (2027:2027:2027) (2179:2179:2179)) + (PORT d[8] (1912:1912:1912) (2044:2044:2044)) + (PORT d[9] (2001:2001:2001) (2165:2165:2165)) + (PORT d[10] (1692:1692:1692) (1849:1849:1849)) + (PORT d[11] (1992:1992:1992) (2092:2092:2092)) + (PORT d[12] (2026:2026:2026) (2206:2206:2206)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1365:1365:1365) (1299:1299:1299)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2229:2229:2229) (2452:2452:2452)) + (PORT datac (917:917:917) (935:935:935)) + (PORT datad (1306:1306:1306) (1332:1332:1332)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2883:2883:2883) (2988:2988:2988)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1960:1960:1960) (2086:2086:2086)) + (PORT d[1] (1945:1945:1945) (2125:2125:2125)) + (PORT d[2] (1971:1971:1971) (2132:2132:2132)) + (PORT d[3] (1766:1766:1766) (1913:1913:1913)) + (PORT d[4] (1945:1945:1945) (2126:2126:2126)) + (PORT d[5] (1865:1865:1865) (2025:2025:2025)) + (PORT d[6] (2059:2059:2059) (2199:2199:2199)) + (PORT d[7] (1959:1959:1959) (2120:2120:2120)) + (PORT d[8] (2245:2245:2245) (2378:2378:2378)) + (PORT d[9] (2021:2021:2021) (2210:2210:2210)) + (PORT d[10] (2196:2196:2196) (2442:2442:2442)) + (PORT d[11] (2254:2254:2254) (2367:2367:2367)) + (PORT d[12] (2061:2061:2061) (2263:2263:2263)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (1539:1539:1539) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1854:1854:1854)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2888:2888:2888) (2993:2993:2993)) + (PORT clk (1871:1871:1871) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (2062:2062:2062)) + (PORT d[1] (1933:1933:1933) (2100:2100:2100)) + (PORT d[2] (1928:1928:1928) (2069:2069:2069)) + (PORT d[3] (1767:1767:1767) (1913:1913:1913)) + (PORT d[4] (1924:1924:1924) (2101:2101:2101)) + (PORT d[5] (1866:1866:1866) (2025:2025:2025)) + (PORT d[6] (2060:2060:2060) (2199:2199:2199)) + (PORT d[7] (1960:1960:1960) (2120:2120:2120)) + (PORT d[8] (2246:2246:2246) (2378:2378:2378)) + (PORT d[9] (2022:2022:2022) (2210:2210:2210)) + (PORT d[10] (2197:2197:2197) (2442:2442:2442)) + (PORT d[11] (2255:2255:2255) (2367:2367:2367)) + (PORT d[12] (2062:2062:2062) (2263:2263:2263)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1896:1896:1896)) + (PORT d[0] (1539:1539:1539) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2303:2303:2303) (2389:2389:2389)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1974:1974:1974) (2117:2117:2117)) + (PORT d[1] (1926:1926:1926) (2107:2107:2107)) + (PORT d[2] (1892:1892:1892) (2023:2023:2023)) + (PORT d[3] (2018:2018:2018) (2177:2177:2177)) + (PORT d[4] (2218:2218:2218) (2413:2413:2413)) + (PORT d[5] (1772:1772:1772) (1925:1925:1925)) + (PORT d[6] (2015:2015:2015) (2155:2155:2155)) + (PORT d[7] (2023:2023:2023) (2199:2199:2199)) + (PORT d[8] (1873:1873:1873) (2013:2013:2013)) + (PORT d[9] (2016:2016:2016) (2205:2205:2205)) + (PORT d[10] (2301:2301:2301) (2478:2478:2478)) + (PORT d[11] (2004:2004:2004) (2138:2138:2138)) + (PORT d[12] (2070:2070:2070) (2273:2273:2273)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT d[0] (1618:1618:1618) (1535:1535:1535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2308:2308:2308) (2394:2394:2394)) + (PORT clk (1873:1873:1873) (1899:1899:1899)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1952:1952:1952) (2092:2092:2092)) + (PORT d[1] (1927:1927:1927) (2107:2107:2107)) + (PORT d[2] (1907:1907:1907) (2055:2055:2055)) + (PORT d[3] (2019:2019:2019) (2177:2177:2177)) + (PORT d[4] (2241:2241:2241) (2431:2431:2431)) + (PORT d[5] (1773:1773:1773) (1925:1925:1925)) + (PORT d[6] (2016:2016:2016) (2155:2155:2155)) + (PORT d[7] (2024:2024:2024) (2199:2199:2199)) + (PORT d[8] (1874:1874:1874) (2013:2013:2013)) + (PORT d[9] (2017:2017:2017) (2205:2205:2205)) + (PORT d[10] (2302:2302:2302) (2478:2478:2478)) + (PORT d[11] (2005:2005:2005) (2138:2138:2138)) + (PORT d[12] (2071:2071:2071) (2273:2273:2273)) + (PORT clk (1869:1869:1869) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (PORT d[0] (1618:1618:1618) (1535:1535:1535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1833:1833:1833) (1858:1858:1858)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (604:604:604)) + (PORT datac (867:867:867) (931:931:931)) + (PORT datad (655:655:655) (682:682:682)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[14\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (374:374:374)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (830:830:830) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (612:612:612) (670:670:670)) + (PORT datad (450:450:450) (522:522:522)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2168:2168:2168) (2212:2212:2212)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1337:1337:1337) (1420:1420:1420)) + (PORT d[1] (1328:1328:1328) (1430:1430:1430)) + (PORT d[2] (1364:1364:1364) (1439:1439:1439)) + (PORT d[3] (1355:1355:1355) (1417:1417:1417)) + (PORT d[4] (1299:1299:1299) (1403:1403:1403)) + (PORT d[5] (1278:1278:1278) (1332:1332:1332)) + (PORT d[6] (1295:1295:1295) (1405:1405:1405)) + (PORT d[7] (1499:1499:1499) (1598:1598:1598)) + (PORT d[8] (1363:1363:1363) (1461:1461:1461)) + (PORT d[9] (1332:1332:1332) (1422:1422:1422)) + (PORT d[10] (1336:1336:1336) (1423:1423:1423)) + (PORT d[11] (1346:1346:1346) (1428:1428:1428)) + (PORT d[12] (1391:1391:1391) (1503:1503:1503)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (982:982:982) (966:966:966)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datac (611:611:611) (671:671:671)) + (PORT datad (452:452:452) (521:521:521)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (905:905:905) (924:924:924)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1580:1580:1580) (1688:1688:1688)) + (PORT d[1] (1302:1302:1302) (1409:1409:1409)) + (PORT d[2] (1611:1611:1611) (1712:1712:1712)) + (PORT d[3] (1734:1734:1734) (1874:1874:1874)) + (PORT d[4] (1682:1682:1682) (1815:1815:1815)) + (PORT d[5] (1491:1491:1491) (1641:1641:1641)) + (PORT d[6] (1673:1673:1673) (1775:1775:1775)) + (PORT d[7] (1894:1894:1894) (1992:1992:1992)) + (PORT d[8] (1660:1660:1660) (1786:1786:1786)) + (PORT d[9] (1691:1691:1691) (1820:1820:1820)) + (PORT d[10] (1748:1748:1748) (1931:1931:1931)) + (PORT d[11] (1900:1900:1900) (2024:2024:2024)) + (PORT d[12] (1764:1764:1764) (1943:1943:1943)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1353:1353:1353) (1332:1332:1332)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (612:612:612) (671:671:671)) + (PORT datad (451:451:451) (521:521:521)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2579:2579:2579) (2676:2676:2676)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1784:1784:1784) (1877:1877:1877)) + (PORT d[1] (1842:1842:1842) (1972:1972:1972)) + (PORT d[2] (1490:1490:1490) (1579:1579:1579)) + (PORT d[3] (1483:1483:1483) (1540:1540:1540)) + (PORT d[4] (1539:1539:1539) (1619:1619:1619)) + (PORT d[5] (1318:1318:1318) (1397:1397:1397)) + (PORT d[6] (1554:1554:1554) (1660:1660:1660)) + (PORT d[7] (1764:1764:1764) (1873:1873:1873)) + (PORT d[8] (1286:1286:1286) (1377:1377:1377)) + (PORT d[9] (1242:1242:1242) (1310:1310:1310)) + (PORT d[10] (1262:1262:1262) (1360:1360:1360)) + (PORT d[11] (1317:1317:1317) (1401:1401:1401)) + (PORT d[12] (1190:1190:1190) (1255:1255:1255)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1069:1069:1069) (1039:1039:1039)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (610:610:610) (668:668:668)) + (PORT datad (448:448:448) (518:518:518)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2427:2427:2427) (2508:2508:2508)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1117:1117:1117)) + (PORT d[1] (1049:1049:1049) (1160:1160:1160)) + (PORT d[2] (1086:1086:1086) (1148:1148:1148)) + (PORT d[3] (1062:1062:1062) (1134:1134:1134)) + (PORT d[4] (1559:1559:1559) (1650:1650:1650)) + (PORT d[5] (1057:1057:1057) (1151:1151:1151)) + (PORT d[6] (1108:1108:1108) (1213:1213:1213)) + (PORT d[7] (1269:1269:1269) (1366:1366:1366)) + (PORT d[8] (1333:1333:1333) (1424:1424:1424)) + (PORT d[9] (1102:1102:1102) (1207:1207:1207)) + (PORT d[10] (1349:1349:1349) (1437:1437:1437)) + (PORT d[11] (1129:1129:1129) (1210:1210:1210)) + (PORT d[12] (1284:1284:1284) (1360:1360:1360)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (846:846:846) (828:828:828)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (657:657:657) (705:705:705)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1889:1889:1889) (1911:1911:1911)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1977:1977:1977)) + (PORT datab (1135:1135:1135) (1147:1147:1147)) + (PORT datac (855:855:855) (891:891:891)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1209:1209:1209)) + (PORT datab (1425:1425:1425) (1483:1483:1483)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1911:1911:1911) (1992:1992:1992)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2172:2172:2172) (2339:2339:2339)) + (PORT d[1] (1564:1564:1564) (1694:1694:1694)) + (PORT d[2] (1725:1725:1725) (1839:1839:1839)) + (PORT d[3] (1747:1747:1747) (1811:1811:1811)) + (PORT d[4] (1741:1741:1741) (1810:1810:1810)) + (PORT d[5] (1548:1548:1548) (1644:1644:1644)) + (PORT d[6] (1530:1530:1530) (1633:1633:1633)) + (PORT d[7] (1459:1459:1459) (1557:1557:1557)) + (PORT d[8] (1541:1541:1541) (1649:1649:1649)) + (PORT d[9] (1471:1471:1471) (1529:1529:1529)) + (PORT d[10] (1489:1489:1489) (1593:1593:1593)) + (PORT d[11] (1557:1557:1557) (1641:1641:1641)) + (PORT d[12] (1770:1770:1770) (1827:1827:1827)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1273:1273:1273) (1267:1267:1267)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2250:2250:2250) (2330:2330:2330)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1978:1978:1978) (2147:2147:2147)) + (PORT d[1] (1517:1517:1517) (1633:1633:1633)) + (PORT d[2] (1736:1736:1736) (1836:1836:1836)) + (PORT d[3] (1746:1746:1746) (1798:1798:1798)) + (PORT d[4] (1738:1738:1738) (1807:1807:1807)) + (PORT d[5] (1573:1573:1573) (1658:1658:1658)) + (PORT d[6] (1555:1555:1555) (1647:1647:1647)) + (PORT d[7] (1442:1442:1442) (1529:1529:1529)) + (PORT d[8] (1539:1539:1539) (1634:1634:1634)) + (PORT d[9] (1492:1492:1492) (1553:1553:1553)) + (PORT d[10] (1509:1509:1509) (1617:1617:1617)) + (PORT d[11] (1582:1582:1582) (1654:1654:1654)) + (PORT d[12] (1740:1740:1740) (1798:1798:1798)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1245:1245:1245) (1209:1209:1209)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2717:2717:2717) (2805:2805:2805)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1059:1059:1059) (1142:1142:1142)) + (PORT d[1] (1091:1091:1091) (1165:1165:1165)) + (PORT d[2] (1060:1060:1060) (1123:1123:1123)) + (PORT d[3] (1344:1344:1344) (1418:1418:1418)) + (PORT d[4] (1302:1302:1302) (1409:1409:1409)) + (PORT d[5] (1050:1050:1050) (1118:1118:1118)) + (PORT d[6] (1031:1031:1031) (1111:1111:1111)) + (PORT d[7] (1231:1231:1231) (1307:1307:1307)) + (PORT d[8] (1068:1068:1068) (1146:1146:1146)) + (PORT d[9] (1109:1109:1109) (1198:1198:1198)) + (PORT d[10] (1092:1092:1092) (1176:1176:1176)) + (PORT d[11] (1106:1106:1106) (1187:1187:1187)) + (PORT d[12] (1080:1080:1080) (1183:1183:1183)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (829:829:829) (786:786:786)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1000:1000:1000) (1004:1004:1004)) @@ -2888,16 +7832,3838 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (992:992:992) (1066:1066:1066)) - (PORT datac (604:604:604) (608:608:608)) - (PORT datad (1039:1039:1039) (1055:1055:1055)) + (PORT dataa (1538:1538:1538) (1685:1685:1685)) + (PORT datab (1502:1502:1502) (1574:1574:1574)) + (PORT datac (1307:1307:1307) (1329:1329:1329)) + (PORT datad (983:983:983) (1060:1060:1060)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (898:898:898) (917:917:917)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1708:1708:1708) (1889:1889:1889)) + (PORT d[1] (1738:1738:1738) (1912:1912:1912)) + (PORT d[2] (2173:2173:2173) (2306:2306:2306)) + (PORT d[3] (1836:1836:1836) (1931:1931:1931)) + (PORT d[4] (2057:2057:2057) (2182:2182:2182)) + (PORT d[5] (1610:1610:1610) (1719:1719:1719)) + (PORT d[6] (1827:1827:1827) (1950:1950:1950)) + (PORT d[7] (2186:2186:2186) (2317:2317:2317)) + (PORT d[8] (1553:1553:1553) (1673:1673:1673)) + (PORT d[9] (1518:1518:1518) (1627:1627:1627)) + (PORT d[10] (1791:1791:1791) (1987:1987:1987)) + (PORT d[11] (1616:1616:1616) (1720:1720:1720)) + (PORT d[12] (1800:1800:1800) (1921:1921:1921)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1172:1172:1172) (1177:1177:1177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1573:1573:1573)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1093:1093:1093) (1101:1101:1101)) + (PORT datad (983:983:983) (1067:1067:1067)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2453:2453:2453) (2542:2542:2542)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1037:1037:1037) (1128:1128:1128)) + (PORT d[1] (1054:1054:1054) (1160:1160:1160)) + (PORT d[2] (1085:1085:1085) (1147:1147:1147)) + (PORT d[3] (1322:1322:1322) (1383:1383:1383)) + (PORT d[4] (1063:1063:1063) (1161:1161:1161)) + (PORT d[5] (1060:1060:1060) (1155:1155:1155)) + (PORT d[6] (1070:1070:1070) (1162:1162:1162)) + (PORT d[7] (1268:1268:1268) (1365:1365:1365)) + (PORT d[8] (1092:1092:1092) (1181:1181:1181)) + (PORT d[9] (1101:1101:1101) (1206:1206:1206)) + (PORT d[10] (1084:1084:1084) (1184:1184:1184)) + (PORT d[11] (1128:1128:1128) (1209:1209:1209)) + (PORT d[12] (1125:1125:1125) (1247:1247:1247)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (769:769:769) (752:752:752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2274:2274:2274) (2350:2350:2350)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1485:1485:1485) (1583:1583:1583)) + (PORT d[1] (1841:1841:1841) (1971:1971:1971)) + (PORT d[2] (1529:1529:1529) (1647:1647:1647)) + (PORT d[3] (1494:1494:1494) (1568:1568:1568)) + (PORT d[4] (1502:1502:1502) (1598:1598:1598)) + (PORT d[5] (1300:1300:1300) (1387:1387:1387)) + (PORT d[6] (1569:1569:1569) (1676:1676:1676)) + (PORT d[7] (1763:1763:1763) (1873:1873:1873)) + (PORT d[8] (1295:1295:1295) (1399:1399:1399)) + (PORT d[9] (1229:1229:1229) (1312:1312:1312)) + (PORT d[10] (1248:1248:1248) (1357:1357:1357)) + (PORT d[11] (1299:1299:1299) (1395:1395:1395)) + (PORT d[12] (1524:1524:1524) (1618:1618:1618)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1054:1054:1054) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2261:2261:2261) (2357:2357:2357)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1737:1737:1737) (1843:1843:1843)) + (PORT d[1] (1850:1850:1850) (1966:1966:1966)) + (PORT d[2] (1540:1540:1540) (1643:1643:1643)) + (PORT d[3] (1525:1525:1525) (1596:1596:1596)) + (PORT d[4] (1540:1540:1540) (1614:1614:1614)) + (PORT d[5] (1306:1306:1306) (1402:1402:1402)) + (PORT d[6] (1565:1565:1565) (1672:1672:1672)) + (PORT d[7] (1724:1724:1724) (1812:1812:1812)) + (PORT d[8] (1273:1273:1273) (1378:1378:1378)) + (PORT d[9] (1270:1270:1270) (1341:1341:1341)) + (PORT d[10] (1253:1253:1253) (1367:1367:1367)) + (PORT d[11] (1339:1339:1339) (1422:1422:1422)) + (PORT d[12] (1201:1201:1201) (1283:1283:1283)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1041:1041:1041) (1051:1051:1051)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1166:1166:1166)) + (PORT datab (302:302:302) (396:396:396)) + (PORT datac (1519:1519:1519) (1629:1629:1629)) + (PORT datad (1138:1138:1138) (1148:1148:1148)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2749:2749:2749) (2863:2863:2863)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (760:760:760) (843:843:843)) + (PORT d[1] (738:738:738) (819:819:819)) + (PORT d[2] (1007:1007:1007) (1067:1067:1067)) + (PORT d[3] (1327:1327:1327) (1409:1409:1409)) + (PORT d[4] (1070:1070:1070) (1153:1153:1153)) + (PORT d[5] (1291:1291:1291) (1393:1393:1393)) + (PORT d[6] (1016:1016:1016) (1096:1096:1096)) + (PORT d[7] (1254:1254:1254) (1327:1327:1327)) + (PORT d[8] (1046:1046:1046) (1125:1125:1125)) + (PORT d[9] (1067:1067:1067) (1150:1150:1150)) + (PORT d[10] (1263:1263:1263) (1344:1344:1344)) + (PORT d[11] (1288:1288:1288) (1365:1365:1365)) + (PORT d[12] (1238:1238:1238) (1306:1306:1306)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (821:821:821) (785:785:785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (865:865:865)) + (PORT datab (301:301:301) (396:396:396)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (818:818:818) (827:827:827)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1913:1913:1913) (1986:1986:1986)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1995:1995:1995) (2182:2182:2182)) + (PORT d[1] (1708:1708:1708) (1871:1871:1871)) + (PORT d[2] (2135:2135:2135) (2280:2280:2280)) + (PORT d[3] (2271:2271:2271) (2418:2418:2418)) + (PORT d[4] (2106:2106:2106) (2226:2226:2226)) + (PORT d[5] (1944:1944:1944) (2065:2065:2065)) + (PORT d[6] (1778:1778:1778) (1904:1904:1904)) + (PORT d[7] (2147:2147:2147) (2267:2267:2267)) + (PORT d[8] (1887:1887:1887) (2041:2041:2041)) + (PORT d[9] (1870:1870:1870) (1997:1997:1997)) + (PORT d[10] (1754:1754:1754) (1977:1977:1977)) + (PORT d[11] (1857:1857:1857) (2005:2005:2005)) + (PORT d[12] (2069:2069:2069) (2211:2211:2211)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1357:1357:1357) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3031:3031:3031) (3166:3166:3166)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1049:1049:1049) (1114:1114:1114)) + (PORT d[1] (1017:1017:1017) (1109:1109:1109)) + (PORT d[2] (1297:1297:1297) (1378:1378:1378)) + (PORT d[3] (1362:1362:1362) (1466:1466:1466)) + (PORT d[4] (1376:1376:1376) (1484:1484:1484)) + (PORT d[5] (1483:1483:1483) (1628:1628:1628)) + (PORT d[6] (1357:1357:1357) (1437:1437:1437)) + (PORT d[7] (1587:1587:1587) (1682:1682:1682)) + (PORT d[8] (1344:1344:1344) (1446:1446:1446)) + (PORT d[9] (1376:1376:1376) (1485:1485:1485)) + (PORT d[10] (1367:1367:1367) (1486:1486:1486)) + (PORT d[11] (1591:1591:1591) (1672:1672:1672)) + (PORT d[12] (1328:1328:1328) (1396:1396:1396)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1101:1101:1101) (1098:1098:1098)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1683:1683:1683)) + (PORT datab (1027:1027:1027) (1106:1106:1106)) + (PORT datac (1437:1437:1437) (1486:1486:1486)) + (PORT datad (1069:1069:1069) (1080:1080:1080)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2589:2589:2589) (2663:2663:2663)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1794:1794:1794) (1905:1905:1905)) + (PORT d[1] (1026:1026:1026) (1096:1096:1096)) + (PORT d[2] (1216:1216:1216) (1322:1322:1322)) + (PORT d[3] (1156:1156:1156) (1234:1234:1234)) + (PORT d[4] (1228:1228:1228) (1312:1312:1312)) + (PORT d[5] (1039:1039:1039) (1118:1118:1118)) + (PORT d[6] (1579:1579:1579) (1705:1705:1705)) + (PORT d[7] (1556:1556:1556) (1623:1623:1623)) + (PORT d[8] (999:999:999) (1083:1083:1083)) + (PORT d[9] (931:931:931) (997:997:997)) + (PORT d[10] (1049:1049:1049) (1130:1130:1130)) + (PORT d[11] (974:974:974) (1054:1054:1054)) + (PORT d[12] (938:938:938) (1003:1003:1003)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (785:785:785) (764:764:764)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3027:3027:3027) (3141:3141:3141)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1116:1116:1116)) + (PORT d[1] (1003:1003:1003) (1076:1076:1076)) + (PORT d[2] (1015:1015:1015) (1094:1094:1094)) + (PORT d[3] (1075:1075:1075) (1152:1152:1152)) + (PORT d[4] (1040:1040:1040) (1142:1142:1142)) + (PORT d[5] (1523:1523:1523) (1680:1680:1680)) + (PORT d[6] (1060:1060:1060) (1132:1132:1132)) + (PORT d[7] (1290:1290:1290) (1385:1385:1385)) + (PORT d[8] (1054:1054:1054) (1146:1146:1146)) + (PORT d[9] (1098:1098:1098) (1199:1199:1199)) + (PORT d[10] (1272:1272:1272) (1371:1371:1371)) + (PORT d[11] (1344:1344:1344) (1414:1414:1414)) + (PORT d[12] (1049:1049:1049) (1145:1145:1145)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (821:821:821) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1022:1022:1022) (1100:1100:1100)) + (PORT datac (1108:1108:1108) (1131:1131:1131)) + (PORT datad (1030:1030:1030) (1028:1028:1028)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2272:2272:2272) (2349:2349:2349)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1442:1442:1442) (1554:1554:1554)) + (PORT d[1] (1253:1253:1253) (1367:1367:1367)) + (PORT d[2] (1540:1540:1540) (1642:1642:1642)) + (PORT d[3] (1521:1521:1521) (1596:1596:1596)) + (PORT d[4] (1539:1539:1539) (1613:1613:1613)) + (PORT d[5] (1333:1333:1333) (1432:1432:1432)) + (PORT d[6] (1253:1253:1253) (1364:1364:1364)) + (PORT d[7] (1206:1206:1206) (1279:1279:1279)) + (PORT d[8] (1272:1272:1272) (1377:1377:1377)) + (PORT d[9] (1269:1269:1269) (1340:1340:1340)) + (PORT d[10] (1253:1253:1253) (1366:1366:1366)) + (PORT d[11] (1311:1311:1311) (1390:1390:1390)) + (PORT d[12] (1228:1228:1228) (1314:1314:1314)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1050:1050:1050) (1057:1057:1057)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1259:1259:1259)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1704:1704:1704) (1863:1863:1863)) + (PORT d[1] (1350:1350:1350) (1444:1444:1444)) + (PORT d[2] (1524:1524:1524) (1626:1626:1626)) + (PORT d[3] (1609:1609:1609) (1701:1701:1701)) + (PORT d[4] (1816:1816:1816) (1915:1915:1915)) + (PORT d[5] (1349:1349:1349) (1449:1449:1449)) + (PORT d[6] (1526:1526:1526) (1631:1631:1631)) + (PORT d[7] (1868:1868:1868) (2005:2005:2005)) + (PORT d[8] (1256:1256:1256) (1354:1354:1354)) + (PORT d[9] (1222:1222:1222) (1313:1313:1313)) + (PORT d[10] (1760:1760:1760) (1983:1983:1983)) + (PORT d[11] (1260:1260:1260) (1360:1360:1360)) + (PORT d[12] (1497:1497:1497) (1594:1594:1594)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1136:1136:1136) (1101:1101:1101)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3295:3295:3295) (3430:3430:3430)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1400:1400:1400) (1465:1465:1465)) + (PORT d[1] (1299:1299:1299) (1392:1392:1392)) + (PORT d[2] (1360:1360:1360) (1457:1457:1457)) + (PORT d[3] (1366:1366:1366) (1473:1473:1473)) + (PORT d[4] (1357:1357:1357) (1492:1492:1492)) + (PORT d[5] (1494:1494:1494) (1624:1624:1624)) + (PORT d[6] (1642:1642:1642) (1736:1736:1736)) + (PORT d[7] (1649:1649:1649) (1735:1735:1735)) + (PORT d[8] (1394:1394:1394) (1494:1494:1494)) + (PORT d[9] (1413:1413:1413) (1542:1542:1542)) + (PORT d[10] (1353:1353:1353) (1458:1458:1458)) + (PORT d[11] (1865:1865:1865) (1964:1964:1964)) + (PORT d[12] (1729:1729:1729) (1881:1881:1881)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1059:1059:1059) (1056:1056:1056)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1685:1685:1685)) + (PORT datab (1024:1024:1024) (1105:1105:1105)) + (PORT datac (844:844:844) (864:864:864)) + (PORT datad (1224:1224:1224) (1255:1255:1255)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (913:913:913) (963:963:963)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1599:1599:1599) (1720:1720:1720)) + (PORT d[1] (2019:2019:2019) (2145:2145:2145)) + (PORT d[2] (1619:1619:1619) (1729:1729:1729)) + (PORT d[3] (1723:1723:1723) (1862:1862:1862)) + (PORT d[4] (1885:1885:1885) (2025:2025:2025)) + (PORT d[5] (1472:1472:1472) (1621:1621:1621)) + (PORT d[6] (1660:1660:1660) (1786:1786:1786)) + (PORT d[7] (1903:1903:1903) (2010:2010:2010)) + (PORT d[8] (1677:1677:1677) (1831:1831:1831)) + (PORT d[9] (1733:1733:1733) (1891:1891:1891)) + (PORT d[10] (1717:1717:1717) (1862:1862:1862)) + (PORT d[11] (1563:1563:1563) (1687:1687:1687)) + (PORT d[12] (1762:1762:1762) (1918:1918:1918)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1302:1302:1302) (1308:1308:1308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1460:1460:1460)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1360:1360:1360) (1372:1372:1372)) + (PORT datad (988:988:988) (1066:1066:1066)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3036:3036:3036) (3166:3166:3166)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1070:1070:1070) (1137:1137:1137)) + (PORT d[1] (1268:1268:1268) (1329:1329:1329)) + (PORT d[2] (1017:1017:1017) (1100:1100:1100)) + (PORT d[3] (1083:1083:1083) (1176:1176:1176)) + (PORT d[4] (1049:1049:1049) (1156:1156:1156)) + (PORT d[5] (1511:1511:1511) (1661:1661:1661)) + (PORT d[6] (1059:1059:1059) (1156:1156:1156)) + (PORT d[7] (1328:1328:1328) (1409:1409:1409)) + (PORT d[8] (1088:1088:1088) (1193:1193:1193)) + (PORT d[9] (1082:1082:1082) (1187:1187:1187)) + (PORT d[10] (1284:1284:1284) (1353:1353:1353)) + (PORT d[11] (1286:1286:1286) (1362:1362:1362)) + (PORT d[12] (1088:1088:1088) (1169:1169:1169)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (790:790:790) (777:777:777)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1515:1515:1515) (1590:1590:1590)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1684:1684:1684) (1856:1856:1856)) + (PORT d[1] (1327:1327:1327) (1417:1417:1417)) + (PORT d[2] (1593:1593:1593) (1712:1712:1712)) + (PORT d[3] (1482:1482:1482) (1558:1558:1558)) + (PORT d[4] (1470:1470:1470) (1568:1568:1568)) + (PORT d[5] (1321:1321:1321) (1416:1416:1416)) + (PORT d[6] (1522:1522:1522) (1622:1622:1622)) + (PORT d[7] (1877:1877:1877) (1993:1993:1993)) + (PORT d[8] (1283:1283:1283) (1385:1385:1385)) + (PORT d[9] (1243:1243:1243) (1337:1337:1337)) + (PORT d[10] (1317:1317:1317) (1437:1437:1437)) + (PORT d[11] (1330:1330:1330) (1417:1417:1417)) + (PORT d[12] (1474:1474:1474) (1569:1569:1569)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1079:1079:1079) (1084:1084:1084)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3126:3126:3126)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1025:1025:1025) (1101:1101:1101)) + (PORT d[1] (1011:1011:1011) (1098:1098:1098)) + (PORT d[2] (1092:1092:1092) (1187:1187:1187)) + (PORT d[3] (1057:1057:1057) (1145:1145:1145)) + (PORT d[4] (1049:1049:1049) (1156:1156:1156)) + (PORT d[5] (1495:1495:1495) (1647:1647:1647)) + (PORT d[6] (1359:1359:1359) (1441:1441:1441)) + (PORT d[7] (1304:1304:1304) (1384:1384:1384)) + (PORT d[8] (1061:1061:1061) (1161:1161:1161)) + (PORT d[9] (1104:1104:1104) (1210:1210:1210)) + (PORT d[10] (1256:1256:1256) (1330:1330:1330)) + (PORT d[11] (1374:1374:1374) (1438:1438:1438)) + (PORT d[12] (1252:1252:1252) (1325:1325:1325)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (853:853:853) (827:827:827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (991:991:991)) + (PORT datab (1027:1027:1027) (1101:1101:1101)) + (PORT datac (1043:1043:1043) (1062:1062:1062)) + (PORT datad (1508:1508:1508) (1635:1635:1635)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3309:3309:3309) (3445:3445:3445)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1367:1367:1367) (1451:1451:1451)) + (PORT d[1] (1291:1291:1291) (1383:1383:1383)) + (PORT d[2] (1315:1315:1315) (1397:1397:1397)) + (PORT d[3] (1366:1366:1366) (1472:1472:1472)) + (PORT d[4] (1347:1347:1347) (1474:1474:1474)) + (PORT d[5] (1507:1507:1507) (1654:1654:1654)) + (PORT d[6] (1385:1385:1385) (1469:1469:1469)) + (PORT d[7] (1626:1626:1626) (1709:1709:1709)) + (PORT d[8] (1351:1351:1351) (1468:1468:1468)) + (PORT d[9] (1407:1407:1407) (1530:1530:1530)) + (PORT d[10] (1617:1617:1617) (1719:1719:1719)) + (PORT d[11] (1604:1604:1604) (1709:1709:1709)) + (PORT d[12] (1333:1333:1333) (1405:1405:1405)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1122:1122:1122) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (828:828:828)) + (PORT datab (1022:1022:1022) (1101:1101:1101)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1084:1084:1084) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1484:1484:1484) (1567:1567:1567)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1829:1829:1829) (1926:1926:1926)) + (PORT d[1] (1342:1342:1342) (1428:1428:1428)) + (PORT d[2] (1473:1473:1473) (1582:1582:1582)) + (PORT d[3] (1480:1480:1480) (1573:1573:1573)) + (PORT d[4] (1466:1466:1466) (1557:1557:1557)) + (PORT d[5] (1316:1316:1316) (1406:1406:1406)) + (PORT d[6] (1540:1540:1540) (1631:1631:1631)) + (PORT d[7] (1258:1258:1258) (1325:1325:1325)) + (PORT d[8] (1542:1542:1542) (1637:1637:1637)) + (PORT d[9] (1242:1242:1242) (1329:1329:1329)) + (PORT d[10] (1550:1550:1550) (1667:1667:1667)) + (PORT d[11] (1256:1256:1256) (1351:1351:1351)) + (PORT d[12] (1498:1498:1498) (1566:1566:1566)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1103:1103:1103) (1091:1091:1091)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2568:2568:2568) (2646:2646:2646)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1806:1806:1806) (1901:1901:1901)) + (PORT d[1] (1552:1552:1552) (1632:1632:1632)) + (PORT d[2] (1513:1513:1513) (1599:1599:1599)) + (PORT d[3] (1504:1504:1504) (1580:1580:1580)) + (PORT d[4] (1464:1464:1464) (1525:1525:1525)) + (PORT d[5] (1285:1285:1285) (1359:1359:1359)) + (PORT d[6] (1247:1247:1247) (1334:1334:1334)) + (PORT d[7] (1543:1543:1543) (1606:1606:1606)) + (PORT d[8] (1265:1265:1265) (1346:1346:1346)) + (PORT d[9] (1205:1205:1205) (1275:1275:1275)) + (PORT d[10] (1613:1613:1613) (1730:1730:1730)) + (PORT d[11] (1283:1283:1283) (1364:1364:1364)) + (PORT d[12] (1460:1460:1460) (1536:1536:1536)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1059:1059:1059) (1032:1032:1032)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1022:1022:1022)) + (PORT datab (882:882:882) (892:892:892)) + (PORT datac (1128:1128:1128) (1124:1124:1124)) + (PORT datad (1708:1708:1708) (1801:1801:1801)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1201:1201:1201) (1251:1251:1251)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1610:1610:1610) (1758:1758:1758)) + (PORT d[1] (1621:1621:1621) (1712:1712:1712)) + (PORT d[2] (1839:1839:1839) (1958:1958:1958)) + (PORT d[3] (1774:1774:1774) (1842:1842:1842)) + (PORT d[4] (1809:1809:1809) (1925:1925:1925)) + (PORT d[5] (1642:1642:1642) (1742:1742:1742)) + (PORT d[6] (1842:1842:1842) (1953:1953:1953)) + (PORT d[7] (1571:1571:1571) (1692:1692:1692)) + (PORT d[8] (1574:1574:1574) (1694:1694:1694)) + (PORT d[9] (1542:1542:1542) (1654:1654:1654)) + (PORT d[10] (1756:1756:1756) (1975:1975:1975)) + (PORT d[11] (1677:1677:1677) (1772:1772:1772)) + (PORT d[12] (1793:1793:1793) (1908:1908:1908)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1243:1243:1243) (1306:1306:1306)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2741:2741:2741) (2845:2845:2845)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (732:732:732) (812:812:812)) + (PORT d[1] (730:730:730) (809:809:809)) + (PORT d[2] (748:748:748) (807:807:807)) + (PORT d[3] (798:798:798) (865:865:865)) + (PORT d[4] (1302:1302:1302) (1410:1410:1410)) + (PORT d[5] (857:857:857) (940:940:940)) + (PORT d[6] (1335:1335:1335) (1404:1404:1404)) + (PORT d[7] (754:754:754) (826:826:826)) + (PORT d[8] (751:751:751) (827:827:827)) + (PORT d[9] (765:765:765) (842:842:842)) + (PORT d[10] (781:781:781) (864:864:864)) + (PORT d[11] (801:801:801) (859:859:859)) + (PORT d[12] (1765:1765:1765) (1920:1920:1920)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (714:714:714) (664:664:664)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1020:1020:1020)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1145:1145:1145) (1151:1151:1151)) + (PORT datad (1040:1040:1040) (1038:1038:1038)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2732:2732:2732) (2820:2820:2820)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1061:1061:1061) (1156:1156:1156)) + (PORT d[1] (1068:1068:1068) (1164:1164:1164)) + (PORT d[2] (1093:1093:1093) (1176:1176:1176)) + (PORT d[3] (1101:1101:1101) (1184:1184:1184)) + (PORT d[4] (1051:1051:1051) (1154:1154:1154)) + (PORT d[5] (1803:1803:1803) (1981:1981:1981)) + (PORT d[6] (1321:1321:1321) (1401:1401:1401)) + (PORT d[7] (1240:1240:1240) (1328:1328:1328)) + (PORT d[8] (1072:1072:1072) (1167:1167:1167)) + (PORT d[9] (1096:1096:1096) (1195:1195:1195)) + (PORT d[10] (1053:1053:1053) (1146:1146:1146)) + (PORT d[11] (1088:1088:1088) (1182:1182:1182)) + (PORT d[12] (1139:1139:1139) (1250:1250:1250)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (820:820:820) (798:798:798)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1186:1186:1186) (1254:1254:1254)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1633:1633:1633) (1730:1730:1730)) + (PORT d[1] (1706:1706:1706) (1835:1835:1835)) + (PORT d[2] (1902:1902:1902) (2011:2011:2011)) + (PORT d[3] (1689:1689:1689) (1841:1841:1841)) + (PORT d[4] (1895:1895:1895) (2039:2039:2039)) + (PORT d[5] (1462:1462:1462) (1587:1587:1587)) + (PORT d[6] (1692:1692:1692) (1844:1844:1844)) + (PORT d[7] (2176:2176:2176) (2279:2279:2279)) + (PORT d[8] (2000:2000:2000) (2161:2161:2161)) + (PORT d[9] (2005:2005:2005) (2193:2193:2193)) + (PORT d[10] (1430:1430:1430) (1590:1590:1590)) + (PORT d[11] (2146:2146:2146) (2285:2285:2285)) + (PORT d[12] (1786:1786:1786) (1943:1943:1943)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1074:1074:1074) (1078:1078:1078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (906:906:906)) + (PORT datab (302:302:302) (396:396:396)) + (PORT datac (1517:1517:1517) (1627:1627:1627)) + (PORT datad (1452:1452:1452) (1515:1515:1515)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3319:3319:3319) (3470:3470:3470)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1379:1379:1379) (1448:1448:1448)) + (PORT d[1] (1321:1321:1321) (1413:1413:1413)) + (PORT d[2] (1557:1557:1557) (1658:1658:1658)) + (PORT d[3] (1719:1719:1719) (1851:1851:1851)) + (PORT d[4] (1357:1357:1357) (1492:1492:1492)) + (PORT d[5] (1462:1462:1462) (1589:1589:1589)) + (PORT d[6] (1645:1645:1645) (1743:1743:1743)) + (PORT d[7] (1604:1604:1604) (1700:1700:1700)) + (PORT d[8] (1383:1383:1383) (1508:1508:1508)) + (PORT d[9] (1391:1391:1391) (1519:1519:1519)) + (PORT d[10] (1384:1384:1384) (1542:1542:1542)) + (PORT d[11] (1581:1581:1581) (1677:1677:1677)) + (PORT d[12] (1786:1786:1786) (1940:1940:1940)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1124:1124:1124) (1095:1095:1095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2440:2440:2440) (2510:2510:2510)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1328:1328:1328) (1418:1418:1418)) + (PORT d[1] (1327:1327:1327) (1415:1415:1415)) + (PORT d[2] (1338:1338:1338) (1400:1400:1400)) + (PORT d[3] (1424:1424:1424) (1493:1493:1493)) + (PORT d[4] (1571:1571:1571) (1657:1657:1657)) + (PORT d[5] (1300:1300:1300) (1371:1371:1371)) + (PORT d[6] (1293:1293:1293) (1389:1389:1389)) + (PORT d[7] (1497:1497:1497) (1583:1583:1583)) + (PORT d[8] (1339:1339:1339) (1429:1429:1429)) + (PORT d[9] (1353:1353:1353) (1446:1446:1446)) + (PORT d[10] (1332:1332:1332) (1421:1421:1421)) + (PORT d[11] (1372:1372:1372) (1441:1441:1441)) + (PORT d[12] (1339:1339:1339) (1448:1448:1448)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1003:1003:1003) (985:985:985)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (303:303:303) (400:400:400)) + (PORT datac (1160:1160:1160) (1176:1176:1176)) + (PORT datad (1074:1074:1074) (1066:1066:1066)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (952:952:952)) + (PORT datac (702:702:702) (800:800:800)) + (PORT datad (645:645:645) (654:654:654)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1105:1105:1105)) + (PORT datac (616:616:616) (620:620:620)) + (PORT datad (342:342:342) (355:355:355)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (996:996:996)) + (PORT datab (1022:1022:1022) (1101:1101:1101)) + (PORT datad (1506:1506:1506) (1591:1591:1591)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1105:1105:1105)) + (PORT datac (646:646:646) (656:656:656)) + (PORT datad (652:652:652) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1024:1024:1024) (1103:1103:1103)) + (PORT datac (1317:1317:1317) (1316:1316:1316)) + (PORT datad (631:631:631) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (697:697:697)) + (PORT datac (994:994:994) (1070:1070:1070)) + (PORT datad (660:660:660) (670:670:670)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1989:1989:1989) (2097:2097:2097)) + (PORT datac (635:635:635) (654:654:654)) + (PORT datad (343:343:343) (356:356:356)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (981:981:981)) + (PORT datac (989:989:989) (1063:1063:1063)) + (PORT datad (1104:1104:1104) (1106:1106:1106)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 3ea9d90..f6a59ff 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:47:24" +// DATE "03/30/2022 14:56:19" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -30,9 +30,11 @@ module spectrum ( CLOCK_50, - LED); + LED, + GPIO_0); input CLOCK_50; output [7:0] LED; +output [33:0] GPIO_0; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -43,6 +45,40 @@ output [7:0] LED; // LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[0] => Location: PIN_D3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[1] => Location: PIN_C3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[2] => Location: PIN_A2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[3] => Location: PIN_A3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[4] => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[5] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[6] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[7] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[8] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[9] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[10] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[11] => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[12] => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[13] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[14] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[15] => Location: PIN_C6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[16] => Location: PIN_C8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[17] => Location: PIN_E6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[18] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[19] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[20] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[21] => Location: PIN_F8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[22] => Location: PIN_F9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[23] => Location: PIN_E9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[24] => Location: PIN_C9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[25] => Location: PIN_D9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[26] => Location: PIN_E11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[27] => Location: PIN_E10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[28] => Location: PIN_C11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[29] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[30] => Location: PIN_A12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[31] => Location: PIN_D11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[32] => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// GPIO_0[33] => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -69,6 +105,40 @@ wire \LED[4]~output_o ; wire \LED[5]~output_o ; wire \LED[6]~output_o ; wire \LED[7]~output_o ; +wire \GPIO_0[0]~output_o ; +wire \GPIO_0[1]~output_o ; +wire \GPIO_0[2]~output_o ; +wire \GPIO_0[3]~output_o ; +wire \GPIO_0[4]~output_o ; +wire \GPIO_0[5]~output_o ; +wire \GPIO_0[6]~output_o ; +wire \GPIO_0[7]~output_o ; +wire \GPIO_0[8]~output_o ; +wire \GPIO_0[9]~output_o ; +wire \GPIO_0[10]~output_o ; +wire \GPIO_0[11]~output_o ; +wire \GPIO_0[12]~output_o ; +wire \GPIO_0[13]~output_o ; +wire \GPIO_0[14]~output_o ; +wire \GPIO_0[15]~output_o ; +wire \GPIO_0[16]~output_o ; +wire \GPIO_0[17]~output_o ; +wire \GPIO_0[18]~output_o ; +wire \GPIO_0[19]~output_o ; +wire \GPIO_0[20]~output_o ; +wire \GPIO_0[21]~output_o ; +wire \GPIO_0[22]~output_o ; +wire \GPIO_0[23]~output_o ; +wire \GPIO_0[24]~output_o ; +wire \GPIO_0[25]~output_o ; +wire \GPIO_0[26]~output_o ; +wire \GPIO_0[27]~output_o ; +wire \GPIO_0[28]~output_o ; +wire \GPIO_0[29]~output_o ; +wire \GPIO_0[30]~output_o ; +wire \GPIO_0[31]~output_o ; +wire \GPIO_0[32]~output_o ; +wire \GPIO_0[33]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; wire \counter[0]~63_combout ; @@ -113,67 +183,200 @@ wire \counter[19]~58 ; wire \counter[20]~59_combout ; wire \counter[20]~60 ; wire \counter[21]~61_combout ; +wire \Equal0~7_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; +wire \A[0]~40_combout ; +wire \A[1]~14_combout ; wire \Equal0~6_combout ; -wire \A[0]~39_combout ; -wire \A[1]~13_combout ; -wire \A[1]~14 ; -wire \A[2]~15_combout ; -wire \A[2]~16 ; -wire \A[3]~17_combout ; -wire \A[3]~18 ; -wire \A[4]~19_combout ; -wire \A[4]~20 ; -wire \A[5]~21_combout ; -wire \A[5]~22 ; -wire \A[6]~23_combout ; -wire \A[6]~24 ; -wire \A[7]~25_combout ; -wire \A[7]~26 ; -wire \A[8]~27_combout ; -wire \A[8]~28 ; -wire \A[9]~29_combout ; -wire \A[9]~30 ; -wire \A[10]~31_combout ; -wire \A[10]~32 ; -wire \A[11]~33_combout ; -wire \A[11]~34 ; -wire \A[12]~35_combout ; -wire \A[12]~36 ; -wire \A[13]~37_combout ; +wire \A[1]~15 ; +wire \A[2]~16_combout ; +wire \A[2]~17 ; +wire \A[3]~18_combout ; +wire \A[3]~19 ; +wire \A[4]~20_combout ; +wire \A[4]~21 ; +wire \A[5]~22_combout ; +wire \A[5]~23 ; +wire \A[6]~24_combout ; +wire \A[6]~25 ; +wire \A[7]~26_combout ; +wire \A[7]~27 ; +wire \A[8]~28_combout ; +wire \A[8]~29 ; +wire \A[9]~30_combout ; +wire \A[9]~31 ; +wire \A[10]~32_combout ; +wire \A[10]~33 ; +wire \A[11]~34_combout ; +wire \A[11]~35 ; +wire \A[12]~36_combout ; +wire \A[12]~37 ; +wire \A[13]~38_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; wire \~GND~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ; +wire \A[13]~39 ; +wire \A[14]~41_combout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ; +wire \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ; wire [21:0] counter; wire [15:0] A; -wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -182,14 +385,102 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_b wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -207,9 +498,105 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +609,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +622,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -248,7 +635,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -261,7 +648,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -274,7 +661,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -287,7 +674,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -300,7 +687,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -311,6 +698,448 @@ defparam \LED[7]~output .bus_hold = "false"; defparam \LED[7]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X1_Y34_N9 +cycloneive_io_obuf \GPIO_0[0]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[0]~output .bus_hold = "false"; +defparam \GPIO_0[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y34_N2 +cycloneive_io_obuf \GPIO_0[1]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[1]~output .bus_hold = "false"; +defparam \GPIO_0[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N9 +cycloneive_io_obuf \GPIO_0[2]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[2]~output .bus_hold = "false"; +defparam \GPIO_0[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N16 +cycloneive_io_obuf \GPIO_0[3]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[3]~output .bus_hold = "false"; +defparam \GPIO_0[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \GPIO_0[4]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[4]~output .bus_hold = "false"; +defparam \GPIO_0[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y34_N2 +cycloneive_io_obuf \GPIO_0[5]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[5]~output .bus_hold = "false"; +defparam \GPIO_0[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N23 +cycloneive_io_obuf \GPIO_0[6]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[6]~output .bus_hold = "false"; +defparam \GPIO_0[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y34_N2 +cycloneive_io_obuf \GPIO_0[7]~output ( + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[7]~output .bus_hold = "false"; +defparam \GPIO_0[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N23 +cycloneive_io_obuf \GPIO_0[8]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[8]~output .bus_hold = "false"; +defparam \GPIO_0[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y34_N16 +cycloneive_io_obuf \GPIO_0[9]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[9]~output .bus_hold = "false"; +defparam \GPIO_0[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N9 +cycloneive_io_obuf \GPIO_0[10]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[10]~output .bus_hold = "false"; +defparam \GPIO_0[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N2 +cycloneive_io_obuf \GPIO_0[11]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[11]~output .bus_hold = "false"; +defparam \GPIO_0[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N2 +cycloneive_io_obuf \GPIO_0[12]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[12]~output .bus_hold = "false"; +defparam \GPIO_0[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y34_N9 +cycloneive_io_obuf \GPIO_0[13]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[13]~output .bus_hold = "false"; +defparam \GPIO_0[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N23 +cycloneive_io_obuf \GPIO_0[14]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[14]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[14]~output .bus_hold = "false"; +defparam \GPIO_0[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y34_N23 +cycloneive_io_obuf \GPIO_0[15]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[15]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[15]~output .bus_hold = "false"; +defparam \GPIO_0[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N16 +cycloneive_io_obuf \GPIO_0[16]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[16]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[16]~output .bus_hold = "false"; +defparam \GPIO_0[16]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y34_N16 +cycloneive_io_obuf \GPIO_0[17]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[17]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[17]~output .bus_hold = "false"; +defparam \GPIO_0[17]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y34_N16 +cycloneive_io_obuf \GPIO_0[18]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[18]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[18]~output .bus_hold = "false"; +defparam \GPIO_0[18]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X23_Y34_N23 +cycloneive_io_obuf \GPIO_0[19]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[19]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[19]~output .bus_hold = "false"; +defparam \GPIO_0[19]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N9 +cycloneive_io_obuf \GPIO_0[20]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[20]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[20]~output .bus_hold = "false"; +defparam \GPIO_0[20]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y34_N16 +cycloneive_io_obuf \GPIO_0[21]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[21]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[21]~output .bus_hold = "false"; +defparam \GPIO_0[21]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y34_N2 +cycloneive_io_obuf \GPIO_0[22]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[22]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[22]~output .bus_hold = "false"; +defparam \GPIO_0[22]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X29_Y34_N16 +cycloneive_io_obuf \GPIO_0[23]~output ( + .i(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[23]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[23]~output .bus_hold = "false"; +defparam \GPIO_0[23]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N2 +cycloneive_io_obuf \GPIO_0[24]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[24]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[24]~output .bus_hold = "false"; +defparam \GPIO_0[24]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X31_Y34_N9 +cycloneive_io_obuf \GPIO_0[25]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[25]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[25]~output .bus_hold = "false"; +defparam \GPIO_0[25]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N9 +cycloneive_io_obuf \GPIO_0[26]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[26]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[26]~output .bus_hold = "false"; +defparam \GPIO_0[26]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X45_Y34_N16 +cycloneive_io_obuf \GPIO_0[27]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[27]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[27]~output .bus_hold = "false"; +defparam \GPIO_0[27]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X38_Y34_N2 +cycloneive_io_obuf \GPIO_0[28]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[28]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[28]~output .bus_hold = "false"; +defparam \GPIO_0[28]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X40_Y34_N9 +cycloneive_io_obuf \GPIO_0[29]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[29]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[29]~output .bus_hold = "false"; +defparam \GPIO_0[29]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N16 +cycloneive_io_obuf \GPIO_0[30]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[30]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[30]~output .bus_hold = "false"; +defparam \GPIO_0[30]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N16 +cycloneive_io_obuf \GPIO_0[31]~output ( + .i(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[31]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[31]~output .bus_hold = "false"; +defparam \GPIO_0[31]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y34_N23 +cycloneive_io_obuf \GPIO_0[32]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[32]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[32]~output .bus_hold = "false"; +defparam \GPIO_0[32]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X43_Y34_N23 +cycloneive_io_obuf \GPIO_0[33]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\GPIO_0[33]~output_o ), + .obar()); +// synopsys translate_off +defparam \GPIO_0[33]~output .bus_hold = "false"; +defparam \GPIO_0[33]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -334,7 +1163,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 +// Location: LCCOMB_X31_Y7_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -351,7 +1180,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X31_Y7_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -370,7 +1199,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 +// Location: LCCOMB_X31_Y7_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -388,7 +1217,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N13 +// Location: FF_X31_Y7_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -407,7 +1236,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N14 +// Location: LCCOMB_X31_Y7_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -425,7 +1254,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N15 +// Location: FF_X31_Y7_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -444,7 +1273,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 +// Location: LCCOMB_X31_Y7_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -462,7 +1291,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N17 +// Location: FF_X31_Y7_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -481,7 +1310,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N18 +// Location: LCCOMB_X31_Y7_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -499,7 +1328,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N19 +// Location: FF_X31_Y7_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -518,7 +1347,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N20 +// Location: LCCOMB_X31_Y7_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -536,7 +1365,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N21 +// Location: FF_X31_Y7_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -555,7 +1384,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N22 +// Location: LCCOMB_X31_Y7_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -573,7 +1402,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N23 +// Location: FF_X31_Y7_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -592,7 +1421,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 +// Location: LCCOMB_X31_Y7_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -610,7 +1439,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N25 +// Location: FF_X31_Y7_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -629,7 +1458,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 +// Location: LCCOMB_X31_Y7_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -647,7 +1476,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N27 +// Location: FF_X31_Y7_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -666,7 +1495,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N28 +// Location: LCCOMB_X31_Y7_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -684,7 +1513,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N29 +// Location: FF_X31_Y7_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -703,7 +1532,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 +// Location: LCCOMB_X31_Y7_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -721,7 +1550,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y14_N31 +// Location: FF_X31_Y7_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -740,7 +1569,7 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N0 +// Location: LCCOMB_X31_Y6_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) @@ -758,7 +1587,7 @@ defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N1 +// Location: FF_X31_Y6_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[11]~41_combout ), @@ -777,7 +1606,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N2 +// Location: LCCOMB_X31_Y6_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -795,7 +1624,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N3 +// Location: FF_X31_Y6_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -814,7 +1643,7 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N4 +// Location: LCCOMB_X31_Y6_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) @@ -832,7 +1661,7 @@ defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N5 +// Location: FF_X31_Y6_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -851,7 +1680,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N6 +// Location: LCCOMB_X31_Y6_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -869,7 +1698,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N7 +// Location: FF_X31_Y6_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -888,25 +1717,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N8 +// Location: LCCOMB_X31_Y6_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(counter[15]), - .datab(gnd), + .dataa(gnd), + .datab(counter[15]), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hA50A; +defparam \counter[15]~49 .lut_mask = 16'hC30C; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N9 +// Location: FF_X31_Y6_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -925,7 +1754,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N10 +// Location: LCCOMB_X31_Y6_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -943,7 +1772,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N11 +// Location: FF_X31_Y6_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -962,7 +1791,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N12 +// Location: LCCOMB_X31_Y6_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -980,7 +1809,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N13 +// Location: FF_X31_Y6_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -999,7 +1828,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N14 +// Location: LCCOMB_X31_Y6_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1017,7 +1846,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N15 +// Location: FF_X31_Y6_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1036,7 +1865,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 +// Location: LCCOMB_X31_Y6_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1054,7 +1883,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N17 +// Location: FF_X31_Y6_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1073,7 +1902,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N18 +// Location: LCCOMB_X31_Y6_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1091,7 +1920,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N19 +// Location: FF_X31_Y6_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1110,7 +1939,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N20 +// Location: LCCOMB_X31_Y6_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1127,7 +1956,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y13_N21 +// Location: FF_X31_Y6_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1146,7 +1975,24 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N24 +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[20] & !counter[21]) + + .dataa(counter[20]), + .datab(gnd), + .datac(counter[21]), + .datad(gnd), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0505; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N24 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): // \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) @@ -1163,7 +2009,7 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N4 +// Location: LCCOMB_X31_Y7_N4 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): // \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) @@ -1180,15 +2026,15 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 +// Location: LCCOMB_X31_Y7_N10 cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) .dataa(counter[6]), - .datab(counter[4]), - .datac(counter[7]), - .datad(counter[5]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), .cin(gnd), .combout(\Equal0~1_combout ), .cout()); @@ -1197,14 +2043,14 @@ defparam \Equal0~1 .lut_mask = 16'h0001; defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N26 +// Location: LCCOMB_X31_Y7_N8 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) +// \Equal0~2_combout = (!counter[8] & (!counter[9] & (!counter[10] & !counter[11]))) - .dataa(counter[10]), + .dataa(counter[8]), .datab(counter[9]), - .datac(counter[8]), + .datac(counter[10]), .datad(counter[11]), .cin(gnd), .combout(\Equal0~2_combout ), @@ -1214,7 +2060,7 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N30 +// Location: LCCOMB_X31_Y6_N30 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): // \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) @@ -1231,7 +2077,7 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N28 +// Location: LCCOMB_X30_Y7_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): // \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) @@ -1248,44 +2094,27 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \Equal0~6 ( +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \A[0]~40 ( // Equation(s): -// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) +// \A[0]~40_combout = A[0] $ (((\Equal0~7_combout & (\Equal0~5_combout & \Equal0~4_combout )))) - .dataa(counter[20]), - .datab(counter[21]), - .datac(\Equal0~5_combout ), + .dataa(\Equal0~7_combout ), + .datab(\Equal0~5_combout ), + .datac(A[0]), .datad(\Equal0~4_combout ), .cin(gnd), - .combout(\Equal0~6_combout ), + .combout(\A[0]~40_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h1000; -defparam \Equal0~6 .sum_lutc_input = "datac"; +defparam \A[0]~40 .lut_mask = 16'h78F0; +defparam \A[0]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \A[0]~39 ( -// Equation(s): -// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(A[0]), - .datad(\Equal0~6_combout ), - .cin(gnd), - .combout(\A[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \A[0]~39 .lut_mask = 16'h0FF0; -defparam \A[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 +// Location: FF_X31_Y7_N1 dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[0]~39_combout ), + .d(\A[0]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1301,28 +2130,45 @@ defparam \A[0] .is_wysiwyg = "true"; defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \A[1]~13 ( +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \A[1]~14 ( // Equation(s): -// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) -// \A[1]~14 = CARRY((A[1] & A[0])) +// \A[1]~14_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~15 = CARRY((A[1] & A[0])) .dataa(A[1]), .datab(A[0]), .datac(gnd), .datad(vcc), .cin(gnd), - .combout(\A[1]~13_combout ), - .cout(\A[1]~14 )); + .combout(\A[1]~14_combout ), + .cout(\A[1]~15 )); // synopsys translate_off -defparam \A[1]~13 .lut_mask = 16'h6688; -defparam \A[1]~13 .sum_lutc_input = "datac"; +defparam \A[1]~14 .lut_mask = 16'h6688; +defparam \A[1]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y14_N1 +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \Equal0~6 ( +// Equation(s): +// \Equal0~6_combout = (!counter[21] & (!counter[20] & (\Equal0~5_combout & \Equal0~4_combout ))) + + .dataa(counter[21]), + .datab(counter[20]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~6 .lut_mask = 16'h1000; +defparam \Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N1 dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[1]~13_combout ), + .d(\A[1]~14_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1338,28 +2184,28 @@ defparam \A[1] .is_wysiwyg = "true"; defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \A[2]~15 ( +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \A[2]~16 ( // Equation(s): -// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) -// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) +// \A[2]~16_combout = (A[2] & (!\A[1]~15 )) # (!A[2] & ((\A[1]~15 ) # (GND))) +// \A[2]~17 = CARRY((!\A[1]~15 ) # (!A[2])) .dataa(gnd), .datab(A[2]), .datac(gnd), .datad(vcc), - .cin(\A[1]~14 ), - .combout(\A[2]~15_combout ), - .cout(\A[2]~16 )); + .cin(\A[1]~15 ), + .combout(\A[2]~16_combout ), + .cout(\A[2]~17 )); // synopsys translate_off -defparam \A[2]~15 .lut_mask = 16'h3C3F; -defparam \A[2]~15 .sum_lutc_input = "cin"; +defparam \A[2]~16 .lut_mask = 16'h3C3F; +defparam \A[2]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N3 +// Location: FF_X30_Y7_N3 dffeas \A[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[2]~15_combout ), + .d(\A[2]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1375,28 +2221,28 @@ defparam \A[2] .is_wysiwyg = "true"; defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \A[3]~17 ( +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \A[3]~18 ( // Equation(s): -// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) -// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) +// \A[3]~18_combout = (A[3] & (\A[2]~17 $ (GND))) # (!A[3] & (!\A[2]~17 & VCC)) +// \A[3]~19 = CARRY((A[3] & !\A[2]~17 )) .dataa(gnd), .datab(A[3]), .datac(gnd), .datad(vcc), - .cin(\A[2]~16 ), - .combout(\A[3]~17_combout ), - .cout(\A[3]~18 )); + .cin(\A[2]~17 ), + .combout(\A[3]~18_combout ), + .cout(\A[3]~19 )); // synopsys translate_off -defparam \A[3]~17 .lut_mask = 16'hC30C; -defparam \A[3]~17 .sum_lutc_input = "cin"; +defparam \A[3]~18 .lut_mask = 16'hC30C; +defparam \A[3]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N5 +// Location: FF_X30_Y7_N5 dffeas \A[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[3]~17_combout ), + .d(\A[3]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1412,28 +2258,28 @@ defparam \A[3] .is_wysiwyg = "true"; defparam \A[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \A[4]~19 ( +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \A[4]~20 ( // Equation(s): -// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) -// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) +// \A[4]~20_combout = (A[4] & (!\A[3]~19 )) # (!A[4] & ((\A[3]~19 ) # (GND))) +// \A[4]~21 = CARRY((!\A[3]~19 ) # (!A[4])) .dataa(A[4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[3]~18 ), - .combout(\A[4]~19_combout ), - .cout(\A[4]~20 )); + .cin(\A[3]~19 ), + .combout(\A[4]~20_combout ), + .cout(\A[4]~21 )); // synopsys translate_off -defparam \A[4]~19 .lut_mask = 16'h5A5F; -defparam \A[4]~19 .sum_lutc_input = "cin"; +defparam \A[4]~20 .lut_mask = 16'h5A5F; +defparam \A[4]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N7 +// Location: FF_X30_Y7_N7 dffeas \A[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[4]~19_combout ), + .d(\A[4]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1449,28 +2295,28 @@ defparam \A[4] .is_wysiwyg = "true"; defparam \A[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \A[5]~21 ( +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \A[5]~22 ( // Equation(s): -// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) -// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) +// \A[5]~22_combout = (A[5] & (\A[4]~21 $ (GND))) # (!A[5] & (!\A[4]~21 & VCC)) +// \A[5]~23 = CARRY((A[5] & !\A[4]~21 )) .dataa(gnd), .datab(A[5]), .datac(gnd), .datad(vcc), - .cin(\A[4]~20 ), - .combout(\A[5]~21_combout ), - .cout(\A[5]~22 )); + .cin(\A[4]~21 ), + .combout(\A[5]~22_combout ), + .cout(\A[5]~23 )); // synopsys translate_off -defparam \A[5]~21 .lut_mask = 16'hC30C; -defparam \A[5]~21 .sum_lutc_input = "cin"; +defparam \A[5]~22 .lut_mask = 16'hC30C; +defparam \A[5]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N9 +// Location: FF_X30_Y7_N9 dffeas \A[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[5]~21_combout ), + .d(\A[5]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1486,28 +2332,28 @@ defparam \A[5] .is_wysiwyg = "true"; defparam \A[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \A[6]~23 ( +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \A[6]~24 ( // Equation(s): -// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) -// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) +// \A[6]~24_combout = (A[6] & (!\A[5]~23 )) # (!A[6] & ((\A[5]~23 ) # (GND))) +// \A[6]~25 = CARRY((!\A[5]~23 ) # (!A[6])) .dataa(A[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[5]~22 ), - .combout(\A[6]~23_combout ), - .cout(\A[6]~24 )); + .cin(\A[5]~23 ), + .combout(\A[6]~24_combout ), + .cout(\A[6]~25 )); // synopsys translate_off -defparam \A[6]~23 .lut_mask = 16'h5A5F; -defparam \A[6]~23 .sum_lutc_input = "cin"; +defparam \A[6]~24 .lut_mask = 16'h5A5F; +defparam \A[6]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N11 +// Location: FF_X30_Y7_N11 dffeas \A[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[6]~23_combout ), + .d(\A[6]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1523,28 +2369,28 @@ defparam \A[6] .is_wysiwyg = "true"; defparam \A[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \A[7]~25 ( +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \A[7]~26 ( // Equation(s): -// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) -// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) +// \A[7]~26_combout = (A[7] & (\A[6]~25 $ (GND))) # (!A[7] & (!\A[6]~25 & VCC)) +// \A[7]~27 = CARRY((A[7] & !\A[6]~25 )) .dataa(A[7]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[6]~24 ), - .combout(\A[7]~25_combout ), - .cout(\A[7]~26 )); + .cin(\A[6]~25 ), + .combout(\A[7]~26_combout ), + .cout(\A[7]~27 )); // synopsys translate_off -defparam \A[7]~25 .lut_mask = 16'hA50A; -defparam \A[7]~25 .sum_lutc_input = "cin"; +defparam \A[7]~26 .lut_mask = 16'hA50A; +defparam \A[7]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N13 +// Location: FF_X30_Y7_N13 dffeas \A[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[7]~25_combout ), + .d(\A[7]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1560,28 +2406,28 @@ defparam \A[7] .is_wysiwyg = "true"; defparam \A[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \A[8]~27 ( +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \A[8]~28 ( // Equation(s): -// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) -// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) +// \A[8]~28_combout = (A[8] & (!\A[7]~27 )) # (!A[8] & ((\A[7]~27 ) # (GND))) +// \A[8]~29 = CARRY((!\A[7]~27 ) # (!A[8])) - .dataa(A[8]), - .datab(gnd), + .dataa(gnd), + .datab(A[8]), .datac(gnd), .datad(vcc), - .cin(\A[7]~26 ), - .combout(\A[8]~27_combout ), - .cout(\A[8]~28 )); + .cin(\A[7]~27 ), + .combout(\A[8]~28_combout ), + .cout(\A[8]~29 )); // synopsys translate_off -defparam \A[8]~27 .lut_mask = 16'h5A5F; -defparam \A[8]~27 .sum_lutc_input = "cin"; +defparam \A[8]~28 .lut_mask = 16'h3C3F; +defparam \A[8]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N15 +// Location: FF_X30_Y7_N15 dffeas \A[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[8]~27_combout ), + .d(\A[8]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1597,28 +2443,28 @@ defparam \A[8] .is_wysiwyg = "true"; defparam \A[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \A[9]~29 ( +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \A[9]~30 ( // Equation(s): -// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) -// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) +// \A[9]~30_combout = (A[9] & (\A[8]~29 $ (GND))) # (!A[9] & (!\A[8]~29 & VCC)) +// \A[9]~31 = CARRY((A[9] & !\A[8]~29 )) .dataa(gnd), .datab(A[9]), .datac(gnd), .datad(vcc), - .cin(\A[8]~28 ), - .combout(\A[9]~29_combout ), - .cout(\A[9]~30 )); + .cin(\A[8]~29 ), + .combout(\A[9]~30_combout ), + .cout(\A[9]~31 )); // synopsys translate_off -defparam \A[9]~29 .lut_mask = 16'hC30C; -defparam \A[9]~29 .sum_lutc_input = "cin"; +defparam \A[9]~30 .lut_mask = 16'hC30C; +defparam \A[9]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N17 +// Location: FF_X30_Y7_N17 dffeas \A[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[9]~29_combout ), + .d(\A[9]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1634,28 +2480,28 @@ defparam \A[9] .is_wysiwyg = "true"; defparam \A[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \A[10]~31 ( +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \A[10]~32 ( // Equation(s): -// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) -// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) +// \A[10]~32_combout = (A[10] & (!\A[9]~31 )) # (!A[10] & ((\A[9]~31 ) # (GND))) +// \A[10]~33 = CARRY((!\A[9]~31 ) # (!A[10])) .dataa(gnd), .datab(A[10]), .datac(gnd), .datad(vcc), - .cin(\A[9]~30 ), - .combout(\A[10]~31_combout ), - .cout(\A[10]~32 )); + .cin(\A[9]~31 ), + .combout(\A[10]~32_combout ), + .cout(\A[10]~33 )); // synopsys translate_off -defparam \A[10]~31 .lut_mask = 16'h3C3F; -defparam \A[10]~31 .sum_lutc_input = "cin"; +defparam \A[10]~32 .lut_mask = 16'h3C3F; +defparam \A[10]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N19 +// Location: FF_X30_Y7_N19 dffeas \A[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[10]~31_combout ), + .d(\A[10]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1671,28 +2517,28 @@ defparam \A[10] .is_wysiwyg = "true"; defparam \A[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \A[11]~33 ( +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \A[11]~34 ( // Equation(s): -// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) -// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) +// \A[11]~34_combout = (A[11] & (\A[10]~33 $ (GND))) # (!A[11] & (!\A[10]~33 & VCC)) +// \A[11]~35 = CARRY((A[11] & !\A[10]~33 )) .dataa(gnd), .datab(A[11]), .datac(gnd), .datad(vcc), - .cin(\A[10]~32 ), - .combout(\A[11]~33_combout ), - .cout(\A[11]~34 )); + .cin(\A[10]~33 ), + .combout(\A[11]~34_combout ), + .cout(\A[11]~35 )); // synopsys translate_off -defparam \A[11]~33 .lut_mask = 16'hC30C; -defparam \A[11]~33 .sum_lutc_input = "cin"; +defparam \A[11]~34 .lut_mask = 16'hC30C; +defparam \A[11]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N21 +// Location: FF_X30_Y7_N21 dffeas \A[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[11]~33_combout ), + .d(\A[11]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1708,28 +2554,28 @@ defparam \A[11] .is_wysiwyg = "true"; defparam \A[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \A[12]~35 ( +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \A[12]~36 ( // Equation(s): -// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) -// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) +// \A[12]~36_combout = (A[12] & (!\A[11]~35 )) # (!A[12] & ((\A[11]~35 ) # (GND))) +// \A[12]~37 = CARRY((!\A[11]~35 ) # (!A[12])) .dataa(A[12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\A[11]~34 ), - .combout(\A[12]~35_combout ), - .cout(\A[12]~36 )); + .cin(\A[11]~35 ), + .combout(\A[12]~36_combout ), + .cout(\A[12]~37 )); // synopsys translate_off -defparam \A[12]~35 .lut_mask = 16'h5A5F; -defparam \A[12]~35 .sum_lutc_input = "cin"; +defparam \A[12]~36 .lut_mask = 16'h5A5F; +defparam \A[12]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N23 +// Location: FF_X30_Y7_N23 dffeas \A[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[12]~35_combout ), + .d(\A[12]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1745,27 +2591,28 @@ defparam \A[12] .is_wysiwyg = "true"; defparam \A[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \A[13]~37 ( +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \A[13]~38 ( // Equation(s): -// \A[13]~37_combout = \A[12]~36 $ (!A[13]) +// \A[13]~38_combout = (A[13] & (\A[12]~37 $ (GND))) # (!A[13] & (!\A[12]~37 & VCC)) +// \A[13]~39 = CARRY((A[13] & !\A[12]~37 )) .dataa(gnd), - .datab(gnd), + .datab(A[13]), .datac(gnd), - .datad(A[13]), - .cin(\A[12]~36 ), - .combout(\A[13]~37_combout ), - .cout()); + .datad(vcc), + .cin(\A[12]~37 ), + .combout(\A[13]~38_combout ), + .cout(\A[13]~39 )); // synopsys translate_off -defparam \A[13]~37 .lut_mask = 16'hF00F; -defparam \A[13]~37 .sum_lutc_input = "cin"; +defparam \A[13]~38 .lut_mask = 16'hC30C; +defparam \A[13]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y14_N25 +// Location: FF_X30_Y7_N25 dffeas \A[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\A[13]~37_combout ), + .d(\A[13]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1781,301 +2628,8 @@ defparam \A[13] .is_wysiwyg = "true"; defparam \A[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(gnd), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(vcc), - .ena1(!A[13]), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\~GND~combout }), - .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2098,39 +2652,1216 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X32_Y26_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N3 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y26_N5 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y28_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X21_Y31_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y28_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .lut_mask = 16'hFA50; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N18 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .lut_mask = 16'hFC0C; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y24_N26 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -2186,97 +3917,81 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] - - .dataa(gnd), - .datab(gnd), - .datac(A[13]), - .datad(gnd), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X27_Y14_N16 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - .dataa(gnd), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datab(gnd), - .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y14_N17 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2332,7 +4047,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y21_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2388,25 +4103,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X21_Y28_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hAAF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2462,7 +4177,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y15_N0 +// Location: M9K_X22_Y12_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -2518,81 +4233,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hFA0A; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(A[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 +// Location: M9K_X22_Y27_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(vcc), .portare(vcc), @@ -2648,22 +4307,3086 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X21_Y27_N30 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y26_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y29_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(gnd), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .lut_mask = 16'hF5A0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \A[14]~41 ( +// Equation(s): +// \A[14]~41_combout = A[14] $ (\A[13]~39 ) + + .dataa(A[14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\A[13]~39 ), + .combout(\A[14]~41_combout ), + .cout()); +// synopsys translate_off +defparam \A[14]~41 .lut_mask = 16'h5A5A; +defparam \A[14]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X30_Y7_N27 +dffeas \A[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[14]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[14]), + .prn(vcc)); +// synopsys translate_off +defparam \A[14] .is_wysiwyg = "true"; +defparam \A[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00F0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout = (A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .lut_mask = 16'hF000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2] = (!A[14] & !A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .lut_mask = 16'h000F; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout = (!A[14] & A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(A[14]), + .datad(A[13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .lut_mask = 16'h0F00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout = A[14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N1 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hAAE4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .lut_mask = 16'hF2C2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hB9A8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hE2CC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hEE50; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(gnd), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\~GND~combout }), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hE6A2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .lut_mask = 16'hAFA0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .lut_mask = 16'hEE22; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N14 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 )) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .lut_mask = 16'hFC30; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .lut_mask = 16'hCFC0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .lut_mask = 16'hF3C0; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 )) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .lut_mask = 16'hFA0A; +defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; @@ -2682,4 +7405,72 @@ assign LED[6] = \LED[6]~output_o ; assign LED[7] = \LED[7]~output_o ; +assign GPIO_0[0] = \GPIO_0[0]~output_o ; + +assign GPIO_0[1] = \GPIO_0[1]~output_o ; + +assign GPIO_0[2] = \GPIO_0[2]~output_o ; + +assign GPIO_0[3] = \GPIO_0[3]~output_o ; + +assign GPIO_0[4] = \GPIO_0[4]~output_o ; + +assign GPIO_0[5] = \GPIO_0[5]~output_o ; + +assign GPIO_0[6] = \GPIO_0[6]~output_o ; + +assign GPIO_0[7] = \GPIO_0[7]~output_o ; + +assign GPIO_0[8] = \GPIO_0[8]~output_o ; + +assign GPIO_0[9] = \GPIO_0[9]~output_o ; + +assign GPIO_0[10] = \GPIO_0[10]~output_o ; + +assign GPIO_0[11] = \GPIO_0[11]~output_o ; + +assign GPIO_0[12] = \GPIO_0[12]~output_o ; + +assign GPIO_0[13] = \GPIO_0[13]~output_o ; + +assign GPIO_0[14] = \GPIO_0[14]~output_o ; + +assign GPIO_0[15] = \GPIO_0[15]~output_o ; + +assign GPIO_0[16] = \GPIO_0[16]~output_o ; + +assign GPIO_0[17] = \GPIO_0[17]~output_o ; + +assign GPIO_0[18] = \GPIO_0[18]~output_o ; + +assign GPIO_0[19] = \GPIO_0[19]~output_o ; + +assign GPIO_0[20] = \GPIO_0[20]~output_o ; + +assign GPIO_0[21] = \GPIO_0[21]~output_o ; + +assign GPIO_0[22] = \GPIO_0[22]~output_o ; + +assign GPIO_0[23] = \GPIO_0[23]~output_o ; + +assign GPIO_0[24] = \GPIO_0[24]~output_o ; + +assign GPIO_0[25] = \GPIO_0[25]~output_o ; + +assign GPIO_0[26] = \GPIO_0[26]~output_o ; + +assign GPIO_0[27] = \GPIO_0[27]~output_o ; + +assign GPIO_0[28] = \GPIO_0[28]~output_o ; + +assign GPIO_0[29] = \GPIO_0[29]~output_o ; + +assign GPIO_0[30] = \GPIO_0[30]~output_o ; + +assign GPIO_0[31] = \GPIO_0[31]~output_o ; + +assign GPIO_0[32] = \GPIO_0[32]~output_o ; + +assign GPIO_0[33] = \GPIO_0[33]~output_o ; + endmodule diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index dc41597..211415e 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:47:24") + (DATE "03/30/2022 14:56:19") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1434:1434:1434)) + (PORT i (593:593:593) (669:669:669)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1564:1564:1564) (1750:1750:1750)) + (PORT i (1090:1090:1090) (1238:1238:1238)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1536:1536:1536) (1717:1717:1717)) + (PORT i (855:855:855) (953:953:953)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1057:1057:1057) (1192:1192:1192)) + (PORT i (1488:1488:1488) (1725:1725:1725)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1350:1350:1350) (1544:1544:1544)) + (PORT i (723:723:723) (829:829:829)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1115:1115:1115) (1270:1270:1270)) + (PORT i (721:721:721) (827:827:827)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1307:1307:1307) (1471:1471:1471)) + (PORT i (907:907:907) (1028:1028:1028)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) ) ) @@ -111,11 +111,331 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (694:694:694) (773:773:773)) + (PORT i (851:851:851) (982:982:982)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (799:799:799) (903:903:903)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (833:833:833) (940:940:940)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (570:570:570) (639:639:639)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1156:1156:1156) (1312:1312:1312)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (760:760:760) (855:855:855)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (699:699:699) (780:780:780)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (923:923:923) (1040:1040:1040)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (688:688:688) (764:764:764)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1023:1023:1023) (1157:1157:1157)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (808:808:808) (937:937:937)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (528:528:528) (587:587:587)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (732:732:732) (830:830:830)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (607:607:607) (680:680:680)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (742:742:742) (847:847:847)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (975:975:975) (1083:1083:1083)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (908:908:908) (1030:1030:1030)) + (IOPATH i o (3177:3177:3177) (2883:2883:2883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[16\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1396:1396:1396) (1569:1569:1569)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[17\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1313:1313:1313) (1488:1488:1488)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[18\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1534:1534:1534) (1750:1750:1750)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[19\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1087:1087:1087) (1219:1219:1219)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[20\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1066:1066:1066) (1206:1206:1206)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[21\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1260:1260:1260) (1419:1419:1419)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[22\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1102:1102:1102) (1228:1228:1228)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[23\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1248:1248:1248) (1395:1395:1395)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[24\]\~output) + (DELAY + (ABSOLUTE + (PORT i (469:469:469) (531:531:531)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[25\]\~output) + (DELAY + (ABSOLUTE + (PORT i (450:450:450) (503:503:503)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[26\]\~output) + (DELAY + (ABSOLUTE + (PORT i (641:641:641) (703:703:703)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[27\]\~output) + (DELAY + (ABSOLUTE + (PORT i (575:575:575) (644:644:644)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[28\]\~output) + (DELAY + (ABSOLUTE + (PORT i (550:550:550) (608:608:608)) + (IOPATH i o (3177:3177:3177) (2883:2883:2883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[29\]\~output) + (DELAY + (ABSOLUTE + (PORT i (542:542:542) (598:598:598)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[30\]\~output) + (DELAY + (ABSOLUTE + (PORT i (796:796:796) (885:885:885)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[31\]\~output) + (DELAY + (ABSOLUTE + (PORT i (779:779:779) (861:861:861)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -148,7 +468,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -177,7 +497,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -205,7 +525,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -233,7 +553,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -247,7 +567,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) + (PORT datab (134:134:134) (183:183:183)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -261,7 +581,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -275,7 +595,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (182:182:182)) + (PORT datab (142:142:142) (189:189:189)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -289,7 +609,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -317,7 +637,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -331,7 +651,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (189:189:189)) + (PORT datab (134:134:134) (183:183:183)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -345,7 +665,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -359,7 +679,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (193:193:193)) + (PORT dataa (135:135:135) (188:188:188)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -373,7 +693,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -387,7 +707,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (141:141:141) (189:189:189)) + (PORT datab (133:133:133) (183:183:183)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -401,7 +721,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -415,7 +735,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (141:141:141) (192:192:192)) + (PORT dataa (133:133:133) (186:186:186)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -429,7 +749,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -457,7 +777,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -471,7 +791,7 @@ (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (182:182:182)) + (PORT datab (213:213:213) (265:265:265)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -485,7 +805,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -513,7 +833,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -541,7 +861,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -555,9 +875,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (270:270:270)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -569,7 +889,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -597,7 +917,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -625,7 +945,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -653,7 +973,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -681,7 +1001,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -709,7 +1029,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -734,7 +1054,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT clk (908:908:908) (912:912:912)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -743,6 +1063,18 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (459:459:459)) + (PORT datac (371:371:371) (449:449:449)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) @@ -781,9 +1113,9 @@ (DELAY (ABSOLUTE (PORT dataa (137:137:137) (191:191:191)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (200:200:200) (246:246:246)) - (PORT datad (123:123:123) (162:162:162)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datac (200:200:200) (245:245:245)) + (PORT datad (122:122:122) (162:162:162)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -796,10 +1128,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (289:289:289)) - (PORT datab (213:213:213) (270:270:270)) - (PORT datac (296:296:296) (349:349:349)) - (PORT datad (300:300:300) (354:354:354)) + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (202:202:202) (246:246:246)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -813,9 +1145,9 @@ (DELAY (ABSOLUTE (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (144:144:144) (193:193:193)) + (PORT datab (138:138:138) (188:188:188)) (PORT datac (131:131:131) (173:173:173)) - (PORT datad (125:125:125) (165:165:165)) + (PORT datad (132:132:132) (170:170:170)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -829,9 +1161,9 @@ (DELAY (ABSOLUTE (PORT dataa (197:197:197) (238:238:238)) - (PORT datab (177:177:177) (218:218:218)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (336:336:336) (394:394:394)) + (PORT datab (180:180:180) (221:221:221)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (325:325:325) (379:379:379)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -841,26 +1173,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~6) + (INSTANCE A\[0\]\~40) (DELAY (ABSOLUTE - (PORT dataa (472:472:472) (559:559:559)) - (PORT datab (488:488:488) (576:576:576)) - (PORT datac (327:327:327) (384:384:384)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT datad (172:172:172) (198:198:198)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (336:336:336) (393:393:393)) + (PORT datad (185:185:185) (214:214:214)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -871,7 +1191,7 @@ (INSTANCE A\[0\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -882,11 +1202,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[1\]\~13) + (INSTANCE A\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (295:295:295)) - (PORT datab (320:320:320) (389:389:389)) + (PORT dataa (238:238:238) (301:301:301)) + (PORT datab (231:231:231) (296:296:296)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -895,14 +1215,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (564:564:564)) + (PORT datab (363:363:363) (441:441:441)) + (PORT datac (307:307:307) (359:359:359)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE A\[1\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -913,7 +1249,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[2\]\~15) + (INSTANCE A\[2\]\~16) (DELAY (ABSOLUTE (PORT datab (141:141:141) (189:189:189)) @@ -930,9 +1266,9 @@ (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -943,7 +1279,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[3\]\~17) + (INSTANCE A\[3\]\~18) (DELAY (ABSOLUTE (PORT datab (141:141:141) (190:190:190)) @@ -960,9 +1296,9 @@ (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -973,7 +1309,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[4\]\~19) + (INSTANCE A\[4\]\~20) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -990,9 +1326,9 @@ (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (430:430:430) (463:463:463)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1003,10 +1339,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[5\]\~21) + (INSTANCE A\[5\]\~22) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) + (PORT datab (154:154:154) (201:201:201)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1020,9 +1356,9 @@ (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1033,10 +1369,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[6\]\~23) + (INSTANCE A\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) + (PORT dataa (155:155:155) (205:205:205)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1050,9 +1386,9 @@ (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1063,10 +1399,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[7\]\~25) + (INSTANCE A\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) + (PORT dataa (155:155:155) (204:204:204)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1080,9 +1416,9 @@ (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1093,12 +1429,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[8\]\~27) + (INSTANCE A\[8\]\~28) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (271:271:271)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -1110,9 +1446,9 @@ (INSTANCE A\[8\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1123,10 +1459,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[9\]\~29) + (INSTANCE A\[9\]\~30) (DELAY (ABSOLUTE - (PORT datab (154:154:154) (202:202:202)) + (PORT datab (142:142:142) (190:190:190)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1140,9 +1476,9 @@ (INSTANCE A\[9\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1153,7 +1489,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[10\]\~31) + (INSTANCE A\[10\]\~32) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -1170,9 +1506,9 @@ (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1183,10 +1519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[11\]\~33) + (INSTANCE A\[11\]\~34) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) + (PORT datab (155:155:155) (202:202:202)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1200,9 +1536,9 @@ (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1213,7 +1549,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[12\]\~35) + (INSTANCE A\[12\]\~36) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -1230,9 +1566,9 @@ (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (1104:1104:1104) (1133:1133:1133)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (415:415:415) (438:438:438)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1243,12 +1579,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[13\]\~37) + (INSTANCE A\[13\]\~38) (DELAY (ABSOLUTE - (PORT datad (141:141:141) (177:177:177)) + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) @@ -1257,9 +1596,9 @@ (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (442:442:442)) + (PORT ena (430:430:430) (463:463:463)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1270,10 +1609,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (575:575:575) (672:672:672)) + (PORT d[0] (1192:1192:1192) (1412:1412:1412)) + (PORT d[1] (1138:1138:1138) (1353:1353:1353)) + (PORT d[2] (1044:1044:1044) (1226:1226:1226)) + (PORT d[3] (1415:1415:1415) (1648:1648:1648)) + (PORT d[4] (1258:1258:1258) (1477:1477:1477)) + (PORT d[5] (1215:1215:1215) (1410:1410:1410)) + (PORT d[6] (1211:1211:1211) (1418:1418:1418)) + (PORT d[7] (1193:1193:1193) (1406:1406:1406)) + (PORT d[8] (1316:1316:1316) (1533:1533:1533)) + (PORT d[9] (1224:1224:1224) (1442:1442:1442)) + (PORT d[10] (1311:1311:1311) (1559:1559:1559)) + (PORT d[11] (1306:1306:1306) (1521:1521:1521)) + (PORT d[12] (1339:1339:1339) (1574:1574:1574)) (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) @@ -1283,51 +1634,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (590:590:590) (696:696:696)) - (PORT d[1] (817:817:817) (948:948:948)) - (PORT d[2] (530:530:530) (622:622:622)) - (PORT d[3] (567:567:567) (666:666:666)) - (PORT d[4] (567:567:567) (666:666:666)) - (PORT d[5] (440:440:440) (515:515:515)) - (PORT d[6] (440:440:440) (515:515:515)) - (PORT d[7] (440:440:440) (515:515:515)) - (PORT d[8] (440:440:440) (515:515:515)) - (PORT d[9] (440:440:440) (515:515:515)) - (PORT d[10] (440:440:440) (515:515:515)) - (PORT d[11] (440:440:440) (515:515:515)) - (PORT d[12] (440:440:440) (515:515:515)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1041:1041:1041) (1194:1194:1194)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) @@ -1335,32 +1652,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1051:1051:1051) (1070:1070:1070)) + (PORT clk (1078:1078:1078) (1094:1094:1094)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -1371,673 +1668,108 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (579:579:579) (676:676:676)) - (PORT clk (1056:1056:1056) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (581:581:581) (685:685:685)) - (PORT d[1] (818:818:818) (948:948:948)) - (PORT d[2] (541:541:541) (634:634:634)) - (PORT d[3] (677:677:677) (784:784:784)) - (PORT d[4] (537:537:537) (629:629:629)) - (PORT d[5] (882:882:882) (1013:1013:1013)) - (PORT d[6] (689:689:689) (790:790:790)) - (PORT d[7] (709:709:709) (819:819:819)) - (PORT d[8] (674:674:674) (787:787:787)) - (PORT d[9] (692:692:692) (792:792:792)) - (PORT d[10] (701:701:701) (805:805:805)) - (PORT d[11] (685:685:685) (787:787:787)) - (PORT d[12] (719:719:719) (829:829:829)) - (PORT clk (1053:1053:1053) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (PORT d[0] (542:542:542) (498:498:498)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + (PORT clk (619:619:619) (627:627:627)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT d[0] (564:564:564) (651:651:651)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT datac (922:922:922) (1074:1074:1074)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT d[0] (587:587:587) (692:692:692)) - (PORT d[1] (673:673:673) (782:782:782)) - (PORT d[2] (535:535:535) (629:629:629)) - (PORT d[3] (576:576:576) (669:669:669)) - (PORT d[4] (576:576:576) (669:669:669)) - (PORT d[5] (461:461:461) (543:543:543)) - (PORT d[6] (461:461:461) (543:543:543)) - (PORT d[7] (461:461:461) (543:543:543)) - (PORT d[8] (461:461:461) (543:543:543)) - (PORT d[9] (461:461:461) (543:543:543)) - (PORT d[10] (461:461:461) (543:543:543)) - (PORT d[11] (461:461:461) (543:543:543)) - (PORT d[12] (461:461:461) (543:543:543)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (568:568:568) (655:655:655)) - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (599:599:599) (705:705:705)) - (PORT d[1] (536:536:536) (629:629:629)) - (PORT d[2] (711:711:711) (827:827:827)) - (PORT d[3] (679:679:679) (777:777:777)) - (PORT d[4] (529:529:529) (615:615:615)) - (PORT d[5] (871:871:871) (1002:1002:1002)) - (PORT d[6] (708:708:708) (816:816:816)) - (PORT d[7] (714:714:714) (824:824:824)) - (PORT d[8] (809:809:809) (929:929:929)) - (PORT d[9] (698:698:698) (799:799:799)) - (PORT d[10] (710:710:710) (818:818:818)) - (PORT d[11] (692:692:692) (794:794:794)) - (PORT d[12] (713:713:713) (817:817:817)) - (PORT clk (1051:1051:1051) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (PORT d[0] (549:549:549) (504:504:504)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (749:749:749) (870:870:870)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (590:590:590) (703:703:703)) - (PORT d[1] (511:511:511) (605:605:605)) - (PORT d[2] (843:843:843) (978:978:978)) - (PORT d[3] (749:749:749) (871:871:871)) - (PORT d[4] (749:749:749) (871:871:871)) - (PORT d[5] (426:426:426) (499:499:499)) - (PORT d[6] (426:426:426) (499:499:499)) - (PORT d[7] (426:426:426) (499:499:499)) - (PORT d[8] (426:426:426) (499:499:499)) - (PORT d[9] (426:426:426) (499:499:499)) - (PORT d[10] (426:426:426) (499:499:499)) - (PORT d[11] (426:426:426) (499:499:499)) - (PORT d[12] (426:426:426) (499:499:499)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (753:753:753) (874:874:874)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (581:581:581) (689:689:689)) - (PORT d[1] (829:829:829) (959:959:959)) - (PORT d[2] (505:505:505) (587:587:587)) - (PORT d[3] (808:808:808) (929:929:929)) - (PORT d[4] (517:517:517) (601:601:601)) - (PORT d[5] (584:584:584) (688:688:688)) - (PORT d[6] (687:687:687) (792:792:792)) - (PORT d[7] (579:579:579) (678:678:678)) - (PORT d[8] (830:830:830) (959:959:959)) - (PORT d[9] (693:693:693) (797:797:797)) - (PORT d[10] (688:688:688) (792:792:792)) - (PORT d[11] (686:686:686) (792:792:792)) - (PORT d[12] (694:694:694) (796:796:796)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - (PORT d[0] (528:528:528) (485:485:485)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (760:760:760) (881:881:881)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (420:420:420) (491:491:491)) - (PORT d[1] (350:350:350) (416:416:416)) - (PORT d[2] (851:851:851) (986:986:986)) - (PORT d[3] (362:362:362) (421:421:421)) - (PORT d[4] (362:362:362) (421:421:421)) - (PORT d[5] (263:263:263) (312:312:312)) - (PORT d[6] (263:263:263) (312:312:312)) - (PORT d[7] (263:263:263) (312:312:312)) - (PORT d[8] (263:263:263) (312:312:312)) - (PORT d[9] (263:263:263) (312:312:312)) - (PORT d[10] (263:263:263) (312:312:312)) - (PORT d[11] (263:263:263) (312:312:312)) - (PORT d[12] (263:263:263) (312:312:312)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (764:764:764) (885:885:885)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (408:408:408) (481:481:481)) - (PORT d[1] (845:845:845) (980:980:980)) - (PORT d[2] (851:851:851) (985:985:985)) - (PORT d[3] (360:360:360) (420:420:420)) - (PORT d[4] (363:363:363) (426:426:426)) - (PORT d[5] (397:397:397) (470:470:470)) - (PORT d[6] (422:422:422) (497:497:497)) - (PORT d[7] (416:416:416) (491:491:491)) - (PORT d[8] (853:853:853) (987:987:987)) - (PORT d[9] (417:417:417) (487:487:487)) - (PORT d[10] (536:536:536) (626:626:626)) - (PORT d[11] (407:407:407) (476:476:476)) - (PORT d[12] (520:520:520) (600:600:600)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - (PORT d[0] (367:367:367) (342:342:342)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (890:890:890) (1046:1046:1046)) - (PORT d[1] (707:707:707) (833:833:833)) - (PORT d[2] (698:698:698) (814:814:814)) - (PORT d[3] (700:700:700) (816:816:816)) - (PORT d[4] (716:716:716) (835:835:835)) - (PORT d[5] (893:893:893) (1047:1047:1047)) - (PORT d[6] (685:685:685) (805:805:805)) - (PORT d[7] (683:683:683) (802:802:802)) - (PORT d[8] (697:697:697) (821:821:821)) - (PORT d[9] (699:699:699) (813:813:813)) - (PORT d[10] (705:705:705) (827:827:827)) - (PORT d[11] (695:695:695) (816:816:816)) - (PORT d[12] (868:868:868) (1002:1002:1002)) + (PORT d[0] (1208:1208:1208) (1437:1437:1437)) + (PORT d[1] (1134:1134:1134) (1341:1341:1341)) + (PORT d[2] (1240:1240:1240) (1449:1449:1449)) + (PORT d[3] (1286:1286:1286) (1506:1506:1506)) + (PORT d[4] (1225:1225:1225) (1436:1436:1436)) + (PORT d[5] (1206:1206:1206) (1396:1396:1396)) + (PORT d[6] (1205:1205:1205) (1409:1409:1409)) + (PORT d[7] (1199:1199:1199) (1418:1418:1418)) + (PORT d[8] (1323:1323:1323) (1536:1536:1536)) + (PORT d[9] (1195:1195:1195) (1406:1406:1406)) + (PORT d[10] (1154:1154:1154) (1375:1375:1375)) + (PORT d[11] (1301:1301:1301) (1516:1516:1516)) + (PORT d[12] (1296:1296:1296) (1520:1520:1520)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -2047,17 +1779,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (652:652:652) (726:726:726)) + (PORT d[0] (1107:1107:1107) (981:981:981)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -2067,7 +1799,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1071:1071:1071) (1087:1087:1087)) @@ -2081,7 +1813,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -2090,7 +1822,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -2099,7 +1831,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -2109,7 +1841,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -2117,24 +1849,135 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (582:582:582)) + (PORT datab (1432:1432:1432) (1679:1679:1679)) + (PORT datac (506:506:506) (569:569:569)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1186:1186:1186) (1411:1411:1411)) + (PORT d[1] (1084:1084:1084) (1282:1282:1282)) + (PORT d[2] (1165:1165:1165) (1364:1364:1364)) + (PORT d[3] (1260:1260:1260) (1484:1484:1484)) + (PORT d[4] (1245:1245:1245) (1460:1460:1460)) + (PORT d[5] (1046:1046:1046) (1223:1223:1223)) + (PORT d[6] (1046:1046:1046) (1226:1226:1226)) + (PORT d[7] (1254:1254:1254) (1475:1475:1475)) + (PORT d[8] (978:978:978) (1152:1152:1152)) + (PORT d[9] (1262:1262:1262) (1470:1470:1470)) + (PORT d[10] (933:933:933) (1116:1116:1116)) + (PORT d[11] (1320:1320:1320) (1538:1538:1538)) + (PORT d[12] (1122:1122:1122) (1324:1324:1324)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT d[0] (1103:1103:1103) (977:977:977)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1084:1084:1084)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (741:741:741) (882:882:882)) - (PORT d[1] (710:710:710) (834:834:834)) - (PORT d[2] (710:710:710) (834:834:834)) - (PORT d[3] (737:737:737) (861:861:861)) - (PORT d[4] (737:737:737) (864:864:864)) - (PORT d[5] (885:885:885) (1039:1039:1039)) - (PORT d[6] (687:687:687) (804:804:804)) - (PORT d[7] (695:695:695) (814:814:814)) - (PORT d[8] (713:713:713) (841:841:841)) - (PORT d[9] (698:698:698) (807:807:807)) - (PORT d[10] (704:704:704) (821:821:821)) - (PORT d[11] (708:708:708) (830:830:830)) - (PORT d[12] (709:709:709) (830:830:830)) + (PORT d[0] (1186:1186:1186) (1406:1406:1406)) + (PORT d[1] (1091:1091:1091) (1296:1296:1296)) + (PORT d[2] (1235:1235:1235) (1445:1445:1445)) + (PORT d[3] (1260:1260:1260) (1479:1479:1479)) + (PORT d[4] (1232:1232:1232) (1447:1447:1447)) + (PORT d[5] (905:905:905) (1064:1064:1064)) + (PORT d[6] (1206:1206:1206) (1396:1396:1396)) + (PORT d[7] (1231:1231:1231) (1440:1440:1440)) + (PORT d[8] (1236:1236:1236) (1422:1422:1422)) + (PORT d[9] (1290:1290:1290) (1507:1507:1507)) + (PORT d[10] (947:947:947) (1130:1130:1130)) + (PORT d[11] (1263:1263:1263) (1460:1460:1460)) + (PORT d[12] (1234:1234:1234) (1462:1462:1462)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -2144,17 +1987,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1088:1088:1088) (1105:1105:1105)) - (PORT d[0] (754:754:754) (674:674:674)) + (PORT d[0] (954:954:954) (1076:1076:1076)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) @@ -2164,7 +2007,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1070:1070:1070) (1086:1086:1086)) @@ -2178,7 +2021,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -2187,7 +2030,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -2196,7 +2039,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -2204,74 +2047,2338 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (534:534:534) (619:619:619)) + (PORT datac (533:533:533) (611:611:611)) + (PORT datad (1552:1552:1552) (1817:1817:1817)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1224:1224:1224) (1454:1454:1454)) + (PORT d[1] (960:960:960) (1146:1146:1146)) + (PORT d[2] (1209:1209:1209) (1416:1416:1416)) + (PORT d[3] (1289:1289:1289) (1514:1514:1514)) + (PORT d[4] (1217:1217:1217) (1426:1426:1426)) + (PORT d[5] (1071:1071:1071) (1255:1255:1255)) + (PORT d[6] (1210:1210:1210) (1397:1397:1397)) + (PORT d[7] (1206:1206:1206) (1421:1421:1421)) + (PORT d[8] (1242:1242:1242) (1425:1425:1425)) + (PORT d[9] (1207:1207:1207) (1418:1418:1418)) + (PORT d[10] (996:996:996) (1198:1198:1198)) + (PORT d[11] (1315:1315:1315) (1532:1532:1532)) + (PORT d[12] (1264:1264:1264) (1499:1499:1499)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (1126:1126:1126) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (606:606:606) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1195:1195:1195) (1416:1416:1416)) + (PORT d[1] (1142:1142:1142) (1357:1357:1357)) + (PORT d[2] (1109:1109:1109) (1305:1305:1305)) + (PORT d[3] (1408:1408:1408) (1641:1641:1641)) + (PORT d[4] (1246:1246:1246) (1474:1474:1474)) + (PORT d[5] (1090:1090:1090) (1274:1274:1274)) + (PORT d[6] (1236:1236:1236) (1449:1449:1449)) + (PORT d[7] (1200:1200:1200) (1414:1414:1414)) + (PORT d[8] (1301:1301:1301) (1516:1516:1516)) + (PORT d[9] (1236:1236:1236) (1458:1458:1458)) + (PORT d[10] (1330:1330:1330) (1577:1577:1577)) + (PORT d[11] (1309:1309:1309) (1524:1524:1524)) + (PORT d[12] (1262:1262:1262) (1482:1482:1482)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (PORT d[0] (1087:1087:1087) (1240:1240:1240)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1117:1117:1117)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1081:1081:1081) (1097:1097:1097)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (621:621:621) (629:629:629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (633:633:633)) + (PORT datac (1367:1367:1367) (1600:1600:1600)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1209:1209:1209)) + (PORT d[1] (1109:1109:1109) (1318:1318:1318)) + (PORT d[2] (1220:1220:1220) (1430:1430:1430)) + (PORT d[3] (1258:1258:1258) (1480:1480:1480)) + (PORT d[4] (1197:1197:1197) (1385:1385:1385)) + (PORT d[5] (1081:1081:1081) (1249:1249:1249)) + (PORT d[6] (1051:1051:1051) (1213:1213:1213)) + (PORT d[7] (1051:1051:1051) (1239:1239:1239)) + (PORT d[8] (1061:1061:1061) (1222:1222:1222)) + (PORT d[9] (1099:1099:1099) (1293:1293:1293)) + (PORT d[10] (1003:1003:1003) (1205:1205:1205)) + (PORT d[11] (1063:1063:1063) (1230:1230:1230)) + (PORT d[12] (1143:1143:1143) (1325:1325:1325)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (960:960:960) (1086:1086:1086)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1145:1145:1145) (1355:1355:1355)) + (PORT d[1] (1077:1077:1077) (1274:1274:1274)) + (PORT d[2] (1228:1228:1228) (1438:1438:1438)) + (PORT d[3] (1255:1255:1255) (1474:1474:1474)) + (PORT d[4] (1223:1223:1223) (1423:1423:1423)) + (PORT d[5] (1033:1033:1033) (1207:1207:1207)) + (PORT d[6] (1034:1034:1034) (1202:1202:1202)) + (PORT d[7] (1087:1087:1087) (1283:1283:1283)) + (PORT d[8] (1078:1078:1078) (1241:1241:1241)) + (PORT d[9] (1273:1273:1273) (1486:1486:1486)) + (PORT d[10] (1224:1224:1224) (1455:1455:1455)) + (PORT d[11] (1078:1078:1078) (1244:1244:1244)) + (PORT d[12] (1209:1209:1209) (1443:1443:1443)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1104:1104:1104) (974:974:974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (475:475:475)) + (PORT datac (1090:1090:1090) (1296:1296:1296)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1249:1249:1249) (1436:1436:1436)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1192:1192:1192) (1416:1416:1416)) + (PORT d[1] (1238:1238:1238) (1442:1442:1442)) + (PORT d[2] (1268:1268:1268) (1483:1483:1483)) + (PORT d[3] (1317:1317:1317) (1536:1536:1536)) + (PORT d[4] (1248:1248:1248) (1464:1464:1464)) + (PORT d[5] (1240:1240:1240) (1440:1440:1440)) + (PORT d[6] (1206:1206:1206) (1406:1406:1406)) + (PORT d[7] (1201:1201:1201) (1420:1420:1420)) + (PORT d[8] (1335:1335:1335) (1556:1556:1556)) + (PORT d[9] (1208:1208:1208) (1422:1422:1422)) + (PORT d[10] (1171:1171:1171) (1400:1400:1400)) + (PORT d[11] (1335:1335:1335) (1558:1558:1558)) + (PORT d[12] (1333:1333:1333) (1563:1563:1563)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1246:1246:1246) (1090:1090:1090)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1253:1253:1253) (1440:1440:1440)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1183:1183:1183) (1403:1403:1403)) + (PORT d[1] (1259:1259:1259) (1469:1469:1469)) + (PORT d[2] (1220:1220:1220) (1431:1431:1431)) + (PORT d[3] (1318:1318:1318) (1536:1536:1536)) + (PORT d[4] (1258:1258:1258) (1476:1476:1476)) + (PORT d[5] (1241:1241:1241) (1440:1440:1440)) + (PORT d[6] (1207:1207:1207) (1406:1406:1406)) + (PORT d[7] (1202:1202:1202) (1420:1420:1420)) + (PORT d[8] (1336:1336:1336) (1556:1556:1556)) + (PORT d[9] (1209:1209:1209) (1422:1422:1422)) + (PORT d[10] (1172:1172:1172) (1400:1400:1400)) + (PORT d[11] (1336:1336:1336) (1558:1558:1558)) + (PORT d[12] (1334:1334:1334) (1563:1563:1563)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1246:1246:1246) (1090:1090:1090)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (2025:2025:2025)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1104:1104:1104) (1288:1288:1288)) + (PORT d[1] (1300:1300:1300) (1538:1538:1538)) + (PORT d[2] (1113:1113:1113) (1299:1299:1299)) + (PORT d[3] (1008:1008:1008) (1183:1183:1183)) + (PORT d[4] (1254:1254:1254) (1467:1467:1467)) + (PORT d[5] (912:912:912) (1074:1074:1074)) + (PORT d[6] (1026:1026:1026) (1213:1213:1213)) + (PORT d[7] (1011:1011:1011) (1192:1192:1192)) + (PORT d[8] (1099:1099:1099) (1292:1292:1292)) + (PORT d[9] (995:995:995) (1159:1159:1159)) + (PORT d[10] (975:975:975) (1149:1149:1149)) + (PORT d[11] (1135:1135:1135) (1317:1317:1317)) + (PORT d[12] (1192:1192:1192) (1396:1396:1396)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (739:739:739) (832:832:832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1079:1079:1079) (1096:1096:1096)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1780:1780:1780) (2029:2029:2029)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1111:1111:1111) (1289:1289:1289)) + (PORT d[1] (1301:1301:1301) (1538:1538:1538)) + (PORT d[2] (1093:1093:1093) (1271:1271:1271)) + (PORT d[3] (1009:1009:1009) (1183:1183:1183)) + (PORT d[4] (1272:1272:1272) (1498:1498:1498)) + (PORT d[5] (913:913:913) (1074:1074:1074)) + (PORT d[6] (1027:1027:1027) (1213:1213:1213)) + (PORT d[7] (1012:1012:1012) (1192:1192:1192)) + (PORT d[8] (1100:1100:1100) (1292:1292:1292)) + (PORT d[9] (996:996:996) (1159:1159:1159)) + (PORT d[10] (976:976:976) (1149:1149:1149)) + (PORT d[11] (1136:1136:1136) (1317:1317:1317)) + (PORT d[12] (1193:1193:1193) (1396:1396:1396)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (PORT d[0] (739:739:739) (832:832:832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1080:1080:1080) (1097:1097:1097)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1532:1532:1532) (1797:1797:1797)) + (PORT datac (350:350:350) (394:394:394)) + (PORT datad (597:597:597) (684:684:684)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1757:1757:1757) (2009:2009:2009)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (946:946:946) (1114:1114:1114)) + (PORT d[1] (1098:1098:1098) (1285:1285:1285)) + (PORT d[2] (1113:1113:1113) (1299:1299:1299)) + (PORT d[3] (1011:1011:1011) (1190:1190:1190)) + (PORT d[4] (1146:1146:1146) (1339:1339:1339)) + (PORT d[5] (1091:1091:1091) (1279:1279:1279)) + (PORT d[6] (1109:1109:1109) (1300:1300:1300)) + (PORT d[7] (1182:1182:1182) (1383:1383:1383)) + (PORT d[8] (1113:1113:1113) (1312:1312:1312)) + (PORT d[9] (1176:1176:1176) (1375:1375:1375)) + (PORT d[10] (1007:1007:1007) (1189:1189:1189)) + (PORT d[11] (1125:1125:1125) (1298:1298:1298)) + (PORT d[12] (1173:1173:1173) (1378:1378:1378)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (990:990:990) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1761:1761:1761) (2013:2013:2013)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (952:952:952) (1112:1112:1112)) + (PORT d[1] (1111:1111:1111) (1297:1297:1297)) + (PORT d[2] (1094:1094:1094) (1272:1272:1272)) + (PORT d[3] (1012:1012:1012) (1190:1190:1190)) + (PORT d[4] (1135:1135:1135) (1323:1323:1323)) + (PORT d[5] (1092:1092:1092) (1279:1279:1279)) + (PORT d[6] (1110:1110:1110) (1300:1300:1300)) + (PORT d[7] (1183:1183:1183) (1383:1383:1383)) + (PORT d[8] (1114:1114:1114) (1312:1312:1312)) + (PORT d[9] (1177:1177:1177) (1375:1375:1375)) + (PORT d[10] (1008:1008:1008) (1189:1189:1189)) + (PORT d[11] (1126:1126:1126) (1298:1298:1298)) + (PORT d[12] (1174:1174:1174) (1378:1378:1378)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (PORT d[0] (990:990:990) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1099:1099:1099)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1780:1780:1780) (2036:2036:2036)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (955:955:955) (1126:1126:1126)) + (PORT d[1] (1112:1112:1112) (1301:1301:1301)) + (PORT d[2] (937:937:937) (1088:1088:1088)) + (PORT d[3] (987:987:987) (1160:1160:1160)) + (PORT d[4] (1114:1114:1114) (1320:1320:1320)) + (PORT d[5] (898:898:898) (1053:1053:1053)) + (PORT d[6] (1179:1179:1179) (1379:1379:1379)) + (PORT d[7] (1007:1007:1007) (1188:1188:1188)) + (PORT d[8] (1092:1092:1092) (1283:1283:1283)) + (PORT d[9] (1174:1174:1174) (1370:1370:1370)) + (PORT d[10] (1273:1273:1273) (1534:1534:1534)) + (PORT d[11] (1140:1140:1140) (1314:1314:1314)) + (PORT d[12] (1184:1184:1184) (1386:1386:1386)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (739:739:739) (832:832:832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1784:1784:1784) (2040:2040:2040)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (946:946:946) (1112:1112:1112)) + (PORT d[1] (1112:1112:1112) (1301:1301:1301)) + (PORT d[2] (945:945:945) (1106:1106:1106)) + (PORT d[3] (988:988:988) (1160:1160:1160)) + (PORT d[4] (1117:1117:1117) (1315:1315:1315)) + (PORT d[5] (899:899:899) (1053:1053:1053)) + (PORT d[6] (1180:1180:1180) (1379:1379:1379)) + (PORT d[7] (1008:1008:1008) (1188:1188:1188)) + (PORT d[8] (1093:1093:1093) (1283:1283:1283)) + (PORT d[9] (1175:1175:1175) (1370:1370:1370)) + (PORT d[10] (1274:1274:1274) (1534:1534:1534)) + (PORT d[11] (1141:1141:1141) (1314:1314:1314)) + (PORT d[12] (1185:1185:1185) (1386:1386:1386)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (739:739:739) (832:832:832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (371:371:371) (434:434:434)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (515:515:515) (593:593:593)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (921:921:921) (1072:1072:1072)) + (PORT d[1] (940:940:940) (1111:1111:1111)) + (PORT d[2] (912:912:912) (1062:1062:1062)) + (PORT d[3] (969:969:969) (1130:1130:1130)) + (PORT d[4] (969:969:969) (1139:1139:1139)) + (PORT d[5] (851:851:851) (998:998:998)) + (PORT d[6] (944:944:944) (1091:1091:1091)) + (PORT d[7] (1103:1103:1103) (1276:1276:1276)) + (PORT d[8] (982:982:982) (1139:1139:1139)) + (PORT d[9] (1010:1010:1010) (1175:1175:1175)) + (PORT d[10] (830:830:830) (996:996:996)) + (PORT d[11] (1080:1080:1080) (1241:1241:1241)) + (PORT d[12] (1001:1001:1001) (1178:1178:1178)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (796:796:796) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (519:519:519) (597:597:597)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (933:933:933) (1086:1086:1086)) + (PORT d[1] (934:934:934) (1096:1096:1096)) + (PORT d[2] (923:923:923) (1065:1065:1065)) + (PORT d[3] (970:970:970) (1130:1130:1130)) + (PORT d[4] (969:969:969) (1138:1138:1138)) + (PORT d[5] (852:852:852) (998:998:998)) + (PORT d[6] (945:945:945) (1091:1091:1091)) + (PORT d[7] (1104:1104:1104) (1276:1276:1276)) + (PORT d[8] (983:983:983) (1139:1139:1139)) + (PORT d[9] (1011:1011:1011) (1175:1175:1175)) + (PORT d[10] (831:831:831) (996:996:996)) + (PORT d[11] (1081:1081:1081) (1241:1241:1241)) + (PORT d[12] (1002:1002:1002) (1178:1178:1178)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (796:796:796) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (507:507:507) (583:583:583)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1100:1100:1100) (1288:1288:1288)) + (PORT d[1] (949:949:949) (1121:1121:1121)) + (PORT d[2] (1081:1081:1081) (1253:1253:1253)) + (PORT d[3] (967:967:967) (1129:1129:1129)) + (PORT d[4] (978:978:978) (1150:1150:1150)) + (PORT d[5] (856:856:856) (1003:1003:1003)) + (PORT d[6] (1068:1068:1068) (1239:1239:1239)) + (PORT d[7] (964:964:964) (1133:1133:1133)) + (PORT d[8] (1005:1005:1005) (1171:1171:1171)) + (PORT d[9] (1008:1008:1008) (1169:1169:1169)) + (PORT d[10] (1001:1001:1001) (1185:1185:1185)) + (PORT d[11] (1075:1075:1075) (1233:1233:1233)) + (PORT d[12] (1001:1001:1001) (1187:1187:1187)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (699:699:699) (786:786:786)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (511:511:511) (587:587:587)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1288:1288:1288)) + (PORT d[1] (940:940:940) (1108:1108:1108)) + (PORT d[2] (931:931:931) (1074:1074:1074)) + (PORT d[3] (968:968:968) (1129:1129:1129)) + (PORT d[4] (973:973:973) (1133:1133:1133)) + (PORT d[5] (857:857:857) (1003:1003:1003)) + (PORT d[6] (1069:1069:1069) (1239:1239:1239)) + (PORT d[7] (965:965:965) (1133:1133:1133)) + (PORT d[8] (1006:1006:1006) (1171:1171:1171)) + (PORT d[9] (1009:1009:1009) (1169:1169:1169)) + (PORT d[10] (1002:1002:1002) (1185:1185:1185)) + (PORT d[11] (1076:1076:1076) (1233:1233:1233)) + (PORT d[12] (1002:1002:1002) (1187:1187:1187)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (699:699:699) (786:786:786)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (561:561:561) (650:650:650)) + (PORT datac (404:404:404) (493:493:493)) + (PORT datad (545:545:545) (630:630:630)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1943:1943:1943) (2218:2218:2218)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (948:948:948) (1115:1115:1115)) + (PORT d[1] (1092:1092:1092) (1278:1278:1278)) + (PORT d[2] (927:927:927) (1085:1085:1085)) + (PORT d[3] (968:968:968) (1135:1135:1135)) + (PORT d[4] (1145:1145:1145) (1338:1338:1338)) + (PORT d[5] (864:864:864) (1020:1020:1020)) + (PORT d[6] (1209:1209:1209) (1415:1415:1415)) + (PORT d[7] (1143:1143:1143) (1337:1337:1337)) + (PORT d[8] (1174:1174:1174) (1360:1360:1360)) + (PORT d[9] (1186:1186:1186) (1389:1389:1389)) + (PORT d[10] (1132:1132:1132) (1327:1327:1327)) + (PORT d[11] (969:969:969) (1134:1134:1134)) + (PORT d[12] (1029:1029:1029) (1213:1213:1213)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT d[0] (792:792:792) (702:702:702)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1947:1947:1947) (2222:2222:2222)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (953:953:953) (1112:1112:1112)) + (PORT d[1] (1083:1083:1083) (1264:1264:1264)) + (PORT d[2] (947:947:947) (1110:1110:1110)) + (PORT d[3] (969:969:969) (1135:1135:1135)) + (PORT d[4] (1140:1140:1140) (1323:1323:1323)) + (PORT d[5] (865:865:865) (1020:1020:1020)) + (PORT d[6] (1210:1210:1210) (1415:1415:1415)) + (PORT d[7] (1144:1144:1144) (1337:1337:1337)) + (PORT d[8] (1175:1175:1175) (1360:1360:1360)) + (PORT d[9] (1187:1187:1187) (1389:1389:1389)) + (PORT d[10] (1133:1133:1133) (1327:1327:1327)) + (PORT d[11] (970:970:970) (1134:1134:1134)) + (PORT d[12] (1030:1030:1030) (1213:1213:1213)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (792:792:792) (702:702:702)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1931:1931:1931) (2203:2203:2203)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1082:1082:1082) (1265:1265:1265)) + (PORT d[1] (1084:1084:1084) (1267:1267:1267)) + (PORT d[2] (946:946:946) (1109:1109:1109)) + (PORT d[3] (984:984:984) (1156:1156:1156)) + (PORT d[4] (1149:1149:1149) (1345:1345:1345)) + (PORT d[5] (879:879:879) (1033:1033:1033)) + (PORT d[6] (1211:1211:1211) (1419:1419:1419)) + (PORT d[7] (994:994:994) (1168:1168:1168)) + (PORT d[8] (910:910:910) (1074:1074:1074)) + (PORT d[9] (1181:1181:1181) (1382:1382:1382)) + (PORT d[10] (998:998:998) (1180:1180:1180)) + (PORT d[11] (1143:1143:1143) (1314:1314:1314)) + (PORT d[12] (1180:1180:1180) (1382:1382:1382)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT d[0] (729:729:729) (824:824:824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1935:1935:1935) (2207:2207:2207)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1100:1100:1100) (1289:1289:1289)) + (PORT d[1] (1101:1101:1101) (1292:1292:1292)) + (PORT d[2] (947:947:947) (1109:1109:1109)) + (PORT d[3] (985:985:985) (1156:1156:1156)) + (PORT d[4] (1150:1150:1150) (1345:1345:1345)) + (PORT d[5] (880:880:880) (1033:1033:1033)) + (PORT d[6] (1212:1212:1212) (1419:1419:1419)) + (PORT d[7] (995:995:995) (1168:1168:1168)) + (PORT d[8] (911:911:911) (1074:1074:1074)) + (PORT d[9] (1182:1182:1182) (1382:1382:1382)) + (PORT d[10] (999:999:999) (1180:1180:1180)) + (PORT d[11] (1144:1144:1144) (1314:1314:1314)) + (PORT d[12] (1181:1181:1181) (1382:1382:1382)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (729:729:729) (824:824:824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (513:513:513)) + (PORT datac (363:363:363) (428:428:428)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1026:1026:1026) (1230:1230:1230)) + (PORT d[1] (1066:1066:1066) (1262:1262:1262)) + (PORT d[2] (1194:1194:1194) (1394:1394:1394)) + (PORT d[3] (1244:1244:1244) (1457:1457:1457)) + (PORT d[4] (1231:1231:1231) (1430:1430:1430)) + (PORT d[5] (1064:1064:1064) (1247:1247:1247)) + (PORT d[6] (1019:1019:1019) (1175:1175:1175)) + (PORT d[7] (1076:1076:1076) (1269:1269:1269)) + (PORT d[8] (1083:1083:1083) (1251:1251:1251)) + (PORT d[9] (1100:1100:1100) (1289:1289:1289)) + (PORT d[10] (1006:1006:1006) (1204:1204:1204)) + (PORT d[11] (1070:1070:1070) (1234:1234:1234)) + (PORT d[12] (1266:1266:1266) (1505:1505:1505)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1090:1090:1090) (964:964:964)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1218:1218:1218) (1448:1448:1448)) + (PORT d[1] (1092:1092:1092) (1290:1290:1290)) + (PORT d[2] (1231:1231:1231) (1441:1441:1441)) + (PORT d[3] (1282:1282:1282) (1504:1504:1504)) + (PORT d[4] (1249:1249:1249) (1465:1465:1465)) + (PORT d[5] (1088:1088:1088) (1277:1277:1277)) + (PORT d[6] (1180:1180:1180) (1378:1378:1378)) + (PORT d[7] (1198:1198:1198) (1413:1413:1413)) + (PORT d[8] (1151:1151:1151) (1346:1346:1346)) + (PORT d[9] (1219:1219:1219) (1437:1437:1437)) + (PORT d[10] (1144:1144:1144) (1363:1363:1363)) + (PORT d[11] (1299:1299:1299) (1510:1510:1510)) + (PORT d[12] (1149:1149:1149) (1360:1360:1360)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (PORT d[0] (975:975:975) (1100:1100:1100)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1068:1068:1068) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (618:618:618)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) (DELAY (ABSOLUTE - (PORT datac (343:343:343) (405:405:405)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (390:390:390)) - (PORT datac (503:503:503) (576:576:576)) - (PORT datad (534:534:534) (639:639:639)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (646:646:646) (750:750:750)) + (PORT datac (1426:1426:1426) (1680:1680:1680)) + (PORT datad (186:186:186) (218:218:218)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -2281,20 +4388,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (902:902:902) (1061:1061:1061)) - (PORT d[1] (541:541:541) (647:647:647)) - (PORT d[2] (549:549:549) (652:652:652)) - (PORT d[3] (570:570:570) (678:678:678)) - (PORT d[4] (543:543:543) (639:639:639)) - (PORT d[5] (894:894:894) (1048:1048:1048)) - (PORT d[6] (530:530:530) (631:631:631)) - (PORT d[7] (520:520:520) (620:620:620)) - (PORT d[8] (555:555:555) (661:661:661)) - (PORT d[9] (827:827:827) (956:956:956)) - (PORT d[10] (807:807:807) (932:932:932)) - (PORT d[11] (518:518:518) (615:615:615)) - (PORT d[12] (549:549:549) (649:649:649)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1193:1193:1193) (1414:1414:1414)) + (PORT d[1] (1111:1111:1111) (1316:1316:1316)) + (PORT d[2] (1192:1192:1192) (1395:1395:1395)) + (PORT d[3] (1250:1250:1250) (1457:1457:1457)) + (PORT d[4] (1233:1233:1233) (1447:1447:1447)) + (PORT d[5] (1075:1075:1075) (1257:1257:1257)) + (PORT d[6] (1216:1216:1216) (1416:1416:1416)) + (PORT d[7] (1216:1216:1216) (1434:1434:1434)) + (PORT d[8] (1007:1007:1007) (1188:1188:1188)) + (PORT d[9] (1225:1225:1225) (1442:1442:1442)) + (PORT d[10] (990:990:990) (1192:1192:1192)) + (PORT d[11] (1304:1304:1304) (1520:1520:1520)) + (PORT d[12] (1145:1145:1145) (1354:1354:1354)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) (TIMINGCHECK @@ -2306,8 +4413,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (497:497:497) (552:552:552)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) + (PORT d[0] (964:964:964) (1087:1087:1087)) ) ) ) @@ -2316,7 +4423,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1082:1082:1082) (1101:1101:1101)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2326,7 +4433,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) + (PORT clk (1063:1063:1063) (1081:1081:1081)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2340,7 +4447,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (603:603:603) (613:613:613)) ) ) ) @@ -2349,7 +4456,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (604:604:604) (614:614:614)) ) ) ) @@ -2358,7 +4465,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (604:604:604) (614:614:614)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2368,7 +4475,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (604:604:604) (614:614:614)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2378,19 +4485,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (709:709:709) (831:831:831)) - (PORT d[1] (717:717:717) (841:841:841)) - (PORT d[2] (701:701:701) (817:817:817)) - (PORT d[3] (729:729:729) (850:850:850)) - (PORT d[4] (722:722:722) (844:844:844)) - (PORT d[5] (871:871:871) (1018:1018:1018)) - (PORT d[6] (705:705:705) (825:825:825)) - (PORT d[7] (701:701:701) (821:821:821)) - (PORT d[8] (720:720:720) (849:849:849)) - (PORT d[9] (704:704:704) (814:814:814)) - (PORT d[10] (710:710:710) (828:828:828)) - (PORT d[11] (701:701:701) (817:817:817)) - (PORT d[12] (850:850:850) (983:983:983)) + (PORT d[0] (1198:1198:1198) (1423:1423:1423)) + (PORT d[1] (981:981:981) (1164:1164:1164)) + (PORT d[2] (1247:1247:1247) (1461:1461:1461)) + (PORT d[3] (1261:1261:1261) (1481:1481:1481)) + (PORT d[4] (1234:1234:1234) (1447:1447:1447)) + (PORT d[5] (913:913:913) (1074:1074:1074)) + (PORT d[6] (1204:1204:1204) (1391:1391:1391)) + (PORT d[7] (1103:1103:1103) (1308:1308:1308)) + (PORT d[8] (994:994:994) (1172:1172:1172)) + (PORT d[9] (1281:1281:1281) (1494:1494:1494)) + (PORT d[10] (979:979:979) (1178:1178:1178)) + (PORT d[11] (1258:1258:1258) (1452:1452:1452)) + (PORT d[12] (1245:1245:1245) (1474:1474:1474)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -2404,7 +4511,7 @@ (DELAY (ABSOLUTE (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (715:715:715) (641:641:641)) + (PORT d[0] (1089:1089:1089) (965:965:965)) ) ) ) @@ -2472,15 +4579,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (396:396:396)) - (PORT datab (391:391:391) (482:482:482)) - (PORT datac (509:509:509) (578:578:578)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (PORT dataa (385:385:385) (446:446:446)) + (PORT datac (533:533:533) (610:610:610)) + (PORT datad (1535:1535:1535) (1793:1793:1793)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -2489,20 +4596,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1062:1062:1062) (1240:1240:1240)) - (PORT d[1] (678:678:678) (795:795:795)) - (PORT d[2] (707:707:707) (825:825:825)) - (PORT d[3] (722:722:722) (850:850:850)) - (PORT d[4] (698:698:698) (818:818:818)) - (PORT d[5] (1071:1071:1071) (1252:1252:1252)) - (PORT d[6] (680:680:680) (794:794:794)) - (PORT d[7] (766:766:766) (911:911:911)) - (PORT d[8] (671:671:671) (789:789:789)) - (PORT d[9] (687:687:687) (798:798:798)) - (PORT d[10] (701:701:701) (824:824:824)) - (PORT d[11] (668:668:668) (774:774:774)) - (PORT d[12] (699:699:699) (819:819:819)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1123:1123:1123) (1330:1330:1330)) + (PORT d[1] (930:930:930) (1089:1089:1089)) + (PORT d[2] (1069:1069:1069) (1239:1239:1239)) + (PORT d[3] (1064:1064:1064) (1247:1247:1247)) + (PORT d[4] (1036:1036:1036) (1204:1204:1204)) + (PORT d[5] (941:941:941) (1099:1099:1099)) + (PORT d[6] (1067:1067:1067) (1238:1238:1238)) + (PORT d[7] (893:893:893) (1045:1045:1045)) + (PORT d[8] (899:899:899) (1041:1041:1041)) + (PORT d[9] (886:886:886) (1039:1039:1039)) + (PORT d[10] (1008:1008:1008) (1210:1210:1210)) + (PORT d[11] (912:912:912) (1055:1055:1055)) + (PORT d[12] (995:995:995) (1161:1161:1161)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) (TIMINGCHECK @@ -2514,8 +4621,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (706:706:706) (636:636:636)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1064:1064:1064) (941:941:941)) ) ) ) @@ -2524,7 +4631,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2534,7 +4641,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1072:1072:1072) (1088:1088:1088)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2548,7 +4655,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -2557,7 +4664,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) ) ) ) @@ -2566,7 +4673,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2576,7 +4683,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2586,20 +4693,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (418:418:418) (498:498:498)) - (PORT d[1] (350:350:350) (416:416:416)) - (PORT d[2] (841:841:841) (972:972:972)) - (PORT d[3] (659:659:659) (763:763:763)) - (PORT d[4] (523:523:523) (608:608:608)) - (PORT d[5] (581:581:581) (682:682:682)) - (PORT d[6] (662:662:662) (762:762:762)) - (PORT d[7] (686:686:686) (794:794:794)) - (PORT d[8] (846:846:846) (974:974:974)) - (PORT d[9] (689:689:689) (796:796:796)) - (PORT d[10] (686:686:686) (791:791:791)) - (PORT d[11] (665:665:665) (765:765:765)) - (PORT d[12] (681:681:681) (783:783:783)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (975:975:975) (1160:1160:1160)) + (PORT d[1] (924:924:924) (1082:1082:1082)) + (PORT d[2] (1030:1030:1030) (1201:1201:1201)) + (PORT d[3] (1006:1006:1006) (1164:1164:1164)) + (PORT d[4] (1020:1020:1020) (1188:1188:1188)) + (PORT d[5] (910:910:910) (1057:1057:1057)) + (PORT d[6] (869:869:869) (1008:1008:1008)) + (PORT d[7] (857:857:857) (1010:1010:1010)) + (PORT d[8] (876:876:876) (1014:1014:1014)) + (PORT d[9] (862:862:862) (1009:1009:1009)) + (PORT d[10] (1027:1027:1027) (1232:1232:1232)) + (PORT d[11] (879:879:879) (1020:1020:1020)) + (PORT d[12] (977:977:977) (1140:1140:1140)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) (TIMINGCHECK @@ -2611,8 +4718,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (487:487:487) (531:531:531)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (925:925:925) (1027:1027:1027)) ) ) ) @@ -2621,7 +4728,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2631,7 +4738,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) + (PORT clk (1070:1070:1070) (1086:1086:1086)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2645,7 +4752,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (610:610:610) (618:618:618)) ) ) ) @@ -2654,7 +4761,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (611:611:611) (619:619:619)) ) ) ) @@ -2663,7 +4770,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (611:611:611) (619:619:619)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2673,141 +4780,44 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (611:611:611) (619:619:619)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) (DELAY (ABSOLUTE - (PORT datab (527:527:527) (627:627:627)) - (PORT datac (326:326:326) (367:367:367)) - (PORT datad (559:559:559) (635:635:635)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (403:403:403) (473:473:473)) + (PORT datac (1064:1064:1064) (1265:1265:1265)) + (PORT datad (544:544:544) (627:627:627)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (870:870:870) (1017:1017:1017)) - (PORT d[1] (729:729:729) (858:858:858)) - (PORT d[2] (709:709:709) (832:832:832)) - (PORT d[3] (754:754:754) (885:885:885)) - (PORT d[4] (892:892:892) (1033:1033:1033)) - (PORT d[5] (722:722:722) (857:857:857)) - (PORT d[6] (718:718:718) (845:845:845)) - (PORT d[7] (702:702:702) (822:822:822)) - (PORT d[8] (708:708:708) (830:830:830)) - (PORT d[9] (718:718:718) (834:834:834)) - (PORT d[10] (724:724:724) (848:848:848)) - (PORT d[11] (702:702:702) (818:818:818)) - (PORT d[12] (705:705:705) (820:820:820)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1102:1102:1102)) - (PORT d[0] (637:637:637) (711:711:711)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (579:579:579) (682:682:682)) - (PORT d[1] (520:520:520) (610:610:610)) - (PORT d[2] (520:520:520) (605:605:605)) - (PORT d[3] (679:679:679) (778:778:778)) - (PORT d[4] (859:859:859) (988:988:988)) - (PORT d[5] (729:729:729) (849:849:849)) - (PORT d[6] (694:694:694) (798:798:798)) - (PORT d[7] (731:731:731) (845:845:845)) - (PORT d[8] (827:827:827) (954:954:954)) - (PORT d[9] (711:711:711) (819:819:819)) - (PORT d[10] (710:710:710) (819:819:819)) - (PORT d[11] (704:704:704) (814:814:814)) - (PORT d[12] (713:713:713) (817:817:817)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1178:1178:1178) (1398:1398:1398)) + (PORT d[1] (1102:1102:1102) (1303:1303:1303)) + (PORT d[2] (1262:1262:1262) (1476:1476:1476)) + (PORT d[3] (1293:1293:1293) (1514:1514:1514)) + (PORT d[4] (1256:1256:1256) (1472:1472:1472)) + (PORT d[5] (1236:1236:1236) (1438:1438:1438)) + (PORT d[6] (1211:1211:1211) (1416:1416:1416)) + (PORT d[7] (1213:1213:1213) (1429:1429:1429)) + (PORT d[8] (1322:1322:1322) (1535:1535:1535)) + (PORT d[9] (1057:1057:1057) (1251:1251:1251)) + (PORT d[10] (1166:1166:1166) (1397:1397:1397)) + (PORT d[11] (1309:1309:1309) (1522:1522:1522)) + (PORT d[12] (1321:1321:1321) (1552:1552:1552)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -2819,8 +4829,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (549:549:549) (505:505:505)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1123:1123:1123) (993:993:993)) ) ) ) @@ -2829,7 +4839,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2839,7 +4849,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1074:1074:1074) (1091:1091:1091)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2853,7 +4863,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (614:614:614) (623:623:623)) ) ) ) @@ -2862,7 +4872,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (615:615:615) (624:624:624)) ) ) ) @@ -2871,7 +4881,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (615:615:615) (624:624:624)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2879,6 +4889,2940 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1182:1182:1182) (1401:1401:1401)) + (PORT d[1] (1255:1255:1255) (1465:1465:1465)) + (PORT d[2] (1303:1303:1303) (1532:1532:1532)) + (PORT d[3] (1282:1282:1282) (1501:1501:1501)) + (PORT d[4] (1259:1259:1259) (1469:1469:1469)) + (PORT d[5] (1203:1203:1203) (1397:1397:1397)) + (PORT d[6] (1106:1106:1106) (1302:1302:1302)) + (PORT d[7] (1199:1199:1199) (1413:1413:1413)) + (PORT d[8] (1140:1140:1140) (1333:1333:1333)) + (PORT d[9] (1222:1222:1222) (1437:1437:1437)) + (PORT d[10] (1157:1157:1157) (1370:1370:1370)) + (PORT d[11] (1327:1327:1327) (1548:1548:1548)) + (PORT d[12] (1273:1273:1273) (1497:1497:1497)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1089:1089:1089) (1245:1245:1245)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1079:1079:1079) (1096:1096:1096)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (628:628:628)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (1561:1561:1561) (1837:1837:1837)) + (PORT datac (295:295:295) (334:334:334)) + (PORT datad (360:360:360) (415:415:415)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1960:1960:1960) (2239:2239:2239)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1124:1124:1124) (1309:1309:1309)) + (PORT d[1] (965:965:965) (1143:1143:1143)) + (PORT d[2] (972:972:972) (1130:1130:1130)) + (PORT d[3] (995:995:995) (1161:1161:1161)) + (PORT d[4] (1145:1145:1145) (1338:1338:1338)) + (PORT d[5] (844:844:844) (987:987:987)) + (PORT d[6] (983:983:983) (1155:1155:1155)) + (PORT d[7] (1282:1282:1282) (1481:1481:1481)) + (PORT d[8] (1161:1161:1161) (1341:1341:1341)) + (PORT d[9] (996:996:996) (1159:1159:1159)) + (PORT d[10] (829:829:829) (993:993:993)) + (PORT d[11] (1245:1245:1245) (1427:1427:1427)) + (PORT d[12] (1004:1004:1004) (1179:1179:1179)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT d[0] (806:806:806) (718:718:718)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1073:1073:1073) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1964:1964:1964) (2243:2243:2243)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1130:1130:1130) (1325:1325:1325)) + (PORT d[1] (956:956:956) (1129:1129:1129)) + (PORT d[2] (983:983:983) (1142:1142:1142)) + (PORT d[3] (996:996:996) (1161:1161:1161)) + (PORT d[4] (1139:1139:1139) (1323:1323:1323)) + (PORT d[5] (845:845:845) (987:987:987)) + (PORT d[6] (984:984:984) (1155:1155:1155)) + (PORT d[7] (1283:1283:1283) (1481:1481:1481)) + (PORT d[8] (1162:1162:1162) (1341:1341:1341)) + (PORT d[9] (997:997:997) (1159:1159:1159)) + (PORT d[10] (830:830:830) (993:993:993)) + (PORT d[11] (1246:1246:1246) (1427:1427:1427)) + (PORT d[12] (1005:1005:1005) (1179:1179:1179)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (806:806:806) (718:718:718)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1961:1961:1961) (2240:2240:2240)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1083:1083:1083) (1266:1266:1266)) + (PORT d[1] (1098:1098:1098) (1290:1290:1290)) + (PORT d[2] (1095:1095:1095) (1268:1268:1268)) + (PORT d[3] (1021:1021:1021) (1203:1203:1203)) + (PORT d[4] (1136:1136:1136) (1329:1329:1329)) + (PORT d[5] (854:854:854) (1000:1000:1000)) + (PORT d[6] (1166:1166:1166) (1365:1365:1365)) + (PORT d[7] (997:997:997) (1177:1177:1177)) + (PORT d[8] (915:915:915) (1080:1080:1080)) + (PORT d[9] (1172:1172:1172) (1367:1367:1367)) + (PORT d[10] (1138:1138:1138) (1333:1333:1333)) + (PORT d[11] (1258:1258:1258) (1444:1444:1444)) + (PORT d[12] (1009:1009:1009) (1188:1188:1188)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (717:717:717) (806:806:806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1075:1075:1075) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1965:1965:1965) (2244:2244:2244)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1105:1105:1105) (1295:1295:1295)) + (PORT d[1] (1105:1105:1105) (1291:1291:1291)) + (PORT d[2] (1117:1117:1117) (1290:1290:1290)) + (PORT d[3] (1022:1022:1022) (1203:1203:1203)) + (PORT d[4] (1137:1137:1137) (1328:1328:1328)) + (PORT d[5] (855:855:855) (1000:1000:1000)) + (PORT d[6] (1167:1167:1167) (1365:1365:1365)) + (PORT d[7] (998:998:998) (1177:1177:1177)) + (PORT d[8] (916:916:916) (1080:1080:1080)) + (PORT d[9] (1173:1173:1173) (1367:1367:1367)) + (PORT d[10] (1139:1139:1139) (1333:1333:1333)) + (PORT d[11] (1259:1259:1259) (1444:1444:1444)) + (PORT d[12] (1010:1010:1010) (1188:1188:1188)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (717:717:717) (806:806:806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (367:367:367) (429:429:429)) + (PORT datad (540:540:540) (622:622:622)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1553:1553:1553) (1772:1772:1772)) + (PORT clk (1105:1105:1105) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1121:1121:1121) (1309:1309:1309)) + (PORT d[1] (1119:1119:1119) (1307:1307:1307)) + (PORT d[2] (1115:1115:1115) (1298:1298:1298)) + (PORT d[3] (1010:1010:1010) (1184:1184:1184)) + (PORT d[4] (1245:1245:1245) (1459:1459:1459)) + (PORT d[5] (1075:1075:1075) (1254:1254:1254)) + (PORT d[6] (1179:1179:1179) (1380:1380:1380)) + (PORT d[7] (1183:1183:1183) (1388:1388:1388)) + (PORT d[8] (1071:1071:1071) (1255:1255:1255)) + (PORT d[9] (1181:1181:1181) (1377:1377:1377)) + (PORT d[10] (1284:1284:1284) (1529:1529:1529)) + (PORT d[11] (1157:1157:1157) (1333:1333:1333)) + (PORT d[12] (1190:1190:1190) (1396:1396:1396)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1123:1123:1123)) + (PORT d[0] (864:864:864) (974:974:974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1102:1102:1102)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1557:1557:1557) (1776:1776:1776)) + (PORT clk (1106:1106:1106) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1121:1121:1121) (1307:1307:1307)) + (PORT d[1] (1131:1131:1131) (1323:1323:1323)) + (PORT d[2] (1116:1116:1116) (1298:1298:1298)) + (PORT d[3] (1011:1011:1011) (1184:1184:1184)) + (PORT d[4] (1267:1267:1267) (1486:1486:1486)) + (PORT d[5] (1076:1076:1076) (1254:1254:1254)) + (PORT d[6] (1180:1180:1180) (1380:1380:1380)) + (PORT d[7] (1184:1184:1184) (1388:1388:1388)) + (PORT d[8] (1072:1072:1072) (1255:1255:1255)) + (PORT d[9] (1182:1182:1182) (1377:1377:1377)) + (PORT d[10] (1285:1285:1285) (1529:1529:1529)) + (PORT d[11] (1158:1158:1158) (1333:1333:1333)) + (PORT d[12] (1191:1191:1191) (1396:1396:1396)) + (PORT clk (1105:1105:1105) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (PORT d[0] (864:864:864) (974:974:974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1543:1543:1543) (1761:1761:1761)) + (PORT clk (1106:1106:1106) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1106:1106:1106) (1283:1283:1283)) + (PORT d[1] (1132:1132:1132) (1325:1325:1325)) + (PORT d[2] (1120:1120:1120) (1296:1296:1296)) + (PORT d[3] (1022:1022:1022) (1200:1200:1200)) + (PORT d[4] (1244:1244:1244) (1461:1461:1461)) + (PORT d[5] (1005:1005:1005) (1167:1167:1167)) + (PORT d[6] (1155:1155:1155) (1348:1348:1348)) + (PORT d[7] (1187:1187:1187) (1391:1391:1391)) + (PORT d[8] (1288:1288:1288) (1509:1509:1509)) + (PORT d[9] (1195:1195:1195) (1396:1396:1396)) + (PORT d[10] (957:957:957) (1125:1125:1125)) + (PORT d[11] (1147:1147:1147) (1319:1319:1319)) + (PORT d[12] (1203:1203:1203) (1413:1413:1413)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (PORT d[0] (973:973:973) (865:865:865)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1547:1547:1547) (1765:1765:1765)) + (PORT clk (1107:1107:1107) (1125:1125:1125)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1114:1114:1114) (1299:1299:1299)) + (PORT d[1] (1122:1122:1122) (1309:1309:1309)) + (PORT d[2] (1292:1292:1292) (1484:1484:1484)) + (PORT d[3] (1023:1023:1023) (1200:1200:1200)) + (PORT d[4] (1122:1122:1122) (1325:1325:1325)) + (PORT d[5] (1006:1006:1006) (1167:1167:1167)) + (PORT d[6] (1156:1156:1156) (1348:1348:1348)) + (PORT d[7] (1188:1188:1188) (1391:1391:1391)) + (PORT d[8] (1289:1289:1289) (1509:1509:1509)) + (PORT d[9] (1196:1196:1196) (1396:1396:1396)) + (PORT d[10] (958:958:958) (1125:1125:1125)) + (PORT d[11] (1148:1148:1148) (1319:1319:1319)) + (PORT d[12] (1204:1204:1204) (1413:1413:1413)) + (PORT clk (1106:1106:1106) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (PORT d[0] (973:973:973) (865:865:865)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (396:396:396)) + (PORT datac (551:551:551) (655:655:655)) + (PORT datad (500:500:500) (562:562:562)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1185:1185:1185) (1367:1367:1367)) + (PORT clk (1101:1101:1101) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1218:1218:1218) (1437:1437:1437)) + (PORT d[1] (1132:1132:1132) (1335:1335:1335)) + (PORT d[2] (1052:1052:1052) (1229:1229:1229)) + (PORT d[3] (1405:1405:1405) (1639:1639:1639)) + (PORT d[4] (1439:1439:1439) (1682:1682:1682)) + (PORT d[5] (1192:1192:1192) (1383:1383:1383)) + (PORT d[6] (1278:1278:1278) (1495:1495:1495)) + (PORT d[7] (1272:1272:1272) (1483:1483:1483)) + (PORT d[8] (1268:1268:1268) (1492:1492:1492)) + (PORT d[9] (1259:1259:1259) (1477:1477:1477)) + (PORT d[10] (1165:1165:1165) (1379:1379:1379)) + (PORT d[11] (1312:1312:1312) (1526:1526:1526)) + (PORT d[12] (1254:1254:1254) (1473:1473:1473)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1119:1119:1119)) + (PORT d[0] (1093:1093:1093) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1081:1081:1081) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1189:1189:1189) (1371:1371:1371)) + (PORT clk (1102:1102:1102) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1214:1214:1214) (1439:1439:1439)) + (PORT d[1] (1143:1143:1143) (1349:1349:1349)) + (PORT d[2] (1050:1050:1050) (1233:1233:1233)) + (PORT d[3] (1406:1406:1406) (1639:1639:1639)) + (PORT d[4] (1325:1325:1325) (1542:1542:1542)) + (PORT d[5] (1193:1193:1193) (1383:1383:1383)) + (PORT d[6] (1279:1279:1279) (1495:1495:1495)) + (PORT d[7] (1273:1273:1273) (1483:1483:1483)) + (PORT d[8] (1269:1269:1269) (1492:1492:1492)) + (PORT d[9] (1260:1260:1260) (1477:1477:1477)) + (PORT d[10] (1166:1166:1166) (1379:1379:1379)) + (PORT d[11] (1313:1313:1313) (1526:1526:1526)) + (PORT d[12] (1255:1255:1255) (1473:1473:1473)) + (PORT clk (1101:1101:1101) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1120:1120:1120)) + (PORT d[0] (1093:1093:1093) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1099:1099:1099)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1781:1781:1781) (2037:2037:2037)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (961:961:961) (1132:1132:1132)) + (PORT d[1] (1124:1124:1124) (1320:1320:1320)) + (PORT d[2] (980:980:980) (1145:1145:1145)) + (PORT d[3] (990:990:990) (1162:1162:1162)) + (PORT d[4] (1145:1145:1145) (1337:1337:1337)) + (PORT d[5] (879:879:879) (1030:1030:1030)) + (PORT d[6] (1204:1204:1204) (1411:1411:1411)) + (PORT d[7] (1175:1175:1175) (1379:1379:1379)) + (PORT d[8] (1080:1080:1080) (1259:1259:1259)) + (PORT d[9] (1152:1152:1152) (1345:1345:1345)) + (PORT d[10] (966:966:966) (1140:1140:1140)) + (PORT d[11] (1138:1138:1138) (1308:1308:1308)) + (PORT d[12] (1177:1177:1177) (1376:1376:1376)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (839:839:839) (742:742:742)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1785:1785:1785) (2041:2041:2041)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (951:951:951) (1118:1118:1118)) + (PORT d[1] (1119:1119:1119) (1303:1303:1303)) + (PORT d[2] (1100:1100:1100) (1282:1282:1282)) + (PORT d[3] (991:991:991) (1162:1162:1162)) + (PORT d[4] (1146:1146:1146) (1337:1337:1337)) + (PORT d[5] (880:880:880) (1030:1030:1030)) + (PORT d[6] (1205:1205:1205) (1411:1411:1411)) + (PORT d[7] (1176:1176:1176) (1379:1379:1379)) + (PORT d[8] (1081:1081:1081) (1259:1259:1259)) + (PORT d[9] (1153:1153:1153) (1345:1345:1345)) + (PORT d[10] (967:967:967) (1140:1140:1140)) + (PORT d[11] (1139:1139:1139) (1308:1308:1308)) + (PORT d[12] (1178:1178:1178) (1376:1376:1376)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (839:839:839) (742:742:742)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1075:1075:1075) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1512:1512:1512)) + (PORT datac (512:512:512) (580:580:580)) + (PORT datad (714:714:714) (815:815:815)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1613:1613:1613) (1842:1842:1842)) + (PORT clk (1104:1104:1104) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1091:1091:1091) (1279:1279:1279)) + (PORT d[1] (1128:1128:1128) (1320:1320:1320)) + (PORT d[2] (1120:1120:1120) (1310:1310:1310)) + (PORT d[3] (1014:1014:1014) (1191:1191:1191)) + (PORT d[4] (1114:1114:1114) (1313:1313:1313)) + (PORT d[5] (1085:1085:1085) (1268:1268:1268)) + (PORT d[6] (1179:1179:1179) (1379:1379:1379)) + (PORT d[7] (1124:1124:1124) (1311:1311:1311)) + (PORT d[8] (1271:1271:1271) (1485:1485:1485)) + (PORT d[9] (1175:1175:1175) (1370:1370:1370)) + (PORT d[10] (1296:1296:1296) (1547:1547:1547)) + (PORT d[11] (1282:1282:1282) (1476:1476:1476)) + (PORT d[12] (1184:1184:1184) (1390:1390:1390)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1120:1120:1120)) + (PORT d[0] (872:872:872) (980:980:980)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1099:1099:1099)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1617:1617:1617) (1846:1846:1846)) + (PORT clk (1105:1105:1105) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1080:1080:1080) (1263:1263:1263)) + (PORT d[1] (1124:1124:1124) (1303:1303:1303)) + (PORT d[2] (1087:1087:1087) (1267:1267:1267)) + (PORT d[3] (1015:1015:1015) (1191:1191:1191)) + (PORT d[4] (1105:1105:1105) (1300:1300:1300)) + (PORT d[5] (1086:1086:1086) (1268:1268:1268)) + (PORT d[6] (1180:1180:1180) (1379:1379:1379)) + (PORT d[7] (1125:1125:1125) (1311:1311:1311)) + (PORT d[8] (1272:1272:1272) (1485:1485:1485)) + (PORT d[9] (1176:1176:1176) (1370:1370:1370)) + (PORT d[10] (1297:1297:1297) (1547:1547:1547)) + (PORT d[11] (1283:1283:1283) (1476:1476:1476)) + (PORT d[12] (1185:1185:1185) (1390:1390:1390)) + (PORT clk (1104:1104:1104) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (PORT d[0] (872:872:872) (980:980:980)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1100:1100:1100)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1284:1284:1284) (1472:1472:1472)) + (PORT clk (1107:1107:1107) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1110:1110:1110) (1300:1300:1300)) + (PORT d[1] (1122:1122:1122) (1310:1310:1310)) + (PORT d[2] (1078:1078:1078) (1245:1245:1245)) + (PORT d[3] (1164:1164:1164) (1353:1353:1353)) + (PORT d[4] (1277:1277:1277) (1496:1496:1496)) + (PORT d[5] (1022:1022:1022) (1190:1190:1190)) + (PORT d[6] (1163:1163:1163) (1359:1359:1359)) + (PORT d[7] (1175:1175:1175) (1371:1371:1371)) + (PORT d[8] (1057:1057:1057) (1233:1233:1233)) + (PORT d[9] (1176:1176:1176) (1371:1371:1371)) + (PORT d[10] (1326:1326:1326) (1546:1546:1546)) + (PORT d[11] (1123:1123:1123) (1309:1309:1309)) + (PORT d[12] (1196:1196:1196) (1401:1401:1401)) + (PORT clk (1105:1105:1105) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1124:1124:1124)) + (PORT d[0] (990:990:990) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1288:1288:1288) (1476:1476:1476)) + (PORT clk (1108:1108:1108) (1125:1125:1125)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1286:1286:1286)) + (PORT d[1] (1123:1123:1123) (1310:1310:1310)) + (PORT d[2] (1085:1085:1085) (1261:1261:1261)) + (PORT d[3] (1165:1165:1165) (1353:1353:1353)) + (PORT d[4] (1288:1288:1288) (1510:1510:1510)) + (PORT d[5] (1023:1023:1023) (1190:1190:1190)) + (PORT d[6] (1164:1164:1164) (1359:1359:1359)) + (PORT d[7] (1176:1176:1176) (1371:1371:1371)) + (PORT d[8] (1058:1058:1058) (1233:1233:1233)) + (PORT d[9] (1177:1177:1177) (1371:1371:1371)) + (PORT d[10] (1327:1327:1327) (1546:1546:1546)) + (PORT d[11] (1124:1124:1124) (1309:1309:1309)) + (PORT d[12] (1197:1197:1197) (1401:1401:1401)) + (PORT clk (1107:1107:1107) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1108:1108:1108) (1125:1125:1125)) + (PORT d[0] (990:990:990) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1109:1109:1109) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1109:1109:1109) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1109:1109:1109) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1109:1109:1109) (1126:1126:1126)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1104:1104:1104)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (361:361:361)) + (PORT datac (474:474:474) (563:563:563)) + (PORT datad (364:364:364) (420:420:420)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[14\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (430:430:430) (463:463:463)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (324:324:324) (385:385:385)) + (PORT datad (240:240:240) (296:296:296)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1222:1222:1222) (1373:1373:1373)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (750:750:750) (881:881:881)) + (PORT d[1] (752:752:752) (885:885:885)) + (PORT d[2] (759:759:759) (883:883:883)) + (PORT d[3] (751:751:751) (877:877:877)) + (PORT d[4] (740:740:740) (858:858:858)) + (PORT d[5] (693:693:693) (792:792:792)) + (PORT d[6] (739:739:739) (858:858:858)) + (PORT d[7] (848:848:848) (971:971:971)) + (PORT d[8] (777:777:777) (904:904:904)) + (PORT d[9] (754:754:754) (868:868:868)) + (PORT d[10] (752:752:752) (879:879:879)) + (PORT d[11] (760:760:760) (877:877:877)) + (PORT d[12] (782:782:782) (915:915:915)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (556:556:556) (593:593:593)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datac (325:325:325) (386:386:386)) + (PORT datad (241:241:241) (297:297:297)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (488:488:488) (559:559:559)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (901:901:901) (1054:1054:1054)) + (PORT d[1] (745:745:745) (868:868:868)) + (PORT d[2] (911:911:911) (1062:1062:1062)) + (PORT d[3] (983:983:983) (1160:1160:1160)) + (PORT d[4] (960:960:960) (1131:1131:1131)) + (PORT d[5] (853:853:853) (1005:1005:1005)) + (PORT d[6] (959:959:959) (1109:1109:1109)) + (PORT d[7] (1074:1074:1074) (1240:1240:1240)) + (PORT d[8] (953:953:953) (1104:1104:1104)) + (PORT d[9] (973:973:973) (1129:1129:1129)) + (PORT d[10] (1014:1014:1014) (1196:1196:1196)) + (PORT d[11] (1083:1083:1083) (1249:1249:1249)) + (PORT d[12] (1013:1013:1013) (1198:1198:1198)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (762:762:762) (841:841:841)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (325:325:325) (385:385:385)) + (PORT datad (240:240:240) (296:296:296)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1463:1463:1463) (1668:1668:1668)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (997:997:997) (1166:1166:1166)) + (PORT d[1] (1057:1057:1057) (1227:1227:1227)) + (PORT d[2] (827:827:827) (962:962:962)) + (PORT d[3] (821:821:821) (948:948:948)) + (PORT d[4] (855:855:855) (1004:1004:1004)) + (PORT d[5] (728:728:728) (850:850:850)) + (PORT d[6] (881:881:881) (1023:1023:1023)) + (PORT d[7] (1001:1001:1001) (1155:1155:1155)) + (PORT d[8] (710:710:710) (835:835:835)) + (PORT d[9] (691:691:691) (815:815:815)) + (PORT d[10] (697:697:697) (823:823:823)) + (PORT d[11] (725:725:725) (846:846:846)) + (PORT d[12] (664:664:664) (776:776:776)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (595:595:595) (646:646:646)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (322:322:322) (383:383:383)) + (PORT datad (238:238:238) (294:294:294)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1373:1373:1373) (1553:1553:1553)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (584:584:584) (682:682:682)) + (PORT d[1] (594:594:594) (705:705:705)) + (PORT d[2] (599:599:599) (706:706:706)) + (PORT d[3] (592:592:592) (698:698:698)) + (PORT d[4] (882:882:882) (1016:1016:1016)) + (PORT d[5] (593:593:593) (694:694:694)) + (PORT d[6] (626:626:626) (736:736:736)) + (PORT d[7] (714:714:714) (825:825:825)) + (PORT d[8] (754:754:754) (873:873:873)) + (PORT d[9] (625:625:625) (732:732:732)) + (PORT d[10] (762:762:762) (891:891:891)) + (PORT d[11] (634:634:634) (743:743:743)) + (PORT d[12] (706:706:706) (823:823:823)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (475:475:475) (507:507:507)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (339:339:339) (400:400:400)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1133:1133:1133)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1053:1053:1053) (1237:1237:1237)) + (PORT datab (633:633:633) (714:714:714)) + (PORT datac (471:471:471) (542:542:542)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (751:751:751)) + (PORT datab (811:811:811) (924:924:924)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1081:1081:1081) (1229:1229:1229)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1446:1446:1446)) + (PORT d[1] (887:887:887) (1040:1040:1040)) + (PORT d[2] (977:977:977) (1123:1123:1123)) + (PORT d[3] (981:981:981) (1125:1125:1125)) + (PORT d[4] (973:973:973) (1125:1125:1125)) + (PORT d[5] (874:874:874) (1008:1008:1008)) + (PORT d[6] (858:858:858) (1004:1004:1004)) + (PORT d[7] (815:815:815) (944:944:944)) + (PORT d[8] (867:867:867) (1006:1006:1006)) + (PORT d[9] (831:831:831) (969:969:969)) + (PORT d[10] (840:840:840) (980:980:980)) + (PORT d[11] (872:872:872) (1005:1005:1005)) + (PORT d[12] (968:968:968) (1124:1124:1124)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (717:717:717) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1267:1267:1267) (1445:1445:1445)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1129:1129:1129) (1330:1330:1330)) + (PORT d[1] (864:864:864) (1008:1008:1008)) + (PORT d[2] (976:976:976) (1124:1124:1124)) + (PORT d[3] (978:978:978) (1122:1122:1122)) + (PORT d[4] (968:968:968) (1120:1120:1120)) + (PORT d[5] (884:884:884) (1020:1020:1020)) + (PORT d[6] (866:866:866) (1015:1015:1015)) + (PORT d[7] (806:806:806) (934:934:934)) + (PORT d[8] (863:863:863) (1002:1002:1002)) + (PORT d[9] (838:838:838) (979:979:979)) + (PORT d[10] (847:847:847) (990:990:990)) + (PORT d[11] (882:882:882) (1017:1017:1017)) + (PORT d[12] (951:951:951) (1104:1104:1104)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (686:686:686) (747:747:747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1548:1548:1548) (1749:1749:1749)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (583:583:583) (695:695:695)) + (PORT d[1] (605:605:605) (721:721:721)) + (PORT d[2] (575:575:575) (678:678:678)) + (PORT d[3] (732:732:732) (858:858:858)) + (PORT d[4] (738:738:738) (863:863:863)) + (PORT d[5] (580:580:580) (680:680:680)) + (PORT d[6] (573:573:573) (669:669:669)) + (PORT d[7] (681:681:681) (785:785:785)) + (PORT d[8] (591:591:591) (691:691:691)) + (PORT d[9] (613:613:613) (721:721:721)) + (PORT d[10] (602:602:602) (715:715:715)) + (PORT d[11] (611:611:611) (717:717:717)) + (PORT d[12] (598:598:598) (704:704:704)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (449:449:449) (478:478:478)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -2888,16 +7832,3838 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (554:554:554) (662:662:662)) - (PORT datac (330:330:330) (371:371:371)) - (PORT datad (564:564:564) (639:639:639)) + (PORT dataa (860:860:860) (1035:1035:1035)) + (PORT datab (839:839:839) (965:965:965)) + (PORT datac (732:732:732) (828:828:828)) + (PORT datad (538:538:538) (635:635:635)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (490:490:490) (557:557:557)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (993:993:993) (1187:1187:1187)) + (PORT d[1] (971:971:971) (1169:1169:1169)) + (PORT d[2] (1235:1235:1235) (1439:1439:1439)) + (PORT d[3] (1035:1035:1035) (1200:1200:1200)) + (PORT d[4] (1182:1182:1182) (1366:1366:1366)) + (PORT d[5] (887:887:887) (1045:1045:1045)) + (PORT d[6] (1050:1050:1050) (1212:1212:1212)) + (PORT d[7] (1252:1252:1252) (1469:1469:1469)) + (PORT d[8] (886:886:886) (1022:1022:1022)) + (PORT d[9] (881:881:881) (1028:1028:1028)) + (PORT d[10] (1019:1019:1019) (1221:1221:1221)) + (PORT d[11] (912:912:912) (1056:1056:1056)) + (PORT d[12] (1006:1006:1006) (1176:1176:1176)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (655:655:655) (737:737:737)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (979:979:979)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (609:609:609) (680:680:680)) + (PORT datad (543:543:543) (641:641:641)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1390:1390:1390) (1575:1575:1575)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (588:588:588) (688:688:688)) + (PORT d[1] (599:599:599) (709:709:709)) + (PORT d[2] (599:599:599) (705:705:705)) + (PORT d[3] (735:735:735) (857:857:857)) + (PORT d[4] (596:596:596) (708:708:708)) + (PORT d[5] (595:595:595) (695:695:695)) + (PORT d[6] (604:604:604) (713:713:713)) + (PORT d[7] (714:714:714) (824:824:824)) + (PORT d[8] (614:614:614) (723:723:723)) + (PORT d[9] (624:624:624) (731:731:731)) + (PORT d[10] (611:611:611) (725:725:725)) + (PORT d[11] (633:633:633) (742:742:742)) + (PORT d[12] (634:634:634) (751:751:751)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (430:430:430) (457:457:457)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1288:1288:1288) (1469:1469:1469)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (827:827:827) (974:974:974)) + (PORT d[1] (1056:1056:1056) (1226:1226:1226)) + (PORT d[2] (856:856:856) (1000:1000:1000)) + (PORT d[3] (835:835:835) (964:964:964)) + (PORT d[4] (835:835:835) (974:974:974)) + (PORT d[5] (729:729:729) (847:847:847)) + (PORT d[6] (880:880:880) (1024:1024:1024)) + (PORT d[7] (1001:1001:1001) (1154:1154:1154)) + (PORT d[8] (723:723:723) (850:850:850)) + (PORT d[9] (695:695:695) (817:817:817)) + (PORT d[10] (700:700:700) (825:825:825)) + (PORT d[11] (725:725:725) (842:842:842)) + (PORT d[12] (828:828:828) (974:974:974)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (593:593:593) (641:641:641)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1280:1280:1280) (1460:1460:1460)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (981:981:981) (1140:1140:1140)) + (PORT d[1] (1048:1048:1048) (1220:1220:1220)) + (PORT d[2] (863:863:863) (1007:1007:1007)) + (PORT d[3] (843:843:843) (989:989:989)) + (PORT d[4] (865:865:865) (1013:1013:1013)) + (PORT d[5] (738:738:738) (857:857:857)) + (PORT d[6] (878:878:878) (1022:1022:1022)) + (PORT d[7] (969:969:969) (1115:1115:1115)) + (PORT d[8] (718:718:718) (840:840:840)) + (PORT d[9] (717:717:717) (847:847:847)) + (PORT d[10] (708:708:708) (834:834:834)) + (PORT d[11] (746:746:746) (870:870:870)) + (PORT d[12] (683:683:683) (795:795:795)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (588:588:588) (644:644:644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (729:729:729)) + (PORT datab (164:164:164) (218:218:218)) + (PORT datac (861:861:861) (1014:1014:1014)) + (PORT datad (642:642:642) (717:717:717)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1568:1568:1568) (1779:1779:1779)) + (PORT clk (1087:1087:1087) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (416:416:416) (498:498:498)) + (PORT d[1] (409:409:409) (486:486:486)) + (PORT d[2] (549:549:549) (642:642:642)) + (PORT d[3] (731:731:731) (855:855:855)) + (PORT d[4] (591:591:591) (702:702:702)) + (PORT d[5] (741:741:741) (852:852:852)) + (PORT d[6] (564:564:564) (658:658:658)) + (PORT d[7] (689:689:689) (797:797:797)) + (PORT d[8] (582:582:582) (679:679:679)) + (PORT d[9] (593:593:593) (694:694:694)) + (PORT d[10] (694:694:694) (805:805:805)) + (PORT d[11] (702:702:702) (817:817:817)) + (PORT d[12] (675:675:675) (785:785:785)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1106:1106:1106)) + (PORT d[0] (447:447:447) (475:475:475)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (533:533:533)) + (PORT datab (164:164:164) (219:219:219)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (446:446:446) (503:503:503)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1083:1083:1083) (1252:1252:1252)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1171:1171:1171) (1388:1388:1388)) + (PORT d[1] (967:967:967) (1155:1155:1155)) + (PORT d[2] (1205:1205:1205) (1409:1409:1409)) + (PORT d[3] (1293:1293:1293) (1521:1521:1521)) + (PORT d[4] (1211:1211:1211) (1407:1407:1407)) + (PORT d[5] (1077:1077:1077) (1262:1262:1262)) + (PORT d[6] (1029:1029:1029) (1186:1186:1186)) + (PORT d[7] (1225:1225:1225) (1433:1433:1433)) + (PORT d[8] (1091:1091:1091) (1260:1260:1260)) + (PORT d[9] (1091:1091:1091) (1276:1276:1276)) + (PORT d[10] (1012:1012:1012) (1210:1210:1210)) + (PORT d[11] (1078:1078:1078) (1243:1243:1243)) + (PORT d[12] (1173:1173:1173) (1363:1363:1363)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (758:758:758) (846:846:846)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1740:1740:1740) (1971:1971:1971)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (579:579:579) (684:684:684)) + (PORT d[1] (573:573:573) (676:676:676)) + (PORT d[2] (724:724:724) (841:841:841)) + (PORT d[3] (775:775:775) (903:903:903)) + (PORT d[4] (776:776:776) (917:917:917)) + (PORT d[5] (854:854:854) (1000:1000:1000)) + (PORT d[6] (771:771:771) (895:895:895)) + (PORT d[7] (890:890:890) (1031:1031:1031)) + (PORT d[8] (764:764:764) (888:888:888)) + (PORT d[9] (784:784:784) (913:913:913)) + (PORT d[10] (776:776:776) (917:917:917)) + (PORT d[11] (883:883:883) (1021:1021:1021)) + (PORT d[12] (745:745:745) (862:862:862)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (627:627:627) (674:674:674)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (1032:1032:1032)) + (PORT datab (562:562:562) (667:667:667)) + (PORT datac (804:804:804) (914:914:914)) + (PORT datad (583:583:583) (663:663:663)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1470:1470:1470) (1676:1676:1676)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1010:1010:1010) (1181:1181:1181)) + (PORT d[1] (569:569:569) (674:674:674)) + (PORT d[2] (676:676:676) (793:793:793)) + (PORT d[3] (641:641:641) (749:749:749)) + (PORT d[4] (680:680:680) (805:805:805)) + (PORT d[5] (580:580:580) (680:680:680)) + (PORT d[6] (897:897:897) (1042:1042:1042)) + (PORT d[7] (864:864:864) (1012:1012:1012)) + (PORT d[8] (544:544:544) (645:645:645)) + (PORT d[9] (517:517:517) (616:616:616)) + (PORT d[10] (576:576:576) (681:681:681)) + (PORT d[11] (534:534:534) (631:631:631)) + (PORT d[12] (516:516:516) (613:613:613)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (437:437:437) (463:463:463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1729:1729:1729) (1957:1957:1957)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (567:567:567) (672:672:672)) + (PORT d[1] (552:552:552) (651:651:651)) + (PORT d[2] (570:570:570) (663:663:663)) + (PORT d[3] (594:594:594) (702:702:702)) + (PORT d[4] (584:584:584) (689:689:689)) + (PORT d[5] (869:869:869) (1027:1027:1027)) + (PORT d[6] (595:595:595) (700:700:700)) + (PORT d[7] (717:717:717) (834:834:834)) + (PORT d[8] (596:596:596) (696:696:696)) + (PORT d[9] (618:618:618) (725:725:725)) + (PORT d[10] (706:706:706) (819:819:819)) + (PORT d[11] (743:743:743) (854:854:854)) + (PORT d[12] (587:587:587) (688:688:688)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (457:457:457) (490:490:490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (559:559:559) (663:663:663)) + (PORT datac (607:607:607) (686:686:686)) + (PORT datad (574:574:574) (641:641:641)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1289:1289:1289) (1470:1470:1470)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (813:813:813) (952:952:952)) + (PORT d[1] (709:709:709) (837:837:837)) + (PORT d[2] (863:863:863) (1007:1007:1007)) + (PORT d[3] (848:848:848) (987:987:987)) + (PORT d[4] (865:865:865) (1012:1012:1012)) + (PORT d[5] (750:750:750) (876:876:876)) + (PORT d[6] (703:703:703) (828:828:828)) + (PORT d[7] (671:671:671) (780:780:780)) + (PORT d[8] (718:718:718) (839:839:839)) + (PORT d[9] (716:716:716) (846:846:846)) + (PORT d[10] (707:707:707) (833:833:833)) + (PORT d[11] (732:732:732) (850:850:850)) + (PORT d[12] (695:695:695) (814:814:814)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (594:594:594) (647:647:647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (669:669:669) (771:771:771)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (986:986:986) (1173:1173:1173)) + (PORT d[1] (763:763:763) (902:902:902)) + (PORT d[2] (860:860:860) (999:999:999)) + (PORT d[3] (902:902:902) (1063:1063:1063)) + (PORT d[4] (1024:1024:1024) (1193:1193:1193)) + (PORT d[5] (757:757:757) (885:885:885)) + (PORT d[6] (868:868:868) (1007:1007:1007)) + (PORT d[7] (1054:1054:1054) (1237:1237:1237)) + (PORT d[8] (705:705:705) (819:819:819)) + (PORT d[9] (701:701:701) (825:825:825)) + (PORT d[10] (1015:1015:1015) (1213:1213:1213)) + (PORT d[11] (711:711:711) (829:829:829)) + (PORT d[12] (822:822:822) (966:966:966)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (626:626:626) (689:689:689)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1898:1898:1898) (2144:2144:2144)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (779:779:779) (916:916:916)) + (PORT d[1] (739:739:739) (862:862:862)) + (PORT d[2] (769:769:769) (899:899:899)) + (PORT d[3] (783:783:783) (913:913:913)) + (PORT d[4] (780:780:780) (918:918:918)) + (PORT d[5] (845:845:845) (993:993:993)) + (PORT d[6] (939:939:939) (1083:1083:1083)) + (PORT d[7] (922:922:922) (1073:1073:1073)) + (PORT d[8] (792:792:792) (925:925:925)) + (PORT d[9] (816:816:816) (952:952:952)) + (PORT d[10] (773:773:773) (908:908:908)) + (PORT d[11] (1050:1050:1050) (1208:1208:1208)) + (PORT d[12] (996:996:996) (1170:1170:1170)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (600:600:600) (648:648:648)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (1034:1034:1034)) + (PORT datab (560:560:560) (665:665:665)) + (PORT datac (459:459:459) (521:521:521)) + (PORT datad (690:690:690) (800:800:800)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (509:509:509) (592:592:592)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (927:927:927) (1075:1075:1075)) + (PORT d[1] (1116:1116:1116) (1310:1310:1310)) + (PORT d[2] (923:923:923) (1076:1076:1076)) + (PORT d[3] (975:975:975) (1149:1149:1149)) + (PORT d[4] (1083:1083:1083) (1262:1262:1262)) + (PORT d[5] (849:849:849) (994:994:994)) + (PORT d[6] (954:954:954) (1111:1111:1111)) + (PORT d[7] (1086:1086:1086) (1254:1254:1254)) + (PORT d[8] (984:984:984) (1140:1140:1140)) + (PORT d[9] (1014:1014:1014) (1180:1180:1180)) + (PORT d[10] (990:990:990) (1170:1170:1170)) + (PORT d[11] (904:904:904) (1036:1036:1036)) + (PORT d[12] (1014:1014:1014) (1193:1193:1193)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (746:746:746) (815:815:815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (900:900:900)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (759:759:759) (861:861:861)) + (PORT datad (542:542:542) (640:640:640)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1743:1743:1743) (1973:1973:1973)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (589:589:589) (699:699:699)) + (PORT d[1] (688:688:688) (800:800:800)) + (PORT d[2] (575:575:575) (669:669:669)) + (PORT d[3] (608:608:608) (720:720:720)) + (PORT d[4] (594:594:594) (701:701:701)) + (PORT d[5] (868:868:868) (1020:1020:1020)) + (PORT d[6] (597:597:597) (698:698:698)) + (PORT d[7] (737:737:737) (859:859:859)) + (PORT d[8] (619:619:619) (727:727:727)) + (PORT d[9] (617:617:617) (721:721:721)) + (PORT d[10] (713:713:713) (827:827:827)) + (PORT d[11] (712:712:712) (826:826:826)) + (PORT d[12] (607:607:607) (714:714:714)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (445:445:445) (479:479:479)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (855:855:855) (984:984:984)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (982:982:982) (1165:1165:1165)) + (PORT d[1] (751:751:751) (885:885:885)) + (PORT d[2] (899:899:899) (1052:1052:1052)) + (PORT d[3] (830:830:830) (966:966:966)) + (PORT d[4] (832:832:832) (969:969:969)) + (PORT d[5] (743:743:743) (864:864:864)) + (PORT d[6] (861:861:861) (999:999:999)) + (PORT d[7] (1059:1059:1059) (1243:1243:1243)) + (PORT d[8] (717:717:717) (837:837:837)) + (PORT d[9] (710:710:710) (837:837:837)) + (PORT d[10] (743:743:743) (884:884:884)) + (PORT d[11] (740:740:740) (866:866:866)) + (PORT d[12] (811:811:811) (951:951:951)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (608:608:608) (664:664:664)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1728:1728:1728) (1953:1953:1953)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (575:575:575) (673:673:673)) + (PORT d[1] (565:565:565) (667:667:667)) + (PORT d[2] (613:613:613) (722:722:722)) + (PORT d[3] (596:596:596) (702:702:702)) + (PORT d[4] (594:594:594) (700:700:700)) + (PORT d[5] (855:855:855) (1006:1006:1006)) + (PORT d[6] (762:762:762) (888:888:888)) + (PORT d[7] (726:726:726) (844:844:844)) + (PORT d[8] (605:605:605) (706:706:706)) + (PORT d[9] (627:627:627) (734:734:734)) + (PORT d[10] (700:700:700) (807:807:807)) + (PORT d[11] (757:757:757) (876:876:876)) + (PORT d[12] (690:690:690) (801:801:801)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (478:478:478) (506:506:506)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (605:605:605)) + (PORT datab (564:564:564) (669:669:669)) + (PORT datac (575:575:575) (653:653:653)) + (PORT datad (842:842:842) (1003:1003:1003)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1900:1900:1900) (2148:2148:2148)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (761:761:761) (893:893:893)) + (PORT d[1] (728:728:728) (851:851:851)) + (PORT d[2] (747:747:747) (864:864:864)) + (PORT d[3] (781:781:781) (910:910:910)) + (PORT d[4] (770:770:770) (906:906:906)) + (PORT d[5] (861:861:861) (1012:1012:1012)) + (PORT d[6] (784:784:784) (915:915:915)) + (PORT d[7] (911:911:911) (1059:1059:1059)) + (PORT d[8] (776:776:776) (900:900:900)) + (PORT d[9] (808:808:808) (942:942:942)) + (PORT d[10] (911:911:911) (1071:1071:1071)) + (PORT d[11] (901:901:901) (1045:1045:1045)) + (PORT d[12] (756:756:756) (873:873:873)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (631:631:631) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (499:499:499)) + (PORT datab (560:560:560) (664:664:664)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (592:592:592) (671:671:671)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (847:847:847) (972:972:972)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1203:1203:1203)) + (PORT d[1] (754:754:754) (892:892:892)) + (PORT d[2] (829:829:829) (964:964:964)) + (PORT d[3] (829:829:829) (964:964:964)) + (PORT d[4] (824:824:824) (958:958:958)) + (PORT d[5] (735:735:735) (855:855:855)) + (PORT d[6] (861:861:861) (1003:1003:1003)) + (PORT d[7] (693:693:693) (818:818:818)) + (PORT d[8] (858:858:858) (996:996:996)) + (PORT d[9] (705:705:705) (834:834:834)) + (PORT d[10] (883:883:883) (1037:1037:1037)) + (PORT d[11] (704:704:704) (820:820:820)) + (PORT d[12] (816:816:816) (960:960:960)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (608:608:608) (666:666:666)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1459:1459:1459) (1662:1662:1662)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1017:1017:1017) (1188:1188:1188)) + (PORT d[1] (846:846:846) (991:991:991)) + (PORT d[2] (843:843:843) (974:974:974)) + (PORT d[3] (831:831:831) (969:969:969)) + (PORT d[4] (816:816:816) (941:941:941)) + (PORT d[5] (712:712:712) (826:826:826)) + (PORT d[6] (694:694:694) (815:815:815)) + (PORT d[7] (854:854:854) (1001:1001:1001)) + (PORT d[8] (695:695:695) (810:810:810)) + (PORT d[9] (676:676:676) (795:795:795)) + (PORT d[10] (916:916:916) (1080:1080:1080)) + (PORT d[11] (707:707:707) (824:824:824)) + (PORT d[12] (790:790:790) (928:928:928)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (581:581:581) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (602:602:602) (611:611:611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (608:608:608)) + (PORT datab (480:480:480) (542:542:542)) + (PORT datac (626:626:626) (702:702:702)) + (PORT datad (956:956:956) (1121:1121:1121)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (662:662:662) (763:763:763)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (924:924:924) (1097:1097:1097)) + (PORT d[1] (922:922:922) (1079:1079:1079)) + (PORT d[2] (1040:1040:1040) (1211:1211:1211)) + (PORT d[3] (1002:1002:1002) (1157:1157:1157)) + (PORT d[4] (1035:1035:1035) (1203:1203:1203)) + (PORT d[5] (928:928:928) (1079:1079:1079)) + (PORT d[6] (1044:1044:1044) (1210:1210:1210)) + (PORT d[7] (883:883:883) (1043:1043:1043)) + (PORT d[8] (891:891:891) (1033:1033:1033)) + (PORT d[9] (887:887:887) (1040:1040:1040)) + (PORT d[10] (1007:1007:1007) (1205:1205:1205)) + (PORT d[11] (942:942:942) (1101:1101:1101)) + (PORT d[12] (997:997:997) (1166:1166:1166)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (720:720:720) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1563:1563:1563) (1768:1768:1768)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (403:403:403) (480:480:480)) + (PORT d[1] (403:403:403) (480:480:480)) + (PORT d[2] (412:412:412) (478:478:478)) + (PORT d[3] (435:435:435) (514:514:514)) + (PORT d[4] (740:740:740) (866:866:866)) + (PORT d[5] (478:478:478) (564:564:564)) + (PORT d[6] (741:741:741) (862:862:862)) + (PORT d[7] (417:417:417) (488:488:488)) + (PORT d[8] (416:416:416) (489:489:489)) + (PORT d[9] (421:421:421) (498:498:498)) + (PORT d[10] (431:431:431) (512:512:512)) + (PORT d[11] (443:443:443) (519:519:519)) + (PORT d[12] (999:999:999) (1182:1182:1182)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (377:377:377) (394:394:394)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (605:605:605)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (634:634:634) (718:718:718)) + (PORT datad (562:562:562) (634:634:634)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1549:1549:1549) (1753:1753:1753)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (591:591:591) (704:704:704)) + (PORT d[1] (598:598:598) (715:715:715)) + (PORT d[2] (600:600:600) (709:709:709)) + (PORT d[3] (604:604:604) (716:716:716)) + (PORT d[4] (590:590:590) (696:696:696)) + (PORT d[5] (1038:1038:1038) (1216:1216:1216)) + (PORT d[6] (744:744:744) (864:864:864)) + (PORT d[7] (695:695:695) (802:802:802)) + (PORT d[8] (602:602:602) (704:704:704)) + (PORT d[9] (616:616:616) (723:723:723)) + (PORT d[10] (591:591:591) (700:700:700)) + (PORT d[11] (612:612:612) (713:713:713)) + (PORT d[12] (637:637:637) (756:756:756)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (457:457:457) (484:484:484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (668:668:668) (768:768:768)) + (PORT clk (1096:1096:1096) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (916:916:916) (1068:1068:1068)) + (PORT d[1] (944:944:944) (1116:1116:1116)) + (PORT d[2] (1090:1090:1090) (1262:1262:1262)) + (PORT d[3] (970:970:970) (1138:1138:1138)) + (PORT d[4] (1093:1093:1093) (1273:1273:1273)) + (PORT d[5] (842:842:842) (985:985:985)) + (PORT d[6] (967:967:967) (1137:1137:1137)) + (PORT d[7] (1247:1247:1247) (1435:1435:1435)) + (PORT d[8] (1166:1166:1166) (1353:1353:1353)) + (PORT d[9] (1166:1166:1166) (1359:1359:1359)) + (PORT d[10] (820:820:820) (978:978:978)) + (PORT d[11] (1231:1231:1231) (1411:1411:1411)) + (PORT d[12] (1024:1024:1024) (1207:1207:1207)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1112:1112:1112)) + (PORT d[0] (596:596:596) (654:654:654)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (559:559:559)) + (PORT datab (165:165:165) (222:222:222)) + (PORT datac (859:859:859) (1011:1011:1011)) + (PORT datad (823:823:823) (949:949:949)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1914:1914:1914) (2164:2164:2164)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (769:769:769) (901:901:901)) + (PORT d[1] (747:747:747) (873:873:873)) + (PORT d[2] (883:883:883) (1016:1016:1016)) + (PORT d[3] (983:983:983) (1158:1158:1158)) + (PORT d[4] (781:781:781) (919:919:919)) + (PORT d[5] (834:834:834) (979:979:979)) + (PORT d[6] (945:945:945) (1090:1090:1090)) + (PORT d[7] (901:901:901) (1043:1043:1043)) + (PORT d[8] (796:796:796) (928:928:928)) + (PORT d[9] (807:807:807) (939:939:939)) + (PORT d[10] (787:787:787) (940:940:940)) + (PORT d[11] (891:891:891) (1027:1027:1027)) + (PORT d[12] (1017:1017:1017) (1205:1205:1205)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (637:637:637) (684:684:684)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1372:1372:1372) (1553:1553:1553)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (745:745:745) (876:876:876)) + (PORT d[1] (748:748:748) (880:880:880)) + (PORT d[2] (743:743:743) (864:864:864)) + (PORT d[3] (792:792:792) (929:929:929)) + (PORT d[4] (882:882:882) (1021:1021:1021)) + (PORT d[5] (732:732:732) (845:845:845)) + (PORT d[6] (734:734:734) (852:852:852)) + (PORT d[7] (843:843:843) (967:967:967)) + (PORT d[8] (763:763:763) (884:884:884)) + (PORT d[9] (760:760:760) (878:878:878)) + (PORT d[10] (747:747:747) (874:874:874)) + (PORT d[11] (769:769:769) (889:889:889)) + (PORT d[12] (754:754:754) (880:880:880)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (561:561:561) (601:601:601)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (164:164:164) (222:222:222)) + (PORT datac (643:643:643) (739:739:739)) + (PORT datad (597:597:597) (678:678:678)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (594:594:594)) + (PORT datac (393:393:393) (475:475:475)) + (PORT datad (346:346:346) (400:400:400)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (674:674:674)) + (PORT datac (336:336:336) (382:382:382)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (622:622:622)) + (PORT datab (564:564:564) (672:672:672)) + (PORT datad (865:865:865) (1021:1021:1021)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (675:675:675)) + (PORT datac (358:358:358) (408:408:408)) + (PORT datad (350:350:350) (403:403:403)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (568:568:568) (676:676:676)) + (PORT datac (740:740:740) (826:826:826)) + (PORT datad (352:352:352) (402:402:402)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (425:425:425)) + (PORT datac (552:552:552) (656:656:656)) + (PORT datad (361:361:361) (417:417:417)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1104:1104:1104) (1288:1288:1288)) + (PORT datac (358:358:358) (413:413:413)) + (PORT datad (185:185:185) (215:215:215)) (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (609:609:609)) + (PORT datac (548:548:548) (651:651:651)) + (PORT datad (614:614:614) (693:693:693)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index ff9bb97..318abe8 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -6,6 +6,8 @@ source_file = 1, /home/benny/work/fpga/projects/rom0.qip source_file = 1, /home/benny/work/fpga/projects/rom0.v source_file = 1, /home/benny/work/fpga/projects/ram16.qip source_file = 1, /home/benny/work/fpga/projects/ram16.v +source_file = 1, /home/benny/work/fpga/projects/ram32.qip +source_file = 1, /home/benny/work/fpga/projects/ram32.v source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc @@ -23,6 +25,10 @@ source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf source_file = 1, /home/benny/work/fpga/projects/db/decode_jsa.tdf +source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf +source_file = 1, /home/benny/work/fpga/projects/db/decode_msa.tdf +source_file = 1, /home/benny/work/fpga/projects/db/decode_f8a.tdf +source_file = 1, /home/benny/work/fpga/projects/db/mux_6nb.tdf design_name = spectrum instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 @@ -32,6 +38,40 @@ instance = comp, \LED[4]~output , LED[4]~output, spectrum, 1 instance = comp, \LED[5]~output , LED[5]~output, spectrum, 1 instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1 instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1 +instance = comp, \GPIO_0[0]~output , GPIO_0[0]~output, spectrum, 1 +instance = comp, \GPIO_0[1]~output , GPIO_0[1]~output, spectrum, 1 +instance = comp, \GPIO_0[2]~output , GPIO_0[2]~output, spectrum, 1 +instance = comp, \GPIO_0[3]~output , GPIO_0[3]~output, spectrum, 1 +instance = comp, \GPIO_0[4]~output , GPIO_0[4]~output, spectrum, 1 +instance = comp, \GPIO_0[5]~output , GPIO_0[5]~output, spectrum, 1 +instance = comp, \GPIO_0[6]~output , GPIO_0[6]~output, spectrum, 1 +instance = comp, \GPIO_0[7]~output , GPIO_0[7]~output, spectrum, 1 +instance = comp, \GPIO_0[8]~output , GPIO_0[8]~output, spectrum, 1 +instance = comp, \GPIO_0[9]~output , GPIO_0[9]~output, spectrum, 1 +instance = comp, \GPIO_0[10]~output , GPIO_0[10]~output, spectrum, 1 +instance = comp, \GPIO_0[11]~output , GPIO_0[11]~output, spectrum, 1 +instance = comp, \GPIO_0[12]~output , GPIO_0[12]~output, spectrum, 1 +instance = comp, \GPIO_0[13]~output , GPIO_0[13]~output, spectrum, 1 +instance = comp, \GPIO_0[14]~output , GPIO_0[14]~output, spectrum, 1 +instance = comp, \GPIO_0[15]~output , GPIO_0[15]~output, spectrum, 1 +instance = comp, \GPIO_0[16]~output , GPIO_0[16]~output, spectrum, 1 +instance = comp, \GPIO_0[17]~output , GPIO_0[17]~output, spectrum, 1 +instance = comp, \GPIO_0[18]~output , GPIO_0[18]~output, spectrum, 1 +instance = comp, \GPIO_0[19]~output , GPIO_0[19]~output, spectrum, 1 +instance = comp, \GPIO_0[20]~output , GPIO_0[20]~output, spectrum, 1 +instance = comp, \GPIO_0[21]~output , GPIO_0[21]~output, spectrum, 1 +instance = comp, \GPIO_0[22]~output , GPIO_0[22]~output, spectrum, 1 +instance = comp, \GPIO_0[23]~output , GPIO_0[23]~output, spectrum, 1 +instance = comp, \GPIO_0[24]~output , GPIO_0[24]~output, spectrum, 1 +instance = comp, \GPIO_0[25]~output , GPIO_0[25]~output, spectrum, 1 +instance = comp, \GPIO_0[26]~output , GPIO_0[26]~output, spectrum, 1 +instance = comp, \GPIO_0[27]~output , GPIO_0[27]~output, spectrum, 1 +instance = comp, \GPIO_0[28]~output , GPIO_0[28]~output, spectrum, 1 +instance = comp, \GPIO_0[29]~output , GPIO_0[29]~output, spectrum, 1 +instance = comp, \GPIO_0[30]~output , GPIO_0[30]~output, spectrum, 1 +instance = comp, \GPIO_0[31]~output , GPIO_0[31]~output, spectrum, 1 +instance = comp, \GPIO_0[32]~output , GPIO_0[32]~output, spectrum, 1 +instance = comp, \GPIO_0[33]~output , GPIO_0[33]~output, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 instance = comp, \counter[0]~63 , counter[0]~63, spectrum, 1 @@ -78,59 +118,158 @@ instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1 instance = comp, \counter[20] , counter[20], spectrum, 1 instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1 instance = comp, \counter[21] , counter[21], spectrum, 1 +instance = comp, \Equal0~7 , Equal0~7, spectrum, 1 instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 -instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 -instance = comp, \A[0]~39 , A[0]~39, spectrum, 1 +instance = comp, \A[0]~40 , A[0]~40, spectrum, 1 instance = comp, \A[0] , A[0], spectrum, 1 -instance = comp, \A[1]~13 , A[1]~13, spectrum, 1 +instance = comp, \A[1]~14 , A[1]~14, spectrum, 1 +instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 instance = comp, \A[1] , A[1], spectrum, 1 -instance = comp, \A[2]~15 , A[2]~15, spectrum, 1 +instance = comp, \A[2]~16 , A[2]~16, spectrum, 1 instance = comp, \A[2] , A[2], spectrum, 1 -instance = comp, \A[3]~17 , A[3]~17, spectrum, 1 +instance = comp, \A[3]~18 , A[3]~18, spectrum, 1 instance = comp, \A[3] , A[3], spectrum, 1 -instance = comp, \A[4]~19 , A[4]~19, spectrum, 1 +instance = comp, \A[4]~20 , A[4]~20, spectrum, 1 instance = comp, \A[4] , A[4], spectrum, 1 -instance = comp, \A[5]~21 , A[5]~21, spectrum, 1 +instance = comp, \A[5]~22 , A[5]~22, spectrum, 1 instance = comp, \A[5] , A[5], spectrum, 1 -instance = comp, \A[6]~23 , A[6]~23, spectrum, 1 +instance = comp, \A[6]~24 , A[6]~24, spectrum, 1 instance = comp, \A[6] , A[6], spectrum, 1 -instance = comp, \A[7]~25 , A[7]~25, spectrum, 1 +instance = comp, \A[7]~26 , A[7]~26, spectrum, 1 instance = comp, \A[7] , A[7], spectrum, 1 -instance = comp, \A[8]~27 , A[8]~27, spectrum, 1 +instance = comp, \A[8]~28 , A[8]~28, spectrum, 1 instance = comp, \A[8] , A[8], spectrum, 1 -instance = comp, \A[9]~29 , A[9]~29, spectrum, 1 +instance = comp, \A[9]~30 , A[9]~30, spectrum, 1 instance = comp, \A[9] , A[9], spectrum, 1 -instance = comp, \A[10]~31 , A[10]~31, spectrum, 1 +instance = comp, \A[10]~32 , A[10]~32, spectrum, 1 instance = comp, \A[10] , A[10], spectrum, 1 -instance = comp, \A[11]~33 , A[11]~33, spectrum, 1 +instance = comp, \A[11]~34 , A[11]~34, spectrum, 1 instance = comp, \A[11] , A[11], spectrum, 1 -instance = comp, \A[12]~35 , A[12]~35, spectrum, 1 +instance = comp, \A[12]~36 , A[12]~36, spectrum, 1 instance = comp, \A[12] , A[12], spectrum, 1 -instance = comp, \A[13]~37 , A[13]~37, spectrum, 1 +instance = comp, \A[13]~38 , A[13]~38, spectrum, 1 instance = comp, \A[13] , A[13], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[3]~3, spectrum, 1 instance = comp, \~GND , ~GND, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 , ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 , ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 , ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 , ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~4, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~2, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~6, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 , ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 , ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 , ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 , ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7, spectrum, 1 +instance = comp, \A[14]~41 , A[14]~41, spectrum, 1 +instance = comp, \A[14] , A[14], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] , ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder , ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder , ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 , ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 , ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 , ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 , ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 , ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 , ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 , ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 , ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 074a56c..75d2580 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:47:24") + (DATE "03/30/2022 14:56:19") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2240:2240:2240) (2288:2288:2288)) + (PORT i (1079:1079:1079) (1118:1118:1118)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2683:2683:2683) (2776:2776:2776)) + (PORT i (1927:1927:1927) (1971:1971:1971)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2672:2672:2672) (2728:2728:2728)) + (PORT i (1553:1553:1553) (1570:1570:1570)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1887:1887:1887) (1922:1922:1922)) + (PORT i (2547:2547:2547) (2782:2782:2782)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2419:2419:2419) (2498:2498:2498)) + (PORT i (1256:1256:1256) (1326:1326:1326)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1958:1958:1958) (2059:2059:2059)) + (PORT i (1315:1315:1315) (1355:1355:1355)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2348:2348:2348) (2361:2361:2361)) + (PORT i (1625:1625:1625) (1695:1695:1695)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,11 +111,331 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1275:1275:1275) (1275:1275:1275)) + (PORT i (1490:1490:1490) (1603:1603:1603)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1423:1423:1423) (1461:1461:1461)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1507:1507:1507) (1522:1522:1522)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1054:1054:1054) (1041:1041:1041)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1986:1986:1986) (2103:2103:2103)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1427:1427:1427) (1432:1432:1432)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1282:1282:1282) (1273:1273:1273)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1710:1710:1710) (1721:1721:1721)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1242:1242:1242) (1238:1238:1238)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1805:1805:1805) (1868:1868:1868)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1456:1456:1456) (1507:1507:1507)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (985:985:985) (976:976:976)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1324:1324:1324) (1362:1362:1362)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1106:1106:1106) (1123:1123:1123)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1331:1331:1331) (1387:1387:1387)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1729:1729:1729) (1767:1767:1767)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1595:1595:1595) (1671:1671:1671)) + (IOPATH i o (4557:4557:4557) (4190:4190:4190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[16\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2420:2420:2420) (2529:2529:2529)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[17\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2351:2351:2351) (2435:2435:2435)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[18\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2730:2730:2730) (2802:2802:2802)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[19\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1903:1903:1903) (1989:1989:1989)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[20\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1900:1900:1900) (1959:1959:1959)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[21\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2199:2199:2199) (2286:2286:2286)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[22\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2004:2004:2004) (2002:2002:2002)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[23\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2135:2135:2135) (2240:2240:2240)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[24\]\~output) + (DELAY + (ABSOLUTE + (PORT i (845:845:845) (883:883:883)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[25\]\~output) + (DELAY + (ABSOLUTE + (PORT i (812:812:812) (809:809:809)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[26\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1171:1171:1171) (1139:1139:1139)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[27\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1042:1042:1042) (1061:1061:1061)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[28\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1020:1020:1020) (1007:1007:1007)) + (IOPATH i o (4557:4557:4557) (4190:4190:4190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[29\]\~output) + (DELAY + (ABSOLUTE + (PORT i (988:988:988) (994:994:994)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[30\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1458:1458:1458) (1462:1462:1462)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE GPIO_0\[31\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1426:1426:1426) (1430:1430:1430)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -148,7 +468,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -177,7 +497,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -205,7 +525,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -233,7 +553,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -247,7 +567,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -261,7 +581,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -275,7 +595,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (263:263:263) (346:346:346)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -289,7 +609,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -317,7 +637,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -331,7 +651,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (262:262:262) (344:344:344)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -345,7 +665,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -359,7 +679,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (350:350:350)) + (PORT dataa (251:251:251) (341:341:341)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -373,7 +693,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -387,7 +707,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (262:262:262) (344:344:344)) + (PORT datab (250:250:250) (334:334:334)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -401,7 +721,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -415,7 +735,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (350:350:350)) + (PORT dataa (252:252:252) (340:340:340)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -429,7 +749,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -457,7 +777,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -471,7 +791,7 @@ (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) + (PORT datab (409:409:409) (473:473:473)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -485,7 +805,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -513,7 +833,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -541,7 +861,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -555,9 +875,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (479:479:479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -569,7 +889,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -597,7 +917,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -625,7 +945,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -653,7 +973,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -681,7 +1001,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -709,7 +1029,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -734,7 +1054,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -743,14 +1063,26 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (771:771:771)) + (PORT datac (699:699:699) (751:751:751)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (253:253:253) (343:343:343)) (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (302:302:302)) + (PORT datac (224:224:224) (303:303:303)) (PORT datad (225:225:225) (298:298:298)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -764,10 +1096,10 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datab (249:249:249) (334:334:334)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (250:250:250) (335:335:335)) (PORT datac (223:223:223) (301:301:301)) - (PORT datad (224:224:224) (296:296:296)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -780,9 +1112,9 @@ (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (381:381:381) (442:442:442)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (380:380:380) (441:441:441)) (PORT datad (226:226:226) (299:299:299)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -796,10 +1128,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (406:406:406) (480:480:480)) - (PORT datac (566:566:566) (611:611:611)) - (PORT datad (576:576:576) (620:620:620)) + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (306:306:306)) + (PORT datad (382:382:382) (438:438:438)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -812,10 +1144,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (238:238:238) (315:315:315)) - (PORT datad (228:228:228) (300:300:300)) + (PORT dataa (255:255:255) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (239:239:239) (316:316:316)) + (PORT datad (240:240:240) (310:310:310)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -829,9 +1161,9 @@ (DELAY (ABSOLUTE (PORT dataa (388:388:388) (416:416:416)) - (PORT datab (345:345:345) (380:380:380)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (640:640:640) (652:652:652)) + (PORT datab (348:348:348) (385:385:385)) + (PORT datac (348:348:348) (372:372:372)) + (PORT datad (612:612:612) (622:622:622)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -841,26 +1173,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~6) + (INSTANCE A\[0\]\~40) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (955:955:955)) - (PORT datab (926:926:926) (973:973:973)) - (PORT datac (615:615:615) (635:635:635)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT datad (330:330:330) (344:344:344)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (634:634:634) (650:650:650)) + (PORT datad (356:356:356) (373:373:373)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -871,7 +1191,7 @@ (INSTANCE A\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -882,11 +1202,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[1\]\~13) + (INSTANCE A\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (449:449:449) (522:522:522)) - (PORT datab (618:618:618) (683:683:683)) + (PORT dataa (454:454:454) (533:533:533)) + (PORT datab (446:446:446) (522:522:522)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -895,14 +1215,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (951:951:951)) + (PORT datab (672:672:672) (743:743:743)) + (PORT datac (574:574:574) (595:595:595)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE A\[1\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -913,7 +1249,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[2\]\~15) + (INSTANCE A\[2\]\~16) (DELAY (ABSOLUTE (PORT datab (261:261:261) (343:343:343)) @@ -930,9 +1266,9 @@ (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -943,7 +1279,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[3\]\~17) + (INSTANCE A\[3\]\~18) (DELAY (ABSOLUTE (PORT datab (262:262:262) (344:344:344)) @@ -960,9 +1296,9 @@ (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -973,10 +1309,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[4\]\~19) + (INSTANCE A\[4\]\~20) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (351:351:351)) + (PORT dataa (264:264:264) (351:351:351)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -990,9 +1326,9 @@ (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (830:830:830) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1003,10 +1339,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[5\]\~21) + (INSTANCE A\[5\]\~22) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (345:345:345)) + (PORT datab (283:283:283) (365:365:365)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1020,9 +1356,9 @@ (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1033,10 +1369,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[6\]\~23) + (INSTANCE A\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) + (PORT dataa (285:285:285) (373:373:373)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1050,9 +1386,9 @@ (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1063,10 +1399,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[7\]\~25) + (INSTANCE A\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) + (PORT dataa (285:285:285) (373:373:373)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1080,9 +1416,9 @@ (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1093,12 +1429,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[8\]\~27) + (INSTANCE A\[8\]\~28) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (480:480:480)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1110,9 +1446,9 @@ (INSTANCE A\[8\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1123,10 +1459,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[9\]\~29) + (INSTANCE A\[9\]\~30) (DELAY (ABSOLUTE - (PORT datab (284:284:284) (367:367:367)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1140,9 +1476,9 @@ (INSTANCE A\[9\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1153,7 +1489,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[10\]\~31) + (INSTANCE A\[10\]\~32) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1170,9 +1506,9 @@ (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1183,10 +1519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[11\]\~33) + (INSTANCE A\[11\]\~34) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) + (PORT datab (284:284:284) (368:368:368)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1200,9 +1536,9 @@ (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1213,7 +1549,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[12\]\~35) + (INSTANCE A\[12\]\~36) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (352:352:352)) @@ -1230,9 +1566,9 @@ (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1889:1889:1889) (1911:1911:1911)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (803:803:803) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1243,12 +1579,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE A\[13\]\~37) + (INSTANCE A\[13\]\~38) (DELAY (ABSOLUTE - (PORT datad (258:258:258) (327:327:327)) + (PORT datab (283:283:283) (366:366:366)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -1257,9 +1596,9 @@ (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (816:816:816) (814:814:814)) + (PORT ena (830:830:830) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1270,11 +1609,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1043:1043:1043) (1097:1097:1097)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (2043:2043:2043) (2263:2263:2263)) + (PORT d[1] (2019:2019:2019) (2202:2202:2202)) + (PORT d[2] (1854:1854:1854) (2009:2009:2009)) + (PORT d[3] (2468:2468:2468) (2633:2633:2633)) + (PORT d[4] (2187:2187:2187) (2357:2357:2357)) + (PORT d[5] (2172:2172:2172) (2317:2317:2317)) + (PORT d[6] (2138:2138:2138) (2285:2285:2285)) + (PORT d[7] (2050:2050:2050) (2279:2279:2279)) + (PORT d[8] (2347:2347:2347) (2486:2486:2486)) + (PORT d[9] (2169:2169:2169) (2346:2346:2346)) + (PORT d[10] (2278:2278:2278) (2456:2456:2456)) + (PORT d[11] (2295:2295:2295) (2429:2429:2429)) + (PORT d[12] (2349:2349:2349) (2504:2504:2504)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -1283,84 +1634,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1047:1047:1047) (1146:1146:1146)) - (PORT d[1] (1492:1492:1492) (1562:1562:1562)) - (PORT d[2] (954:954:954) (1036:1036:1036)) - (PORT d[3] (1018:1018:1018) (1075:1075:1075)) - (PORT d[4] (1018:1018:1018) (1075:1075:1075)) - (PORT d[5] (783:783:783) (838:838:838)) - (PORT d[6] (783:783:783) (838:838:838)) - (PORT d[7] (783:783:783) (838:838:838)) - (PORT d[8] (783:783:783) (838:838:838)) - (PORT d[9] (783:783:783) (838:838:838)) - (PORT d[10] (783:783:783) (838:838:838)) - (PORT d[11] (783:783:783) (838:838:838)) - (PORT d[12] (783:783:783) (838:838:838)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (1825:1825:1825) (1943:1943:1943)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT clk (1858:1858:1858) (1883:1883:1883)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1813:1813:1813) (1809:1809:1809)) + (PORT clk (1820:1820:1820) (1845:1845:1845)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1371,98 +1668,109 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1102:1102:1102)) - (PORT clk (1823:1823:1823) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1028:1028:1028) (1127:1127:1127)) - (PORT d[1] (1493:1493:1493) (1562:1562:1562)) - (PORT d[2] (979:979:979) (1058:1058:1058)) - (PORT d[3] (1250:1250:1250) (1312:1312:1312)) - (PORT d[4] (967:967:967) (1025:1025:1025)) - (PORT d[5] (1558:1558:1558) (1643:1643:1643)) - (PORT d[6] (1237:1237:1237) (1323:1323:1323)) - (PORT d[7] (1284:1284:1284) (1363:1363:1363)) - (PORT d[8] (1214:1214:1214) (1273:1273:1273)) - (PORT d[9] (1235:1235:1235) (1302:1302:1302)) - (PORT d[10] (1250:1250:1250) (1318:1318:1318)) - (PORT d[11] (1232:1232:1232) (1314:1314:1314)) - (PORT d[12] (1287:1287:1287) (1358:1358:1358)) - (PORT clk (1819:1819:1819) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1815:1815:1815)) - (PORT d[0] (903:903:903) (890:890:890)) + (PORT clk (1005:1005:1005) (1008:1008:1008)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1816:1816:1816)) + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT d[0] (1006:1006:1006) (1061:1061:1061)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT datac (1619:1619:1619) (1769:1769:1769)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2095:2095:2095) (2299:2299:2299)) + (PORT d[1] (1981:1981:1981) (2171:2171:2171)) + (PORT d[2] (2178:2178:2178) (2333:2333:2333)) + (PORT d[3] (2235:2235:2235) (2394:2394:2394)) + (PORT d[4] (2150:2150:2150) (2298:2298:2298)) + (PORT d[5] (2138:2138:2138) (2260:2260:2260)) + (PORT d[6] (2153:2153:2153) (2309:2309:2309)) + (PORT d[7] (2077:2077:2077) (2297:2297:2297)) + (PORT d[8] (2333:2333:2333) (2484:2484:2484)) + (PORT d[9] (2128:2128:2128) (2284:2284:2284)) + (PORT d[10] (1989:1989:1989) (2169:2169:2169)) + (PORT d[11] (2292:2292:2292) (2429:2429:2429)) + (PORT d[12] (2279:2279:2279) (2438:2438:2438)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -1471,84 +1779,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1030:1030:1030) (1132:1132:1132)) - (PORT d[1] (1194:1194:1194) (1270:1270:1270)) - (PORT d[2] (957:957:957) (1039:1039:1039)) - (PORT d[3] (1025:1025:1025) (1086:1086:1086)) - (PORT d[4] (1025:1025:1025) (1086:1086:1086)) - (PORT d[5] (813:813:813) (881:881:881)) - (PORT d[6] (813:813:813) (881:881:881)) - (PORT d[7] (813:813:813) (881:881:881)) - (PORT d[8] (813:813:813) (881:881:881)) - (PORT d[9] (813:813:813) (881:881:881)) - (PORT d[10] (813:813:813) (881:881:881)) - (PORT d[11] (813:813:813) (881:881:881)) - (PORT d[12] (813:813:813) (881:881:881)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1788:1788:1788) (1705:1705:1705)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1811:1811:1811) (1808:1808:1808)) + (PORT clk (1812:1812:1812) (1839:1839:1839)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1559,98 +1813,75 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1011:1011:1011) (1066:1066:1066)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1054:1054:1054) (1156:1156:1156)) - (PORT d[1] (960:960:960) (1039:1039:1039)) - (PORT d[2] (1276:1276:1276) (1350:1350:1350)) - (PORT d[3] (1249:1249:1249) (1279:1279:1279)) - (PORT d[4] (941:941:941) (1014:1014:1014)) - (PORT d[5] (1553:1553:1553) (1633:1633:1633)) - (PORT d[6] (1275:1275:1275) (1334:1334:1334)) - (PORT d[7] (1286:1286:1286) (1364:1364:1364)) - (PORT d[8] (1442:1442:1442) (1487:1487:1487)) - (PORT d[9] (1239:1239:1239) (1309:1309:1309)) - (PORT d[10] (1259:1259:1259) (1333:1333:1333)) - (PORT d[11] (1243:1243:1243) (1305:1305:1305)) - (PORT d[12] (1271:1271:1271) (1318:1318:1318)) - (PORT clk (1817:1817:1817) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1814:1814:1814)) - (PORT d[0] (908:908:908) (894:894:894)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (998:998:998) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (998:998:998) (1003:1003:1003)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (998:998:998) (1003:1003:1003)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (1352:1352:1352) (1400:1400:1400)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT dataa (925:925:925) (930:930:930)) + (PORT datab (2498:2498:2498) (2712:2712:2712)) + (PORT datac (903:903:903) (906:906:906)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2065:2065:2065) (2268:2268:2268)) + (PORT d[1] (1940:1940:1940) (2074:2074:2074)) + (PORT d[2] (2079:2079:2079) (2206:2206:2206)) + (PORT d[3] (2222:2222:2222) (2377:2377:2377)) + (PORT d[4] (2175:2175:2175) (2348:2348:2348)) + (PORT d[5] (1890:1890:1890) (2010:2010:2010)) + (PORT d[6] (1854:1854:1854) (1985:1985:1985)) + (PORT d[7] (2198:2198:2198) (2368:2368:2368)) + (PORT d[8] (1757:1757:1757) (1867:1867:1867)) + (PORT d[9] (2154:2154:2154) (2298:2298:2298)) + (PORT d[10] (1641:1641:1641) (1806:1806:1806)) + (PORT d[11] (2317:2317:2317) (2449:2449:2449)) + (PORT d[12] (1976:1976:1976) (2131:2131:2131)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) ) ) (TIMINGCHECK @@ -1659,84 +1890,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1071:1071:1071) (1146:1146:1146)) - (PORT d[1] (935:935:935) (1004:1004:1004)) - (PORT d[2] (1531:1531:1531) (1621:1621:1621)) - (PORT d[3] (1349:1349:1349) (1401:1401:1401)) - (PORT d[4] (1349:1349:1349) (1401:1401:1401)) - (PORT d[5] (773:773:773) (814:814:814)) - (PORT d[6] (773:773:773) (814:814:814)) - (PORT d[7] (773:773:773) (814:814:814)) - (PORT d[8] (773:773:773) (814:814:814)) - (PORT d[9] (773:773:773) (814:814:814)) - (PORT d[10] (773:773:773) (814:814:814)) - (PORT d[11] (773:773:773) (814:814:814)) - (PORT d[12] (773:773:773) (814:814:814)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT d[0] (1789:1789:1789) (1707:1707:1707)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) + (PORT clk (1808:1808:1808) (1835:1835:1835)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -1747,297 +1924,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1357:1357:1357) (1405:1405:1405)) - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1049:1049:1049) (1122:1122:1122)) - (PORT d[1] (1503:1503:1503) (1591:1591:1591)) - (PORT d[2] (917:917:917) (979:979:979)) - (PORT d[3] (1464:1464:1464) (1521:1521:1521)) - (PORT d[4] (935:935:935) (996:996:996)) - (PORT d[5] (1058:1058:1058) (1128:1128:1128)) - (PORT d[6] (1250:1250:1250) (1319:1319:1319)) - (PORT d[7] (1047:1047:1047) (1105:1105:1105)) - (PORT d[8] (1486:1486:1486) (1542:1542:1542)) - (PORT d[9] (1254:1254:1254) (1312:1312:1312)) - (PORT d[10] (1242:1242:1242) (1297:1297:1297)) - (PORT d[11] (1250:1250:1250) (1319:1319:1319)) - (PORT d[12] (1251:1251:1251) (1299:1299:1299)) - (PORT clk (1820:1820:1820) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1817:1817:1817)) - (PORT d[0] (880:880:880) (882:882:882)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (994:994:994) (999:999:999)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT clk (994:994:994) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT clk (994:994:994) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1362:1362:1362) (1429:1429:1429)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (762:762:762) (824:824:824)) - (PORT d[1] (644:644:644) (706:706:706)) - (PORT d[2] (1543:1543:1543) (1614:1614:1614)) - (PORT d[3] (664:664:664) (693:693:693)) - (PORT d[4] (664:664:664) (693:693:693)) - (PORT d[5] (484:484:484) (522:522:522)) - (PORT d[6] (484:484:484) (522:522:522)) - (PORT d[7] (484:484:484) (522:522:522)) - (PORT d[8] (484:484:484) (522:522:522)) - (PORT d[9] (484:484:484) (522:522:522)) - (PORT d[10] (484:484:484) (522:522:522)) - (PORT d[11] (484:484:484) (522:522:522)) - (PORT d[12] (484:484:484) (522:522:522)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1367:1367:1367) (1434:1434:1434)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (735:735:735) (812:812:812)) - (PORT d[1] (1534:1534:1534) (1599:1599:1599)) - (PORT d[2] (1545:1545:1545) (1615:1615:1615)) - (PORT d[3] (659:659:659) (709:709:709)) - (PORT d[4] (664:664:664) (725:725:725)) - (PORT d[5] (722:722:722) (794:794:794)) - (PORT d[6] (766:766:766) (839:839:839)) - (PORT d[7] (749:749:749) (827:827:827)) - (PORT d[8] (1517:1517:1517) (1590:1590:1590)) - (PORT d[9] (761:761:761) (822:822:822)) - (PORT d[10] (979:979:979) (1037:1037:1037)) - (PORT d[11] (734:734:734) (803:803:803)) - (PORT d[12] (940:940:940) (991:991:991)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (PORT d[0] (628:628:628) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1580:1580:1580) (1693:1693:1693)) - (PORT d[1] (1272:1272:1272) (1354:1354:1354)) - (PORT d[2] (1245:1245:1245) (1308:1308:1308)) - (PORT d[3] (1263:1263:1263) (1339:1339:1339)) - (PORT d[4] (1283:1283:1283) (1370:1370:1370)) - (PORT d[5] (1569:1569:1569) (1701:1701:1701)) - (PORT d[6] (1243:1243:1243) (1329:1329:1329)) - (PORT d[7] (1231:1231:1231) (1310:1310:1310)) - (PORT d[8] (1267:1267:1267) (1363:1363:1363)) - (PORT d[9] (1273:1273:1273) (1361:1361:1361)) - (PORT d[10] (1275:1275:1275) (1366:1366:1366)) - (PORT d[11] (1259:1259:1259) (1344:1344:1344)) - (PORT d[12] (1532:1532:1532) (1614:1614:1614)) + (PORT d[0] (2019:2019:2019) (2227:2227:2227)) + (PORT d[1] (1947:1947:1947) (2115:2115:2115)) + (PORT d[2] (2170:2170:2170) (2334:2334:2334)) + (PORT d[3] (2218:2218:2218) (2359:2359:2359)) + (PORT d[4] (2158:2158:2158) (2329:2329:2329)) + (PORT d[5] (1630:1630:1630) (1742:1742:1742)) + (PORT d[6] (2095:2095:2095) (2239:2239:2239)) + (PORT d[7] (2150:2150:2150) (2292:2292:2292)) + (PORT d[8] (2149:2149:2149) (2291:2291:2291)) + (PORT d[9] (2220:2220:2220) (2350:2350:2350)) + (PORT d[10] (1655:1655:1655) (1834:1834:1834)) + (PORT d[11] (2184:2184:2184) (2353:2353:2353)) + (PORT d[12] (2144:2144:2144) (2362:2362:2362)) (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) @@ -2047,17 +1987,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1172:1172:1172) (1188:1188:1188)) + (PORT d[0] (1680:1680:1680) (1746:1746:1746)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) @@ -2067,7 +2007,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1837:1837:1837)) @@ -2081,7 +2021,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (1000:1000:1000)) @@ -2090,7 +2030,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2099,7 +2039,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2109,7 +2049,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2117,25 +2057,39 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (993:993:993)) + (PORT datac (927:927:927) (988:988:988)) + (PORT datad (2737:2737:2737) (2929:2929:2929)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1320:1320:1320) (1440:1440:1440)) - (PORT d[1] (1259:1259:1259) (1353:1353:1353)) - (PORT d[2] (1264:1264:1264) (1323:1323:1323)) - (PORT d[3] (1324:1324:1324) (1419:1419:1419)) - (PORT d[4] (1316:1316:1316) (1418:1418:1418)) - (PORT d[5] (1564:1564:1564) (1691:1691:1691)) - (PORT d[6] (1229:1229:1229) (1326:1326:1326)) - (PORT d[7] (1239:1239:1239) (1332:1332:1332)) - (PORT d[8] (1280:1280:1280) (1393:1393:1393)) - (PORT d[9] (1254:1254:1254) (1351:1351:1351)) - (PORT d[10] (1258:1258:1258) (1357:1357:1357)) - (PORT d[11] (1267:1267:1267) (1367:1367:1367)) - (PORT d[12] (1266:1266:1266) (1351:1351:1351)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (2114:2114:2114) (2311:2311:2311)) + (PORT d[1] (1686:1686:1686) (1848:1848:1848)) + (PORT d[2] (2168:2168:2168) (2314:2314:2314)) + (PORT d[3] (2251:2251:2251) (2410:2410:2410)) + (PORT d[4] (2142:2142:2142) (2284:2284:2284)) + (PORT d[5] (1925:1925:1925) (2063:2063:2063)) + (PORT d[6] (2081:2081:2081) (2241:2241:2241)) + (PORT d[7] (2063:2063:2063) (2296:2296:2296)) + (PORT d[8] (2131:2131:2131) (2296:2296:2296)) + (PORT d[9] (2131:2131:2131) (2289:2289:2289)) + (PORT d[10] (1732:1732:1732) (1913:1913:1913)) + (PORT d[11] (2308:2308:2308) (2449:2449:2449)) + (PORT d[12] (2190:2190:2190) (2407:2407:2407)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -2144,30 +2098,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1872:1872:1872)) - (PORT d[0] (1215:1215:1215) (1202:1202:1202)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1818:1818:1818) (1733:1733:1733)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1806:1806:1806) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2178,122 +2132,171 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (991:991:991) (997:997:997)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (992:992:992) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2045:2045:2045) (2260:2260:2260)) + (PORT d[1] (2023:2023:2023) (2209:2209:2209)) + (PORT d[2] (1962:1962:1962) (2121:2121:2121)) + (PORT d[3] (2465:2465:2465) (2628:2628:2628)) + (PORT d[4] (2184:2184:2184) (2381:2381:2381)) + (PORT d[5] (1958:1958:1958) (2089:2089:2089)) + (PORT d[6] (2196:2196:2196) (2345:2345:2345)) + (PORT d[7] (2053:2053:2053) (2286:2286:2286)) + (PORT d[8] (2335:2335:2335) (2452:2452:2452)) + (PORT d[9] (2180:2180:2180) (2364:2364:2364)) + (PORT d[10] (2313:2313:2313) (2485:2485:2485)) + (PORT d[11] (2298:2298:2298) (2430:2430:2430)) + (PORT d[12] (2225:2225:2225) (2392:2392:2392)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (1894:1894:1894) (2005:2005:2005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (643:643:643) (706:706:706)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (628:628:628) (637:637:637)) - (PORT datac (922:922:922) (922:922:922)) - (PORT datad (973:973:973) (1040:1040:1040)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (964:964:964) (1029:1029:1029)) + (PORT datac (2401:2401:2401) (2590:2590:2590)) + (PORT datad (348:348:348) (364:364:364)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1588:1588:1588) (1696:1696:1696)) - (PORT d[1] (980:980:980) (1067:1067:1067)) - (PORT d[2] (995:995:995) (1068:1068:1068)) - (PORT d[3] (1044:1044:1044) (1123:1123:1123)) - (PORT d[4] (975:975:975) (1061:1061:1061)) - (PORT d[5] (1570:1570:1570) (1702:1702:1702)) - (PORT d[6] (974:974:974) (1057:1057:1057)) - (PORT d[7] (950:950:950) (1029:1029:1029)) - (PORT d[8] (1007:1007:1007) (1107:1107:1107)) - (PORT d[9] (1511:1511:1511) (1583:1583:1583)) - (PORT d[10] (1476:1476:1476) (1552:1552:1552)) - (PORT d[11] (949:949:949) (1029:1029:1029)) - (PORT d[12] (993:993:993) (1056:1056:1056)) + (PORT d[0] (1733:1733:1733) (1922:1922:1922)) + (PORT d[1] (1970:1970:1970) (2131:2131:2131)) + (PORT d[2] (2159:2159:2159) (2306:2306:2306)) + (PORT d[3] (2219:2219:2219) (2360:2360:2360)) + (PORT d[4] (2084:2084:2084) (2195:2195:2195)) + (PORT d[5] (1896:1896:1896) (1993:1993:1993)) + (PORT d[6] (1827:1827:1827) (1951:1951:1951)) + (PORT d[7] (1862:1862:1862) (1984:1984:1984)) + (PORT d[8] (1868:1868:1868) (1994:1994:1994)) + (PORT d[9] (1908:1908:1908) (2030:2030:2030)) + (PORT d[10] (1767:1767:1767) (1972:1972:1972)) + (PORT d[11] (1868:1868:1868) (1996:1996:1996)) + (PORT d[12] (2048:2048:2048) (2130:2130:2130)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2303,17 +2306,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (897:897:897) (921:921:921)) + (PORT d[0] (1685:1685:1685) (1767:1767:1767)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1849:1849:1849) (1876:1876:1876)) @@ -2323,7 +2326,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -2337,7 +2340,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -2346,7 +2349,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2355,7 +2358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2365,7 +2368,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -2373,25 +2376,2129 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1982:1982:1982) (2177:2177:2177)) + (PORT d[1] (1928:1928:1928) (2063:2063:2063)) + (PORT d[2] (2166:2166:2166) (2327:2327:2327)) + (PORT d[3] (2210:2210:2210) (2351:2351:2351)) + (PORT d[4] (2129:2129:2129) (2252:2252:2252)) + (PORT d[5] (1872:1872:1872) (1985:1985:1985)) + (PORT d[6] (1796:1796:1796) (1941:1941:1941)) + (PORT d[7] (1902:1902:1902) (2083:2083:2083)) + (PORT d[8] (1861:1861:1861) (2011:2011:2011)) + (PORT d[9] (2186:2186:2186) (2333:2333:2333)) + (PORT d[10] (2118:2118:2118) (2300:2300:2300)) + (PORT d[11] (1858:1858:1858) (2006:2006:2006)) + (PORT d[12] (2105:2105:2105) (2343:2343:2343)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1792:1792:1792) (1727:1727:1727)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (773:773:773)) + (PORT datac (1897:1897:1897) (2091:2091:2091)) + (PORT datad (348:348:348) (363:363:363)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2186:2186:2186) (2285:2285:2285)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2065:2065:2065) (2268:2268:2268)) + (PORT d[1] (2187:2187:2187) (2316:2316:2316)) + (PORT d[2] (2211:2211:2211) (2384:2384:2384)) + (PORT d[3] (2281:2281:2281) (2440:2440:2440)) + (PORT d[4] (2169:2169:2169) (2344:2344:2344)) + (PORT d[5] (2210:2210:2210) (2364:2364:2364)) + (PORT d[6] (2149:2149:2149) (2283:2283:2283)) + (PORT d[7] (2077:2077:2077) (2302:2302:2302)) + (PORT d[8] (2367:2367:2367) (2522:2522:2522)) + (PORT d[9] (2150:2150:2150) (2314:2314:2314)) + (PORT d[10] (2027:2027:2027) (2231:2231:2231)) + (PORT d[11] (2348:2348:2348) (2486:2486:2486)) + (PORT d[12] (2333:2333:2333) (2496:2496:2496)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (2022:2022:2022) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2191:2191:2191) (2290:2290:2290)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (2243:2243:2243)) + (PORT d[1] (2233:2233:2233) (2365:2365:2365)) + (PORT d[2] (2159:2159:2159) (2330:2330:2330)) + (PORT d[3] (2282:2282:2282) (2440:2440:2440)) + (PORT d[4] (2187:2187:2187) (2356:2356:2356)) + (PORT d[5] (2211:2211:2211) (2364:2364:2364)) + (PORT d[6] (2150:2150:2150) (2283:2283:2283)) + (PORT d[7] (2078:2078:2078) (2302:2302:2302)) + (PORT d[8] (2368:2368:2368) (2522:2522:2522)) + (PORT d[9] (2151:2151:2151) (2314:2314:2314)) + (PORT d[10] (2028:2028:2028) (2231:2231:2231)) + (PORT d[11] (2349:2349:2349) (2486:2486:2486)) + (PORT d[12] (2334:2334:2334) (2496:2496:2496)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2022:2022:2022) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3174:3174:3174) (3285:3285:3285)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1967:1967:1967) (2086:2086:2086)) + (PORT d[1] (2293:2293:2293) (2486:2486:2486)) + (PORT d[2] (1954:1954:1954) (2112:2112:2112)) + (PORT d[3] (1742:1742:1742) (1900:1900:1900)) + (PORT d[4] (2207:2207:2207) (2364:2364:2364)) + (PORT d[5] (1570:1570:1570) (1733:1733:1733)) + (PORT d[6] (1787:1787:1787) (1945:1945:1945)) + (PORT d[7] (1752:1752:1752) (1914:1914:1914)) + (PORT d[8] (1950:1950:1950) (2065:2065:2065)) + (PORT d[9] (1769:1769:1769) (1880:1880:1880)) + (PORT d[10] (1682:1682:1682) (1838:1838:1838)) + (PORT d[11] (2015:2015:2015) (2121:2121:2121)) + (PORT d[12] (2067:2067:2067) (2250:2250:2250)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1850:1850:1850)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3179:3179:3179) (3290:3290:3290)) + (PORT clk (1866:1866:1866) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1976:1976:1976) (2082:2082:2082)) + (PORT d[1] (2294:2294:2294) (2486:2486:2486)) + (PORT d[2] (1911:1911:1911) (2064:2064:2064)) + (PORT d[3] (1743:1743:1743) (1900:1900:1900)) + (PORT d[4] (2244:2244:2244) (2421:2421:2421)) + (PORT d[5] (1571:1571:1571) (1733:1733:1733)) + (PORT d[6] (1788:1788:1788) (1945:1945:1945)) + (PORT d[7] (1753:1753:1753) (1914:1914:1914)) + (PORT d[8] (1951:1951:1951) (2065:2065:2065)) + (PORT d[9] (1770:1770:1770) (1880:1880:1880)) + (PORT d[10] (1683:1683:1683) (1838:1838:1838)) + (PORT d[11] (2016:2016:2016) (2121:2121:2121)) + (PORT d[12] (2068:2068:2068) (2250:2250:2250)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1892:1892:1892)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1851:1851:1851)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2697:2697:2697) (2912:2912:2912)) + (PORT datac (642:642:642) (662:662:662)) + (PORT datad (1091:1091:1091) (1109:1109:1109)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3157:3157:3157) (3259:3259:3259)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1684:1684:1684) (1814:1814:1814)) + (PORT d[1] (1912:1912:1912) (2072:2072:2072)) + (PORT d[2] (1954:1954:1954) (2112:2112:2112)) + (PORT d[3] (1766:1766:1766) (1915:1915:1915)) + (PORT d[4] (1998:1998:1998) (2150:2150:2150)) + (PORT d[5] (1881:1881:1881) (2064:2064:2064)) + (PORT d[6] (1954:1954:1954) (2093:2093:2093)) + (PORT d[7] (2034:2034:2034) (2198:2198:2198)) + (PORT d[8] (1978:1978:1978) (2097:2097:2097)) + (PORT d[9] (2037:2037:2037) (2220:2220:2220)) + (PORT d[10] (1742:1742:1742) (1908:1908:1908)) + (PORT d[11] (1966:1966:1966) (2088:2088:2088)) + (PORT d[12] (2052:2052:2052) (2237:2237:2237)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (1617:1617:1617) (1549:1549:1549)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1852:1852:1852)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3162:3162:3162) (3264:3264:3264)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1694:1694:1694) (1812:1812:1812)) + (PORT d[1] (1917:1917:1917) (2089:2089:2089)) + (PORT d[2] (1911:1911:1911) (2064:2064:2064)) + (PORT d[3] (1767:1767:1767) (1915:1915:1915)) + (PORT d[4] (1977:1977:1977) (2126:2126:2126)) + (PORT d[5] (1882:1882:1882) (2064:2064:2064)) + (PORT d[6] (1955:1955:1955) (2093:2093:2093)) + (PORT d[7] (2035:2035:2035) (2198:2198:2198)) + (PORT d[8] (1979:1979:1979) (2097:2097:2097)) + (PORT d[9] (2038:2038:2038) (2220:2220:2220)) + (PORT d[10] (1743:1743:1743) (1908:1908:1908)) + (PORT d[11] (1967:1967:1967) (2088:2088:2088)) + (PORT d[12] (2053:2053:2053) (2237:2237:2237)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (1617:1617:1617) (1549:1549:1549)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1853:1853:1853)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3172:3172:3172) (3285:3285:3285)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1706:1706:1706) (1842:1842:1842)) + (PORT d[1] (1974:1974:1974) (2127:2127:2127)) + (PORT d[2] (1651:1651:1651) (1764:1764:1764)) + (PORT d[3] (1724:1724:1724) (1872:1872:1872)) + (PORT d[4] (1952:1952:1952) (2127:2127:2127)) + (PORT d[5] (1542:1542:1542) (1700:1700:1700)) + (PORT d[6] (2052:2052:2052) (2207:2207:2207)) + (PORT d[7] (1747:1747:1747) (1911:1911:1911)) + (PORT d[8] (1938:1938:1938) (2069:2069:2069)) + (PORT d[9] (2028:2028:2028) (2200:2200:2200)) + (PORT d[10] (2188:2188:2188) (2417:2417:2417)) + (PORT d[11] (2008:2008:2008) (2111:2111:2111)) + (PORT d[12] (2045:2045:2045) (2242:2242:2242)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3177:3177:3177) (3290:3290:3290)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1685:1685:1685) (1817:1817:1817)) + (PORT d[1] (1975:1975:1975) (2132:2132:2132)) + (PORT d[2] (1665:1665:1665) (1796:1796:1796)) + (PORT d[3] (1725:1725:1725) (1872:1872:1872)) + (PORT d[4] (1960:1960:1960) (2115:2115:2115)) + (PORT d[5] (1543:1543:1543) (1700:1700:1700)) + (PORT d[6] (2053:2053:2053) (2207:2207:2207)) + (PORT d[7] (1748:1748:1748) (1911:1911:1911)) + (PORT d[8] (1939:1939:1939) (2069:2069:2069)) + (PORT d[9] (2029:2029:2029) (2200:2200:2200)) + (PORT d[10] (2189:2189:2189) (2417:2417:2417)) + (PORT d[11] (2009:2009:2009) (2111:2111:2111)) + (PORT d[12] (2046:2046:2046) (2242:2242:2242)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1283:1283:1283) (1352:1352:1352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (271:271:271) (357:357:357)) + (PORT datac (681:681:681) (694:694:694)) + (PORT datad (348:348:348) (364:364:364)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (929:929:929) (968:968:968)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1594:1594:1594) (1715:1715:1715)) + (PORT d[1] (1702:1702:1702) (1831:1831:1831)) + (PORT d[2] (1596:1596:1596) (1703:1703:1703)) + (PORT d[3] (1706:1706:1706) (1830:1830:1830)) + (PORT d[4] (1670:1670:1670) (1826:1826:1826)) + (PORT d[5] (1479:1479:1479) (1627:1627:1627)) + (PORT d[6] (1631:1631:1631) (1770:1770:1770)) + (PORT d[7] (1937:1937:1937) (2048:2048:2048)) + (PORT d[8] (1681:1681:1681) (1829:1829:1829)) + (PORT d[9] (1735:1735:1735) (1889:1889:1889)) + (PORT d[10] (1456:1456:1456) (1610:1610:1610)) + (PORT d[11] (1888:1888:1888) (2010:2010:2010)) + (PORT d[12] (1744:1744:1744) (1905:1905:1905)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1312:1312:1312) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (934:934:934) (973:973:973)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1617:1617:1617) (1734:1734:1734)) + (PORT d[1] (1689:1689:1689) (1799:1799:1799)) + (PORT d[2] (1610:1610:1610) (1731:1731:1731)) + (PORT d[3] (1707:1707:1707) (1830:1830:1830)) + (PORT d[4] (1671:1671:1671) (1832:1832:1832)) + (PORT d[5] (1480:1480:1480) (1627:1627:1627)) + (PORT d[6] (1632:1632:1632) (1770:1770:1770)) + (PORT d[7] (1938:1938:1938) (2048:2048:2048)) + (PORT d[8] (1682:1682:1682) (1829:1829:1829)) + (PORT d[9] (1736:1736:1736) (1889:1889:1889)) + (PORT d[10] (1457:1457:1457) (1610:1610:1610)) + (PORT d[11] (1889:1889:1889) (2010:2010:2010)) + (PORT d[12] (1745:1745:1745) (1905:1905:1905)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1312:1312:1312) (1246:1246:1246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (901:901:901) (948:948:948)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1970:1970:1970) (2104:2104:2104)) + (PORT d[1] (1716:1716:1716) (1847:1847:1847)) + (PORT d[2] (1895:1895:1895) (2002:2002:2002)) + (PORT d[3] (1692:1692:1692) (1826:1826:1826)) + (PORT d[4] (1680:1680:1680) (1846:1846:1846)) + (PORT d[5] (1484:1484:1484) (1636:1636:1636)) + (PORT d[6] (1880:1880:1880) (2002:2002:2002)) + (PORT d[7] (1679:1679:1679) (1844:1844:1844)) + (PORT d[8] (1716:1716:1716) (1877:1877:1877)) + (PORT d[9] (1718:1718:1718) (1874:1874:1874)) + (PORT d[10] (1753:1753:1753) (1899:1899:1899)) + (PORT d[11] (1880:1880:1880) (1999:1999:1999)) + (PORT d[12] (1753:1753:1753) (1919:1919:1919)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1244:1244:1244) (1290:1290:1290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (906:906:906) (953:953:953)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1971:1971:1971) (2104:2104:2104)) + (PORT d[1] (1695:1695:1695) (1822:1822:1822)) + (PORT d[2] (1615:1615:1615) (1740:1740:1740)) + (PORT d[3] (1693:1693:1693) (1826:1826:1826)) + (PORT d[4] (1667:1667:1667) (1814:1814:1814)) + (PORT d[5] (1485:1485:1485) (1636:1636:1636)) + (PORT d[6] (1881:1881:1881) (2002:2002:2002)) + (PORT d[7] (1680:1680:1680) (1844:1844:1844)) + (PORT d[8] (1717:1717:1717) (1877:1877:1877)) + (PORT d[9] (1719:1719:1719) (1874:1874:1874)) + (PORT d[10] (1754:1754:1754) (1899:1899:1899)) + (PORT d[11] (1881:1881:1881) (1999:1999:1999)) + (PORT d[12] (1754:1754:1754) (1919:1919:1919)) + (PORT clk (1858:1858:1858) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (1244:1244:1244) (1290:1290:1290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (992:992:992) (1034:1034:1034)) + (PORT datac (735:735:735) (831:831:831)) + (PORT datad (969:969:969) (1010:1010:1010)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3451:3451:3451) (3568:3568:3568)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1695:1695:1695) (1821:1821:1821)) + (PORT d[1] (1961:1961:1961) (2101:2101:2101)) + (PORT d[2] (1635:1635:1635) (1763:1763:1763)) + (PORT d[3] (1691:1691:1691) (1829:1829:1829)) + (PORT d[4] (1958:1958:1958) (2143:2143:2143)) + (PORT d[5] (1514:1514:1514) (1654:1654:1654)) + (PORT d[6] (2088:2088:2088) (2262:2262:2262)) + (PORT d[7] (1969:1969:1969) (2129:2129:2129)) + (PORT d[8] (1996:1996:1996) (2177:2177:2177)) + (PORT d[9] (2062:2062:2062) (2258:2258:2258)) + (PORT d[10] (1974:1974:1974) (2129:2129:2129)) + (PORT d[11] (1732:1732:1732) (1851:1851:1851)) + (PORT d[12] (1780:1780:1780) (1964:1964:1964)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (1309:1309:1309) (1248:1248:1248)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3456:3456:3456) (3573:3573:3573)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1705:1705:1705) (1819:1819:1819)) + (PORT d[1] (1940:1940:1940) (2077:2077:2077)) + (PORT d[2] (1677:1677:1677) (1808:1808:1808)) + (PORT d[3] (1692:1692:1692) (1829:1829:1829)) + (PORT d[4] (1945:1945:1945) (2111:2111:2111)) + (PORT d[5] (1515:1515:1515) (1654:1654:1654)) + (PORT d[6] (2089:2089:2089) (2262:2262:2262)) + (PORT d[7] (1970:1970:1970) (2129:2129:2129)) + (PORT d[8] (1997:1997:1997) (2177:2177:2177)) + (PORT d[9] (2063:2063:2063) (2258:2258:2258)) + (PORT d[10] (1975:1975:1975) (2129:2129:2129)) + (PORT d[11] (1733:1733:1733) (1851:1851:1851)) + (PORT d[12] (1781:1781:1781) (1964:1964:1964)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1309:1309:1309) (1248:1248:1248)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3433:3433:3433) (3533:3533:3533)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1935:1935:1935) (2059:2059:2059)) + (PORT d[1] (1879:1879:1879) (2055:2055:2055)) + (PORT d[2] (1673:1673:1673) (1806:1806:1806)) + (PORT d[3] (1719:1719:1719) (1862:1862:1862)) + (PORT d[4] (2011:2011:2011) (2162:2162:2162)) + (PORT d[5] (1532:1532:1532) (1674:1674:1674)) + (PORT d[6] (2091:2091:2091) (2267:2267:2267)) + (PORT d[7] (1723:1723:1723) (1889:1889:1889)) + (PORT d[8] (1623:1623:1623) (1738:1738:1738)) + (PORT d[9] (2043:2043:2043) (2237:2237:2237)) + (PORT d[10] (1745:1745:1745) (1889:1889:1889)) + (PORT d[11] (1993:1993:1993) (2111:2111:2111)) + (PORT d[12] (2047:2047:2047) (2224:2224:2224)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1291:1291:1291) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3438:3438:3438) (3538:3538:3538)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1990:1990:1990) (2109:2109:2109)) + (PORT d[1] (1965:1965:1965) (2111:2111:2111)) + (PORT d[2] (1674:1674:1674) (1806:1806:1806)) + (PORT d[3] (1720:1720:1720) (1862:1862:1862)) + (PORT d[4] (2012:2012:2012) (2162:2162:2162)) + (PORT d[5] (1533:1533:1533) (1674:1674:1674)) + (PORT d[6] (2092:2092:2092) (2267:2267:2267)) + (PORT d[7] (1724:1724:1724) (1889:1889:1889)) + (PORT d[8] (1624:1624:1624) (1738:1738:1738)) + (PORT d[9] (2044:2044:2044) (2237:2237:2237)) + (PORT d[10] (1746:1746:1746) (1889:1889:1889)) + (PORT d[11] (1994:1994:1994) (2111:2111:2111)) + (PORT d[12] (2048:2048:2048) (2224:2224:2224)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1291:1291:1291) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1841:1841:1841)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (767:767:767) (864:864:864)) + (PORT datac (674:674:674) (687:687:687)) + (PORT datad (349:349:349) (365:365:365)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1759:1759:1759) (1954:1954:1954)) + (PORT d[1] (1921:1921:1921) (2055:2055:2055)) + (PORT d[2] (2115:2115:2115) (2262:2262:2262)) + (PORT d[3] (2204:2204:2204) (2339:2339:2339)) + (PORT d[4] (2144:2144:2144) (2260:2260:2260)) + (PORT d[5] (1918:1918:1918) (2036:2036:2036)) + (PORT d[6] (1770:1770:1770) (1893:1893:1893)) + (PORT d[7] (1884:1884:1884) (2012:2012:2012)) + (PORT d[8] (1882:1882:1882) (2030:2030:2030)) + (PORT d[9] (1891:1891:1891) (2020:2020:2020)) + (PORT d[10] (1752:1752:1752) (1953:1953:1953)) + (PORT d[11] (1851:1851:1851) (1994:1994:1994)) + (PORT d[12] (2201:2201:2201) (2421:2421:2421)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1773:1773:1773) (1689:1689:1689)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2105:2105:2105) (2311:2311:2311)) + (PORT d[1] (1947:1947:1947) (2084:2084:2084)) + (PORT d[2] (2166:2166:2166) (2324:2324:2324)) + (PORT d[3] (2248:2248:2248) (2396:2396:2396)) + (PORT d[4] (2176:2176:2176) (2348:2348:2348)) + (PORT d[5] (1952:1952:1952) (2095:2095:2095)) + (PORT d[6] (2117:2117:2117) (2251:2251:2251)) + (PORT d[7] (2058:2058:2058) (2288:2288:2288)) + (PORT d[8] (2060:2060:2060) (2177:2177:2177)) + (PORT d[9] (2163:2163:2163) (2322:2322:2322)) + (PORT d[10] (1982:1982:1982) (2160:2160:2160)) + (PORT d[11] (2269:2269:2269) (2403:2403:2403)) + (PORT d[12] (2020:2020:2020) (2182:2182:2182)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (1701:1701:1701) (1783:1783:1783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1214:1214:1214)) + (PORT datac (2506:2506:2506) (2721:2721:2721)) + (PORT datad (346:346:346) (361:361:361)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2054:2054:2054) (2271:2271:2271)) + (PORT d[1] (1989:1989:1989) (2131:2131:2131)) + (PORT d[2] (2133:2133:2133) (2280:2280:2280)) + (PORT d[3] (2185:2185:2185) (2313:2313:2313)) + (PORT d[4] (2173:2173:2173) (2323:2323:2323)) + (PORT d[5] (1924:1924:1924) (2063:2063:2063)) + (PORT d[6] (2151:2151:2151) (2279:2279:2279)) + (PORT d[7] (2084:2084:2084) (2320:2320:2320)) + (PORT d[8] (1814:1814:1814) (1935:1935:1935)) + (PORT d[9] (2164:2164:2164) (2343:2343:2343)) + (PORT d[10] (1715:1715:1715) (1899:1899:1899)) + (PORT d[11] (2299:2299:2299) (2432:2432:2432)) + (PORT d[12] (2017:2017:2017) (2181:2181:2181)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1694:1694:1694) (1761:1761:1761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1251:1251:1251) (1346:1346:1346)) - (PORT d[1] (1263:1263:1263) (1359:1359:1359)) - (PORT d[2] (1230:1230:1230) (1312:1312:1312)) - (PORT d[3] (1305:1305:1305) (1378:1378:1378)) - (PORT d[4] (1268:1268:1268) (1374:1374:1374)) - (PORT d[5] (1558:1558:1558) (1661:1661:1661)) - (PORT d[6] (1255:1255:1255) (1359:1359:1359)) - (PORT d[7] (1243:1243:1243) (1338:1338:1338)) - (PORT d[8] (1284:1284:1284) (1400:1400:1400)) - (PORT d[9] (1257:1257:1257) (1358:1358:1358)) - (PORT d[10] (1261:1261:1261) (1362:1362:1362)) - (PORT d[11] (1244:1244:1244) (1341:1341:1341)) - (PORT d[12] (1513:1513:1513) (1597:1597:1597)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (2042:2042:2042) (2251:2251:2251)) + (PORT d[1] (1726:1726:1726) (1880:1880:1880)) + (PORT d[2] (2193:2193:2193) (2359:2359:2359)) + (PORT d[3] (2213:2213:2213) (2374:2374:2374)) + (PORT d[4] (2158:2158:2158) (2320:2320:2320)) + (PORT d[5] (1641:1641:1641) (1756:1756:1756)) + (PORT d[6] (2078:2078:2078) (2220:2220:2220)) + (PORT d[7] (1942:1942:1942) (2112:2112:2112)) + (PORT d[8] (1789:1789:1789) (1911:1911:1911)) + (PORT d[9] (2199:2199:2199) (2326:2326:2326)) + (PORT d[10] (1702:1702:1702) (1882:1882:1882)) + (PORT d[11] (2172:2172:2172) (2318:2318:2318)) + (PORT d[12] (2153:2153:2153) (2388:2388:2388)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -2403,8 +4510,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1844:1844:1844) (1871:1871:1871)) - (PORT d[0] (1181:1181:1181) (1146:1146:1146)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (1766:1766:1766) (1700:1700:1700)) ) ) ) @@ -2413,7 +4520,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2423,7 +4530,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) + (PORT clk (1809:1809:1809) (1836:1836:1836)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2437,7 +4544,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) + (PORT clk (994:994:994) (999:999:999)) ) ) ) @@ -2446,7 +4553,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) @@ -2455,7 +4562,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2465,22 +4572,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (995:995:995) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (648:648:648)) - (PORT datab (722:722:722) (791:791:791)) - (PORT datac (902:902:902) (941:941:941)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (693:693:693) (733:733:733)) + (PORT datac (925:925:925) (989:989:989)) + (PORT datad (2699:2699:2699) (2890:2890:2890)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -2489,19 +4596,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1869:1869:1869) (2011:2011:2011)) - (PORT d[1] (1219:1219:1219) (1293:1293:1293)) - (PORT d[2] (1262:1262:1262) (1328:1328:1328)) - (PORT d[3] (1315:1315:1315) (1385:1385:1385)) - (PORT d[4] (1268:1268:1268) (1345:1345:1345)) - (PORT d[5] (1878:1878:1878) (2013:2013:2013)) - (PORT d[6] (1241:1241:1241) (1311:1311:1311)) - (PORT d[7] (1353:1353:1353) (1455:1455:1455)) - (PORT d[8] (1215:1215:1215) (1306:1306:1306)) - (PORT d[9] (1254:1254:1254) (1335:1335:1335)) - (PORT d[10] (1270:1270:1270) (1354:1354:1354)) - (PORT d[11] (1212:1212:1212) (1279:1279:1279)) - (PORT d[12] (1262:1262:1262) (1346:1346:1346)) + (PORT d[0] (1958:1958:1958) (2119:2119:2119)) + (PORT d[1] (1627:1627:1627) (1734:1734:1734)) + (PORT d[2] (1870:1870:1870) (2003:2003:2003)) + (PORT d[3] (1889:1889:1889) (1979:1979:1979)) + (PORT d[4] (1810:1810:1810) (1926:1926:1926)) + (PORT d[5] (1669:1669:1669) (1774:1774:1774)) + (PORT d[6] (1873:1873:1873) (2001:2001:2001)) + (PORT d[7] (1570:1570:1570) (1685:1685:1685)) + (PORT d[8] (1579:1579:1579) (1703:1703:1703)) + (PORT d[9] (1542:1542:1542) (1637:1637:1637)) + (PORT d[10] (1774:1774:1774) (1984:1984:1984)) + (PORT d[11] (1616:1616:1616) (1719:1719:1719)) + (PORT d[12] (1777:1777:1777) (1896:1896:1896)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2515,7 +4622,7 @@ (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1161:1161:1161) (1144:1144:1144)) + (PORT d[0] (1741:1741:1741) (1677:1677:1677)) ) ) ) @@ -2586,20 +4693,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (767:767:767) (837:837:837)) - (PORT d[1] (644:644:644) (707:707:707)) - (PORT d[2] (1522:1522:1522) (1591:1591:1591)) - (PORT d[3] (1232:1232:1232) (1276:1276:1276)) - (PORT d[4] (948:948:948) (1009:1009:1009)) - (PORT d[5] (1053:1053:1053) (1132:1132:1132)) - (PORT d[6] (1198:1198:1198) (1268:1268:1268)) - (PORT d[7] (1251:1251:1251) (1321:1321:1321)) - (PORT d[8] (1492:1492:1492) (1563:1563:1563)) - (PORT d[9] (1256:1256:1256) (1307:1307:1307)) - (PORT d[10] (1239:1239:1239) (1292:1292:1292)) - (PORT d[11] (1213:1213:1213) (1275:1275:1275)) - (PORT d[12] (1242:1242:1242) (1308:1308:1308)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1696:1696:1696) (1855:1855:1855)) + (PORT d[1] (1624:1624:1624) (1716:1716:1716)) + (PORT d[2] (1829:1829:1829) (1941:1941:1941)) + (PORT d[3] (1799:1799:1799) (1866:1866:1866)) + (PORT d[4] (1795:1795:1795) (1904:1904:1904)) + (PORT d[5] (1607:1607:1607) (1721:1721:1721)) + (PORT d[6] (1527:1527:1527) (1632:1632:1632)) + (PORT d[7] (1539:1539:1539) (1667:1667:1667)) + (PORT d[8] (1561:1561:1561) (1665:1665:1665)) + (PORT d[9] (1507:1507:1507) (1599:1599:1599)) + (PORT d[10] (1787:1787:1787) (2014:2014:2014)) + (PORT d[11] (1560:1560:1560) (1657:1657:1657)) + (PORT d[12] (1765:1765:1765) (1857:1857:1857)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) ) ) (TIMINGCHECK @@ -2611,8 +4718,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (890:890:890) (887:887:887)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1628:1628:1628) (1667:1667:1667)) ) ) ) @@ -2621,7 +4728,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2631,7 +4738,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) + (PORT clk (1809:1809:1809) (1835:1835:1835)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2645,7 +4752,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) + (PORT clk (994:994:994) (998:998:998)) ) ) ) @@ -2654,7 +4761,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) ) ) ) @@ -2663,7 +4770,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2673,141 +4780,44 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (995:995:995) (999:999:999)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) (DELAY (ABSOLUTE - (PORT datab (938:938:938) (1009:1009:1009)) - (PORT datac (597:597:597) (600:600:600)) - (PORT datad (1037:1037:1037) (1036:1036:1036)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (726:726:726) (771:771:771)) + (PORT datac (1862:1862:1862) (2046:2046:2046)) + (PORT datad (959:959:959) (1001:1001:1001)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1536:1536:1536) (1641:1641:1641)) - (PORT d[1] (1285:1285:1285) (1385:1385:1385)) - (PORT d[2] (1257:1257:1257) (1341:1341:1341)) - (PORT d[3] (1362:1362:1362) (1438:1438:1438)) - (PORT d[4] (1567:1567:1567) (1669:1669:1669)) - (PORT d[5] (1299:1299:1299) (1410:1410:1410)) - (PORT d[6] (1283:1283:1283) (1391:1391:1391)) - (PORT d[7] (1243:1243:1243) (1339:1339:1339)) - (PORT d[8] (1257:1257:1257) (1369:1369:1369)) - (PORT d[9] (1285:1285:1285) (1390:1390:1390)) - (PORT d[10] (1289:1289:1289) (1395:1395:1395)) - (PORT d[11] (1244:1244:1244) (1342:1342:1342)) - (PORT d[12] (1238:1238:1238) (1316:1316:1316)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1869:1869:1869)) - (PORT d[0] (1140:1140:1140) (1166:1166:1166)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1019:1019:1019) (1118:1118:1118)) - (PORT d[1] (928:928:928) (1013:1013:1013)) - (PORT d[2] (926:926:926) (1007:1007:1007)) - (PORT d[3] (1249:1249:1249) (1279:1279:1279)) - (PORT d[4] (1509:1509:1509) (1612:1612:1612)) - (PORT d[5] (1306:1306:1306) (1397:1397:1397)) - (PORT d[6] (1247:1247:1247) (1313:1313:1313)) - (PORT d[7] (1321:1321:1321) (1414:1414:1414)) - (PORT d[8] (1471:1471:1471) (1521:1521:1521)) - (PORT d[9] (1265:1265:1265) (1341:1341:1341)) - (PORT d[10] (1259:1259:1259) (1333:1333:1333)) - (PORT d[11] (1270:1270:1270) (1337:1337:1337)) - (PORT d[12] (1271:1271:1271) (1319:1319:1319)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2034:2034:2034) (2233:2233:2233)) + (PORT d[1] (1965:1965:1965) (2106:2106:2106)) + (PORT d[2] (2209:2209:2209) (2367:2367:2367)) + (PORT d[3] (2240:2240:2240) (2404:2404:2404)) + (PORT d[4] (2184:2184:2184) (2357:2357:2357)) + (PORT d[5] (2204:2204:2204) (2358:2358:2358)) + (PORT d[6] (2164:2164:2164) (2290:2290:2290)) + (PORT d[7] (2094:2094:2094) (2301:2301:2301)) + (PORT d[8] (2332:2332:2332) (2483:2483:2483)) + (PORT d[9] (1879:1879:1879) (2041:2041:2041)) + (PORT d[10] (2031:2031:2031) (2222:2222:2222)) + (PORT d[11] (2277:2277:2277) (2430:2430:2430)) + (PORT d[12] (2315:2315:2315) (2497:2497:2497)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -2819,8 +4829,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (909:909:909) (894:894:894)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1813:1813:1813) (1728:1728:1728)) ) ) ) @@ -2829,7 +4839,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2839,7 +4849,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) + (PORT clk (1815:1815:1815) (1842:1842:1842)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2853,7 +4863,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) + (PORT clk (1000:1000:1000) (1005:1005:1005)) ) ) ) @@ -2862,7 +4872,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (1001:1001:1001) (1006:1006:1006)) ) ) ) @@ -2871,7 +4881,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (1001:1001:1001) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2879,6 +4889,2940 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2036:2036:2036) (2238:2238:2238)) + (PORT d[1] (2208:2208:2208) (2355:2355:2355)) + (PORT d[2] (2290:2290:2290) (2482:2482:2482)) + (PORT d[3] (2227:2227:2227) (2392:2392:2392)) + (PORT d[4] (2188:2188:2188) (2350:2350:2350)) + (PORT d[5] (2163:2163:2163) (2296:2296:2296)) + (PORT d[6] (1938:1938:1938) (2096:2096:2096)) + (PORT d[7] (2053:2053:2053) (2285:2285:2285)) + (PORT d[8] (2038:2038:2038) (2172:2172:2172)) + (PORT d[9] (2152:2152:2152) (2331:2331:2331)) + (PORT d[10] (2012:2012:2012) (2207:2207:2207)) + (PORT d[11] (2331:2331:2331) (2476:2476:2476)) + (PORT d[12] (2240:2240:2240) (2416:2416:2416)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (1909:1909:1909) (2020:2020:2020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (2760:2760:2760) (2963:2963:2963)) + (PORT datac (556:556:556) (558:558:558)) + (PORT datad (649:649:649) (676:676:676)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3478:3478:3478) (3599:3599:3599)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2019:2019:2019) (2126:2126:2126)) + (PORT d[1] (1744:1744:1744) (1872:1872:1872)) + (PORT d[2] (1727:1727:1727) (1824:1824:1824)) + (PORT d[3] (1724:1724:1724) (1879:1879:1879)) + (PORT d[4] (1958:1958:1958) (2143:2143:2143)) + (PORT d[5] (1471:1471:1471) (1597:1597:1597)) + (PORT d[6] (1707:1707:1707) (1863:1863:1863)) + (PORT d[7] (2243:2243:2243) (2372:2372:2372)) + (PORT d[8] (1971:1971:1971) (2145:2145:2145)) + (PORT d[9] (1769:1769:1769) (1882:1882:1882)) + (PORT d[10] (1445:1445:1445) (1602:1602:1602)) + (PORT d[11] (2162:2162:2162) (2306:2306:2306)) + (PORT d[12] (1740:1740:1740) (1899:1899:1899)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1319:1319:1319) (1255:1255:1255)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3483:3483:3483) (3604:3604:3604)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2034:2034:2034) (2152:2152:2152)) + (PORT d[1] (1723:1723:1723) (1848:1848:1848)) + (PORT d[2] (1752:1752:1752) (1847:1847:1847)) + (PORT d[3] (1725:1725:1725) (1879:1879:1879)) + (PORT d[4] (1945:1945:1945) (2111:2111:2111)) + (PORT d[5] (1472:1472:1472) (1597:1597:1597)) + (PORT d[6] (1708:1708:1708) (1863:1863:1863)) + (PORT d[7] (2244:2244:2244) (2372:2372:2372)) + (PORT d[8] (1972:1972:1972) (2145:2145:2145)) + (PORT d[9] (1770:1770:1770) (1882:1882:1882)) + (PORT d[10] (1446:1446:1446) (1602:1602:1602)) + (PORT d[11] (2163:2163:2163) (2306:2306:2306)) + (PORT d[12] (1741:1741:1741) (1899:1899:1899)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (1319:1319:1319) (1255:1255:1255)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3478:3478:3478) (3600:3600:3600)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1943:1943:1943) (2073:2073:2073)) + (PORT d[1] (1998:1998:1998) (2125:2125:2125)) + (PORT d[2] (1904:1904:1904) (2028:2028:2028)) + (PORT d[3] (1782:1782:1782) (1923:1923:1923)) + (PORT d[4] (1950:1950:1950) (2124:2124:2124)) + (PORT d[5] (1477:1477:1477) (1622:1622:1622)) + (PORT d[6] (2045:2045:2045) (2181:2181:2181)) + (PORT d[7] (1737:1737:1737) (1896:1896:1896)) + (PORT d[8] (1640:1640:1640) (1754:1754:1754)) + (PORT d[9] (2015:2015:2015) (2206:2206:2206)) + (PORT d[10] (1977:1977:1977) (2149:2149:2149)) + (PORT d[11] (2188:2188:2188) (2337:2337:2337)) + (PORT d[12] (1746:1746:1746) (1924:1924:1924)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (1256:1256:1256) (1318:1318:1318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3483:3483:3483) (3605:3605:3605)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1989:1989:1989) (2122:2122:2122)) + (PORT d[1] (2007:2007:2007) (2122:2122:2122)) + (PORT d[2] (1944:1944:1944) (2065:2065:2065)) + (PORT d[3] (1783:1783:1783) (1923:1923:1923)) + (PORT d[4] (1951:1951:1951) (2130:2130:2130)) + (PORT d[5] (1478:1478:1478) (1622:1622:1622)) + (PORT d[6] (2046:2046:2046) (2181:2181:2181)) + (PORT d[7] (1738:1738:1738) (1896:1896:1896)) + (PORT d[8] (1641:1641:1641) (1754:1754:1754)) + (PORT d[9] (2016:2016:2016) (2206:2206:2206)) + (PORT d[10] (1978:1978:1978) (2149:2149:2149)) + (PORT d[11] (2189:2189:2189) (2337:2337:2337)) + (PORT d[12] (1747:1747:1747) (1924:1924:1924)) + (PORT clk (1856:1856:1856) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1256:1256:1256) (1318:1318:1318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (355:355:355)) + (PORT datac (649:649:649) (696:696:696)) + (PORT datad (965:965:965) (1003:1003:1003)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2795:2795:2795) (2881:2881:2881)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1986:1986:1986) (2096:2096:2096)) + (PORT d[1] (1924:1924:1924) (2104:2104:2104)) + (PORT d[2] (1955:1955:1955) (2104:2104:2104)) + (PORT d[3] (1736:1736:1736) (1899:1899:1899)) + (PORT d[4] (2176:2176:2176) (2350:2350:2350)) + (PORT d[5] (1843:1843:1843) (2000:2000:2000)) + (PORT d[6] (2047:2047:2047) (2218:2218:2218)) + (PORT d[7] (2035:2035:2035) (2190:2190:2190)) + (PORT d[8] (1909:1909:1909) (2029:2029:2029)) + (PORT d[9] (2025:2025:2025) (2217:2217:2217)) + (PORT d[10] (2173:2173:2173) (2412:2412:2412)) + (PORT d[11] (2021:2021:2021) (2147:2147:2147)) + (PORT d[12] (2070:2070:2070) (2251:2251:2251)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (1526:1526:1526) (1593:1593:1593)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2800:2800:2800) (2886:2886:2886)) + (PORT clk (1872:1872:1872) (1897:1897:1897)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1987:1987:1987) (2103:2103:2103)) + (PORT d[1] (1947:1947:1947) (2127:2127:2127)) + (PORT d[2] (1956:1956:1956) (2104:2104:2104)) + (PORT d[3] (1737:1737:1737) (1899:1899:1899)) + (PORT d[4] (2222:2222:2222) (2399:2399:2399)) + (PORT d[5] (1844:1844:1844) (2000:2000:2000)) + (PORT d[6] (2048:2048:2048) (2218:2218:2218)) + (PORT d[7] (2036:2036:2036) (2190:2190:2190)) + (PORT d[8] (1910:1910:1910) (2029:2029:2029)) + (PORT d[9] (2026:2026:2026) (2217:2217:2217)) + (PORT d[10] (2174:2174:2174) (2412:2412:2412)) + (PORT d[11] (2022:2022:2022) (2147:2147:2147)) + (PORT d[12] (2071:2071:2071) (2251:2251:2251)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (PORT d[0] (1526:1526:1526) (1593:1593:1593)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2785:2785:2785) (2862:2862:2862)) + (PORT clk (1870:1870:1870) (1897:1897:1897)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1953:1953:1953) (2079:2079:2079)) + (PORT d[1] (1947:1947:1947) (2130:2130:2130)) + (PORT d[2] (1994:1994:1994) (2095:2095:2095)) + (PORT d[3] (1760:1760:1760) (1926:1926:1926)) + (PORT d[4] (2185:2185:2185) (2357:2357:2357)) + (PORT d[5] (1741:1741:1741) (1881:1881:1881)) + (PORT d[6] (2007:2007:2007) (2161:2161:2161)) + (PORT d[7] (2039:2039:2039) (2194:2194:2194)) + (PORT d[8] (2281:2281:2281) (2397:2397:2397)) + (PORT d[9] (2052:2052:2052) (2249:2249:2249)) + (PORT d[10] (1662:1662:1662) (1830:1830:1830)) + (PORT d[11] (1999:1999:1999) (2122:2122:2122)) + (PORT d[12] (2091:2091:2091) (2299:2299:2299)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT d[0] (1591:1591:1591) (1526:1526:1526)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2790:2790:2790) (2867:2867:2867)) + (PORT clk (1872:1872:1872) (1898:1898:1898)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1967:1967:1967) (2105:2105:2105)) + (PORT d[1] (1926:1926:1926) (2106:2106:2106)) + (PORT d[2] (2313:2313:2313) (2399:2399:2399)) + (PORT d[3] (1761:1761:1761) (1926:1926:1926)) + (PORT d[4] (1962:1962:1962) (2131:2131:2131)) + (PORT d[5] (1742:1742:1742) (1881:1881:1881)) + (PORT d[6] (2008:2008:2008) (2161:2161:2161)) + (PORT d[7] (2040:2040:2040) (2194:2194:2194)) + (PORT d[8] (2282:2282:2282) (2397:2397:2397)) + (PORT d[9] (2053:2053:2053) (2249:2249:2249)) + (PORT d[10] (1663:1663:1663) (1830:1830:1830)) + (PORT d[11] (2000:2000:2000) (2122:2122:2122)) + (PORT d[12] (2092:2092:2092) (2299:2299:2299)) + (PORT clk (1868:1868:1868) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1898:1898:1898)) + (PORT d[0] (1591:1591:1591) (1526:1526:1526)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (645:645:645)) + (PORT datac (993:993:993) (1070:1070:1070)) + (PORT datad (902:902:902) (910:910:910)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2129:2129:2129) (2209:2209:2209)) + (PORT clk (1862:1862:1862) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2080:2080:2080) (2290:2290:2290)) + (PORT d[1] (1984:1984:1984) (2161:2161:2161)) + (PORT d[2] (1864:1864:1864) (2019:2019:2019)) + (PORT d[3] (2469:2469:2469) (2619:2619:2619)) + (PORT d[4] (2505:2505:2505) (2677:2677:2677)) + (PORT d[5] (2155:2155:2155) (2279:2279:2279)) + (PORT d[6] (2240:2240:2240) (2392:2392:2392)) + (PORT d[7] (2203:2203:2203) (2386:2386:2386)) + (PORT d[8] (2230:2230:2230) (2405:2405:2405)) + (PORT d[9] (2206:2206:2206) (2378:2378:2378)) + (PORT d[10] (2026:2026:2026) (2221:2221:2221)) + (PORT d[11] (2288:2288:2288) (2426:2426:2426)) + (PORT d[12] (2218:2218:2218) (2381:2381:2381)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1889:1889:1889)) + (PORT d[0] (1896:1896:1896) (2026:2026:2026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1890:1890:1890)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2134:2134:2134) (2214:2214:2214)) + (PORT clk (1864:1864:1864) (1890:1890:1890)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2073:2073:2073) (2293:2293:2293)) + (PORT d[1] (2007:2007:2007) (2186:2186:2186)) + (PORT d[2] (1860:1860:1860) (2030:2030:2030)) + (PORT d[3] (2470:2470:2470) (2619:2619:2619)) + (PORT d[4] (2337:2337:2337) (2481:2481:2481)) + (PORT d[5] (2156:2156:2156) (2279:2279:2279)) + (PORT d[6] (2241:2241:2241) (2392:2392:2392)) + (PORT d[7] (2204:2204:2204) (2386:2386:2386)) + (PORT d[8] (2231:2231:2231) (2405:2405:2405)) + (PORT d[9] (2207:2207:2207) (2378:2378:2378)) + (PORT d[10] (2027:2027:2027) (2221:2221:2221)) + (PORT d[11] (2289:2289:2289) (2426:2426:2426)) + (PORT d[12] (2219:2219:2219) (2381:2381:2381)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1890:1890:1890)) + (PORT d[0] (1896:1896:1896) (2026:2026:2026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1891:1891:1891)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1849:1849:1849)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3173:3173:3173) (3286:3286:3286)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1718:1718:1718) (1848:1848:1848)) + (PORT d[1] (2002:2002:2002) (2154:2154:2154)) + (PORT d[2] (1745:1745:1745) (1851:1851:1851)) + (PORT d[3] (1732:1732:1732) (1875:1875:1875)) + (PORT d[4] (1993:1993:1993) (2145:2145:2145)) + (PORT d[5] (1514:1514:1514) (1664:1664:1664)) + (PORT d[6] (2087:2087:2087) (2261:2261:2261)) + (PORT d[7] (2026:2026:2026) (2179:2179:2179)) + (PORT d[8] (1911:1911:1911) (2044:2044:2044)) + (PORT d[9] (2000:2000:2000) (2165:2165:2165)) + (PORT d[10] (1691:1691:1691) (1849:1849:1849)) + (PORT d[11] (1991:1991:1991) (2092:2092:2092)) + (PORT d[12] (2025:2025:2025) (2206:2206:2206)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1365:1365:1365) (1299:1299:1299)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1844:1844:1844)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3178:3178:3178) (3291:3291:3291)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1697:1697:1697) (1824:1824:1824)) + (PORT d[1] (1990:1990:1990) (2122:2122:2122)) + (PORT d[2] (1947:1947:1947) (2080:2080:2080)) + (PORT d[3] (1733:1733:1733) (1875:1875:1875)) + (PORT d[4] (1994:1994:1994) (2145:2145:2145)) + (PORT d[5] (1515:1515:1515) (1664:1664:1664)) + (PORT d[6] (2088:2088:2088) (2261:2261:2261)) + (PORT d[7] (2027:2027:2027) (2179:2179:2179)) + (PORT d[8] (1912:1912:1912) (2044:2044:2044)) + (PORT d[9] (2001:2001:2001) (2165:2165:2165)) + (PORT d[10] (1692:1692:1692) (1849:1849:1849)) + (PORT d[11] (1992:1992:1992) (2092:2092:2092)) + (PORT d[12] (2026:2026:2026) (2206:2206:2206)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1365:1365:1365) (1299:1299:1299)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2229:2229:2229) (2452:2452:2452)) + (PORT datac (917:917:917) (935:935:935)) + (PORT datad (1306:1306:1306) (1332:1332:1332)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2883:2883:2883) (2988:2988:2988)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1960:1960:1960) (2086:2086:2086)) + (PORT d[1] (1945:1945:1945) (2125:2125:2125)) + (PORT d[2] (1971:1971:1971) (2132:2132:2132)) + (PORT d[3] (1766:1766:1766) (1913:1913:1913)) + (PORT d[4] (1945:1945:1945) (2126:2126:2126)) + (PORT d[5] (1865:1865:1865) (2025:2025:2025)) + (PORT d[6] (2059:2059:2059) (2199:2199:2199)) + (PORT d[7] (1959:1959:1959) (2120:2120:2120)) + (PORT d[8] (2245:2245:2245) (2378:2378:2378)) + (PORT d[9] (2021:2021:2021) (2210:2210:2210)) + (PORT d[10] (2196:2196:2196) (2442:2442:2442)) + (PORT d[11] (2254:2254:2254) (2367:2367:2367)) + (PORT d[12] (2061:2061:2061) (2263:2263:2263)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (1539:1539:1539) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1854:1854:1854)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2888:2888:2888) (2993:2993:2993)) + (PORT clk (1871:1871:1871) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (2062:2062:2062)) + (PORT d[1] (1933:1933:1933) (2100:2100:2100)) + (PORT d[2] (1928:1928:1928) (2069:2069:2069)) + (PORT d[3] (1767:1767:1767) (1913:1913:1913)) + (PORT d[4] (1924:1924:1924) (2101:2101:2101)) + (PORT d[5] (1866:1866:1866) (2025:2025:2025)) + (PORT d[6] (2060:2060:2060) (2199:2199:2199)) + (PORT d[7] (1960:1960:1960) (2120:2120:2120)) + (PORT d[8] (2246:2246:2246) (2378:2378:2378)) + (PORT d[9] (2022:2022:2022) (2210:2210:2210)) + (PORT d[10] (2197:2197:2197) (2442:2442:2442)) + (PORT d[11] (2255:2255:2255) (2367:2367:2367)) + (PORT d[12] (2062:2062:2062) (2263:2263:2263)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1896:1896:1896)) + (PORT d[0] (1539:1539:1539) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2303:2303:2303) (2389:2389:2389)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1974:1974:1974) (2117:2117:2117)) + (PORT d[1] (1926:1926:1926) (2107:2107:2107)) + (PORT d[2] (1892:1892:1892) (2023:2023:2023)) + (PORT d[3] (2018:2018:2018) (2177:2177:2177)) + (PORT d[4] (2218:2218:2218) (2413:2413:2413)) + (PORT d[5] (1772:1772:1772) (1925:1925:1925)) + (PORT d[6] (2015:2015:2015) (2155:2155:2155)) + (PORT d[7] (2023:2023:2023) (2199:2199:2199)) + (PORT d[8] (1873:1873:1873) (2013:2013:2013)) + (PORT d[9] (2016:2016:2016) (2205:2205:2205)) + (PORT d[10] (2301:2301:2301) (2478:2478:2478)) + (PORT d[11] (2004:2004:2004) (2138:2138:2138)) + (PORT d[12] (2070:2070:2070) (2273:2273:2273)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT d[0] (1618:1618:1618) (1535:1535:1535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1872:1872:1872) (1899:1899:1899)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2308:2308:2308) (2394:2394:2394)) + (PORT clk (1873:1873:1873) (1899:1899:1899)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1952:1952:1952) (2092:2092:2092)) + (PORT d[1] (1927:1927:1927) (2107:2107:2107)) + (PORT d[2] (1907:1907:1907) (2055:2055:2055)) + (PORT d[3] (2019:2019:2019) (2177:2177:2177)) + (PORT d[4] (2241:2241:2241) (2431:2431:2431)) + (PORT d[5] (1773:1773:1773) (1925:1925:1925)) + (PORT d[6] (2016:2016:2016) (2155:2155:2155)) + (PORT d[7] (2024:2024:2024) (2199:2199:2199)) + (PORT d[8] (1874:1874:1874) (2013:2013:2013)) + (PORT d[9] (2017:2017:2017) (2205:2205:2205)) + (PORT d[10] (2302:2302:2302) (2478:2478:2478)) + (PORT d[11] (2005:2005:2005) (2138:2138:2138)) + (PORT d[12] (2071:2071:2071) (2273:2273:2273)) + (PORT clk (1869:1869:1869) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1899:1899:1899)) + (PORT d[0] (1618:1618:1618) (1535:1535:1535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1900:1900:1900)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1833:1833:1833) (1858:1858:1858)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (604:604:604)) + (PORT datac (867:867:867) (931:931:931)) + (PORT datad (655:655:655) (682:682:682)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[14\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (374:374:374)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (830:830:830) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (612:612:612) (670:670:670)) + (PORT datad (450:450:450) (522:522:522)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2168:2168:2168) (2212:2212:2212)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1337:1337:1337) (1420:1420:1420)) + (PORT d[1] (1328:1328:1328) (1430:1430:1430)) + (PORT d[2] (1364:1364:1364) (1439:1439:1439)) + (PORT d[3] (1355:1355:1355) (1417:1417:1417)) + (PORT d[4] (1299:1299:1299) (1403:1403:1403)) + (PORT d[5] (1278:1278:1278) (1332:1332:1332)) + (PORT d[6] (1295:1295:1295) (1405:1405:1405)) + (PORT d[7] (1499:1499:1499) (1598:1598:1598)) + (PORT d[8] (1363:1363:1363) (1461:1461:1461)) + (PORT d[9] (1332:1332:1332) (1422:1422:1422)) + (PORT d[10] (1336:1336:1336) (1423:1423:1423)) + (PORT d[11] (1346:1346:1346) (1428:1428:1428)) + (PORT d[12] (1391:1391:1391) (1503:1503:1503)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (982:982:982) (966:966:966)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datac (611:611:611) (671:671:671)) + (PORT datad (452:452:452) (521:521:521)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (905:905:905) (924:924:924)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1580:1580:1580) (1688:1688:1688)) + (PORT d[1] (1302:1302:1302) (1409:1409:1409)) + (PORT d[2] (1611:1611:1611) (1712:1712:1712)) + (PORT d[3] (1734:1734:1734) (1874:1874:1874)) + (PORT d[4] (1682:1682:1682) (1815:1815:1815)) + (PORT d[5] (1491:1491:1491) (1641:1641:1641)) + (PORT d[6] (1673:1673:1673) (1775:1775:1775)) + (PORT d[7] (1894:1894:1894) (1992:1992:1992)) + (PORT d[8] (1660:1660:1660) (1786:1786:1786)) + (PORT d[9] (1691:1691:1691) (1820:1820:1820)) + (PORT d[10] (1748:1748:1748) (1931:1931:1931)) + (PORT d[11] (1900:1900:1900) (2024:2024:2024)) + (PORT d[12] (1764:1764:1764) (1943:1943:1943)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1353:1353:1353) (1332:1332:1332)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (612:612:612) (671:671:671)) + (PORT datad (451:451:451) (521:521:521)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2579:2579:2579) (2676:2676:2676)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1784:1784:1784) (1877:1877:1877)) + (PORT d[1] (1842:1842:1842) (1972:1972:1972)) + (PORT d[2] (1490:1490:1490) (1579:1579:1579)) + (PORT d[3] (1483:1483:1483) (1540:1540:1540)) + (PORT d[4] (1539:1539:1539) (1619:1619:1619)) + (PORT d[5] (1318:1318:1318) (1397:1397:1397)) + (PORT d[6] (1554:1554:1554) (1660:1660:1660)) + (PORT d[7] (1764:1764:1764) (1873:1873:1873)) + (PORT d[8] (1286:1286:1286) (1377:1377:1377)) + (PORT d[9] (1242:1242:1242) (1310:1310:1310)) + (PORT d[10] (1262:1262:1262) (1360:1360:1360)) + (PORT d[11] (1317:1317:1317) (1401:1401:1401)) + (PORT d[12] (1190:1190:1190) (1255:1255:1255)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1069:1069:1069) (1039:1039:1039)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (610:610:610) (668:668:668)) + (PORT datad (448:448:448) (518:518:518)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2427:2427:2427) (2508:2508:2508)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1117:1117:1117)) + (PORT d[1] (1049:1049:1049) (1160:1160:1160)) + (PORT d[2] (1086:1086:1086) (1148:1148:1148)) + (PORT d[3] (1062:1062:1062) (1134:1134:1134)) + (PORT d[4] (1559:1559:1559) (1650:1650:1650)) + (PORT d[5] (1057:1057:1057) (1151:1151:1151)) + (PORT d[6] (1108:1108:1108) (1213:1213:1213)) + (PORT d[7] (1269:1269:1269) (1366:1366:1366)) + (PORT d[8] (1333:1333:1333) (1424:1424:1424)) + (PORT d[9] (1102:1102:1102) (1207:1207:1207)) + (PORT d[10] (1349:1349:1349) (1437:1437:1437)) + (PORT d[11] (1129:1129:1129) (1210:1210:1210)) + (PORT d[12] (1284:1284:1284) (1360:1360:1360)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (846:846:846) (828:828:828)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (657:657:657) (705:705:705)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1889:1889:1889) (1911:1911:1911)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1977:1977:1977)) + (PORT datab (1135:1135:1135) (1147:1147:1147)) + (PORT datac (855:855:855) (891:891:891)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1209:1209:1209)) + (PORT datab (1425:1425:1425) (1483:1483:1483)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1911:1911:1911) (1992:1992:1992)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2172:2172:2172) (2339:2339:2339)) + (PORT d[1] (1564:1564:1564) (1694:1694:1694)) + (PORT d[2] (1725:1725:1725) (1839:1839:1839)) + (PORT d[3] (1747:1747:1747) (1811:1811:1811)) + (PORT d[4] (1741:1741:1741) (1810:1810:1810)) + (PORT d[5] (1548:1548:1548) (1644:1644:1644)) + (PORT d[6] (1530:1530:1530) (1633:1633:1633)) + (PORT d[7] (1459:1459:1459) (1557:1557:1557)) + (PORT d[8] (1541:1541:1541) (1649:1649:1649)) + (PORT d[9] (1471:1471:1471) (1529:1529:1529)) + (PORT d[10] (1489:1489:1489) (1593:1593:1593)) + (PORT d[11] (1557:1557:1557) (1641:1641:1641)) + (PORT d[12] (1770:1770:1770) (1827:1827:1827)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1273:1273:1273) (1267:1267:1267)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2250:2250:2250) (2330:2330:2330)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1978:1978:1978) (2147:2147:2147)) + (PORT d[1] (1517:1517:1517) (1633:1633:1633)) + (PORT d[2] (1736:1736:1736) (1836:1836:1836)) + (PORT d[3] (1746:1746:1746) (1798:1798:1798)) + (PORT d[4] (1738:1738:1738) (1807:1807:1807)) + (PORT d[5] (1573:1573:1573) (1658:1658:1658)) + (PORT d[6] (1555:1555:1555) (1647:1647:1647)) + (PORT d[7] (1442:1442:1442) (1529:1529:1529)) + (PORT d[8] (1539:1539:1539) (1634:1634:1634)) + (PORT d[9] (1492:1492:1492) (1553:1553:1553)) + (PORT d[10] (1509:1509:1509) (1617:1617:1617)) + (PORT d[11] (1582:1582:1582) (1654:1654:1654)) + (PORT d[12] (1740:1740:1740) (1798:1798:1798)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1245:1245:1245) (1209:1209:1209)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2717:2717:2717) (2805:2805:2805)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1059:1059:1059) (1142:1142:1142)) + (PORT d[1] (1091:1091:1091) (1165:1165:1165)) + (PORT d[2] (1060:1060:1060) (1123:1123:1123)) + (PORT d[3] (1344:1344:1344) (1418:1418:1418)) + (PORT d[4] (1302:1302:1302) (1409:1409:1409)) + (PORT d[5] (1050:1050:1050) (1118:1118:1118)) + (PORT d[6] (1031:1031:1031) (1111:1111:1111)) + (PORT d[7] (1231:1231:1231) (1307:1307:1307)) + (PORT d[8] (1068:1068:1068) (1146:1146:1146)) + (PORT d[9] (1109:1109:1109) (1198:1198:1198)) + (PORT d[10] (1092:1092:1092) (1176:1176:1176)) + (PORT d[11] (1106:1106:1106) (1187:1187:1187)) + (PORT d[12] (1080:1080:1080) (1183:1183:1183)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (829:829:829) (786:786:786)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1000:1000:1000) (1004:1004:1004)) @@ -2888,16 +7832,3838 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (992:992:992) (1066:1066:1066)) - (PORT datac (604:604:604) (608:608:608)) - (PORT datad (1039:1039:1039) (1055:1055:1055)) + (PORT dataa (1538:1538:1538) (1685:1685:1685)) + (PORT datab (1502:1502:1502) (1574:1574:1574)) + (PORT datac (1307:1307:1307) (1329:1329:1329)) + (PORT datad (983:983:983) (1060:1060:1060)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (898:898:898) (917:917:917)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1708:1708:1708) (1889:1889:1889)) + (PORT d[1] (1738:1738:1738) (1912:1912:1912)) + (PORT d[2] (2173:2173:2173) (2306:2306:2306)) + (PORT d[3] (1836:1836:1836) (1931:1931:1931)) + (PORT d[4] (2057:2057:2057) (2182:2182:2182)) + (PORT d[5] (1610:1610:1610) (1719:1719:1719)) + (PORT d[6] (1827:1827:1827) (1950:1950:1950)) + (PORT d[7] (2186:2186:2186) (2317:2317:2317)) + (PORT d[8] (1553:1553:1553) (1673:1673:1673)) + (PORT d[9] (1518:1518:1518) (1627:1627:1627)) + (PORT d[10] (1791:1791:1791) (1987:1987:1987)) + (PORT d[11] (1616:1616:1616) (1720:1720:1720)) + (PORT d[12] (1800:1800:1800) (1921:1921:1921)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1172:1172:1172) (1177:1177:1177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1573:1573:1573)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1093:1093:1093) (1101:1101:1101)) + (PORT datad (983:983:983) (1067:1067:1067)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2453:2453:2453) (2542:2542:2542)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1037:1037:1037) (1128:1128:1128)) + (PORT d[1] (1054:1054:1054) (1160:1160:1160)) + (PORT d[2] (1085:1085:1085) (1147:1147:1147)) + (PORT d[3] (1322:1322:1322) (1383:1383:1383)) + (PORT d[4] (1063:1063:1063) (1161:1161:1161)) + (PORT d[5] (1060:1060:1060) (1155:1155:1155)) + (PORT d[6] (1070:1070:1070) (1162:1162:1162)) + (PORT d[7] (1268:1268:1268) (1365:1365:1365)) + (PORT d[8] (1092:1092:1092) (1181:1181:1181)) + (PORT d[9] (1101:1101:1101) (1206:1206:1206)) + (PORT d[10] (1084:1084:1084) (1184:1184:1184)) + (PORT d[11] (1128:1128:1128) (1209:1209:1209)) + (PORT d[12] (1125:1125:1125) (1247:1247:1247)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (769:769:769) (752:752:752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2274:2274:2274) (2350:2350:2350)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1485:1485:1485) (1583:1583:1583)) + (PORT d[1] (1841:1841:1841) (1971:1971:1971)) + (PORT d[2] (1529:1529:1529) (1647:1647:1647)) + (PORT d[3] (1494:1494:1494) (1568:1568:1568)) + (PORT d[4] (1502:1502:1502) (1598:1598:1598)) + (PORT d[5] (1300:1300:1300) (1387:1387:1387)) + (PORT d[6] (1569:1569:1569) (1676:1676:1676)) + (PORT d[7] (1763:1763:1763) (1873:1873:1873)) + (PORT d[8] (1295:1295:1295) (1399:1399:1399)) + (PORT d[9] (1229:1229:1229) (1312:1312:1312)) + (PORT d[10] (1248:1248:1248) (1357:1357:1357)) + (PORT d[11] (1299:1299:1299) (1395:1395:1395)) + (PORT d[12] (1524:1524:1524) (1618:1618:1618)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1054:1054:1054) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2261:2261:2261) (2357:2357:2357)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1737:1737:1737) (1843:1843:1843)) + (PORT d[1] (1850:1850:1850) (1966:1966:1966)) + (PORT d[2] (1540:1540:1540) (1643:1643:1643)) + (PORT d[3] (1525:1525:1525) (1596:1596:1596)) + (PORT d[4] (1540:1540:1540) (1614:1614:1614)) + (PORT d[5] (1306:1306:1306) (1402:1402:1402)) + (PORT d[6] (1565:1565:1565) (1672:1672:1672)) + (PORT d[7] (1724:1724:1724) (1812:1812:1812)) + (PORT d[8] (1273:1273:1273) (1378:1378:1378)) + (PORT d[9] (1270:1270:1270) (1341:1341:1341)) + (PORT d[10] (1253:1253:1253) (1367:1367:1367)) + (PORT d[11] (1339:1339:1339) (1422:1422:1422)) + (PORT d[12] (1201:1201:1201) (1283:1283:1283)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1041:1041:1041) (1051:1051:1051)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1166:1166:1166)) + (PORT datab (302:302:302) (396:396:396)) + (PORT datac (1519:1519:1519) (1629:1629:1629)) + (PORT datad (1138:1138:1138) (1148:1148:1148)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2749:2749:2749) (2863:2863:2863)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (760:760:760) (843:843:843)) + (PORT d[1] (738:738:738) (819:819:819)) + (PORT d[2] (1007:1007:1007) (1067:1067:1067)) + (PORT d[3] (1327:1327:1327) (1409:1409:1409)) + (PORT d[4] (1070:1070:1070) (1153:1153:1153)) + (PORT d[5] (1291:1291:1291) (1393:1393:1393)) + (PORT d[6] (1016:1016:1016) (1096:1096:1096)) + (PORT d[7] (1254:1254:1254) (1327:1327:1327)) + (PORT d[8] (1046:1046:1046) (1125:1125:1125)) + (PORT d[9] (1067:1067:1067) (1150:1150:1150)) + (PORT d[10] (1263:1263:1263) (1344:1344:1344)) + (PORT d[11] (1288:1288:1288) (1365:1365:1365)) + (PORT d[12] (1238:1238:1238) (1306:1306:1306)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (821:821:821) (785:785:785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (865:865:865)) + (PORT datab (301:301:301) (396:396:396)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (818:818:818) (827:827:827)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1913:1913:1913) (1986:1986:1986)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1995:1995:1995) (2182:2182:2182)) + (PORT d[1] (1708:1708:1708) (1871:1871:1871)) + (PORT d[2] (2135:2135:2135) (2280:2280:2280)) + (PORT d[3] (2271:2271:2271) (2418:2418:2418)) + (PORT d[4] (2106:2106:2106) (2226:2226:2226)) + (PORT d[5] (1944:1944:1944) (2065:2065:2065)) + (PORT d[6] (1778:1778:1778) (1904:1904:1904)) + (PORT d[7] (2147:2147:2147) (2267:2267:2267)) + (PORT d[8] (1887:1887:1887) (2041:2041:2041)) + (PORT d[9] (1870:1870:1870) (1997:1997:1997)) + (PORT d[10] (1754:1754:1754) (1977:1977:1977)) + (PORT d[11] (1857:1857:1857) (2005:2005:2005)) + (PORT d[12] (2069:2069:2069) (2211:2211:2211)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1357:1357:1357) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3031:3031:3031) (3166:3166:3166)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1049:1049:1049) (1114:1114:1114)) + (PORT d[1] (1017:1017:1017) (1109:1109:1109)) + (PORT d[2] (1297:1297:1297) (1378:1378:1378)) + (PORT d[3] (1362:1362:1362) (1466:1466:1466)) + (PORT d[4] (1376:1376:1376) (1484:1484:1484)) + (PORT d[5] (1483:1483:1483) (1628:1628:1628)) + (PORT d[6] (1357:1357:1357) (1437:1437:1437)) + (PORT d[7] (1587:1587:1587) (1682:1682:1682)) + (PORT d[8] (1344:1344:1344) (1446:1446:1446)) + (PORT d[9] (1376:1376:1376) (1485:1485:1485)) + (PORT d[10] (1367:1367:1367) (1486:1486:1486)) + (PORT d[11] (1591:1591:1591) (1672:1672:1672)) + (PORT d[12] (1328:1328:1328) (1396:1396:1396)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1101:1101:1101) (1098:1098:1098)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1683:1683:1683)) + (PORT datab (1027:1027:1027) (1106:1106:1106)) + (PORT datac (1437:1437:1437) (1486:1486:1486)) + (PORT datad (1069:1069:1069) (1080:1080:1080)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2589:2589:2589) (2663:2663:2663)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1794:1794:1794) (1905:1905:1905)) + (PORT d[1] (1026:1026:1026) (1096:1096:1096)) + (PORT d[2] (1216:1216:1216) (1322:1322:1322)) + (PORT d[3] (1156:1156:1156) (1234:1234:1234)) + (PORT d[4] (1228:1228:1228) (1312:1312:1312)) + (PORT d[5] (1039:1039:1039) (1118:1118:1118)) + (PORT d[6] (1579:1579:1579) (1705:1705:1705)) + (PORT d[7] (1556:1556:1556) (1623:1623:1623)) + (PORT d[8] (999:999:999) (1083:1083:1083)) + (PORT d[9] (931:931:931) (997:997:997)) + (PORT d[10] (1049:1049:1049) (1130:1130:1130)) + (PORT d[11] (974:974:974) (1054:1054:1054)) + (PORT d[12] (938:938:938) (1003:1003:1003)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (785:785:785) (764:764:764)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3027:3027:3027) (3141:3141:3141)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1116:1116:1116)) + (PORT d[1] (1003:1003:1003) (1076:1076:1076)) + (PORT d[2] (1015:1015:1015) (1094:1094:1094)) + (PORT d[3] (1075:1075:1075) (1152:1152:1152)) + (PORT d[4] (1040:1040:1040) (1142:1142:1142)) + (PORT d[5] (1523:1523:1523) (1680:1680:1680)) + (PORT d[6] (1060:1060:1060) (1132:1132:1132)) + (PORT d[7] (1290:1290:1290) (1385:1385:1385)) + (PORT d[8] (1054:1054:1054) (1146:1146:1146)) + (PORT d[9] (1098:1098:1098) (1199:1199:1199)) + (PORT d[10] (1272:1272:1272) (1371:1371:1371)) + (PORT d[11] (1344:1344:1344) (1414:1414:1414)) + (PORT d[12] (1049:1049:1049) (1145:1145:1145)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (821:821:821) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1022:1022:1022) (1100:1100:1100)) + (PORT datac (1108:1108:1108) (1131:1131:1131)) + (PORT datad (1030:1030:1030) (1028:1028:1028)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2272:2272:2272) (2349:2349:2349)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1442:1442:1442) (1554:1554:1554)) + (PORT d[1] (1253:1253:1253) (1367:1367:1367)) + (PORT d[2] (1540:1540:1540) (1642:1642:1642)) + (PORT d[3] (1521:1521:1521) (1596:1596:1596)) + (PORT d[4] (1539:1539:1539) (1613:1613:1613)) + (PORT d[5] (1333:1333:1333) (1432:1432:1432)) + (PORT d[6] (1253:1253:1253) (1364:1364:1364)) + (PORT d[7] (1206:1206:1206) (1279:1279:1279)) + (PORT d[8] (1272:1272:1272) (1377:1377:1377)) + (PORT d[9] (1269:1269:1269) (1340:1340:1340)) + (PORT d[10] (1253:1253:1253) (1366:1366:1366)) + (PORT d[11] (1311:1311:1311) (1390:1390:1390)) + (PORT d[12] (1228:1228:1228) (1314:1314:1314)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1050:1050:1050) (1057:1057:1057)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1259:1259:1259)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1704:1704:1704) (1863:1863:1863)) + (PORT d[1] (1350:1350:1350) (1444:1444:1444)) + (PORT d[2] (1524:1524:1524) (1626:1626:1626)) + (PORT d[3] (1609:1609:1609) (1701:1701:1701)) + (PORT d[4] (1816:1816:1816) (1915:1915:1915)) + (PORT d[5] (1349:1349:1349) (1449:1449:1449)) + (PORT d[6] (1526:1526:1526) (1631:1631:1631)) + (PORT d[7] (1868:1868:1868) (2005:2005:2005)) + (PORT d[8] (1256:1256:1256) (1354:1354:1354)) + (PORT d[9] (1222:1222:1222) (1313:1313:1313)) + (PORT d[10] (1760:1760:1760) (1983:1983:1983)) + (PORT d[11] (1260:1260:1260) (1360:1360:1360)) + (PORT d[12] (1497:1497:1497) (1594:1594:1594)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1136:1136:1136) (1101:1101:1101)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3295:3295:3295) (3430:3430:3430)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1400:1400:1400) (1465:1465:1465)) + (PORT d[1] (1299:1299:1299) (1392:1392:1392)) + (PORT d[2] (1360:1360:1360) (1457:1457:1457)) + (PORT d[3] (1366:1366:1366) (1473:1473:1473)) + (PORT d[4] (1357:1357:1357) (1492:1492:1492)) + (PORT d[5] (1494:1494:1494) (1624:1624:1624)) + (PORT d[6] (1642:1642:1642) (1736:1736:1736)) + (PORT d[7] (1649:1649:1649) (1735:1735:1735)) + (PORT d[8] (1394:1394:1394) (1494:1494:1494)) + (PORT d[9] (1413:1413:1413) (1542:1542:1542)) + (PORT d[10] (1353:1353:1353) (1458:1458:1458)) + (PORT d[11] (1865:1865:1865) (1964:1964:1964)) + (PORT d[12] (1729:1729:1729) (1881:1881:1881)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1059:1059:1059) (1056:1056:1056)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1685:1685:1685)) + (PORT datab (1024:1024:1024) (1105:1105:1105)) + (PORT datac (844:844:844) (864:864:864)) + (PORT datad (1224:1224:1224) (1255:1255:1255)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (913:913:913) (963:963:963)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1599:1599:1599) (1720:1720:1720)) + (PORT d[1] (2019:2019:2019) (2145:2145:2145)) + (PORT d[2] (1619:1619:1619) (1729:1729:1729)) + (PORT d[3] (1723:1723:1723) (1862:1862:1862)) + (PORT d[4] (1885:1885:1885) (2025:2025:2025)) + (PORT d[5] (1472:1472:1472) (1621:1621:1621)) + (PORT d[6] (1660:1660:1660) (1786:1786:1786)) + (PORT d[7] (1903:1903:1903) (2010:2010:2010)) + (PORT d[8] (1677:1677:1677) (1831:1831:1831)) + (PORT d[9] (1733:1733:1733) (1891:1891:1891)) + (PORT d[10] (1717:1717:1717) (1862:1862:1862)) + (PORT d[11] (1563:1563:1563) (1687:1687:1687)) + (PORT d[12] (1762:1762:1762) (1918:1918:1918)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1302:1302:1302) (1308:1308:1308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1460:1460:1460)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1360:1360:1360) (1372:1372:1372)) + (PORT datad (988:988:988) (1066:1066:1066)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3036:3036:3036) (3166:3166:3166)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1070:1070:1070) (1137:1137:1137)) + (PORT d[1] (1268:1268:1268) (1329:1329:1329)) + (PORT d[2] (1017:1017:1017) (1100:1100:1100)) + (PORT d[3] (1083:1083:1083) (1176:1176:1176)) + (PORT d[4] (1049:1049:1049) (1156:1156:1156)) + (PORT d[5] (1511:1511:1511) (1661:1661:1661)) + (PORT d[6] (1059:1059:1059) (1156:1156:1156)) + (PORT d[7] (1328:1328:1328) (1409:1409:1409)) + (PORT d[8] (1088:1088:1088) (1193:1193:1193)) + (PORT d[9] (1082:1082:1082) (1187:1187:1187)) + (PORT d[10] (1284:1284:1284) (1353:1353:1353)) + (PORT d[11] (1286:1286:1286) (1362:1362:1362)) + (PORT d[12] (1088:1088:1088) (1169:1169:1169)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (790:790:790) (777:777:777)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1515:1515:1515) (1590:1590:1590)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1684:1684:1684) (1856:1856:1856)) + (PORT d[1] (1327:1327:1327) (1417:1417:1417)) + (PORT d[2] (1593:1593:1593) (1712:1712:1712)) + (PORT d[3] (1482:1482:1482) (1558:1558:1558)) + (PORT d[4] (1470:1470:1470) (1568:1568:1568)) + (PORT d[5] (1321:1321:1321) (1416:1416:1416)) + (PORT d[6] (1522:1522:1522) (1622:1622:1622)) + (PORT d[7] (1877:1877:1877) (1993:1993:1993)) + (PORT d[8] (1283:1283:1283) (1385:1385:1385)) + (PORT d[9] (1243:1243:1243) (1337:1337:1337)) + (PORT d[10] (1317:1317:1317) (1437:1437:1437)) + (PORT d[11] (1330:1330:1330) (1417:1417:1417)) + (PORT d[12] (1474:1474:1474) (1569:1569:1569)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1079:1079:1079) (1084:1084:1084)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3126:3126:3126)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1025:1025:1025) (1101:1101:1101)) + (PORT d[1] (1011:1011:1011) (1098:1098:1098)) + (PORT d[2] (1092:1092:1092) (1187:1187:1187)) + (PORT d[3] (1057:1057:1057) (1145:1145:1145)) + (PORT d[4] (1049:1049:1049) (1156:1156:1156)) + (PORT d[5] (1495:1495:1495) (1647:1647:1647)) + (PORT d[6] (1359:1359:1359) (1441:1441:1441)) + (PORT d[7] (1304:1304:1304) (1384:1384:1384)) + (PORT d[8] (1061:1061:1061) (1161:1161:1161)) + (PORT d[9] (1104:1104:1104) (1210:1210:1210)) + (PORT d[10] (1256:1256:1256) (1330:1330:1330)) + (PORT d[11] (1374:1374:1374) (1438:1438:1438)) + (PORT d[12] (1252:1252:1252) (1325:1325:1325)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (853:853:853) (827:827:827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (991:991:991)) + (PORT datab (1027:1027:1027) (1101:1101:1101)) + (PORT datac (1043:1043:1043) (1062:1062:1062)) + (PORT datad (1508:1508:1508) (1635:1635:1635)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3309:3309:3309) (3445:3445:3445)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1367:1367:1367) (1451:1451:1451)) + (PORT d[1] (1291:1291:1291) (1383:1383:1383)) + (PORT d[2] (1315:1315:1315) (1397:1397:1397)) + (PORT d[3] (1366:1366:1366) (1472:1472:1472)) + (PORT d[4] (1347:1347:1347) (1474:1474:1474)) + (PORT d[5] (1507:1507:1507) (1654:1654:1654)) + (PORT d[6] (1385:1385:1385) (1469:1469:1469)) + (PORT d[7] (1626:1626:1626) (1709:1709:1709)) + (PORT d[8] (1351:1351:1351) (1468:1468:1468)) + (PORT d[9] (1407:1407:1407) (1530:1530:1530)) + (PORT d[10] (1617:1617:1617) (1719:1719:1719)) + (PORT d[11] (1604:1604:1604) (1709:1709:1709)) + (PORT d[12] (1333:1333:1333) (1405:1405:1405)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1122:1122:1122) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (828:828:828)) + (PORT datab (1022:1022:1022) (1101:1101:1101)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1084:1084:1084) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1484:1484:1484) (1567:1567:1567)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1829:1829:1829) (1926:1926:1926)) + (PORT d[1] (1342:1342:1342) (1428:1428:1428)) + (PORT d[2] (1473:1473:1473) (1582:1582:1582)) + (PORT d[3] (1480:1480:1480) (1573:1573:1573)) + (PORT d[4] (1466:1466:1466) (1557:1557:1557)) + (PORT d[5] (1316:1316:1316) (1406:1406:1406)) + (PORT d[6] (1540:1540:1540) (1631:1631:1631)) + (PORT d[7] (1258:1258:1258) (1325:1325:1325)) + (PORT d[8] (1542:1542:1542) (1637:1637:1637)) + (PORT d[9] (1242:1242:1242) (1329:1329:1329)) + (PORT d[10] (1550:1550:1550) (1667:1667:1667)) + (PORT d[11] (1256:1256:1256) (1351:1351:1351)) + (PORT d[12] (1498:1498:1498) (1566:1566:1566)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1103:1103:1103) (1091:1091:1091)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2568:2568:2568) (2646:2646:2646)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1806:1806:1806) (1901:1901:1901)) + (PORT d[1] (1552:1552:1552) (1632:1632:1632)) + (PORT d[2] (1513:1513:1513) (1599:1599:1599)) + (PORT d[3] (1504:1504:1504) (1580:1580:1580)) + (PORT d[4] (1464:1464:1464) (1525:1525:1525)) + (PORT d[5] (1285:1285:1285) (1359:1359:1359)) + (PORT d[6] (1247:1247:1247) (1334:1334:1334)) + (PORT d[7] (1543:1543:1543) (1606:1606:1606)) + (PORT d[8] (1265:1265:1265) (1346:1346:1346)) + (PORT d[9] (1205:1205:1205) (1275:1275:1275)) + (PORT d[10] (1613:1613:1613) (1730:1730:1730)) + (PORT d[11] (1283:1283:1283) (1364:1364:1364)) + (PORT d[12] (1460:1460:1460) (1536:1536:1536)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1059:1059:1059) (1032:1032:1032)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1022:1022:1022)) + (PORT datab (882:882:882) (892:892:892)) + (PORT datac (1128:1128:1128) (1124:1124:1124)) + (PORT datad (1708:1708:1708) (1801:1801:1801)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1201:1201:1201) (1251:1251:1251)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1610:1610:1610) (1758:1758:1758)) + (PORT d[1] (1621:1621:1621) (1712:1712:1712)) + (PORT d[2] (1839:1839:1839) (1958:1958:1958)) + (PORT d[3] (1774:1774:1774) (1842:1842:1842)) + (PORT d[4] (1809:1809:1809) (1925:1925:1925)) + (PORT d[5] (1642:1642:1642) (1742:1742:1742)) + (PORT d[6] (1842:1842:1842) (1953:1953:1953)) + (PORT d[7] (1571:1571:1571) (1692:1692:1692)) + (PORT d[8] (1574:1574:1574) (1694:1694:1694)) + (PORT d[9] (1542:1542:1542) (1654:1654:1654)) + (PORT d[10] (1756:1756:1756) (1975:1975:1975)) + (PORT d[11] (1677:1677:1677) (1772:1772:1772)) + (PORT d[12] (1793:1793:1793) (1908:1908:1908)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1243:1243:1243) (1306:1306:1306)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2741:2741:2741) (2845:2845:2845)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (732:732:732) (812:812:812)) + (PORT d[1] (730:730:730) (809:809:809)) + (PORT d[2] (748:748:748) (807:807:807)) + (PORT d[3] (798:798:798) (865:865:865)) + (PORT d[4] (1302:1302:1302) (1410:1410:1410)) + (PORT d[5] (857:857:857) (940:940:940)) + (PORT d[6] (1335:1335:1335) (1404:1404:1404)) + (PORT d[7] (754:754:754) (826:826:826)) + (PORT d[8] (751:751:751) (827:827:827)) + (PORT d[9] (765:765:765) (842:842:842)) + (PORT d[10] (781:781:781) (864:864:864)) + (PORT d[11] (801:801:801) (859:859:859)) + (PORT d[12] (1765:1765:1765) (1920:1920:1920)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (714:714:714) (664:664:664)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1020:1020:1020)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1145:1145:1145) (1151:1151:1151)) + (PORT datad (1040:1040:1040) (1038:1038:1038)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2732:2732:2732) (2820:2820:2820)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1061:1061:1061) (1156:1156:1156)) + (PORT d[1] (1068:1068:1068) (1164:1164:1164)) + (PORT d[2] (1093:1093:1093) (1176:1176:1176)) + (PORT d[3] (1101:1101:1101) (1184:1184:1184)) + (PORT d[4] (1051:1051:1051) (1154:1154:1154)) + (PORT d[5] (1803:1803:1803) (1981:1981:1981)) + (PORT d[6] (1321:1321:1321) (1401:1401:1401)) + (PORT d[7] (1240:1240:1240) (1328:1328:1328)) + (PORT d[8] (1072:1072:1072) (1167:1167:1167)) + (PORT d[9] (1096:1096:1096) (1195:1195:1195)) + (PORT d[10] (1053:1053:1053) (1146:1146:1146)) + (PORT d[11] (1088:1088:1088) (1182:1182:1182)) + (PORT d[12] (1139:1139:1139) (1250:1250:1250)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (820:820:820) (798:798:798)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1186:1186:1186) (1254:1254:1254)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1633:1633:1633) (1730:1730:1730)) + (PORT d[1] (1706:1706:1706) (1835:1835:1835)) + (PORT d[2] (1902:1902:1902) (2011:2011:2011)) + (PORT d[3] (1689:1689:1689) (1841:1841:1841)) + (PORT d[4] (1895:1895:1895) (2039:2039:2039)) + (PORT d[5] (1462:1462:1462) (1587:1587:1587)) + (PORT d[6] (1692:1692:1692) (1844:1844:1844)) + (PORT d[7] (2176:2176:2176) (2279:2279:2279)) + (PORT d[8] (2000:2000:2000) (2161:2161:2161)) + (PORT d[9] (2005:2005:2005) (2193:2193:2193)) + (PORT d[10] (1430:1430:1430) (1590:1590:1590)) + (PORT d[11] (2146:2146:2146) (2285:2285:2285)) + (PORT d[12] (1786:1786:1786) (1943:1943:1943)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1074:1074:1074) (1078:1078:1078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (906:906:906)) + (PORT datab (302:302:302) (396:396:396)) + (PORT datac (1517:1517:1517) (1627:1627:1627)) + (PORT datad (1452:1452:1452) (1515:1515:1515)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3319:3319:3319) (3470:3470:3470)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1379:1379:1379) (1448:1448:1448)) + (PORT d[1] (1321:1321:1321) (1413:1413:1413)) + (PORT d[2] (1557:1557:1557) (1658:1658:1658)) + (PORT d[3] (1719:1719:1719) (1851:1851:1851)) + (PORT d[4] (1357:1357:1357) (1492:1492:1492)) + (PORT d[5] (1462:1462:1462) (1589:1589:1589)) + (PORT d[6] (1645:1645:1645) (1743:1743:1743)) + (PORT d[7] (1604:1604:1604) (1700:1700:1700)) + (PORT d[8] (1383:1383:1383) (1508:1508:1508)) + (PORT d[9] (1391:1391:1391) (1519:1519:1519)) + (PORT d[10] (1384:1384:1384) (1542:1542:1542)) + (PORT d[11] (1581:1581:1581) (1677:1677:1677)) + (PORT d[12] (1786:1786:1786) (1940:1940:1940)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1124:1124:1124) (1095:1095:1095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2440:2440:2440) (2510:2510:2510)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1328:1328:1328) (1418:1418:1418)) + (PORT d[1] (1327:1327:1327) (1415:1415:1415)) + (PORT d[2] (1338:1338:1338) (1400:1400:1400)) + (PORT d[3] (1424:1424:1424) (1493:1493:1493)) + (PORT d[4] (1571:1571:1571) (1657:1657:1657)) + (PORT d[5] (1300:1300:1300) (1371:1371:1371)) + (PORT d[6] (1293:1293:1293) (1389:1389:1389)) + (PORT d[7] (1497:1497:1497) (1583:1583:1583)) + (PORT d[8] (1339:1339:1339) (1429:1429:1429)) + (PORT d[9] (1353:1353:1353) (1446:1446:1446)) + (PORT d[10] (1332:1332:1332) (1421:1421:1421)) + (PORT d[11] (1372:1372:1372) (1441:1441:1441)) + (PORT d[12] (1339:1339:1339) (1448:1448:1448)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1003:1003:1003) (985:985:985)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (303:303:303) (400:400:400)) + (PORT datac (1160:1160:1160) (1176:1176:1176)) + (PORT datad (1074:1074:1074) (1066:1066:1066)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (952:952:952)) + (PORT datac (702:702:702) (800:800:800)) + (PORT datad (645:645:645) (654:654:654)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1105:1105:1105)) + (PORT datac (616:616:616) (620:620:620)) + (PORT datad (342:342:342) (355:355:355)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (996:996:996)) + (PORT datab (1022:1022:1022) (1101:1101:1101)) + (PORT datad (1506:1506:1506) (1591:1591:1591)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1105:1105:1105)) + (PORT datac (646:646:646) (656:656:656)) + (PORT datad (652:652:652) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1024:1024:1024) (1103:1103:1103)) + (PORT datac (1317:1317:1317) (1316:1316:1316)) + (PORT datad (631:631:631) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (697:697:697)) + (PORT datac (994:994:994) (1070:1070:1070)) + (PORT datad (660:660:660) (670:670:670)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1989:1989:1989) (2097:2097:2097)) + (PORT datac (635:635:635) (654:654:654)) + (PORT datad (343:343:343) (356:356:356)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (981:981:981)) + (PORT datac (989:989:989) (1063:1063:1063)) + (PORT datad (1104:1104:1104) (1106:1106:1106)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) ) diff --git a/spectrum.qsf b/spectrum.qsf index 527833d..1dba503 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -411,4 +411,5 @@ set_global_assignment -name MIF_FILE output_files/led_patterns.mif set_global_assignment -name MIF_FILE led_patterns.mif set_global_assignment -name QIP_FILE rom0.qip set_global_assignment -name QIP_FILE ram16.qip +set_global_assignment -name QIP_FILE ram32.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.v b/spectrum.v index 8dab1aa..3a73535 100644 --- a/spectrum.v +++ b/spectrum.v @@ -1,53 +1,72 @@ -module spectrum( - input CLOCK_50, - output wire[7:0] LED -); +module spectrum(input CLOCK_50, + output wire[7:0] LED, + output wire[33:0] GPIO_0); + + + // ROM, 16K + wire[7:0] rom_data; + rom0 rom( + .address(A), + .clock(CLOCK_50), + .q(rom_data) + ); + + + reg [15:0] A; // Global address bus + wire [7:0] D; // CPU data bus + wire [7:0] ram0_data; // Internal 16K RAM data + wire RamWE; + // assign RamWE = A[15:14] == 2'b01 && nIORQ == 1 && nRD == 1 && nWR == 0; + assign RamWE = 0; + + // VRAM, 16K + wire[12:0] vram_address; + wire[7:0] vram_data; + ram16 ram0( + .clock(CLOCK_50), + + .address_a(A[13:0]), + .data_a(D), + .q_a(ram0_data), + .wren_a(0), + + // .address_b({1'b0, vram_address}), + .address_b(A[13:0]), + .data_b(8'b0), + .q_b(vram_data), + .wren_b(0) + ); + + // Rest of RAM, 32K + wire[7:0] ram1_data; + ram32 ram1( + .clock(CLOCK_50), + + .address(A[14:0]), + .data(D), + .q(ram1_data), + .wren(0) + ); + + + reg[21:0] counter; + always @(posedge CLOCK_50) + begin + counter <= counter + 1; + if (counter == 0) + begin + A <= A + 1; + end + end -reg[13:0] address; -wire[7:0] mem_data; - -rom0 rom( - .address(address), - .clock(CLOCK_50), - .q(mem_data) -); - - -reg [15:0] A; // Global address bus -wire [7:0] D; // CPU data bus -wire [7:0] ram_data; // Internal 16K RAM data -wire RamWE; -// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0; -assign RamWE = 0; -wire[12:0] vram_address; -wire[7:0] vram_data; - -ram16 ram0( - .clock(CLOCK_50), - - .address_a({12'b0, A[2:0]}), - .data_a(D), - .q_a(ram_data), - .wren_a(0), - -// .address_b({1'b0, vram_address}), - .address_b(A[13:0]), - .data_b(8'b0), - .q_b(vram_data), - .wren_b(0) -); - -reg[21:0] counter; -always @(posedge CLOCK_50) -begin - counter <= counter + 1; - if (counter == 0) - begin - address <= address + 1; - A <= A + 1; - end -end -assign LED[3:0] = ram_data[3:0]; -assign LED[7:4] = mem_data[7:4]; - -endmodule \ No newline at end of file + // make the leds blink with rom and ram0 data + assign LED[3:0] = rom_data[3:0]; + assign LED[7:4] = ram0_data[7:4]; + + // expose memories at A to GPIO_0 + assign GPIO_0[7:0] = rom_data; + assign GPIO_0[15:8] = ram0_data; + assign GPIO_0[23:16] = ram1_data; + assign GPIO_0[31:24] = vram_data; + +endmodule

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