Sample memory model with all components

2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
@@ -1,53 +1,72 @@
-module spectrum(
-	input CLOCK_50,
-	output wire[7:0] LED
-);
+module spectrum(input CLOCK_50,
+                output wire[7:0] LED,
+                output wire[33:0] GPIO_0);
+    
+    
+    // ROM, 16K
+    wire[7:0]  rom_data;
+    rom0 rom(
+		.address(A),
+		.clock(CLOCK_50),
+		.q(rom_data)
+    );
+    
+    
+    reg [15:0] A;                 // Global address bus
+    wire [7:0] D;                 // CPU data bus
+    wire [7:0] ram0_data;         // Internal 16K RAM data
+    wire RamWE;
+    // assign RamWE = A[15:14] == 2'b01 && nIORQ == 1 && nRD == 1 && nWR == 0;
+    assign RamWE    = 0;
+    
+    // VRAM, 16K
+    wire[12:0] vram_address;
+    wire[7:0] vram_data;
+    ram16 ram0(
+		.clock(CLOCK_50),
+		
+		.address_a(A[13:0]),
+		.data_a(D),
+		.q_a(ram0_data),
+		.wren_a(0),
+		
+		//	.address_b({1'b0, vram_address}),
+		.address_b(A[13:0]),
+		.data_b(8'b0),
+		.q_b(vram_data),
+		.wren_b(0)
+    );
+    
+    // Rest of RAM, 32K
+    wire[7:0] ram1_data;
+    ram32 ram1(
+		.clock(CLOCK_50),
+		
+		.address(A[14:0]),
+		.data(D),
+		.q(ram1_data),
+		.wren(0)
+    );
+    
+    
+    reg[21:0] counter;
+    always @(posedge CLOCK_50)
+    begin
+        counter <= counter + 1;
+        if (counter == 0)
+        begin
+            A <= A + 1;
+        end
+    end

-reg[13:0]  address;
-wire[7:0]  mem_data;
-	
-rom0 rom(
-	.address(address),
-	.clock(CLOCK_50),
-	.q(mem_data)
-);
-
-
-reg [15:0] A;                  // Global address bus
-wire [7:0] D;                   // CPU data bus
-wire [7:0] ram_data;            // Internal 16K RAM data
-wire RamWE;
-// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;
-assign RamWE = 0;
-wire[12:0] vram_address;
-wire[7:0] vram_data;
-
-ram16 ram0(
-	.clock(CLOCK_50),
-	
-	.address_a({12'b0, A[2:0]}),
-	.data_a(D),
-	.q_a(ram_data),
-	.wren_a(0),
-	
-//	.address_b({1'b0, vram_address}),
-	.address_b(A[13:0]),
-	.data_b(8'b0),
-	.q_b(vram_data),
-	.wren_b(0)
-);
-
-reg[21:0] counter;
-always @(posedge CLOCK_50) 
-begin
-	counter <= counter + 1;
-	if (counter == 0)
-	begin
-		address <= address + 1;
-		A <= A + 1;
-	end
-end
-assign LED[3:0] = ram_data[3:0];
-assign LED[7:4] = mem_data[7:4];
-
-endmodule
+	// make the leds blink with rom and ram0 data
+    assign LED[3:0] = rom_data[3:0];
+    assign LED[7:4] = ram0_data[7:4];
+    
+	// expose memories at A to GPIO_0
+    assign GPIO_0[7:0]   = rom_data;
+    assign GPIO_0[15:8]  = ram0_data;
+    assign GPIO_0[23:16] = ram1_data;
+    assign GPIO_0[31:24] = vram_data;
+    
+endmodule