Sample memory model with all components

2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram32.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram32_bb.v"]