Sample memory model with all components
This commit is contained in:
+527
-148
@@ -1,5 +1,5 @@
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Analysis & Synthesis report for spectrum
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Wed Mar 30 13:47:09 2022
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Wed Mar 30 14:56:01 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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@@ -16,17 +16,19 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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8. Analysis & Synthesis RAM Summary
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9. Analysis & Synthesis IP Cores Summary
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10. Registers Removed During Synthesis
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11. Removed Registers Triggering Further Register Optimizations
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12. General Register Statistics
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13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
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14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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11. General Register Statistics
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12. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
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13. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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14. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
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15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
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16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
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17. altsyncram Parameter Settings by Entity Instance
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18. Port Connectivity Checks: "ram16:ram0"
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19. Port Connectivity Checks: "rom0:rom"
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20. Elapsed Time Per Partition
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21. Analysis & Synthesis Messages
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17. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
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18. altsyncram Parameter Settings by Entity Instance
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19. Port Connectivity Checks: "ram32:ram1"
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20. Port Connectivity Checks: "ram16:ram0"
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21. Port Connectivity Checks: "rom0:rom"
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22. Elapsed Time Per Partition
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23. Analysis & Synthesis Messages
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@@ -52,18 +54,18 @@ applicable agreement for further details.
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+---------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+--------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ;
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; Analysis & Synthesis Status ; Successful - Wed Mar 30 14:56:01 2022 ;
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; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 50 ;
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; Total combinational functions ; 48 ;
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; Dedicated logic registers ; 38 ;
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; Total registers ; 38 ;
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; Total pins ; 9 ;
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; Total logic elements ; 94 ;
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; Total combinational functions ; 90 ;
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; Dedicated logic registers ; 41 ;
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; Total registers ; 41 ;
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; Total pins ; 43 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 98,304 ;
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; Total memory bits ; 524,288 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+--------------------------------------------+
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@@ -429,6 +431,12 @@ File Type : User Wizard-Generated File
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File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
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Library :
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File Name with User-Entered Path : ram32.v
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Used in Netlist : yes
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File Type : User Wizard-Generated File
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File Name with Absolute Path : /home/benny/work/fpga/projects/ram32.v
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Library :
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File Name with User-Entered Path : altsyncram.tdf
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Used in Netlist : yes
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File Type : Megafunction
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@@ -518,6 +526,30 @@ Used in Netlist : yes
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File Type : Auto-Generated Megafunction
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File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
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Library :
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File Name with User-Entered Path : db/altsyncram_g9i1.tdf
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Used in Netlist : yes
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File Type : Auto-Generated Megafunction
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File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf
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Library :
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File Name with User-Entered Path : db/decode_msa.tdf
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Used in Netlist : yes
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File Type : Auto-Generated Megafunction
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File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_msa.tdf
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Library :
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File Name with User-Entered Path : db/decode_f8a.tdf
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Used in Netlist : yes
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File Type : Auto-Generated Megafunction
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File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_f8a.tdf
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Library :
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File Name with User-Entered Path : db/mux_6nb.tdf
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Used in Netlist : yes
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File Type : Auto-Generated Megafunction
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File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_6nb.tdf
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Library :
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+--------------------------------------------------------------------------------+
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@@ -527,29 +559,29 @@ Library :
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+---------------------------------------------+----------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------+
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; Estimated Total logic elements ; 50 ;
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; Estimated Total logic elements ; 94 ;
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; ; ;
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; Total combinational functions ; 48 ;
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; Total combinational functions ; 90 ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 7 ;
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; -- 3 input functions ; 6 ;
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; -- <=2 input functions ; 35 ;
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; -- 4 input functions ; 24 ;
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; -- 3 input functions ; 26 ;
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; -- <=2 input functions ; 40 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 16 ;
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; -- arithmetic mode ; 32 ;
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; -- normal mode ; 57 ;
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; -- arithmetic mode ; 33 ;
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; ; ;
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; Total registers ; 38 ;
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; -- Dedicated logic registers ; 38 ;
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; Total registers ; 41 ;
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; -- Dedicated logic registers ; 41 ;
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; -- I/O registers ; 0 ;
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; ; ;
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; I/O pins ; 9 ;
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; Total memory bits ; 98304 ;
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; I/O pins ; 43 ;
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; Total memory bits ; 524288 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Maximum fan-out node ; CLOCK_50~input ;
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; Maximum fan-out ; 50 ;
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; Total fan-out ; 401 ;
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; Average fan-out ; 3.46 ;
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; Maximum fan-out ; 105 ;
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; Total fan-out ; 1436 ;
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; Average fan-out ; 5.11 ;
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+---------------------------------------------+----------------+
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@@ -557,21 +589,21 @@ Library :
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; Analysis & Synthesis Resource Utilization by Entity ;
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+--------------------------------------------------------------------------------+
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Compilation Hierarchy Node : |spectrum
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LC Combinationals : 48 (44)
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LC Registers : 38 (36)
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Memory Bits : 98304
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LC Combinationals : 90 (46)
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LC Registers : 41 (37)
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Memory Bits : 524288
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 9
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Pins : 43
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum
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Library Name : work
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Compilation Hierarchy Node : |ram16:ram0|
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LC Combinationals : 0 (0)
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LC Combinationals : 16 (0)
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LC Registers : 0 (0)
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Memory Bits : 32768
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -581,9 +613,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0
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Library Name : work
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Compilation Hierarchy Node : |altsyncram:altsyncram_component|
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LC Combinationals : 0 (0)
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LC Combinationals : 16 (0)
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LC Registers : 0 (0)
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Memory Bits : 32768
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -593,9 +625,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
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Library Name : work
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Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
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LC Combinationals : 0 (0)
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LC Combinationals : 16 (0)
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LC Registers : 0 (0)
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Memory Bits : 32768
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -604,10 +636,94 @@ Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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Library Name : work
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Compilation Hierarchy Node : |mux_3nb:mux4|
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LC Combinationals : 8 (8)
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LC Registers : 0 (0)
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Memory Bits : 0
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4
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Library Name : work
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Compilation Hierarchy Node : |mux_3nb:mux5|
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LC Combinationals : 8 (8)
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LC Registers : 0 (0)
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Memory Bits : 0
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5
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Library Name : work
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Compilation Hierarchy Node : |ram32:ram1|
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LC Combinationals : 20 (0)
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LC Registers : 4 (0)
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Memory Bits : 262144
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram32:ram1
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Library Name : work
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Compilation Hierarchy Node : |altsyncram:altsyncram_component|
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LC Combinationals : 20 (0)
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LC Registers : 4 (0)
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Memory Bits : 262144
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component
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Library Name : work
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Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
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LC Combinationals : 20 (0)
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LC Registers : 4 (4)
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Memory Bits : 262144
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
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Library Name : work
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Compilation Hierarchy Node : |decode_f8a:rden_decode|
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LC Combinationals : 4 (4)
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LC Registers : 0 (0)
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Memory Bits : 0
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
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Library Name : work
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Compilation Hierarchy Node : |mux_6nb:mux2|
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LC Combinationals : 16 (16)
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LC Registers : 0 (0)
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Memory Bits : 0
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 0
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
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Library Name : work
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Compilation Hierarchy Node : |rom0:rom|
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LC Combinationals : 4 (0)
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LC Registers : 2 (0)
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Memory Bits : 65536
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LC Combinationals : 8 (0)
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LC Registers : 0 (0)
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -617,9 +733,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
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Library Name : work
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Compilation Hierarchy Node : |altsyncram:altsyncram_component|
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LC Combinationals : 4 (0)
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LC Registers : 2 (0)
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Memory Bits : 65536
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LC Combinationals : 8 (0)
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LC Registers : 0 (0)
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -629,9 +745,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
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Library Name : work
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Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
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LC Combinationals : 4 (0)
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LC Registers : 2 (2)
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Memory Bits : 65536
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LC Combinationals : 8 (0)
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LC Registers : 0 (0)
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Memory Bits : 131072
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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@@ -641,7 +757,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
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Library Name : work
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Compilation Hierarchy Node : |mux_3nb:mux2|
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LC Combinationals : 4 (4)
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LC Combinationals : 8 (8)
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LC Registers : 0 (0)
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Memory Bits : 0
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DSP Elements : 0
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@@ -669,6 +785,16 @@ Port B Width : 8
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Size : 131072
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MIF : led_patterns.mif
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Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM
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Type : AUTO
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Mode : Single Port
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Port A Depth : 32768
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Port A Width : 8
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Port B Depth : --
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Port B Width : --
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Size : 262144
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MIF : led_patterns.mif
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Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
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Type : AUTO
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Mode : ROM
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@@ -693,6 +819,14 @@ License Type : N/A
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Entity Instance : |spectrum|ram16:ram0
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IP Include File : /home/benny/work/fpga/projects/ram16.v
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Vendor : Altera
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IP Core Name : RAM: 1-PORT
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Version : 13.1
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Release Date : N/A
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License Type : N/A
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Entity Instance : |spectrum|ram32:ram1
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IP Include File : /home/benny/work/fpga/projects/ram32.v
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Vendor : Altera
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IP Core Name : ROM: 1-PORT
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||||
Version : 13.1
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@@ -704,40 +838,20 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
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+-----------------------------------------------------------------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+------------------------------------------------------------------------------------------------+----------------------------------------+
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; Register name ; Reason for Removal ;
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+------------------------------------------------------------------------------------------------+----------------------------------------+
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; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
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; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
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; address[0] ; Merged with A[0] ;
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||||
; address[1] ; Merged with A[1] ;
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||||
; address[2] ; Merged with A[2] ;
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; address[3] ; Merged with A[3] ;
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||||
; address[4] ; Merged with A[4] ;
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||||
; address[5] ; Merged with A[5] ;
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||||
; address[6] ; Merged with A[6] ;
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||||
; address[7] ; Merged with A[7] ;
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||||
; address[8] ; Merged with A[8] ;
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||||
; address[9] ; Merged with A[9] ;
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||||
; address[10] ; Merged with A[10] ;
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||||
; address[11] ; Merged with A[11] ;
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||||
; address[12] ; Merged with A[12] ;
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||||
; address[13] ; Merged with A[13] ;
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||||
; A[14,15] ; Lost fanout ;
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||||
; Total Number of Removed Registers = 18 ; ;
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||||
+------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
|
||||
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||||
+--------------------------------------------------------------------------------+
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; Removed Registers Triggering Further Register Optimizations ;
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||||
+--------------------------------------------------------------------------------+
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||||
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
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Reason for Removal : Stuck at GNDdue to stuck port data_in
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Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
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||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Registers Removed During Synthesis ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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||||
; Register name ; Reason for Removal ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; A[15] ; Lost fanout ;
|
||||
; Total Number of Removed Registers = 7 ; ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
@@ -745,12 +859,12 @@ Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_compon
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 38 ;
|
||||
; Total registers ; 41 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 13 ;
|
||||
; Number of registers using Clock Enable ; 14 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@@ -777,6 +891,17 @@ To : -
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
|
||||
Value : NORMAL_COMPILATION
|
||||
From : -
|
||||
To : -
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
@@ -1207,12 +1332,227 @@ Type : Untyped
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : BYTE_SIZE_BLOCK
|
||||
Value : 8
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : AUTO_CARRY_CHAINS
|
||||
Value : ON
|
||||
Type : AUTO_CARRY
|
||||
|
||||
Parameter Name : IGNORE_CARRY_BUFFERS
|
||||
Value : OFF
|
||||
Type : IGNORE_CARRY
|
||||
|
||||
Parameter Name : AUTO_CASCADE_CHAINS
|
||||
Value : ON
|
||||
Type : AUTO_CASCADE
|
||||
|
||||
Parameter Name : IGNORE_CASCADE_BUFFERS
|
||||
Value : OFF
|
||||
Type : IGNORE_CASCADE
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OPERATION_MODE
|
||||
Value : SINGLE_PORT
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_A
|
||||
Value : 8
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : WIDTHAD_A
|
||||
Value : 15
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : NUMWORDS_A
|
||||
Value : 32768
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : OUTDATA_REG_A
|
||||
Value : CLOCK0
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTHAD_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : NUMWORDS_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_WRADDRESS_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RDCONTROL_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_REG_B
|
||||
Value : UNREGISTERED
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RDCONTROL_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA_A
|
||||
Value : 1
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RAM_BLOCK_TYPE
|
||||
Value : AUTO
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTE_SIZE
|
||||
Value : 8
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
|
||||
Value : DONT_CARE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
|
||||
Value : NEW_DATA_NO_NBE_READ
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
|
||||
Value : NEW_DATA_NO_NBE_READ
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INIT_FILE
|
||||
Value : led_patterns.mif
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INIT_FILE_LAYOUT
|
||||
Value : PORT_A
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : MAXIMUM_DEPTH
|
||||
Value : 0
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_INPUT_A
|
||||
Value : BYPASS
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_INPUT_B
|
||||
Value : NORMAL
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_OUTPUT_A
|
||||
Value : BYPASS
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_OUTPUT_B
|
||||
Value : NORMAL
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_CORE_A
|
||||
Value : USE_INPUT_CLKEN
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_CORE_B
|
||||
Value : USE_INPUT_CLKEN
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ENABLE_ECC
|
||||
Value : FALSE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
|
||||
Value : FALSE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_ECCSTATUS
|
||||
Value : 3
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : DEVICE_FAMILY
|
||||
Value : Cyclone IV E
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CBXI_PARAMETER
|
||||
Value : altsyncram_g9i1
|
||||
Type : Untyped
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; altsyncram Parameter Settings by Entity Instance ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
; Name ; Value ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
; Number of entity instances ; 2 ;
|
||||
; Number of entity instances ; 3 ;
|
||||
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
|
||||
; -- OPERATION_MODE ; ROM ;
|
||||
; -- WIDTH_A ; 8 ;
|
||||
@@ -1235,27 +1575,39 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
; -- OUTDATA_REG_B ; CLOCK0 ;
|
||||
; -- RAM_BLOCK_TYPE ; AUTO ;
|
||||
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
||||
; Entity Instance ; ram32:ram1|altsyncram:altsyncram_component ;
|
||||
; -- OPERATION_MODE ; SINGLE_PORT ;
|
||||
; -- WIDTH_A ; 8 ;
|
||||
; -- NUMWORDS_A ; 32768 ;
|
||||
; -- OUTDATA_REG_A ; CLOCK0 ;
|
||||
; -- WIDTH_B ; 1 ;
|
||||
; -- NUMWORDS_B ; 1 ;
|
||||
; -- ADDRESS_REG_B ; CLOCK1 ;
|
||||
; -- OUTDATA_REG_B ; UNREGISTERED ;
|
||||
; -- RAM_BLOCK_TYPE ; AUTO ;
|
||||
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "ram32:ram1" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : wren
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
|
||||
Port : wren[-1]
|
||||
Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "ram16:ram0" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : address_a
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
|
||||
Port : address_a[13..3]
|
||||
Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
|
||||
Port : q_a[7..4]
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
|
||||
Port : wren_a
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
@@ -1271,11 +1623,6 @@ Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
|
||||
Port : q_b
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
|
||||
Port : wren_b
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
@@ -1292,10 +1639,10 @@ Details : Stuck at GND
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "rom0:rom" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : q[3..0]
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
Port : address
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (16 bits) is wider than the input port (14 bits) it drives. The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
@@ -1315,7 +1662,7 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Wed Mar 30 13:47:07 2022
|
||||
Info: Processing started: Wed Mar 30 14:55:59 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
|
||||
@@ -1324,11 +1671,13 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
|
||||
Info (12023): Found entity 1: rom0
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
|
||||
Info (12023): Found entity 1: ram16
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
|
||||
Info (12023): Found entity 1: ram32
|
||||
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(18): object "RamWE" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(55): truncated value with size 32 to match size of target (22)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(58): truncated value with size 32 to match size of target (16)
|
||||
Warning (10034): Output port "GPIO_0[33..32]" at spectrum.v(3) has no driver
|
||||
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
|
||||
@@ -1393,41 +1742,71 @@ Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|alt
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
|
||||
Info (12023): Found entity 1: decode_jsa
|
||||
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
|
||||
Warning (14284): Synthesized away the following node(s):
|
||||
Warning (14285): Synthesized away the following RAM node(s):
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"
|
||||
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Info (12128): Elaborating entity "ram32" for hierarchy "ram32:ram1"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram32:ram1|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "ram32:ram1|altsyncram:altsyncram_component"
|
||||
Info (12133): Instantiated megafunction "ram32:ram1|altsyncram:altsyncram_component" with the following parameter:
|
||||
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
|
||||
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
|
||||
Info (12134): Parameter "init_file" = "led_patterns.mif"
|
||||
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
||||
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
|
||||
Info (12134): Parameter "lpm_type" = "altsyncram"
|
||||
Info (12134): Parameter "numwords_a" = "32768"
|
||||
Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
|
||||
Info (12134): Parameter "outdata_aclr_a" = "NONE"
|
||||
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
|
||||
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
|
||||
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
|
||||
Info (12134): Parameter "widthad_a" = "15"
|
||||
Info (12134): Parameter "width_a" = "8"
|
||||
Info (12134): Parameter "width_byteena_a" = "1"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf
|
||||
Info (12023): Found entity 1: altsyncram_g9i1
|
||||
Info (12128): Elaborating entity "altsyncram_g9i1" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
|
||||
Info (12023): Found entity 1: decode_msa
|
||||
Info (12128): Elaborating entity "decode_msa" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf
|
||||
Info (12023): Found entity 1: decode_f8a
|
||||
Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf
|
||||
Info (12023): Found entity 1: mux_6nb
|
||||
Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2"
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[7]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[6]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[5]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[4]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[3]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[2]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[1]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[0]" is missing source, defaulting to GND
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[7]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[6]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[5]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[4]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[3]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[2]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[1]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[0]" is missing source, defaulting to GND
|
||||
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "GPIO_0[32]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_0[33]" is stuck at GND
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
|
||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 201 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 1 input pins
|
||||
Info (21059): Implemented 8 output pins
|
||||
Info (21061): Implemented 50 logic cells
|
||||
Info (21064): Implemented 12 RAM segments
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings
|
||||
Info: Peak virtual memory: 388 megabytes
|
||||
Info: Processing ended: Wed Mar 30 13:47:09 2022
|
||||
Info (21059): Implemented 42 output pins
|
||||
Info (21061): Implemented 94 logic cells
|
||||
Info (21064): Implemented 64 RAM segments
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 27 warnings
|
||||
Info: Peak virtual memory: 395 megabytes
|
||||
Info: Processing ended: Wed Mar 30 14:56:01 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
Reference in New Issue
Block a user