Sample memory model with all components
This commit is contained in:
@@ -1,5 +1,5 @@
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Assembler report for spectrum
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Wed Mar 30 13:47:19 2022
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Wed Mar 30 14:56:13 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||||
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@@ -37,7 +37,7 @@ applicable agreement for further details.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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||||
; Assembler Status ; Successful - Wed Mar 30 13:47:19 2022 ;
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; Assembler Status ; Successful - Wed Mar 30 14:56:13 2022 ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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@@ -162,8 +162,8 @@ Default Value : On
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; Option ; Setting ;
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+----------------+-----------------------+
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; Device ; EP4CE22F17C6 ;
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; JTAG usercode ; 0x0021F0FE ;
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; Checksum ; 0x0021F0FE ;
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; JTAG usercode ; 0x00342FB4 ;
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; Checksum ; 0x00342FB4 ;
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+----------------+-----------------------+
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@@ -173,14 +173,14 @@ Default Value : On
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Info: *******************************************************************
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Info: Running Quartus II 32-bit Assembler
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Info: Processing started: Wed Mar 30 13:47:18 2022
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Info: Processing started: Wed Mar 30 14:56:12 2022
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 375 megabytes
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Info: Processing ended: Wed Mar 30 13:47:19 2022
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Info: Peak virtual memory: 394 megabytes
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Info: Processing ended: Wed Mar 30 14:56:13 2022
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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Info: Total CPU time (on all processors): 00:00:02
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@@ -1 +1 @@
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Wed Mar 30 13:47:24 2022
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Wed Mar 30 14:56:19 2022
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@@ -1,5 +1,5 @@
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EDA Netlist Writer report for spectrum
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Wed Mar 30 13:47:24 2022
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Wed Mar 30 14:56:19 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||||
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@@ -36,7 +36,7 @@ applicable agreement for further details.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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||||
+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:47:24 2022 ;
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; EDA Netlist Writer Status ; Successful - Wed Mar 30 14:56:19 2022 ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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@@ -88,7 +88,7 @@ applicable agreement for further details.
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Info: *******************************************************************
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Info: Running Quartus II 32-bit EDA Netlist Writer
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Info: Processing started: Wed Mar 30 13:47:24 2022
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Info: Processing started: Wed Mar 30 14:56:18 2022
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
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Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
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@@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
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Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
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Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 347 megabytes
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Info: Processing ended: Wed Mar 30 13:47:24 2022
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Info: Elapsed time: 00:00:00
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Info: Peak virtual memory: 357 megabytes
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Info: Processing ended: Wed Mar 30 14:56:19 2022
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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+9478
-3172
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
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Fitter Status : Successful - Wed Mar 30 13:47:16 2022
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Fitter Status : Successful - Wed Mar 30 14:56:10 2022
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Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||||
Revision Name : spectrum
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Top-level Entity Name : spectrum
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Family : Cyclone IV E
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Device : EP4CE22F17C6
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Timing Models : Final
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Total logic elements : 50 / 22,320 ( < 1 % )
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Total combinational functions : 48 / 22,320 ( < 1 % )
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Dedicated logic registers : 38 / 22,320 ( < 1 % )
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Total registers : 38
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Total pins : 9 / 154 ( 6 % )
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Total logic elements : 94 / 22,320 ( < 1 % )
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Total combinational functions : 90 / 22,320 ( < 1 % )
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Dedicated logic registers : 41 / 22,320 ( < 1 % )
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Total registers : 41
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Total pins : 43 / 154 ( 28 % )
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Total virtual pins : 0
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Total memory bits : 98,304 / 608,256 ( 16 % )
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Total memory bits : 524,288 / 608,256 ( 86 % )
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Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
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Total PLLs : 0 / 4 ( 0 % )
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@@ -1,5 +1,5 @@
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Flow report for spectrum
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Wed Mar 30 13:47:24 2022
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Wed Mar 30 14:56:19 2022
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||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||||
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||||
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@@ -40,20 +40,20 @@ applicable agreement for further details.
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+---------------------------------------------------------------------------------+
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; Flow Summary ;
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||||
+------------------------------------+--------------------------------------------+
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||||
; Flow Status ; Successful - Wed Mar 30 13:47:24 2022 ;
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; Flow Status ; Successful - Wed Mar 30 14:56:19 2022 ;
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||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
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||||
; Revision Name ; spectrum ;
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||||
; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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||||
; Device ; EP4CE22F17C6 ;
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; Timing Models ; Final ;
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; Total logic elements ; 50 / 22,320 ( < 1 % ) ;
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; Total combinational functions ; 48 / 22,320 ( < 1 % ) ;
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; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
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; Total registers ; 38 ;
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; Total pins ; 9 / 154 ( 6 % ) ;
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; Total logic elements ; 94 / 22,320 ( < 1 % ) ;
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; Total combinational functions ; 90 / 22,320 ( < 1 % ) ;
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; Dedicated logic registers ; 41 / 22,320 ( < 1 % ) ;
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; Total registers ; 41 ;
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; Total pins ; 43 / 154 ( 28 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 98,304 / 608,256 ( 16 % ) ;
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; Total memory bits ; 524,288 / 608,256 ( 86 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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||||
+------------------------------------+--------------------------------------------+
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||||
@@ -64,7 +64,7 @@ applicable agreement for further details.
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||||
+-------------------+---------------------+
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||||
; Option ; Setting ;
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||||
+-------------------+---------------------+
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||||
; Start date & time ; 03/30/2022 13:47:07 ;
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; Start date & time ; 03/30/2022 14:55:59 ;
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; Main task ; Compilation ;
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; Revision Name ; spectrum ;
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+-------------------+---------------------+
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||||
@@ -74,7 +74,7 @@ applicable agreement for further details.
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||||
; Flow Non-Default Global Settings ;
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||||
+--------------------------------------------------------------------------------+
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||||
Assignment Name : COMPILER_SIGNATURE_ID
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||||
Value : 0.164863722728310
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||||
Value : 0.164864135934045
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||||
Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
@@ -103,6 +103,18 @@ Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
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Assignment Name : IP_TOOL_NAME
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Value : RAM: 1-PORT
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Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
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||||
Assignment Name : IP_TOOL_VERSION
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Value : 13.1
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||||
Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
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||||
Assignment Name : IP_TOOL_VERSION
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||||
Value : 13.1
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Default Value : --
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||||
@@ -139,6 +151,12 @@ Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
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||||
Assignment Name : MISC_FILE
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Value : ram32_bb.v
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Default Value : --
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||||
Entity Name : --
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||||
Section Id : --
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||||
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||||
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
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Value : 1.2V
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||||
Default Value : --
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@@ -178,38 +196,38 @@ Section Id : --
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Module Name : Analysis & Synthesis
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Elapsed Time : 00:00:01
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Average Processors Used : 1.0
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Peak Virtual Memory : 384 MB
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||||
Peak Virtual Memory : 387 MB
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||||
Total CPU Time (on all processors) : 00:00:02
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||||
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||||
Module Name : Fitter
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||||
Elapsed Time : 00:00:07
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||||
Elapsed Time : 00:00:09
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||||
Average Processors Used : 1.0
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||||
Peak Virtual Memory : 594 MB
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||||
Total CPU Time (on all processors) : 00:00:06
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Peak Virtual Memory : 603 MB
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||||
Total CPU Time (on all processors) : 00:00:08
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||||
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||||
Module Name : Assembler
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||||
Elapsed Time : 00:00:01
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||||
Average Processors Used : 1.0
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||||
Peak Virtual Memory : 375 MB
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||||
Total CPU Time (on all processors) : 00:00:01
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||||
Peak Virtual Memory : 394 MB
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||||
Total CPU Time (on all processors) : 00:00:02
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||||
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||||
Module Name : TimeQuest Timing Analyzer
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||||
Elapsed Time : 00:00:02
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||||
Average Processors Used : 1.0
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||||
Peak Virtual Memory : 419 MB
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||||
Peak Virtual Memory : 420 MB
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||||
Total CPU Time (on all processors) : 00:00:02
|
||||
|
||||
Module Name : EDA Netlist Writer
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||||
Elapsed Time : 00:00:00
|
||||
Elapsed Time : 00:00:01
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 339 MB
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||||
Peak Virtual Memory : 345 MB
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||||
Total CPU Time (on all processors) : 00:00:01
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||||
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||||
Module Name : Total
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||||
Elapsed Time : 00:00:11
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||||
Elapsed Time : 00:00:14
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||||
Average Processors Used : --
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||||
Peak Virtual Memory : --
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||||
Total CPU Time (on all processors) : 00:00:12
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||||
Total CPU Time (on all processors) : 00:00:15
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||||
+--------------------------------------------------------------------------------+
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||||
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||||
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||||
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||||
@@ -1,6 +1,6 @@
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||||
<sld_project_info>
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||||
<project>
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||||
<hash md5_digest_80b="a9c298635caa38134033"/>
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||||
<hash md5_digest_80b="6802ba978e6c87432815"/>
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||||
</project>
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||||
<file_info>
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||||
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
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||||
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||||
+527
-148
@@ -1,5 +1,5 @@
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Analysis & Synthesis report for spectrum
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||||
Wed Mar 30 13:47:09 2022
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||||
Wed Mar 30 14:56:01 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
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||||
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||||
@@ -16,17 +16,19 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||||
8. Analysis & Synthesis RAM Summary
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||||
9. Analysis & Synthesis IP Cores Summary
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||||
10. Registers Removed During Synthesis
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||||
11. Removed Registers Triggering Further Register Optimizations
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||||
12. General Register Statistics
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||||
13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
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14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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||||
11. General Register Statistics
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||||
12. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
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||||
13. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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||||
14. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
|
||||
15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
|
||||
16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
|
||||
17. altsyncram Parameter Settings by Entity Instance
|
||||
18. Port Connectivity Checks: "ram16:ram0"
|
||||
19. Port Connectivity Checks: "rom0:rom"
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||||
20. Elapsed Time Per Partition
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||||
21. Analysis & Synthesis Messages
|
||||
17. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
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||||
18. altsyncram Parameter Settings by Entity Instance
|
||||
19. Port Connectivity Checks: "ram32:ram1"
|
||||
20. Port Connectivity Checks: "ram16:ram0"
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||||
21. Port Connectivity Checks: "rom0:rom"
|
||||
22. Elapsed Time Per Partition
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||||
23. Analysis & Synthesis Messages
|
||||
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||||
|
||||
|
||||
@@ -52,18 +54,18 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ;
|
||||
; Analysis & Synthesis Status ; Successful - Wed Mar 30 14:56:01 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
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||||
; Total logic elements ; 50 ;
|
||||
; Total combinational functions ; 48 ;
|
||||
; Dedicated logic registers ; 38 ;
|
||||
; Total registers ; 38 ;
|
||||
; Total pins ; 9 ;
|
||||
; Total logic elements ; 94 ;
|
||||
; Total combinational functions ; 90 ;
|
||||
; Dedicated logic registers ; 41 ;
|
||||
; Total registers ; 41 ;
|
||||
; Total pins ; 43 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 98,304 ;
|
||||
; Total memory bits ; 524,288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 0 ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
@@ -429,6 +431,12 @@ File Type : User Wizard-Generated File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : ram32.v
|
||||
Used in Netlist : yes
|
||||
File Type : User Wizard-Generated File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/ram32.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : altsyncram.tdf
|
||||
Used in Netlist : yes
|
||||
File Type : Megafunction
|
||||
@@ -518,6 +526,30 @@ Used in Netlist : yes
|
||||
File Type : Auto-Generated Megafunction
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : db/altsyncram_g9i1.tdf
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Generated Megafunction
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_g9i1.tdf
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : db/decode_msa.tdf
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Generated Megafunction
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_msa.tdf
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : db/decode_f8a.tdf
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Generated Megafunction
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_f8a.tdf
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : db/mux_6nb.tdf
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Generated Megafunction
|
||||
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_6nb.tdf
|
||||
Library :
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
@@ -527,29 +559,29 @@ Library :
|
||||
+---------------------------------------------+----------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+----------------+
|
||||
; Estimated Total logic elements ; 50 ;
|
||||
; Estimated Total logic elements ; 94 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 48 ;
|
||||
; Total combinational functions ; 90 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 7 ;
|
||||
; -- 3 input functions ; 6 ;
|
||||
; -- <=2 input functions ; 35 ;
|
||||
; -- 4 input functions ; 24 ;
|
||||
; -- 3 input functions ; 26 ;
|
||||
; -- <=2 input functions ; 40 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 16 ;
|
||||
; -- arithmetic mode ; 32 ;
|
||||
; -- normal mode ; 57 ;
|
||||
; -- arithmetic mode ; 33 ;
|
||||
; ; ;
|
||||
; Total registers ; 38 ;
|
||||
; -- Dedicated logic registers ; 38 ;
|
||||
; Total registers ; 41 ;
|
||||
; -- Dedicated logic registers ; 41 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 9 ;
|
||||
; Total memory bits ; 98304 ;
|
||||
; I/O pins ; 43 ;
|
||||
; Total memory bits ; 524288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Maximum fan-out node ; CLOCK_50~input ;
|
||||
; Maximum fan-out ; 50 ;
|
||||
; Total fan-out ; 401 ;
|
||||
; Average fan-out ; 3.46 ;
|
||||
; Maximum fan-out ; 105 ;
|
||||
; Total fan-out ; 1436 ;
|
||||
; Average fan-out ; 5.11 ;
|
||||
+---------------------------------------------+----------------+
|
||||
|
||||
|
||||
@@ -557,21 +589,21 @@ Library :
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Compilation Hierarchy Node : |spectrum
|
||||
LC Combinationals : 48 (44)
|
||||
LC Registers : 38 (36)
|
||||
Memory Bits : 98304
|
||||
LC Combinationals : 90 (46)
|
||||
LC Registers : 41 (37)
|
||||
Memory Bits : 524288
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 9
|
||||
Pins : 43
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram16:ram0|
|
||||
LC Combinationals : 0 (0)
|
||||
LC Combinationals : 16 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 32768
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -581,9 +613,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
LC Combinationals : 0 (0)
|
||||
LC Combinationals : 16 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 32768
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -593,9 +625,9 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
|
||||
LC Combinationals : 0 (0)
|
||||
LC Combinationals : 16 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 32768
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -604,10 +636,94 @@ Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_3nb:mux4|
|
||||
LC Combinationals : 8 (8)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_3nb:mux5|
|
||||
LC Combinationals : 8 (8)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram32:ram1|
|
||||
LC Combinationals : 20 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram32:ram1
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
LC Combinationals : 20 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
|
||||
LC Combinationals : 20 (0)
|
||||
LC Registers : 4 (4)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |decode_f8a:rden_decode|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_6nb:mux2|
|
||||
LC Combinationals : 16 (16)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |rom0:rom|
|
||||
LC Combinationals : 4 (0)
|
||||
LC Registers : 2 (0)
|
||||
Memory Bits : 65536
|
||||
LC Combinationals : 8 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -617,9 +733,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
LC Combinationals : 4 (0)
|
||||
LC Registers : 2 (0)
|
||||
Memory Bits : 65536
|
||||
LC Combinationals : 8 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -629,9 +745,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
|
||||
LC Combinationals : 4 (0)
|
||||
LC Registers : 2 (2)
|
||||
Memory Bits : 65536
|
||||
LC Combinationals : 8 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 131072
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
@@ -641,7 +757,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_3nb:mux2|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Combinationals : 8 (8)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -669,6 +785,16 @@ Port B Width : 8
|
||||
Size : 131072
|
||||
MIF : led_patterns.mif
|
||||
|
||||
Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM
|
||||
Type : AUTO
|
||||
Mode : Single Port
|
||||
Port A Depth : 32768
|
||||
Port A Width : 8
|
||||
Port B Depth : --
|
||||
Port B Width : --
|
||||
Size : 262144
|
||||
MIF : led_patterns.mif
|
||||
|
||||
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
|
||||
Type : AUTO
|
||||
Mode : ROM
|
||||
@@ -693,6 +819,14 @@ License Type : N/A
|
||||
Entity Instance : |spectrum|ram16:ram0
|
||||
IP Include File : /home/benny/work/fpga/projects/ram16.v
|
||||
|
||||
Vendor : Altera
|
||||
IP Core Name : RAM: 1-PORT
|
||||
Version : 13.1
|
||||
Release Date : N/A
|
||||
License Type : N/A
|
||||
Entity Instance : |spectrum|ram32:ram1
|
||||
IP Include File : /home/benny/work/fpga/projects/ram32.v
|
||||
|
||||
Vendor : Altera
|
||||
IP Core Name : ROM: 1-PORT
|
||||
Version : 13.1
|
||||
@@ -704,40 +838,20 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Registers Removed During Synthesis ;
|
||||
+------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
; Register name ; Reason for Removal ;
|
||||
+------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
|
||||
; address[0] ; Merged with A[0] ;
|
||||
; address[1] ; Merged with A[1] ;
|
||||
; address[2] ; Merged with A[2] ;
|
||||
; address[3] ; Merged with A[3] ;
|
||||
; address[4] ; Merged with A[4] ;
|
||||
; address[5] ; Merged with A[5] ;
|
||||
; address[6] ; Merged with A[6] ;
|
||||
; address[7] ; Merged with A[7] ;
|
||||
; address[8] ; Merged with A[8] ;
|
||||
; address[9] ; Merged with A[9] ;
|
||||
; address[10] ; Merged with A[10] ;
|
||||
; address[11] ; Merged with A[11] ;
|
||||
; address[12] ; Merged with A[12] ;
|
||||
; address[13] ; Merged with A[13] ;
|
||||
; A[14,15] ; Lost fanout ;
|
||||
; Total Number of Removed Registers = 18 ; ;
|
||||
+------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Removed Registers Triggering Further Register Optimizations ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
|
||||
Reason for Removal : Stuck at GNDdue to stuck port data_in
|
||||
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Registers Removed During Synthesis ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
; Register name ; Reason for Removal ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_b[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
|
||||
; A[15] ; Lost fanout ;
|
||||
; Total Number of Removed Registers = 7 ; ;
|
||||
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
@@ -745,12 +859,12 @@ Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_compon
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 38 ;
|
||||
; Total registers ; 41 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 13 ;
|
||||
; Number of registers using Clock Enable ; 14 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@@ -777,6 +891,17 @@ To : -
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
|
||||
Value : NORMAL_COMPILATION
|
||||
From : -
|
||||
To : -
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
@@ -1207,12 +1332,227 @@ Type : Untyped
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : BYTE_SIZE_BLOCK
|
||||
Value : 8
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : AUTO_CARRY_CHAINS
|
||||
Value : ON
|
||||
Type : AUTO_CARRY
|
||||
|
||||
Parameter Name : IGNORE_CARRY_BUFFERS
|
||||
Value : OFF
|
||||
Type : IGNORE_CARRY
|
||||
|
||||
Parameter Name : AUTO_CASCADE_CHAINS
|
||||
Value : ON
|
||||
Type : AUTO_CASCADE
|
||||
|
||||
Parameter Name : IGNORE_CASCADE_BUFFERS
|
||||
Value : OFF
|
||||
Type : IGNORE_CASCADE
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OPERATION_MODE
|
||||
Value : SINGLE_PORT
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_A
|
||||
Value : 8
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : WIDTHAD_A
|
||||
Value : 15
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : NUMWORDS_A
|
||||
Value : 32768
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : OUTDATA_REG_A
|
||||
Value : CLOCK0
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_ACLR_A
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTHAD_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : NUMWORDS_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_WRADDRESS_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RDCONTROL_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_REG_B
|
||||
Value : UNREGISTERED
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_REG_B
|
||||
Value : CLOCK1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INDATA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WRCONTROL_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ADDRESS_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : OUTDATA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RDCONTROL_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTEENA_ACLR_B
|
||||
Value : NONE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA_A
|
||||
Value : 1
|
||||
Type : Signed Integer
|
||||
|
||||
Parameter Name : WIDTH_BYTEENA_B
|
||||
Value : 1
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : RAM_BLOCK_TYPE
|
||||
Value : AUTO
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : BYTE_SIZE
|
||||
Value : 8
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
|
||||
Value : DONT_CARE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
|
||||
Value : NEW_DATA_NO_NBE_READ
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
|
||||
Value : NEW_DATA_NO_NBE_READ
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INIT_FILE
|
||||
Value : led_patterns.mif
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : INIT_FILE_LAYOUT
|
||||
Value : PORT_A
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : MAXIMUM_DEPTH
|
||||
Value : 0
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_INPUT_A
|
||||
Value : BYPASS
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_INPUT_B
|
||||
Value : NORMAL
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_OUTPUT_A
|
||||
Value : BYPASS
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_OUTPUT_B
|
||||
Value : NORMAL
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_CORE_A
|
||||
Value : USE_INPUT_CLKEN
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CLOCK_ENABLE_CORE_B
|
||||
Value : USE_INPUT_CLKEN
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ENABLE_ECC
|
||||
Value : FALSE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
|
||||
Value : FALSE
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : WIDTH_ECCSTATUS
|
||||
Value : 3
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : DEVICE_FAMILY
|
||||
Value : Cyclone IV E
|
||||
Type : Untyped
|
||||
|
||||
Parameter Name : CBXI_PARAMETER
|
||||
Value : altsyncram_g9i1
|
||||
Type : Untyped
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; altsyncram Parameter Settings by Entity Instance ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
; Name ; Value ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
; Number of entity instances ; 2 ;
|
||||
; Number of entity instances ; 3 ;
|
||||
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
|
||||
; -- OPERATION_MODE ; ROM ;
|
||||
; -- WIDTH_A ; 8 ;
|
||||
@@ -1235,27 +1575,39 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
; -- OUTDATA_REG_B ; CLOCK0 ;
|
||||
; -- RAM_BLOCK_TYPE ; AUTO ;
|
||||
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
||||
; Entity Instance ; ram32:ram1|altsyncram:altsyncram_component ;
|
||||
; -- OPERATION_MODE ; SINGLE_PORT ;
|
||||
; -- WIDTH_A ; 8 ;
|
||||
; -- NUMWORDS_A ; 32768 ;
|
||||
; -- OUTDATA_REG_A ; CLOCK0 ;
|
||||
; -- WIDTH_B ; 1 ;
|
||||
; -- NUMWORDS_B ; 1 ;
|
||||
; -- ADDRESS_REG_B ; CLOCK1 ;
|
||||
; -- OUTDATA_REG_B ; UNREGISTERED ;
|
||||
; -- RAM_BLOCK_TYPE ; AUTO ;
|
||||
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
||||
+-------------------------------------------+--------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "ram32:ram1" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : wren
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
|
||||
Port : wren[-1]
|
||||
Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "ram16:ram0" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : address_a
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
|
||||
Port : address_a[13..3]
|
||||
Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
|
||||
Port : q_a[7..4]
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
|
||||
Port : wren_a
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
@@ -1271,11 +1623,6 @@ Type : Input
|
||||
Severity : Info
|
||||
Details : Stuck at GND
|
||||
|
||||
Port : q_b
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
|
||||
Port : wren_b
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
@@ -1292,10 +1639,10 @@ Details : Stuck at GND
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "rom0:rom" ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Port : q[3..0]
|
||||
Type : Output
|
||||
Severity : Info
|
||||
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
|
||||
Port : address
|
||||
Type : Input
|
||||
Severity : Warning
|
||||
Details : Input port expression (16 bits) is wider than the input port (14 bits) it drives. The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
@@ -1315,7 +1662,7 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Wed Mar 30 13:47:07 2022
|
||||
Info: Processing started: Wed Mar 30 14:55:59 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
|
||||
@@ -1324,11 +1671,13 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
|
||||
Info (12023): Found entity 1: rom0
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
|
||||
Info (12023): Found entity 1: ram16
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
|
||||
Info (12023): Found entity 1: ram32
|
||||
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(18): object "RamWE" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(55): truncated value with size 32 to match size of target (22)
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.v(58): truncated value with size 32 to match size of target (16)
|
||||
Warning (10034): Output port "GPIO_0[33..32]" at spectrum.v(3) has no driver
|
||||
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
|
||||
@@ -1393,41 +1742,71 @@ Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|alt
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
|
||||
Info (12023): Found entity 1: decode_jsa
|
||||
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
|
||||
Warning (14284): Synthesized away the following node(s):
|
||||
Warning (14285): Synthesized away the following RAM node(s):
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"
|
||||
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"
|
||||
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"
|
||||
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Info (12128): Elaborating entity "ram32" for hierarchy "ram32:ram1"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram32:ram1|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "ram32:ram1|altsyncram:altsyncram_component"
|
||||
Info (12133): Instantiated megafunction "ram32:ram1|altsyncram:altsyncram_component" with the following parameter:
|
||||
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
|
||||
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
|
||||
Info (12134): Parameter "init_file" = "led_patterns.mif"
|
||||
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
||||
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
|
||||
Info (12134): Parameter "lpm_type" = "altsyncram"
|
||||
Info (12134): Parameter "numwords_a" = "32768"
|
||||
Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
|
||||
Info (12134): Parameter "outdata_aclr_a" = "NONE"
|
||||
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
|
||||
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
|
||||
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
|
||||
Info (12134): Parameter "widthad_a" = "15"
|
||||
Info (12134): Parameter "width_a" = "8"
|
||||
Info (12134): Parameter "width_byteena_a" = "1"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf
|
||||
Info (12023): Found entity 1: altsyncram_g9i1
|
||||
Info (12128): Elaborating entity "altsyncram_g9i1" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
|
||||
Info (12023): Found entity 1: decode_msa
|
||||
Info (12128): Elaborating entity "decode_msa" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf
|
||||
Info (12023): Found entity 1: decode_f8a
|
||||
Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode"
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf
|
||||
Info (12023): Found entity 1: mux_6nb
|
||||
Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2"
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[7]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[6]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[5]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[4]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[3]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[2]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[1]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[0]" is missing source, defaulting to GND
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[7]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[6]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[5]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[4]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[3]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[2]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[1]" is missing source, defaulting to GND
|
||||
Warning (12110): Net "D[0]" is missing source, defaulting to GND
|
||||
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "GPIO_0[32]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_0[33]" is stuck at GND
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
|
||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 201 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 1 input pins
|
||||
Info (21059): Implemented 8 output pins
|
||||
Info (21061): Implemented 50 logic cells
|
||||
Info (21064): Implemented 12 RAM segments
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings
|
||||
Info: Peak virtual memory: 388 megabytes
|
||||
Info: Processing ended: Wed Mar 30 13:47:09 2022
|
||||
Info (21059): Implemented 42 output pins
|
||||
Info (21061): Implemented 94 logic cells
|
||||
Info (21064): Implemented 64 RAM segments
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 27 warnings
|
||||
Info: Peak virtual memory: 395 megabytes
|
||||
Info: Processing ended: Wed Mar 30 14:56:01 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
Analysis & Synthesis Status : Successful - Wed Mar 30 13:47:09 2022
|
||||
Analysis & Synthesis Status : Successful - Wed Mar 30 14:56:01 2022
|
||||
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Revision Name : spectrum
|
||||
Top-level Entity Name : spectrum
|
||||
Family : Cyclone IV E
|
||||
Total logic elements : 50
|
||||
Total combinational functions : 48
|
||||
Dedicated logic registers : 38
|
||||
Total registers : 38
|
||||
Total pins : 9
|
||||
Total logic elements : 94
|
||||
Total combinational functions : 90
|
||||
Dedicated logic registers : 41
|
||||
Total registers : 41
|
||||
Total pins : 43
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 98,304
|
||||
Total memory bits : 524,288
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total PLLs : 0
|
||||
|
||||
+38
-38
@@ -33,7 +33,7 @@
|
||||
-- Bank 5: 2.5V
|
||||
-- Bank 6: 2.5V
|
||||
-- Bank 7: 3.3V
|
||||
-- Bank 8: 2.5V
|
||||
-- Bank 8: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
@@ -68,49 +68,49 @@ CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
VCCIO8 : A1 : power : : 2.5V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
|
||||
VCCIO8 : A1 : power : : 3.3V : 8 :
|
||||
GPIO_0[2] : A2 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[3] : A3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[6] : A4 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[8] : A5 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[11] : A6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[14] : A7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : A8 : : : : 8 :
|
||||
GND+ : A9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
|
||||
LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
|
||||
GPIO_0[30] : A12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
|
||||
LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCIO7 : A16 : power : : 3.3V : 7 :
|
||||
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
GND : B2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
|
||||
GPIO_0[4] : B3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[5] : B4 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[7] : B5 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[10] : B6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[12] : B7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : B8 : : : : 8 :
|
||||
GND+ : B9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 :
|
||||
GPIO_0[29] : B11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GPIO_0[33] : B12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
|
||||
GND : B15 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 :
|
||||
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
|
||||
VCCIO8 : C4 : power : : 2.5V : 8 :
|
||||
GPIO_0[1] : C3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VCCIO8 : C4 : power : : 3.3V : 8 :
|
||||
GND : C5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
|
||||
VCCIO8 : C7 : power : : 2.5V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
|
||||
GPIO_0[15] : C6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VCCIO8 : C7 : power : : 3.3V : 8 :
|
||||
GPIO_0[16] : C8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[24] : C9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCIO7 : C10 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
|
||||
GPIO_0[28] : C11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : C12 : gnd : : : :
|
||||
VCCIO7 : C13 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
|
||||
@@ -118,16 +118,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 :
|
||||
LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
|
||||
GPIO_0[0] : D3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VCCD_PLL3 : D4 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
|
||||
GPIO_0[9] : D5 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[13] : D6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GND : D7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 :
|
||||
GPIO_0[19] : D8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[25] : D9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : D10 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
|
||||
GPIO_0[31] : D11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GPIO_0[32] : D12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCD_PLL2 : D13 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 :
|
||||
@@ -137,12 +137,12 @@ GND : E2 : gnd : :
|
||||
VCCIO1 : E3 : power : : 3.3V : 1 :
|
||||
GND : E4 : gnd : : : :
|
||||
GNDA3 : E5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 :
|
||||
GPIO_0[17] : E6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[18] : E7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[20] : E8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[23] : E9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GPIO_0[27] : E10 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GPIO_0[26] : E11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GNDA2 : E12 : gnd : : : :
|
||||
GND : E13 : gnd : : : :
|
||||
VCCIO6 : E14 : power : : 2.5V : 6 :
|
||||
@@ -155,8 +155,8 @@ nSTATUS : F4 : : :
|
||||
VCCA3 : F5 : power : : 2.5V : :
|
||||
GND : F6 : gnd : : : :
|
||||
VCCINT : F7 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 :
|
||||
GPIO_0[21] : F8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GPIO_0[22] : F9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : F10 : gnd : : : :
|
||||
VCCINT : F11 : power : : 1.2V : :
|
||||
VCCA2 : F12 : power : : 2.5V : :
|
||||
|
||||
Binary file not shown.
+10038
-4858
File diff suppressed because it is too large
Load Diff
@@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
|
||||
Slack : -1.812
|
||||
TNS : -85.179
|
||||
Slack : -2.088
|
||||
TNS : -422.664
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
|
||||
Slack : 0.343
|
||||
Slack : 0.337
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : -3.000
|
||||
TNS : -119.480
|
||||
TNS : -532.995
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -1.531
|
||||
TNS : -69.352
|
||||
Slack : -1.813
|
||||
TNS : -354.793
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.299
|
||||
Slack : 0.312
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : -3.000
|
||||
TNS : -119.478
|
||||
TNS : -532.816
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -0.444
|
||||
TNS : -17.149
|
||||
Slack : -0.824
|
||||
TNS : -117.237
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.178
|
||||
Slack : 0.169
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : -3.000
|
||||
TNS : -99.404
|
||||
TNS : -347.907
|
||||
|
||||
------------------------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user