Sample memory model with all components

This commit is contained in:
2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
+4 -24
View File
@@ -1,37 +1,17 @@
ADDRESS_REG_B=CLOCK0
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INDATA_REG_B=CLOCK0
INIT_FILE=./led_patterns.mif
INIT_FILE=led_patterns.mif
INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_TYPE=altsyncram
NUMWORDS_A=16384
NUMWORDS_B=16384
OPERATION_MODE=BIDIR_DUAL_PORT
NUMWORDS_A=32768
OPERATION_MODE=SINGLE_PORT
OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=CLOCK0
OUTDATA_REG_B=CLOCK0
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
WIDTHAD_A=14
WIDTHAD_B=14
WIDTHAD_A=15
WIDTH_A=8
WIDTH_B=8
WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK0
DEVICE_FAMILY="Cyclone IV E"
address_a
address_b
clock0
data_a
data_b
wren_a
wren_b
q_a
q_b