Sample memory model with all components

This commit is contained in:
2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
+85 -5
View File
@@ -16,6 +16,86 @@
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|mux2</TD>
<TD >34</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|rden_decode</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated|decode3</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1|altsyncram_component|auto_generated</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram1</TD>
<TD >25</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >8</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|mux5</TD>
<TD >17</TD>
<TD >0</TD>
@@ -130,13 +210,13 @@
<TR >
<TD >ram0</TD>
<TD >47</TD>
<TD >21</TD>
<TD >10</TD>
<TD >0</TD>
<TD >21</TD>
<TD >10</TD>
<TD >16</TD>
<TD >21</TD>
<TD >21</TD>
<TD >21</TD>
<TD >10</TD>
<TD >10</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>