Sample memory model with all components

2022-03-30 14:57:41 +03:00
parent bd2a66037c
commit 107dded913
115 changed files with 87135 additions and 16174 deletions
@@ -0,0 +1,49 @@
+--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 4 
+SUBDESIGN decode_msa
+( 
+	data[1..0]	:	input;
+	enable	:	input;
+	eq[3..0]	:	output;
+) 
+VARIABLE 
+	data_wire[1..0]	: WIRE;
+	enable_wire	: WIRE;
+	eq_node[3..0]	: WIRE;
+	eq_wire[3..0]	: WIRE;
+	w_anode223w[2..0]	: WIRE;
+	w_anode236w[2..0]	: WIRE;
+	w_anode244w[2..0]	: WIRE;
+	w_anode252w[2..0]	: WIRE;
+
+BEGIN 
+	data_wire[] = data[];
+	enable_wire = enable;
+	eq[] = eq_node[];
+	eq_node[3..0] = eq_wire[3..0];
+	eq_wire[] = ( w_anode252w[2..2], w_anode244w[2..2], w_anode236w[2..2], w_anode223w[2..2]);
+	w_anode223w[] = ( (w_anode223w[1..1] & (! data_wire[1..1])), (w_anode223w[0..0] & (! data_wire[0..0])), enable_wire);
+	w_anode236w[] = ( (w_anode236w[1..1] & (! data_wire[1..1])), (w_anode236w[0..0] & data_wire[0..0]), enable_wire);
+	w_anode244w[] = ( (w_anode244w[1..1] & data_wire[1..1]), (w_anode244w[0..0] & (! data_wire[0..0])), enable_wire);
+	w_anode252w[] = ( (w_anode252w[1..1] & data_wire[1..1]), (w_anode252w[0..0] & data_wire[0..0]), enable_wire);
+END;
+--VALID FILE