{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648828519240 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519297 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648828519365 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648828519447 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648828519460 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648828519687 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648828519697 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648828519704 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648828520893 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""}
{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648828520917 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648828520963 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648828520965 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828522862 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648828531514 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X32_Y11 X42_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} 32 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648828532126 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648828532126 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828535524 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648828535527 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648828535527 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.92 " "Total time spent on timing analysis during the Fitter is 1.92 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648828535674 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828538397 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648828538877 ""}
