benny/de0-zx-spectrum
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Files
61ed88ce64dd94d566aa1eee0ff752a79a5cf427
de0-zx-spectrum/db/spectrum.fit.qmsg
T

72 lines
220 KiB
Plaintext
Raw Normal View History

Fixed video, kbd and buzzer
2022-03-31 14:13:34 +03:00
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648724632438 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648724632454 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632498 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632499 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632499 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648724632565 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648724632644 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648724632657 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648724632881 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5271 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5273 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5275 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5277 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5279 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648724632888 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648724632891 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648724632897 ""}
{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648724634095 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634103 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument <targets> is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634103 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724634103 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648724634105 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634105 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument <targets> is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634106 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648724634106 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""}
{ "Warning" "WSTA_SCC_LOOP" "514 " "Found combinational loop of 514 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|combout " "Node \"z80_\|bus_control_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|combout " "Node \"z80_\|alu_control_\|db\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datad " "Node \"z80_\|alu_control_\|db\[2\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|combout " "Node \"z80_\|alu_control_\|db\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|
{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "514 " "Design contains combinational loop of 514 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648724634131 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724634163 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724634163 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648724634177 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648724634179 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648724634179 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5259 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2628 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1220 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3834 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 61 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1377 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634363 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3867 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3840 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3841 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 1
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 911 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634363 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634364 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 746 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634364 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648724635145 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724635148 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724635149 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724635153 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724635158 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648724635161 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648724635161 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648724635164 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648724635927 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648724635931 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648724635931 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648724635931 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724636057 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648724637543 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724638279 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648724638301 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648724641101 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724641101 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648724641951 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X43_Y11 X53_Y22 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} 43 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648724644603 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648724644603 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724648077 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648724648079 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648724648079 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.36 " "Total time spent on timing analysis during the Fitter is 2.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648724648234 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724648294 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724649040 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724649092 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724649775 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724650913 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648724651413 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "40 Cyclone IV E " "40 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648724651780 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 613 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 613 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "633 " "Peak virtual memory: 633 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:12 2022 " "Processing ended: Thu Mar 31 14:04:12 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648724652593 ""}
Reference in New Issue Copy Permalink