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Analysis & Synthesis report for spectrum
2022-04-02 14:56:02 +03:00
Sat Apr 2 14:50:45 2022
2022-03-30 11:53:01 +03:00
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
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8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
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10. State Machine - |spectrum|ula:ula_|i2c_loader:i2c_loader_|state
11. Registers Removed During Synthesis
12. Removed Registers Triggering Further Register Optimizations
13. General Register Statistics
14. Inverted Register Statistics
15. Multiplexer Restructuring Statistics (Restructuring Performed)
16. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
17. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated
18. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
19. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
20. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
21. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
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22. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
23. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component
24. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_
25. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_
26. altsyncram Parameter Settings by Entity Instance
27. altpll Parameter Settings by Entity Instance
28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_"
29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2"
30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
31. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
32. Port Connectivity Checks: "z80_top_direct_n:z80_"
33. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_"
34. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_"
35. Port Connectivity Checks: "ula:ula_"
36. Port Connectivity Checks: "sdram_controller:sdram_"
37. Port Connectivity Checks: "ram16:ram0"
38. Port Connectivity Checks: "rom0:rom"
39. Elapsed Time Per Partition
40. Analysis & Synthesis Messages
41. Analysis & Synthesis Suppressed Messages
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----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
2022-04-02 14:56:02 +03:00
; Analysis & Synthesis Status ; Successful - Sat Apr 2 14:50:45 2022 ;
2022-03-30 11:53:01 +03:00
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
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; Total logic elements ; 2,751 ;
; Total combinational functions ; 2,480 ;
; Dedicated logic registers ; 649 ;
; Total registers ; 649 ;
; Total pins ; 114 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 524,288 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 2 ;
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+------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+
Option : Device
Setting : EP4CE22F17C6
Default Value :
Option : Top-level entity name
Setting : spectrum
Default Value : spectrum
Option : Family name
Setting : Cyclone IV E
Default Value : Cyclone IV GX
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting : On
Default Value : On
Option : Enable compact report table
Setting : Off
Default Value : Off
Option : Restructure Multiplexers
Setting : Auto
Default Value : Auto
Option : Create Debugging Nodes for IP Cores
Setting : Off
Default Value : Off
Option : Preserve fewer node names
Setting : On
Default Value : On
Option : Disable OpenCore Plus hardware evaluation
Setting : Off
Default Value : Off
Option : Verilog Version
Setting : Verilog_2001
Default Value : Verilog_2001
Option : VHDL Version
Setting : VHDL_1993
Default Value : VHDL_1993
Option : State Machine Processing
Setting : Auto
Default Value : Auto
Option : Safe State Machine
Setting : Off
Default Value : Off
Option : Extract Verilog State Machines
Setting : On
Default Value : On
Option : Extract VHDL State Machines
Setting : On
Default Value : On
Option : Ignore Verilog initial constructs
Setting : Off
Default Value : Off
Option : Iteration limit for constant Verilog loops
Setting : 5000
Default Value : 5000
Option : Iteration limit for non-constant Verilog loops
Setting : 250
Default Value : 250
Option : Add Pass-Through Logic to Inferred RAMs
Setting : On
Default Value : On
Option : Infer RAMs from Raw Logic
Setting : On
Default Value : On
Option : Parallel Synthesis
Setting : On
Default Value : On
Option : DSP Block Balancing
Setting : Auto
Default Value : Auto
Option : NOT Gate Push-Back
Setting : On
Default Value : On
Option : Power-Up Don't Care
Setting : On
Default Value : On
Option : Remove Redundant Logic Cells
Setting : Off
Default Value : Off
Option : Remove Duplicate Registers
Setting : On
Default Value : On
Option : Ignore CARRY Buffers
Setting : Off
Default Value : Off
Option : Ignore CASCADE Buffers
Setting : Off
Default Value : Off
Option : Ignore GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore ROW GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore LCELL Buffers
Setting : Off
Default Value : Off
Option : Ignore SOFT Buffers
Setting : On
Default Value : On
Option : Limit AHDL Integers to 32 Bits
Setting : Off
Default Value : Off
Option : Optimization Technique
Setting : Balanced
Default Value : Balanced
Option : Carry Chain Length
Setting : 70
Default Value : 70
Option : Auto Carry Chains
Setting : On
Default Value : On
Option : Auto Open-Drain Pins
Setting : On
Default Value : On
Option : Perform WYSIWYG Primitive Resynthesis
Setting : Off
Default Value : Off
Option : Auto ROM Replacement
Setting : On
Default Value : On
Option : Auto RAM Replacement
Setting : On
Default Value : On
Option : Auto DSP Block Replacement
Setting : On
Default Value : On
Option : Auto Shift Register Replacement
Setting : Auto
Default Value : Auto
Option : Allow Shift Register Merging across Hierarchies
Setting : Auto
Default Value : Auto
Option : Auto Clock Enable Replacement
Setting : On
Default Value : On
Option : Strict RAM Replacement
Setting : Off
Default Value : Off
Option : Allow Synchronous Control Signals
Setting : On
Default Value : On
Option : Force Use of Synchronous Clear Signals
Setting : Off
Default Value : Off
Option : Auto RAM Block Balancing
Setting : On
Default Value : On
Option : Auto RAM to Logic Cell Conversion
Setting : Off
Default Value : Off
Option : Auto Resource Sharing
Setting : Off
Default Value : Off
Option : Allow Any RAM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any ROM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any Shift Register Size For Recognition
Setting : Off
Default Value : Off
Option : Use LogicLock Constraints during Resource Balancing
Setting : On
Default Value : On
Option : Ignore translate_off and synthesis_off directives
Setting : Off
Default Value : Off
Option : Timing-Driven Synthesis
Setting : On
Default Value : On
Option : Report Parameter Settings
Setting : On
Default Value : On
Option : Report Source Assignments
Setting : On
Default Value : On
Option : Report Connectivity Checks
Setting : On
Default Value : On
Option : Ignore Maximum Fan-Out Assignments
Setting : Off
Default Value : Off
Option : Synchronization Register Chain Length
Setting : 2
Default Value : 2
Option : PowerPlay Power Optimization
Setting : Normal compilation
Default Value : Normal compilation
Option : HDL message level
Setting : Level2
Default Value : Level2
Option : Suppress Register Optimization Related Messages
Setting : Off
Default Value : Off
Option : Number of Removed Registers Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Swept Nodes Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Inverted Registers Reported in Synthesis Report
Setting : 100
Default Value : 100
Option : Clock MUX Protection
Setting : On
Default Value : On
Option : Auto Gated Clock Conversion
Setting : Off
Default Value : Off
Option : Block Design Naming
Setting : Auto
Default Value : Auto
Option : SDC constraint protection
Setting : Off
Default Value : Off
Option : Synthesis Effort
Setting : Auto
Default Value : Auto
Option : Shift Register Replacement - Allow Asynchronous Clear Signal
Setting : On
Default Value : On
Option : Pre-Mapping Resynthesis Optimization
Setting : Off
Default Value : Off
Option : Analysis & Synthesis Message Level
Setting : Medium
Default Value : Medium
Option : Disable Register Merging Across Hierarchies
Setting : Auto
Default Value : Auto
Option : Resource Aware Inference For Block RAM
Setting : On
Default Value : On
Option : Synthesis Seed
Setting : 1
Default Value : 1
+--------------------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------------------------+
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File Name with User-Entered Path : spectrum.sv
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Used in Netlist : yes
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File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/spectrum.sv
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Library :
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2022-03-30 14:23:28 +03:00
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
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File Name with Absolute Path : /home/benny/work/fpga/spectrum/led_patterns.mif
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Library :
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File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
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File Name with Absolute Path : /home/benny/work/fpga/spectrum/rom0.v
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Library :
2022-03-30 14:23:28 +03:00
File Name with User-Entered Path : ram16.v
Used in Netlist : yes
File Type : User Wizard-Generated File
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File Name with Absolute Path : /home/benny/work/fpga/spectrum/ram16.v
2022-03-30 14:23:28 +03:00
Library :
2022-03-30 14:57:41 +03:00
File Name with User-Entered Path : ram32.v
Used in Netlist : yes
File Type : User Wizard-Generated File
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ram32.v
Library :
File Name with User-Entered Path : pll.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/pll.v
Library :
File Name with User-Entered Path : cpu/alu/alu.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu.v
Library :
File Name with User-Entered Path : cpu/alu/alu_bit_select.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v
Library :
File Name with User-Entered Path : cpu/alu/alu_control.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_control.v
Library :
File Name with User-Entered Path : cpu/alu/alu_core.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_core.v
Library :
File Name with User-Entered Path : cpu/alu/alu_flags.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v
Library :
File Name with User-Entered Path : cpu/alu/alu_mux_2.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v
Library :
File Name with User-Entered Path : cpu/alu/alu_mux_2z.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v
Library :
File Name with User-Entered Path : cpu/alu/alu_mux_3z.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v
Library :
File Name with User-Entered Path : cpu/alu/alu_mux_4.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v
Library :
File Name with User-Entered Path : cpu/alu/alu_mux_8.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v
Library :
File Name with User-Entered Path : cpu/alu/alu_prep_daa.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v
Library :
File Name with User-Entered Path : cpu/alu/alu_select.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_select.v
Library :
File Name with User-Entered Path : cpu/alu/alu_shifter_core.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v
Library :
File Name with User-Entered Path : cpu/alu/alu_slice.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v
Library :
File Name with User-Entered Path : cpu/control/clk_delay.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/clk_delay.v
Library :
File Name with User-Entered Path : cpu/control/decode_state.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/decode_state.v
Library :
File Name with User-Entered Path : cpu/control/execute.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/execute.v
Library :
File Name with User-Entered Path : cpu/control/interrupts.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/interrupts.v
Library :
File Name with User-Entered Path : cpu/control/ir.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/ir.v
Library :
File Name with User-Entered Path : cpu/control/memory_ifc.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v
Library :
File Name with User-Entered Path : cpu/control/pin_control.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/pin_control.v
Library :
File Name with User-Entered Path : cpu/control/pla_decode.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/pla_decode.v
Library :
File Name with User-Entered Path : cpu/control/resets.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/resets.v
Library :
File Name with User-Entered Path : cpu/control/sequencer.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/sequencer.v
Library :
File Name with User-Entered Path : cpu/bus/address_latch.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/address_latch.v
Library :
File Name with User-Entered Path : cpu/bus/address_mux.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/address_mux.v
Library :
File Name with User-Entered Path : cpu/bus/address_pins.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/address_pins.v
Library :
File Name with User-Entered Path : cpu/bus/bus_control.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/bus_control.v
Library :
File Name with User-Entered Path : cpu/bus/bus_switch.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v
Library :
File Name with User-Entered Path : cpu/bus/control_pins_n.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v
Library :
File Name with User-Entered Path : cpu/bus/data_pins.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/data_pins.v
Library :
File Name with User-Entered Path : cpu/bus/data_switch.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/data_switch.v
Library :
File Name with User-Entered Path : cpu/bus/data_switch_mask.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v
Library :
File Name with User-Entered Path : cpu/bus/inc_dec.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v
Library :
File Name with User-Entered Path : cpu/bus/inc_dec_2bit.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v
Library :
File Name with User-Entered Path : cpu/toplevel/z80_top_direct_n.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v
Library :
File Name with User-Entered Path : cpu/registers/reg_control.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/registers/reg_control.v
Library :
File Name with User-Entered Path : cpu/registers/reg_file.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/registers/reg_file.v
Library :
File Name with User-Entered Path : cpu/registers/reg_latch.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v
Library :
File Name with User-Entered Path : ula/clocks.sv
Used in Netlist : yes
File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/clocks.sv
Library :
File Name with User-Entered Path : ula/zx_kbd.sv
Used in Netlist : yes
File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/zx_kbd.sv
Library :
File Name with User-Entered Path : ula/video.sv
Used in Netlist : yes
File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/video.sv
Library :
File Name with User-Entered Path : ula/ula.sv
Used in Netlist : yes
File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/ula.sv
Library :
File Name with User-Entered Path : ula/ps2_kbd.sv
Used in Netlist : yes
File Type : User SystemVerilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/ps2_kbd.sv
Library :
File Name with User-Entered Path : ula/i2c_loader.vhd
Used in Netlist : yes
File Type : User VHDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/i2c_loader.vhd
Library :
File Name with User-Entered Path : ula/i2s_intf.vhd
Used in Netlist : yes
File Type : User VHDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/i2s_intf.vhd
Library :
2022-04-02 14:56:02 +03:00
File Name with User-Entered Path : sdram.vhdl
Used in Netlist : yes
File Type : User VHDL File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram.vhdl
Library :
File Name with User-Entered Path : sdram_clk_gen.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram_clk_gen.v
Library :
2022-03-31 14:13:34 +03:00
File Name with User-Entered Path : cpu/toplevel/globals.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/toplevel/globals.vh
Library :
File Name with User-Entered Path : cpu/toplevel/coremodules.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh
Library :
File Name with User-Entered Path : cpu/toplevel/core.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/toplevel/core.vh
Library :
File Name with User-Entered Path : cpu/control/exec_matrix_compiled.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/exec_matrix_compiled.vh
Library :
File Name with User-Entered Path : cpu/control/temp_wires.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/temp_wires.vh
Library :
File Name with User-Entered Path : cpu/control/exec_zero.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/exec_zero.vh
Library :
File Name with User-Entered Path : cpu/control/exec_module.vh
Used in Netlist : yes
File Type : Auto-Found Unspecified File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/cpu/control/exec_module.vh
2022-03-30 14:57:41 +03:00
Library :
2022-03-30 12:47:42 +03:00
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
Library :
File Name with User-Entered Path : stratix_ram_block.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
Library :
File Name with User-Entered Path : lpm_mux.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc
Library :
File Name with User-Entered Path : lpm_decode.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc
Library :
File Name with User-Entered Path : aglobal131.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc
Library :
File Name with User-Entered Path : a_rdenreg.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
Library :
File Name with User-Entered Path : altrom.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc
Library :
File Name with User-Entered Path : altram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
Library :
File Name with User-Entered Path : altdpram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library :
2022-03-30 13:18:06 +03:00
File Name with User-Entered Path : db/altsyncram_qh91.tdf
2022-03-30 12:47:42 +03:00
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf
2022-03-30 13:18:06 +03:00
Library :
File Name with User-Entered Path : rom/gw03.hex
Used in Netlist : yes
File Type : Auto-Found Memory Initialization File
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/rom/gw03.hex
2022-03-30 13:18:06 +03:00
Library :
File Name with User-Entered Path : db/decode_c8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/decode_c8a.tdf
2022-03-30 13:18:06 +03:00
Library :
File Name with User-Entered Path : db/mux_3nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/mux_3nb.tdf
2022-03-30 12:47:42 +03:00
Library :
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
File Name with User-Entered Path : db/altsyncram_7ti2.tdf
2022-03-30 14:23:28 +03:00
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf
Library :
File Name with User-Entered Path : ula/test_scr.hex
Used in Netlist : yes
File Type : Auto-Found Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/test_scr.hex
2022-03-30 14:23:28 +03:00
Library :
File Name with User-Entered Path : db/decode_jsa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/decode_jsa.tdf
2022-03-30 14:23:28 +03:00
Library :
2022-03-30 14:57:41 +03:00
File Name with User-Entered Path : db/altsyncram_g9i1.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf
2022-03-30 14:57:41 +03:00
Library :
File Name with User-Entered Path : db/decode_msa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/decode_msa.tdf
2022-03-30 14:57:41 +03:00
Library :
File Name with User-Entered Path : db/decode_f8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/decode_f8a.tdf
2022-03-30 14:57:41 +03:00
Library :
File Name with User-Entered Path : db/mux_6nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
2022-03-31 14:13:34 +03:00
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/mux_6nb.tdf
Library :
File Name with User-Entered Path : altpll.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf
Library :
File Name with User-Entered Path : stratix_pll.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc
Library :
File Name with User-Entered Path : stratixii_pll.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc
Library :
File Name with User-Entered Path : cycloneii_pll.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
Library :
2022-04-02 14:56:02 +03:00
File Name with User-Entered Path : db/sdram_clk_gen_altpll.v
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v
Library :
2022-03-31 14:13:34 +03:00
File Name with User-Entered Path : db/pll_altpll.v
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/pll_altpll.v
Library :
+--------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------+
2022-04-02 14:56:02 +03:00
; Estimated Total logic elements ; 2,751 ;
2022-03-31 14:13:34 +03:00
; ; ;
2022-04-02 14:56:02 +03:00
; Total combinational functions ; 2480 ;
2022-03-31 14:13:34 +03:00
; Logic element usage by number of LUT inputs ; ;
2022-04-02 14:56:02 +03:00
; -- 4 input functions ; 1776 ;
; -- 3 input functions ; 416 ;
; -- <=2 input functions ; 288 ;
2022-03-31 14:13:34 +03:00
; ; ;
; Logic elements by mode ; ;
2022-04-02 14:56:02 +03:00
; -- normal mode ; 2404 ;
; -- arithmetic mode ; 76 ;
2022-03-31 14:13:34 +03:00
; ; ;
2022-04-02 14:56:02 +03:00
; Total registers ; 649 ;
; -- Dedicated logic registers ; 649 ;
2022-03-31 14:13:34 +03:00
; -- I/O registers ; 0 ;
; ; ;
2022-04-02 14:56:02 +03:00
; I/O pins ; 114 ;
2022-03-31 14:13:34 +03:00
; Total memory bits ; 524288 ;
; Embedded Multiplier 9-bit elements ; 0 ;
2022-04-02 14:56:02 +03:00
; Total PLLs ; 2 ;
; -- PLLs ; 2 ;
2022-03-31 14:13:34 +03:00
; ; ;
; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ;
2022-04-01 18:58:14 +03:00
; Maximum fan-out ; 436 ;
2022-04-02 14:56:02 +03:00
; Total fan-out ; 12502 ;
; Average fan-out ; 3.63 ;
2022-03-31 14:13:34 +03:00
+---------------------------------------------+---------------------------------+
2022-03-30 11:53:01 +03:00
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
2022-04-02 14:56:02 +03:00
LC Combinationals : 2480 (108)
LC Registers : 649 (0)
2022-03-30 14:57:41 +03:00
Memory Bits : 524288
2022-03-30 11:53:01 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
2022-04-02 14:56:02 +03:00
Pins : 114
2022-03-30 11:53:01 +03:00
Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
2022-03-30 12:47:42 +03:00
2022-03-30 14:23:28 +03:00
Compilation Hierarchy Node : |ram16:ram0|
2022-03-31 14:13:34 +03:00
LC Combinationals : 2 (0)
LC Registers : 2 (0)
2022-03-30 14:57:41 +03:00
Memory Bits : 131072
2022-03-30 14:23:28 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
2022-03-31 14:13:34 +03:00
LC Combinationals : 2 (0)
LC Registers : 2 (0)
2022-03-30 14:57:41 +03:00
Memory Bits : 131072
2022-03-30 14:23:28 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component
Library Name : work
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |altsyncram_7ti2:auto_generated|
LC Combinationals : 2 (0)
LC Registers : 2 (2)
2022-03-30 14:57:41 +03:00
Memory Bits : 131072
2022-03-30 14:23:28 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
2022-03-31 14:13:34 +03:00
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated
2022-03-30 14:57:41 +03:00
Library Name : work
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |decode_jsa:decode2|
LC Combinationals : 2 (2)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
2022-03-31 14:13:34 +03:00
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2
2022-03-30 14:57:41 +03:00
Library Name : work
Compilation Hierarchy Node : |ram32:ram1|
2022-04-02 14:56:02 +03:00
LC Combinationals : 12 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
2022-04-02 14:56:02 +03:00
LC Combinationals : 12 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
2022-04-02 14:56:02 +03:00
LC Combinationals : 12 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 4 (4)
Memory Bits : 262144
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
Library Name : work
Compilation Hierarchy Node : |decode_f8a:rden_decode|
2022-03-31 14:13:34 +03:00
LC Combinationals : 1 (1)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
Library Name : work
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |decode_msa:decode3|
LC Combinationals : 7 (7)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3
Library Name : work
2022-03-30 14:57:41 +03:00
Compilation Hierarchy Node : |mux_6nb:mux2|
2022-04-02 14:56:02 +03:00
LC Combinationals : 4 (4)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
Library Name : work
2022-03-30 12:47:42 +03:00
Compilation Hierarchy Node : |rom0:rom|
2022-03-31 14:13:34 +03:00
LC Combinationals : 0 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 131072
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
2022-03-31 14:13:34 +03:00
LC Combinationals : 0 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 131072
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
2022-03-30 13:18:06 +03:00
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
2022-03-31 14:13:34 +03:00
LC Combinationals : 0 (0)
2022-03-30 14:57:41 +03:00
LC Registers : 0 (0)
Memory Bits : 131072
2022-03-30 13:18:06 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
Library Name : work
2022-04-02 14:56:02 +03:00
Compilation Hierarchy Node : |sdram_controller:sdram_|
LC Combinationals : 217 (217)
LC Registers : 57 (57)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|sdram_controller:sdram_
Library Name : work
Compilation Hierarchy Node : |sdram_clk_gen:sdram_clk_pll|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
Library Name : work
Compilation Hierarchy Node : |altpll:altpll_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
Library Name : work
Compilation Hierarchy Node : |sdram_clk_gen_altpll:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated
Library Name : work
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |ula:ula_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 418 (4)
2022-03-31 14:13:34 +03:00
LC Registers : 224 (7)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_
Library Name : work
Compilation Hierarchy Node : |clocks:clocks_|
LC Combinationals : 2 (2)
LC Registers : 2 (2)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|clocks:clocks_
Library Name : work
Compilation Hierarchy Node : |i2c_loader:i2c_loader_|
LC Combinationals : 81 (81)
LC Registers : 34 (34)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_
Library Name : work
Compilation Hierarchy Node : |i2s_intf:i2s_intf_|
LC Combinationals : 68 (68)
LC Registers : 42 (42)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_
Library Name : work
Compilation Hierarchy Node : |pll:pll_|
LC Combinationals : 0 (0)
2022-03-30 12:47:42 +03:00
LC Registers : 0 (0)
2022-03-30 13:18:06 +03:00
Memory Bits : 0
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
2022-03-31 14:13:34 +03:00
Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_
2022-03-30 12:47:42 +03:00
Library Name : work
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |altpll:altpll_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component
Library Name : work
Compilation Hierarchy Node : |pll_altpll:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated
Library Name : work
Compilation Hierarchy Node : |ps2_keyboard:ps2_keyboard_|
LC Combinationals : 16 (16)
LC Registers : 24 (24)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_
Library Name : work
Compilation Hierarchy Node : |video:video_|
LC Combinationals : 99 (99)
LC Registers : 72 (72)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|video:video_
Library Name : work
Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 148 (148)
2022-03-31 14:13:34 +03:00
LC Registers : 43 (43)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_
Library Name : work
Compilation Hierarchy Node : |z80_top_direct_n:z80_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 1723 (2)
2022-03-31 14:13:34 +03:00
LC Registers : 362 (1)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_
Library Name : work
Compilation Hierarchy Node : |address_latch:address_latch_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 45 (16)
2022-03-31 14:13:34 +03:00
LC Registers : 16 (16)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_
Library Name : work
Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec|
2022-04-02 14:56:02 +03:00
LC Combinationals : 29 (12)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0|
2022-04-02 14:56:02 +03:00
LC Combinationals : 3 (3)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_10|
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_2|
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_4|
LC Combinationals : 2 (2)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_7|
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_9|
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9
Library Name : work
Compilation Hierarchy Node : |address_pins:address_pins_|
LC Combinationals : 32 (32)
LC Registers : 16 (16)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_
Library Name : work
Compilation Hierarchy Node : |alu:alu_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 128 (75)
2022-03-31 14:13:34 +03:00
LC Registers : 20 (20)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_
Library Name : work
Compilation Hierarchy Node : |alu_bit_select:b2v_input_bit_select|
LC Combinationals : 2 (2)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select
Library Name : work
Compilation Hierarchy Node : |alu_core:b2v_core|
2022-04-01 18:58:14 +03:00
LC Combinationals : 20 (0)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core
Library Name : work
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_0|
LC Combinationals : 5 (5)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0
Library Name : work
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1|
2022-04-02 14:56:02 +03:00
LC Combinationals : 5 (5)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1
Library Name : work
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_2|
2022-04-02 14:56:02 +03:00
LC Combinationals : 7 (7)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2
Library Name : work
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3|
2022-04-02 14:56:02 +03:00
LC Combinationals : 3 (3)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3
Library Name : work
Compilation Hierarchy Node : |alu_mux_2z:b2v_op1_latch_mux_high|
LC Combinationals : 5 (5)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high
Library Name : work
Compilation Hierarchy Node : |alu_mux_3z:b2v_op1_latch_mux_low|
LC Combinationals : 9 (9)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low
Library Name : work
Compilation Hierarchy Node : |alu_mux_3z:b2v_op2_latch_mux_high|
LC Combinationals : 9 (9)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high
Library Name : work
Compilation Hierarchy Node : |alu_mux_3z:b2v_op2_latch_mux_low|
LC Combinationals : 8 (8)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_low
Library Name : work
Compilation Hierarchy Node : |alu_control:alu_control_|
LC Combinationals : 40 (35)
LC Registers : 2 (2)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_
Library Name : work
Compilation Hierarchy Node : |alu_mux_4:b2v_inst_cond_mux|
LC Combinationals : 2 (2)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_4:b2v_inst_cond_mux
Library Name : work
Compilation Hierarchy Node : |alu_mux_8:b2v_inst_shift_mux|
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux
Library Name : work
Compilation Hierarchy Node : |alu_flags:alu_flags_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 61 (61)
2022-03-31 14:13:34 +03:00
LC Registers : 10 (10)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_
Library Name : work
Compilation Hierarchy Node : |bus_control:bus_control_|
LC Combinationals : 18 (18)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_
Library Name : work
Compilation Hierarchy Node : |clk_delay:clk_delay_|
LC Combinationals : 2 (2)
LC Registers : 2 (2)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_
Library Name : work
2022-04-02 14:56:02 +03:00
Compilation Hierarchy Node : |control_pins_n:control_pins_|
LC Combinationals : 1 (1)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_
Library Name : work
2022-03-31 14:13:34 +03:00
Compilation Hierarchy Node : |data_pins:data_pins_|
LC Combinationals : 9 (9)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_
Library Name : work
Compilation Hierarchy Node : |data_switch:sw2_|
LC Combinationals : 1 (1)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_
Library Name : work
Compilation Hierarchy Node : |data_switch_mask:sw1_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 4 (4)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_
Library Name : work
Compilation Hierarchy Node : |decode_state:decode_state_|
LC Combinationals : 11 (11)
LC Registers : 6 (6)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode_state_
Library Name : work
Compilation Hierarchy Node : |execute:execute_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 926 (926)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_
Library Name : work
Compilation Hierarchy Node : |interrupts:interrupts_|
LC Combinationals : 10 (10)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_
Library Name : work
Compilation Hierarchy Node : |ir:ir_|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_
Library Name : work
Compilation Hierarchy Node : |memory_ifc:memory_ifc_|
LC Combinationals : 11 (11)
LC Registers : 20 (20)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_
Library Name : work
Compilation Hierarchy Node : |pin_control:pin_control_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 20 (20)
2022-03-31 14:13:34 +03:00
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_control_
Library Name : work
Compilation Hierarchy Node : |pla_decode:pla_decode_|
LC Combinationals : 74 (74)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_decode_
Library Name : work
Compilation Hierarchy Node : |reg_control:reg_control_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 30 (30)
2022-03-31 14:13:34 +03:00
LC Registers : 4 (4)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_control_
Library Name : work
Compilation Hierarchy Node : |reg_file:reg_file_|
2022-04-02 14:56:02 +03:00
LC Combinationals : 281 (270)
2022-03-31 14:13:34 +03:00
LC Registers : 224 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_af2_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_af2_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi|
2022-04-01 18:58:14 +03:00
LC Combinationals : 8 (8)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_af_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_bc2_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_bc2_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_bc_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_bc_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_lo|
2022-04-01 18:58:14 +03:00
LC Combinationals : 0 (0)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_de_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_de_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_hi|
2022-04-01 18:58:14 +03:00
LC Combinationals : 0 (0)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_lo|
2022-04-02 14:56:02 +03:00
LC Combinationals : 0 (0)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo|
2022-04-02 14:56:02 +03:00
LC Combinationals : 1 (1)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_ir_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_ir_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_ix_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_ix_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_iy_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_iy_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_pc_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_pc_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_sp_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_sp_lo|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_lo
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_hi|
LC Combinationals : 0 (0)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo|
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LC Combinationals : 2 (2)
2022-03-31 14:13:34 +03:00
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo
Library Name : work
Compilation Hierarchy Node : |resets:resets_|
LC Combinationals : 6 (6)
LC Registers : 6 (6)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|resets:resets_
Library Name : work
Compilation Hierarchy Node : |sequencer:sequencer_|
LC Combinationals : 11 (11)
LC Registers : 11 (11)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|sequencer:sequencer_
Library Name : work
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : True Dual Port
Port A Depth : 16384
Port A Width : 8
Port B Depth : 16384
Port B Width : 8
Size : 131072
MIF : ula/test_scr.hex
Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : Single Port
Port A Depth : 32768
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 262144
MIF : led_patterns.mif
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Port A Depth : 16384
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 131072
MIF : ./rom/gw03.hex
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+
Vendor : Altera
IP Core Name : RAM: 2-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram16:ram0
IP Include File : /home/benny/work/fpga/spectrum/ram16.v
Vendor : Altera
IP Core Name : RAM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram32:ram1
IP Include File : /home/benny/work/fpga/spectrum/ram32.v
Vendor : Altera
IP Core Name : ROM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|rom0:rom
IP Include File : /home/benny/work/fpga/spectrum/rom0.v
2022-04-02 14:56:02 +03:00
Vendor : Altera
IP Core Name : ALTPLL
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
IP Include File : /home/benny/work/fpga/spectrum/sdram_clk_gen.v
2022-03-31 14:13:34 +03:00
Vendor : Altera
IP Core Name : ALTPLL
Version : 13.0
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ula:ula_|pll:pll_
IP Include File : /home/benny/work/fpga/spectrum/pll.v
+--------------------------------------------------------------------------------+
Encoding Type: One-Hot
+--------------------------------------------------------------------------------+
; State Machine - |spectrum|ula:ula_|i2c_loader:i2c_loader_|state ;
+--------------------------------------------------------------------------------+
Name : state.Idle
state.Done : 0
state.Pause : 0
state.Stop : 0
state.Ack : 0
state.Data : 0
state.Start : 0
state.Idle : 0
Name : state.Start
state.Done : 0
state.Pause : 0
state.Stop : 0
state.Ack : 0
state.Data : 0
state.Start : 1
state.Idle : 1
Name : state.Data
state.Done : 0
state.Pause : 0
state.Stop : 0
state.Ack : 0
state.Data : 1
state.Start : 0
state.Idle : 1
Name : state.Ack
state.Done : 0
state.Pause : 0
state.Stop : 0
state.Ack : 1
state.Data : 0
state.Start : 0
state.Idle : 1
Name : state.Stop
state.Done : 0
state.Pause : 0
state.Stop : 1
state.Ack : 0
state.Data : 0
state.Start : 0
state.Idle : 1
Name : state.Pause
state.Done : 0
state.Pause : 1
state.Stop : 0
state.Ack : 0
state.Data : 0
state.Start : 0
state.Idle : 1
Name : state.Done
state.Done : 1
state.Pause : 0
state.Stop : 0
state.Ack : 0
state.Data : 0
state.Start : 0
state.Idle : 1
+--------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
; z80_top_direct_n:z80_|clk_delay:clk_delay_|SYNTHESIZED_WIRE_9 ; Stuck at GND due to stuck port data_in ;
; z80_top_direct_n:z80_|clk_delay:clk_delay_|SYNTHESIZED_WIRE_8 ; Stuck at GND due to stuck port data_in ;
; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_busrq_ALTERA_SYNTHESIZED ; Stuck at GND due to stuck port data_in ;
2022-04-02 14:56:02 +03:00
; sdram_controller:sdram_|r.state[3] ; Stuck at GND due to stuck port data_in ;
2022-03-31 14:13:34 +03:00
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_b[0] ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_b[0] ; Stuck at GND due to stuck port data_in ;
2022-04-02 14:56:02 +03:00
; sdram_controller:sdram_|r.address[12] ; Merged with sdram_controller:sdram_|r.address[11] ;
; sdram_controller:sdram_|r.act_row[5..9,11,12] ; Merged with sdram_controller:sdram_|r.act_row[10] ;
2022-03-31 14:13:34 +03:00
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ;
; ula:ula_|pcm_outr[14] ; Merged with ula:ula_|pcm_outl[14] ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] ;
; ula:ula_|pcm_outr[13] ; Merged with ula:ula_|pcm_outl[13] ;
; ula:ula_|pcm_outr[12] ; Merged with ula:ula_|pcm_outl[12] ;
; ula:ula_|i2c_loader:i2c_loader_|retries ; Stuck at GND due to stuck port data_in ;
; ula:ula_|i2c_loader:i2c_loader_|nak ; Lost fanout ;
; ula:ula_|i2c_loader:i2c_loader_|state.Done ; Lost fanout ;
2022-04-02 14:56:02 +03:00
; sdram_controller:sdram_|r.act_row[10] ; Stuck at GND due to stuck port data_in ;
2022-03-31 14:13:34 +03:00
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[0] ; Merged with ula:ula_|i2s_intf:i2s_intf_|mclk_r ;
2022-04-02 14:56:02 +03:00
; Total Number of Removed Registers = 24 ; ;
2022-03-31 14:13:34 +03:00
+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------+
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_b[0]
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_b[0]
Register name : ula:ula_|i2c_loader:i2c_loader_|retries
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
+--------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
2022-04-02 14:56:02 +03:00
; Total registers ; 649 ;
; Number of registers using Synchronous Clear ; 13 ;
; Number of registers using Synchronous Load ; 34 ;
2022-03-31 14:13:34 +03:00
; Number of registers using Asynchronous Clear ; 221 ;
; Number of registers using Asynchronous Load ; 0 ;
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; Number of registers using Clock Enable ; 464 ;
2022-03-31 14:13:34 +03:00
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------------------------+---------+
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ;
; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ;
2022-04-02 14:56:02 +03:00
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 150 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ;
; ula:ula_|i2s_intf:i2s_intf_|bdivider[4] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|bdivider[2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
2022-04-02 14:56:02 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ;
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ;
2022-04-02 14:56:02 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ;
2022-04-02 14:56:02 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ;
2022-04-01 18:58:14 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ;
2022-04-02 14:56:02 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
2022-04-02 14:56:02 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
2022-03-31 14:13:34 +03:00
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ;
2022-04-02 14:56:02 +03:00
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ;
2022-03-31 14:13:34 +03:00
; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ;
; z80_top_direct_n:z80_|fpga_reset ; 2 ;
2022-04-02 14:56:02 +03:00
; sdram_controller:sdram_|r.init_counter[3] ; 3 ;
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; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ;
; ula:ula_|i2c_loader:i2c_loader_|scl_out ; 2 ;
; ula:ula_|i2c_loader:i2c_loader_|sda_out ; 3 ;
; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ;
; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ;
2022-04-02 14:56:02 +03:00
; Total number of inverted registers = 62 ; ;
2022-03-31 14:13:34 +03:00
+----------------------------------------------------------+---------+
+--------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------------------------------------------------------------------+
Multiplexer Inputs : 3:1
Bus Width : 10 bits
Baseline Area : 20 LEs
Area if Restructured : 10 LEs
Saving if Restructured : 10 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[5]
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Multiplexer Inputs : 3:1
Bus Width : 4 bits
Baseline Area : 8 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 4 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3]
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Multiplexer Inputs : 4:1
Bus Width : 2 bits
Baseline Area : 4 LEs
Area if Restructured : 2 LEs
Saving if Restructured : 2 LEs
Registered : Yes
2022-04-02 14:56:02 +03:00
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Multiplexer Inputs : 4:1
Bus Width : 10 bits
Baseline Area : 20 LEs
Area if Restructured : 10 LEs
Saving if Restructured : 10 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[3]
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Multiplexer Inputs : 6:1
Bus Width : 5 bits
Baseline Area : 20 LEs
Area if Restructured : 5 LEs
Saving if Restructured : 15 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
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Multiplexer Inputs : 5:1
Bus Width : 3 bits
Baseline Area : 9 LEs
Area if Restructured : 3 LEs
Saving if Restructured : 6 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
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Multiplexer Inputs : 5:1
Bus Width : 14 bits
Baseline Area : 42 LEs
Area if Restructured : 14 LEs
Saving if Restructured : 28 LEs
Registered : Yes
2022-04-02 14:56:02 +03:00
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
2022-03-31 14:13:34 +03:00
Multiplexer Inputs : 5:1
Bus Width : 3 bits
Baseline Area : 9 LEs
Area if Restructured : 3 LEs
Saving if Restructured : 6 LEs
Registered : Yes
2022-04-02 14:56:02 +03:00
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
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Multiplexer Inputs : 10:1
Bus Width : 2 bits
Baseline Area : 12 LEs
Area if Restructured : 2 LEs
Saving if Restructured : 10 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[11]
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Multiplexer Inputs : 10:1
Bus Width : 2 bits
Baseline Area : 12 LEs
Area if Restructured : 2 LEs
Saving if Restructured : 10 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[8]
Multiplexer Inputs : 32:1
Bus Width : 5 bits
Baseline Area : 105 LEs
Area if Restructured : 0 LEs
Saving if Restructured : 105 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[1]
2022-03-31 14:13:34 +03:00
Multiplexer Inputs : 8:1
Bus Width : 2 bits
Baseline Area : 10 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 6 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
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Multiplexer Inputs : 32:1
Bus Width : 2 bits
Baseline Area : 42 LEs
Area if Restructured : 2 LEs
Saving if Restructured : 40 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.bank[0]
Multiplexer Inputs : 31:1
Bus Width : 4 bits
Baseline Area : 80 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 76 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[8]
Multiplexer Inputs : 31:1
Bus Width : 2 bits
Baseline Area : 40 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 36 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[3]
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Multiplexer Inputs : 10:1
Bus Width : 2 bits
Baseline Area : 12 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 8 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Multiplexer Inputs : 9:1
Bus Width : 3 bits
Baseline Area : 18 LEs
Area if Restructured : 3 LEs
Saving if Restructured : 15 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Multiplexer Inputs : 27:1
Bus Width : 4 bits
Baseline Area : 72 LEs
Area if Restructured : 52 LEs
Saving if Restructured : 20 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
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Multiplexer Inputs : 3:1
Bus Width : 16 bits
Baseline Area : 32 LEs
Area if Restructured : 32 LEs
Saving if Restructured : 0 LEs
Registered : Yes
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Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0]
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Multiplexer Inputs : 4:1
Bus Width : 3 bits
Baseline Area : 6 LEs
Area if Restructured : 3 LEs
Saving if Restructured : 3 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Multiplexer Inputs : 5:1
Bus Width : 2 bits
Baseline Area : 6 LEs
Area if Restructured : 2 LEs
Saving if Restructured : 4 LEs
Registered : Yes
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Multiplexer Inputs : 5:1
Bus Width : 3 bits
Baseline Area : 9 LEs
Area if Restructured : 6 LEs
Saving if Restructured : 3 LEs
Registered : No
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Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[2]
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Multiplexer Inputs : 6:1
Bus Width : 2 bits
Baseline Area : 8 LEs
Area if Restructured : 6 LEs
Saving if Restructured : 2 LEs
Registered : No
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Example Multiplexer Output : |spectrum|Mux0
Multiplexer Inputs : 4:1
Bus Width : 8 bits
Baseline Area : 16 LEs
Area if Restructured : 8 LEs
Saving if Restructured : 8 LEs
Registered : No
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|Mux74
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Multiplexer Inputs : 8:1
Bus Width : 6 bits
Baseline Area : 30 LEs
Area if Restructured : 24 LEs
Saving if Restructured : 6 LEs
Registered : No
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Example Multiplexer Output : |spectrum|Selector0
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Multiplexer Inputs : 9:1
Bus Width : 2 bits
Baseline Area : 12 LEs
Area if Restructured : 6 LEs
Saving if Restructured : 6 LEs
Registered : No
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Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Idle
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Multiplexer Inputs : 11:1
Bus Width : 2 bits
Baseline Area : 14 LEs
Area if Restructured : 4 LEs
Saving if Restructured : 10 LEs
Registered : No
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Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Pause
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+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : ROM
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : ./rom/gw03.hex
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_qh91
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : BIDIR_DUAL_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_B
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_B
Value : 16384
Type : Signed Integer
Parameter Name : INDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Signed Integer
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : ula/test_scr.hex
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_7ti2
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : SINGLE_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 15
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 32768
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_g9i1
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
2022-04-02 14:56:02 +03:00
; Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component ;
2022-03-31 14:13:34 +03:00
+--------------------------------------------------------------------------------+
Parameter Name : OPERATION_MODE
Value : NORMAL
Type : Untyped
Parameter Name : PLL_TYPE
Value : AUTO
Type : Untyped
Parameter Name : LPM_HINT
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Value : CBX_MODULE_PREFIX=sdram_clk_gen
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Type : Untyped
Parameter Name : QUALIFY_CONF_DONE
Value : OFF
Type : Untyped
Parameter Name : COMPENSATE_CLOCK
Value : CLK0
Type : Untyped
Parameter Name : SCAN_CHAIN
Value : LONG
Type : Untyped
Parameter Name : PRIMARY_CLOCK
Value : INCLK0
Type : Untyped
Parameter Name : INCLK0_INPUT_FREQUENCY
Value : 20000
Type : Signed Integer
Parameter Name : INCLK1_INPUT_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : GATE_LOCK_SIGNAL
Value : NO
Type : Untyped
Parameter Name : GATE_LOCK_COUNTER
Value : 0
Type : Untyped
Parameter Name : LOCK_HIGH
Value : 1
Type : Untyped
Parameter Name : LOCK_LOW
Value : 1
Type : Untyped
Parameter Name : VALID_LOCK_MULTIPLIER
Value : 1
Type : Untyped
Parameter Name : INVALID_LOCK_MULTIPLIER
Value : 5
Type : Untyped
Parameter Name : SWITCH_OVER_ON_LOSSCLK
Value : OFF
Type : Untyped
Parameter Name : SWITCH_OVER_ON_GATED_LOCK
Value : OFF
Type : Untyped
Parameter Name : ENABLE_SWITCH_OVER_COUNTER
Value : OFF
Type : Untyped
Parameter Name : SKIP_VCO
Value : OFF
Type : Untyped
Parameter Name : SWITCH_OVER_COUNTER
Value : 0
Type : Untyped
Parameter Name : SWITCH_OVER_TYPE
Value : AUTO
Type : Untyped
Parameter Name : FEEDBACK_SOURCE
Value : EXTCLK0
Type : Untyped
Parameter Name : BANDWIDTH
Value : 0
Type : Untyped
Parameter Name : BANDWIDTH_TYPE
Value : AUTO
Type : Untyped
Parameter Name : SPREAD_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : DOWN_SPREAD
Value : 0
Type : Untyped
Parameter Name : SELF_RESET_ON_GATED_LOSS_LOCK
Value : OFF
Type : Untyped
Parameter Name : SELF_RESET_ON_LOSS_LOCK
Value : OFF
Type : Untyped
Parameter Name : CLK9_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK8_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK7_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK6_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK5_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK4_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK3_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK2_MULTIPLY_BY
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Value : 1
Type : Untyped
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Parameter Name : CLK1_MULTIPLY_BY
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Value : 2
2022-03-31 14:13:34 +03:00
Type : Signed Integer
Parameter Name : CLK0_MULTIPLY_BY
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Value : 2
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Type : Signed Integer
Parameter Name : CLK9_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK8_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK7_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK6_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK5_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK4_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK3_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK2_DIVIDE_BY
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Value : 1
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK1_DIVIDE_BY
2022-04-02 14:56:02 +03:00
Value : 1
2022-03-31 14:13:34 +03:00
Type : Signed Integer
Parameter Name : CLK0_DIVIDE_BY
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Value : 1
2022-03-31 14:13:34 +03:00
Type : Signed Integer
Parameter Name : CLK9_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK8_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK7_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK6_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK5_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK4_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK3_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK2_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK1_PHASE_SHIFT
2022-04-02 14:56:02 +03:00
Value : 3000
2022-03-31 14:13:34 +03:00
Type : Untyped
Parameter Name : CLK0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK5_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK4_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK9_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK8_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK7_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK6_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK5_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK4_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK3_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK2_DUTY_CYCLE
Value : 50
2022-04-02 14:56:02 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK1_DUTY_CYCLE
Value : 50
Type : Signed Integer
Parameter Name : CLK0_DUTY_CYCLE
Value : 50
Type : Signed Integer
Parameter Name : CLK9_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK8_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK7_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK6_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK5_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK4_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK3_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK2_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK1_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK0_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK9_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK8_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK7_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK6_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK5_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK4_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK3_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK2_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK1_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK0_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : LOCK_WINDOW_UI
Value : 0.05
Type : Untyped
Parameter Name : LOCK_WINDOW_UI_BITS
Value : UNUSED
Type : Untyped
Parameter Name : VCO_RANGE_DETECTOR_LOW_BITS
Value : UNUSED
Type : Untyped
Parameter Name : VCO_RANGE_DETECTOR_HIGH_BITS
Value : UNUSED
Type : Untyped
Parameter Name : DPA_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : DPA_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : DPA_DIVIDER
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK2_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK1_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK0_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK3_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK2_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK1_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK0_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK3_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK2_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK1_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK2_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK1_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK0_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : VCO_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : VCO_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : SCLKOUT0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : SCLKOUT1_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : VCO_MIN
Value : 0
Type : Untyped
Parameter Name : VCO_MAX
Value : 0
Type : Untyped
Parameter Name : VCO_CENTER
Value : 0
Type : Untyped
Parameter Name : PFD_MIN
Value : 0
Type : Untyped
Parameter Name : PFD_MAX
Value : 0
Type : Untyped
Parameter Name : M_INITIAL
Value : 0
Type : Untyped
Parameter Name : M
Value : 0
Type : Untyped
Parameter Name : N
Value : 1
Type : Untyped
Parameter Name : M2
Value : 1
Type : Untyped
Parameter Name : N2
Value : 1
Type : Untyped
Parameter Name : SS
Value : 1
Type : Untyped
Parameter Name : C0_HIGH
Value : 0
Type : Untyped
Parameter Name : C1_HIGH
Value : 0
Type : Untyped
Parameter Name : C2_HIGH
Value : 0
Type : Untyped
Parameter Name : C3_HIGH
Value : 0
Type : Untyped
Parameter Name : C4_HIGH
Value : 0
Type : Untyped
Parameter Name : C5_HIGH
Value : 0
Type : Untyped
Parameter Name : C6_HIGH
Value : 0
Type : Untyped
Parameter Name : C7_HIGH
Value : 0
Type : Untyped
Parameter Name : C8_HIGH
Value : 0
Type : Untyped
Parameter Name : C9_HIGH
Value : 0
Type : Untyped
Parameter Name : C0_LOW
Value : 0
Type : Untyped
Parameter Name : C1_LOW
Value : 0
Type : Untyped
Parameter Name : C2_LOW
Value : 0
Type : Untyped
Parameter Name : C3_LOW
Value : 0
Type : Untyped
Parameter Name : C4_LOW
Value : 0
Type : Untyped
Parameter Name : C5_LOW
Value : 0
Type : Untyped
Parameter Name : C6_LOW
Value : 0
Type : Untyped
Parameter Name : C7_LOW
Value : 0
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C8_LOW
Value : 0
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C9_LOW
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C0_INITIAL
Value : 0
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C1_INITIAL
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C2_INITIAL
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C3_INITIAL
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C4_INITIAL
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C5_INITIAL
Value : 0
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C6_INITIAL
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C7_INITIAL
Value : 0
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C8_INITIAL
Value : 0
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C9_INITIAL
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C0_MODE
Value : BYPASS
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C1_MODE
Value : BYPASS
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C2_MODE
Value : BYPASS
Type : Untyped
2022-03-30 11:53:01 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C3_MODE
Value : BYPASS
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C4_MODE
Value : BYPASS
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C5_MODE
Value : BYPASS
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C6_MODE
Value : BYPASS
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C7_MODE
Value : BYPASS
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C8_MODE
Value : BYPASS
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C9_MODE
Value : BYPASS
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C0_PH
Value : 0
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C1_PH
Value : 0
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C2_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C3_PH
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C4_PH
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C5_PH
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C6_PH
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : C7_PH
Value : 0
Type : Untyped
Parameter Name : C8_PH
Value : 0
Type : Untyped
Parameter Name : C9_PH
Value : 0
Type : Untyped
Parameter Name : L0_HIGH
2022-03-30 12:47:42 +03:00
Value : 1
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L1_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G0_HIGH
Value : 1
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G1_HIGH
Value : 1
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G2_HIGH
Value : 1
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G3_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E0_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E1_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E2_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E3_HIGH
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L0_LOW
Value : 1
Type : Untyped
Parameter Name : L1_LOW
Value : 1
Type : Untyped
Parameter Name : G0_LOW
Value : 1
Type : Untyped
Parameter Name : G1_LOW
Value : 1
Type : Untyped
Parameter Name : G2_LOW
Value : 1
Type : Untyped
Parameter Name : G3_LOW
Value : 1
Type : Untyped
Parameter Name : E0_LOW
Value : 1
Type : Untyped
Parameter Name : E1_LOW
Value : 1
Type : Untyped
Parameter Name : E2_LOW
Value : 1
Type : Untyped
Parameter Name : E3_LOW
Value : 1
Type : Untyped
Parameter Name : L0_INITIAL
Value : 1
Type : Untyped
Parameter Name : L1_INITIAL
Value : 1
Type : Untyped
Parameter Name : G0_INITIAL
Value : 1
Type : Untyped
Parameter Name : G1_INITIAL
Value : 1
Type : Untyped
Parameter Name : G2_INITIAL
Value : 1
Type : Untyped
Parameter Name : G3_INITIAL
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E0_INITIAL
2022-03-30 12:47:42 +03:00
Value : 1
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E1_INITIAL
2022-03-30 12:47:42 +03:00
Value : 1
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E2_INITIAL
2022-03-30 12:47:42 +03:00
Value : 1
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E3_INITIAL
Value : 1
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L0_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L1_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G0_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G1_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G2_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G3_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E0_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E1_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E2_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E3_MODE
Value : BYPASS
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L0_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L1_PH
Value : 0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G0_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G1_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G2_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G3_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E0_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E1_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E2_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E3_PH
Value : 0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : M_PH
2022-03-30 12:47:42 +03:00
Value : 0
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C1_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C2_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C3_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C4_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C5_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C6_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C7_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C8_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C9_USE_CASC_IN
Value : OFF
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK0_COUNTER
Value : G0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK1_COUNTER
Value : G0
2022-03-30 12:47:42 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK2_COUNTER
Value : G0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK3_COUNTER
Value : G0
Type : Untyped
2022-03-30 12:47:42 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK4_COUNTER
Value : G0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK5_COUNTER
Value : G0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK6_COUNTER
Value : E0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK7_COUNTER
Value : E1
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK8_COUNTER
Value : E2
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK9_COUNTER
Value : E3
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L0_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : L1_TIME_DELAY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G0_TIME_DELAY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G1_TIME_DELAY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : G2_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : G3_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E0_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E1_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E2_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : E3_TIME_DELAY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : M_TIME_DELAY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : N_TIME_DELAY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : EXTCLK3_COUNTER
Value : E3
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : EXTCLK2_COUNTER
Value : E2
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : EXTCLK1_COUNTER
Value : E1
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : EXTCLK0_COUNTER
Value : E0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : ENABLE0_COUNTER
Value : L0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : ENABLE1_COUNTER
Value : L0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CHARGE_PUMP_CURRENT
Value : 2
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : LOOP_FILTER_R
Value : 1.000000
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : LOOP_FILTER_C
Value : 5
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CHARGE_PUMP_CURRENT_BITS
Value : 9999
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : LOOP_FILTER_R_BITS
Value : 9999
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : LOOP_FILTER_C_BITS
Value : 9999
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : VCO_POST_SCALE
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CLK2_OUTPUT_FREQUENCY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK1_OUTPUT_FREQUENCY
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : CLK0_OUTPUT_FREQUENCY
Value : 0
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : INTENDED_DEVICE_FAMILY
Value : Cyclone IV E
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA0
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA1
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA2
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA3
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA4
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKENA5
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLKENA0
Value : PORT_CONNECTIVITY
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLKENA1
Value : PORT_CONNECTIVITY
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLKENA2
Value : PORT_CONNECTIVITY
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLKENA3
Value : PORT_CONNECTIVITY
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLK0
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLK1
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLK2
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_EXTCLK3
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKBAD0
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKBAD1
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK0
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CLK1
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CLK2
2022-04-02 14:56:02 +03:00
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK3
Value : PORT_UNUSED
2022-03-30 14:23:28 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK4
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK5
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK6
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK7
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK8
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLK9
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANDATA
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANDATAOUT
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANDONE
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCLKOUT1
Value : PORT_CONNECTIVITY
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCLKOUT0
Value : PORT_CONNECTIVITY
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_ACTIVECLOCK
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKLOSS
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_INCLK1
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_INCLK0
Value : PORT_USED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_FBIN
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PLLENA
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CLKSWITCH
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_ARESET
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PFDENA
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANCLK
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANACLR
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANREAD
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANWRITE
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_ENABLE0
Value : PORT_CONNECTIVITY
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_ENABLE1
Value : PORT_CONNECTIVITY
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_LOCKED
2022-04-02 14:56:02 +03:00
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_CONFIGUPDATE
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_FBOUT
Value : PORT_CONNECTIVITY
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PHASEDONE
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PHASESTEP
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PHASEUPDOWN
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_SCANCLKENA
Value : PORT_UNUSED
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_PHASECOUNTERSELECT
Value : PORT_UNUSED
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_VCOOVERRANGE
Value : PORT_CONNECTIVITY
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : PORT_VCOUNDERRANGE
Value : PORT_CONNECTIVITY
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : M_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C0_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C1_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C2_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C3_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C4_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C5_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C6_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C7_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C8_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : C9_TEST_SOURCE
Value : 5
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : CBXI_PARAMETER
2022-04-02 14:56:02 +03:00
Value : sdram_clk_gen_altpll
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : VCO_FREQUENCY_CONTROL
Value : AUTO
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : VCO_PHASE_SHIFT_STEP
Value : 0
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : WIDTH_CLOCK
Value : 5
Type : Signed Integer
Parameter Name : WIDTH_PHASECOUNTERSELECT
Value : 4
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : USING_FBMIMICBIDIR_PORT
Value : OFF
2022-03-30 14:57:41 +03:00
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : SCAN_CHAIN_MIF_FILE
Value : UNUSED
Type : Untyped
Parameter Name : SIM_GATE_LOCK_DEVICE_BEHAVIOR
Value : OFF
2022-03-30 14:57:41 +03:00
Type : Untyped
2022-03-31 14:13:34 +03:00
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
2022-04-02 14:56:02 +03:00
; Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component ;
2022-03-31 14:13:34 +03:00
+--------------------------------------------------------------------------------+
2022-04-02 14:56:02 +03:00
Parameter Name : OPERATION_MODE
Value : NORMAL
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : PLL_TYPE
Value : AUTO
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : LPM_HINT
Value : CBX_MODULE_PREFIX=pll
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : QUALIFY_CONF_DONE
Value : OFF
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : COMPENSATE_CLOCK
Value : CLK0
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : SCAN_CHAIN
Value : LONG
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : PRIMARY_CLOCK
Value : INCLK0
Type : Untyped
2022-03-31 14:13:34 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : INCLK0_INPUT_FREQUENCY
Value : 20000
2022-03-31 14:13:34 +03:00
Type : Signed Integer
2022-03-30 14:57:41 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : INCLK1_INPUT_FREQUENCY
Value : 0
Type : Untyped
2022-03-30 14:57:41 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : GATE_LOCK_SIGNAL
Value : NO
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : GATE_LOCK_COUNTER
Value : 0
Type : Untyped
2022-03-30 14:23:28 +03:00
2022-04-02 14:56:02 +03:00
Parameter Name : LOCK_HIGH
Value : 1
Type : Untyped
Parameter Name : LOCK_LOW
Value : 1
Type : Untyped
Parameter Name : VALID_LOCK_MULTIPLIER
Value : 1
Type : Untyped
Parameter Name : INVALID_LOCK_MULTIPLIER
Value : 5
Type : Untyped
Parameter Name : SWITCH_OVER_ON_LOSSCLK
Value : OFF
Type : Untyped
Parameter Name : SWITCH_OVER_ON_GATED_LOCK
Value : OFF
Type : Untyped
Parameter Name : ENABLE_SWITCH_OVER_COUNTER
Value : OFF
Type : Untyped
Parameter Name : SKIP_VCO
Value : OFF
Type : Untyped
Parameter Name : SWITCH_OVER_COUNTER
Value : 0
Type : Untyped
Parameter Name : SWITCH_OVER_TYPE
Value : AUTO
Type : Untyped
Parameter Name : FEEDBACK_SOURCE
Value : EXTCLK0
Type : Untyped
Parameter Name : BANDWIDTH
Value : 0
Type : Untyped
Parameter Name : BANDWIDTH_TYPE
Value : AUTO
Type : Untyped
Parameter Name : SPREAD_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : DOWN_SPREAD
Value : 0
Type : Untyped
Parameter Name : SELF_RESET_ON_GATED_LOSS_LOCK
Value : OFF
Type : Untyped
Parameter Name : SELF_RESET_ON_LOSS_LOCK
Value : OFF
Type : Untyped
Parameter Name : CLK9_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK8_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK7_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK6_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : CLK5_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK4_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK3_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : CLK2_MULTIPLY_BY
Value : 12
Type : Signed Integer
Parameter Name : CLK1_MULTIPLY_BY
Value : 7
Type : Signed Integer
Parameter Name : CLK0_MULTIPLY_BY
Value : 1007
Type : Signed Integer
Parameter Name : CLK9_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK8_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK7_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK6_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : CLK5_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK4_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK3_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : CLK2_DIVIDE_BY
Value : 25
Type : Signed Integer
Parameter Name : CLK1_DIVIDE_BY
Value : 25
Type : Signed Integer
Parameter Name : CLK0_DIVIDE_BY
Value : 2000
Type : Signed Integer
Parameter Name : CLK9_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK8_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK7_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK6_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK5_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK4_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK3_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK2_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK1_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : CLK5_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK4_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : CLK9_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK8_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK7_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK6_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK5_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK4_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK3_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : CLK2_DUTY_CYCLE
Value : 50
Type : Signed Integer
Parameter Name : CLK1_DUTY_CYCLE
Value : 50
Type : Signed Integer
Parameter Name : CLK0_DUTY_CYCLE
Value : 50
Type : Signed Integer
Parameter Name : CLK9_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK8_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK7_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK6_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK5_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK4_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK3_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK2_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK1_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK0_USE_EVEN_COUNTER_MODE
Value : OFF
Type : Untyped
Parameter Name : CLK9_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK8_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK7_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK6_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK5_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK4_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK3_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK2_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK1_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : CLK0_USE_EVEN_COUNTER_VALUE
Value : OFF
Type : Untyped
Parameter Name : LOCK_WINDOW_UI
Value : 0.05
Type : Untyped
Parameter Name : LOCK_WINDOW_UI_BITS
Value : UNUSED
Type : Untyped
Parameter Name : VCO_RANGE_DETECTOR_LOW_BITS
Value : UNUSED
Type : Untyped
Parameter Name : VCO_RANGE_DETECTOR_HIGH_BITS
Value : UNUSED
Type : Untyped
Parameter Name : DPA_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : DPA_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : DPA_DIVIDER
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK2_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK1_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK0_MULTIPLY_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK3_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK2_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK1_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK0_DIVIDE_BY
Value : 1
Type : Untyped
Parameter Name : EXTCLK3_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK2_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK1_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK2_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK1_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : EXTCLK0_DUTY_CYCLE
Value : 50
Type : Untyped
Parameter Name : VCO_MULTIPLY_BY
Value : 0
Type : Untyped
Parameter Name : VCO_DIVIDE_BY
Value : 0
Type : Untyped
Parameter Name : SCLKOUT0_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : SCLKOUT1_PHASE_SHIFT
Value : 0
Type : Untyped
Parameter Name : VCO_MIN
Value : 0
Type : Untyped
Parameter Name : VCO_MAX
Value : 0
Type : Untyped
Parameter Name : VCO_CENTER
Value : 0
Type : Untyped
Parameter Name : PFD_MIN
Value : 0
Type : Untyped
Parameter Name : PFD_MAX
Value : 0
Type : Untyped
Parameter Name : M_INITIAL
Value : 0
Type : Untyped
Parameter Name : M
Value : 0
Type : Untyped
Parameter Name : N
Value : 1
Type : Untyped
Parameter Name : M2
Value : 1
Type : Untyped
Parameter Name : N2
Value : 1
Type : Untyped
Parameter Name : SS
Value : 1
Type : Untyped
Parameter Name : C0_HIGH
Value : 0
Type : Untyped
Parameter Name : C1_HIGH
Value : 0
Type : Untyped
Parameter Name : C2_HIGH
Value : 0
Type : Untyped
Parameter Name : C3_HIGH
Value : 0
Type : Untyped
Parameter Name : C4_HIGH
Value : 0
Type : Untyped
Parameter Name : C5_HIGH
Value : 0
Type : Untyped
Parameter Name : C6_HIGH
Value : 0
Type : Untyped
Parameter Name : C7_HIGH
Value : 0
Type : Untyped
Parameter Name : C8_HIGH
Value : 0
Type : Untyped
Parameter Name : C9_HIGH
Value : 0
Type : Untyped
Parameter Name : C0_LOW
Value : 0
Type : Untyped
Parameter Name : C1_LOW
Value : 0
Type : Untyped
Parameter Name : C2_LOW
Value : 0
Type : Untyped
Parameter Name : C3_LOW
Value : 0
Type : Untyped
Parameter Name : C4_LOW
Value : 0
Type : Untyped
Parameter Name : C5_LOW
Value : 0
Type : Untyped
Parameter Name : C6_LOW
Value : 0
Type : Untyped
Parameter Name : C7_LOW
Value : 0
Type : Untyped
Parameter Name : C8_LOW
Value : 0
Type : Untyped
Parameter Name : C9_LOW
Value : 0
Type : Untyped
Parameter Name : C0_INITIAL
Value : 0
Type : Untyped
Parameter Name : C1_INITIAL
Value : 0
Type : Untyped
Parameter Name : C2_INITIAL
Value : 0
Type : Untyped
Parameter Name : C3_INITIAL
Value : 0
Type : Untyped
Parameter Name : C4_INITIAL
Value : 0
Type : Untyped
Parameter Name : C5_INITIAL
Value : 0
Type : Untyped
Parameter Name : C6_INITIAL
Value : 0
Type : Untyped
Parameter Name : C7_INITIAL
Value : 0
Type : Untyped
Parameter Name : C8_INITIAL
Value : 0
Type : Untyped
Parameter Name : C9_INITIAL
Value : 0
Type : Untyped
Parameter Name : C0_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C1_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C2_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C3_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C4_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C5_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C6_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C7_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C8_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C9_MODE
Value : BYPASS
Type : Untyped
Parameter Name : C0_PH
Value : 0
Type : Untyped
Parameter Name : C1_PH
Value : 0
Type : Untyped
Parameter Name : C2_PH
Value : 0
Type : Untyped
Parameter Name : C3_PH
Value : 0
Type : Untyped
Parameter Name : C4_PH
Value : 0
Type : Untyped
Parameter Name : C5_PH
Value : 0
Type : Untyped
Parameter Name : C6_PH
Value : 0
Type : Untyped
Parameter Name : C7_PH
Value : 0
Type : Untyped
Parameter Name : C8_PH
Value : 0
Type : Untyped
Parameter Name : C9_PH
Value : 0
Type : Untyped
Parameter Name : L0_HIGH
Value : 1
Type : Untyped
Parameter Name : L1_HIGH
Value : 1
Type : Untyped
Parameter Name : G0_HIGH
Value : 1
Type : Untyped
Parameter Name : G1_HIGH
Value : 1
Type : Untyped
Parameter Name : G2_HIGH
Value : 1
Type : Untyped
Parameter Name : G3_HIGH
Value : 1
Type : Untyped
Parameter Name : E0_HIGH
Value : 1
Type : Untyped
Parameter Name : E1_HIGH
Value : 1
Type : Untyped
Parameter Name : E2_HIGH
Value : 1
Type : Untyped
Parameter Name : E3_HIGH
Value : 1
Type : Untyped
Parameter Name : L0_LOW
Value : 1
Type : Untyped
Parameter Name : L1_LOW
Value : 1
Type : Untyped
Parameter Name : G0_LOW
Value : 1
Type : Untyped
Parameter Name : G1_LOW
Value : 1
Type : Untyped
Parameter Name : G2_LOW
Value : 1
Type : Untyped
Parameter Name : G3_LOW
Value : 1
Type : Untyped
Parameter Name : E0_LOW
Value : 1
Type : Untyped
Parameter Name : E1_LOW
Value : 1
Type : Untyped
Parameter Name : E2_LOW
Value : 1
Type : Untyped
Parameter Name : E3_LOW
Value : 1
Type : Untyped
Parameter Name : L0_INITIAL
Value : 1
Type : Untyped
Parameter Name : L1_INITIAL
Value : 1
Type : Untyped
Parameter Name : G0_INITIAL
Value : 1
Type : Untyped
Parameter Name : G1_INITIAL
Value : 1
Type : Untyped
Parameter Name : G2_INITIAL
Value : 1
Type : Untyped
Parameter Name : G3_INITIAL
Value : 1
Type : Untyped
Parameter Name : E0_INITIAL
Value : 1
Type : Untyped
Parameter Name : E1_INITIAL
Value : 1
Type : Untyped
Parameter Name : E2_INITIAL
Value : 1
Type : Untyped
Parameter Name : E3_INITIAL
Value : 1
Type : Untyped
Parameter Name : L0_MODE
Value : BYPASS
Type : Untyped
Parameter Name : L1_MODE
Value : BYPASS
Type : Untyped
Parameter Name : G0_MODE
Value : BYPASS
Type : Untyped
Parameter Name : G1_MODE
Value : BYPASS
Type : Untyped
Parameter Name : G2_MODE
Value : BYPASS
Type : Untyped
Parameter Name : G3_MODE
Value : BYPASS
Type : Untyped
Parameter Name : E0_MODE
Value : BYPASS
Type : Untyped
Parameter Name : E1_MODE
Value : BYPASS
Type : Untyped
Parameter Name : E2_MODE
Value : BYPASS
Type : Untyped
Parameter Name : E3_MODE
Value : BYPASS
Type : Untyped
Parameter Name : L0_PH
Value : 0
Type : Untyped
Parameter Name : L1_PH
Value : 0
Type : Untyped
Parameter Name : G0_PH
Value : 0
Type : Untyped
Parameter Name : G1_PH
Value : 0
Type : Untyped
Parameter Name : G2_PH
Value : 0
Type : Untyped
Parameter Name : G3_PH
Value : 0
Type : Untyped
Parameter Name : E0_PH
Value : 0
Type : Untyped
Parameter Name : E1_PH
Value : 0
Type : Untyped
Parameter Name : E2_PH
Value : 0
Type : Untyped
Parameter Name : E3_PH
Value : 0
Type : Untyped
Parameter Name : M_PH
Value : 0
Type : Untyped
Parameter Name : C1_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C2_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C3_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C4_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C5_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C6_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C7_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C8_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : C9_USE_CASC_IN
Value : OFF
Type : Untyped
Parameter Name : CLK0_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK1_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK2_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK3_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK4_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK5_COUNTER
Value : G0
Type : Untyped
Parameter Name : CLK6_COUNTER
Value : E0
Type : Untyped
Parameter Name : CLK7_COUNTER
Value : E1
Type : Untyped
Parameter Name : CLK8_COUNTER
Value : E2
Type : Untyped
Parameter Name : CLK9_COUNTER
Value : E3
Type : Untyped
Parameter Name : L0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : L1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : G0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : G1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : G2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : G3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : E0_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : E1_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : E2_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : E3_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : M_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : N_TIME_DELAY
Value : 0
Type : Untyped
Parameter Name : EXTCLK3_COUNTER
Value : E3
Type : Untyped
Parameter Name : EXTCLK2_COUNTER
Value : E2
Type : Untyped
Parameter Name : EXTCLK1_COUNTER
Value : E1
Type : Untyped
Parameter Name : EXTCLK0_COUNTER
Value : E0
Type : Untyped
Parameter Name : ENABLE0_COUNTER
Value : L0
Type : Untyped
Parameter Name : ENABLE1_COUNTER
Value : L0
Type : Untyped
Parameter Name : CHARGE_PUMP_CURRENT
Value : 2
Type : Untyped
Parameter Name : LOOP_FILTER_R
Value : 1.000000
Type : Untyped
Parameter Name : LOOP_FILTER_C
Value : 5
Type : Untyped
Parameter Name : CHARGE_PUMP_CURRENT_BITS
Value : 9999
Type : Untyped
Parameter Name : LOOP_FILTER_R_BITS
Value : 9999
Type : Untyped
Parameter Name : LOOP_FILTER_C_BITS
Value : 9999
Type : Untyped
Parameter Name : VCO_POST_SCALE
Value : 0
Type : Untyped
Parameter Name : CLK2_OUTPUT_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : CLK1_OUTPUT_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : CLK0_OUTPUT_FREQUENCY
Value : 0
Type : Untyped
Parameter Name : INTENDED_DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : PORT_CLKENA0
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKENA1
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKENA2
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKENA3
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKENA4
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKENA5
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_EXTCLKENA0
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_EXTCLKENA1
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_EXTCLKENA2
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_EXTCLKENA3
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_EXTCLK0
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_EXTCLK1
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_EXTCLK2
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_EXTCLK3
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKBAD0
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKBAD1
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK0
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CLK1
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CLK2
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CLK3
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK4
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK5
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK6
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK7
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK8
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLK9
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANDATA
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANDATAOUT
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANDONE
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCLKOUT1
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_SCLKOUT0
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_ACTIVECLOCK
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKLOSS
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_INCLK1
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_INCLK0
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_FBIN
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_PLLENA
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_CLKSWITCH
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_ARESET
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_PFDENA
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANCLK
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANACLR
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANREAD
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANWRITE
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_ENABLE0
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_ENABLE1
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_LOCKED
Value : PORT_USED
Type : Untyped
Parameter Name : PORT_CONFIGUPDATE
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_FBOUT
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_PHASEDONE
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_PHASESTEP
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_PHASEUPDOWN
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_SCANCLKENA
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_PHASECOUNTERSELECT
Value : PORT_UNUSED
Type : Untyped
Parameter Name : PORT_VCOOVERRANGE
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : PORT_VCOUNDERRANGE
Value : PORT_CONNECTIVITY
Type : Untyped
Parameter Name : M_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C0_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C1_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C2_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C3_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C4_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C5_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C6_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C7_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C8_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : C9_TEST_SOURCE
Value : 5
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : pll_altpll
Type : Untyped
Parameter Name : VCO_FREQUENCY_CONTROL
Value : AUTO
Type : Untyped
Parameter Name : VCO_PHASE_SHIFT_STEP
Value : 0
Type : Untyped
Parameter Name : WIDTH_CLOCK
Value : 5
Type : Signed Integer
Parameter Name : WIDTH_PHASECOUNTERSELECT
Value : 4
Type : Untyped
Parameter Name : USING_FBMIMICBIDIR_PORT
Value : OFF
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : SCAN_CHAIN_MIF_FILE
Value : UNUSED
Type : Untyped
Parameter Name : SIM_GATE_LOCK_DEVICE_BEHAVIOR
Value : OFF
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_ ;
+--------------------------------------------------------------------------------+
Parameter Name : device_address
Value : 26
Type : Signed Integer
Parameter Name : num_retries
Value : 0
Type : Signed Integer
Parameter Name : log2_divider
Value : 6
Type : Signed Integer
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_ ;
+--------------------------------------------------------------------------------+
Parameter Name : mclk_rate
Value : 12000000
Type : Signed Integer
Parameter Name : sample_rate
Value : 8000
Type : Signed Integer
Parameter Name : preamble
Value : 1
Type : Signed Integer
Parameter Name : word_length
Value : 16
Type : Signed Integer
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+--------------------------------------------+
; Name ; Value ;
+-------------------------------------------+--------------------------------------------+
; Number of entity instances ; 3 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; ram16:ram0|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; BIDIR_DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 16384 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; CLOCK0 ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; ram32:ram1|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 32768 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------+
+-------------------------------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+-----------------------------------------------------------------------------+
; Name ; Value ;
+-------------------------------+-----------------------------------------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 20000 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
; Entity Instance ; ula:ula_|pll:pll_|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 20000 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
+-------------------------------+-----------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
2022-03-30 14:23:28 +03:00
+--------------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
; Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_" ;
2022-03-30 14:23:28 +03:00
+--------------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
Port : test_db_high
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : test_db_low
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2" ;
+--------------------------------------------------------------------------------+
Port : in3
2022-03-30 14:23:28 +03:00
Type : Input
Severity : Info
Details : Stuck at GND
2022-03-30 14:57:41 +03:00
+--------------------------------------------------------------------------------+
2022-03-30 14:23:28 +03:00
2022-03-30 14:57:41 +03:00
+--------------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
; Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux" ;
2022-03-30 14:57:41 +03:00
+--------------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
Port : in6
2022-03-30 14:23:28 +03:00
Type : Input
2022-03-31 14:13:34 +03:00
Severity : Info
Details : Stuck at VCC
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_" ;
+--------------------------------------------------------------------------------+
Port : wait_m1
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "z80_top_direct_n:z80_" ;
+--------------------------------------------------------------------------------+
Port : nWAIT
Type : Input
Severity : Info
Details : Stuck at VCC
Port : nBUSRQ
Type : Input
Severity : Info
Details : Stuck at VCC
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_" ;
+--------------------------------------------------------------------------------+
Port : pcm_inl[13..0]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : pcm_inl[15]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
2022-03-30 14:23:28 +03:00
2022-03-31 14:13:34 +03:00
Port : pcm_inr[13..0]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : pcm_inr[15]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_" ;
+--------------------------------------------------------------------------------+
Port : is_done
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : is_error
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ula:ula_" ;
+--------------------------------------------------------------------------------+
Port : pressed
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : beeper
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
2022-04-02 14:56:02 +03:00
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "sdram_controller:sdram_" ;
+--------------------------------------------------------------------------------+
Port : address[23..16]
Type : Input
Severity : Info
Details : Stuck at GND
Port : data_out
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : data_out_valid
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : data_in[31..8]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
2022-03-31 14:13:34 +03:00
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram16:ram0" ;
+--------------------------------------------------------------------------------+
Port : address_b[13]
2022-03-30 14:23:28 +03:00
Type : Input
Severity : Info
Details : Stuck at GND
Port : data_b
Type : Input
Severity : Info
Details : Stuck at GND
Port : wren_b
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_b[-1]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "rom0:rom" ;
+--------------------------------------------------------------------------------+
2022-03-30 14:57:41 +03:00
Port : address
Type : Input
Severity : Warning
Details : Input port expression (16 bits) is wider than the input port (14 bits) it drives. The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
2022-03-30 14:23:28 +03:00
+--------------------------------------------------------------------------------+
2022-03-30 12:47:42 +03:00
2022-03-30 11:53:01 +03:00
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
2022-04-02 14:56:02 +03:00
; Top ; 00:00:11 ;
2022-03-30 11:53:01 +03:00
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
2022-04-02 14:56:02 +03:00
Info: Processing started: Sat Apr 2 14:50:31 2022
2022-03-30 11:53:01 +03:00
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
2022-03-31 14:13:34 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
2022-03-30 11:53:01 +03:00
Info (12023): Found entity 1: spectrum
2022-03-30 12:47:42 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
2022-03-30 14:23:28 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
Info (12023): Found entity 1: ram16
2022-03-30 14:57:41 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
Info (12023): Found entity 1: ram32
2022-03-31 14:13:34 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
Info (12023): Found entity 1: pll
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu.v
Info (12023): Found entity 1: alu
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v
Info (12023): Found entity 1: alu_bit_select
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v
Info (12023): Found entity 1: alu_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v
Info (12023): Found entity 1: alu_core
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v
Info (12023): Found entity 1: alu_flags
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v
Info (12023): Found entity 1: alu_mux_2
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v
Info (12023): Found entity 1: alu_mux_2z
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v
Info (12023): Found entity 1: alu_mux_3z
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v
Info (12023): Found entity 1: alu_mux_4
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v
Info (12023): Found entity 1: alu_mux_8
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v
Info (12023): Found entity 1: alu_prep_daa
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v
Info (12023): Found entity 1: alu_select
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v
Info (12023): Found entity 1: alu_shifter_core
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v
Info (12023): Found entity 1: alu_slice
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v
Info (12023): Found entity 1: clk_delay
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v
Info (12023): Found entity 1: decode_state
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/execute.v
Info (12023): Found entity 1: execute
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v
Info (12023): Found entity 1: interrupts
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/ir.v
Info (12023): Found entity 1: ir
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v
Info (12023): Found entity 1: memory_ifc
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v
Info (12023): Found entity 1: pin_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v
Info (12023): Found entity 1: pla_decode
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/resets.v
Info (12023): Found entity 1: resets
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v
Info (12023): Found entity 1: sequencer
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v
Info (12023): Found entity 1: address_latch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v
Info (12023): Found entity 1: address_mux
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v
Info (12023): Found entity 1: address_pins
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v
Info (12023): Found entity 1: bus_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v
Info (12023): Found entity 1: bus_switch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v
Info (12023): Found entity 1: control_pins_n
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v
Info (12023): Found entity 1: data_pins
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v
Info (12023): Found entity 1: data_switch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v
Info (12023): Found entity 1: data_switch_mask
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v
Info (12023): Found entity 1: inc_dec
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v
Info (12023): Found entity 1: inc_dec_2bit
Info (12021): Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v
Info (12023): Found entity 1: z80_top_direct_n
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v
Info (12023): Found entity 1: reg_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v
Info (12023): Found entity 1: reg_file
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v
Info (12023): Found entity 1: reg_latch
Info (12021): Found 1 design units, including 1 entities, in source file ula/clocks.sv
Info (12023): Found entity 1: clocks
Info (12021): Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv
Info (12023): Found entity 1: zx_keyboard
Info (12021): Found 1 design units, including 1 entities, in source file ula/video.sv
Info (12023): Found entity 1: video
Info (12021): Found 1 design units, including 1 entities, in source file ula/ula.sv
Info (12023): Found entity 1: ula
Info (12021): Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv
Info (12023): Found entity 1: ps2_keyboard
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd
Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
Info (12023): Found entity 1: i2c_loader
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd
Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
Info (12023): Found entity 1: i2s_intf
Info (12021): Found 1 design units, including 1 entities, in source file rom_scr.v
Info (12023): Found entity 1: rom_scr
Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v
Info (12023): Found entity 1: pll_video
2022-04-01 18:58:14 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v
Info (12023): Found entity 1: ram_video
2022-04-02 14:56:02 +03:00
Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl
Info (12022): Found design unit 1: sdram_controller-rtl
Info (12023): Found entity 1: sdram_controller
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
Info (12023): Found entity 1: sdram_clk_gen
2022-03-30 11:53:01 +03:00
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
2022-04-01 18:58:14 +03:00
Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver
2022-03-31 14:13:34 +03:00
Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver
Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver
2022-03-30 12:47:42 +03:00
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "init_file" = "./rom/gw03.hex"
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "numwords_a" = "16384"
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "widthad_a" = "14"
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
2022-03-30 13:18:06 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf
Info (12023): Found entity 1: altsyncram_qh91
Info (12128): Elaborating entity "altsyncram_qh91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
Info (12023): Found entity 1: decode_c8a
Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
2022-03-30 14:23:28 +03:00
Info (12128): Elaborating entity "ram16" for hierarchy "ram16:ram0"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram16:ram0|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram16:ram0|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram16:ram0|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_reg_b" = "CLOCK0"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
Info (12134): Parameter "indata_reg_b" = "CLOCK0"
2022-03-31 14:13:34 +03:00
Info (12134): Parameter "init_file" = "ula/test_scr.hex"
2022-03-30 14:23:28 +03:00
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "numwords_b" = "16384"
Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_aclr_b" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "widthad_b" = "14"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_b" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12134): Parameter "width_byteena_b" = "1"
Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
2022-03-31 14:13:34 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf
Info (12023): Found entity 1: altsyncram_7ti2
Info (12128): Elaborating entity "altsyncram_7ti2" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated"
2022-03-30 14:23:28 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
2022-03-31 14:13:34 +03:00
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2"
2022-03-30 14:57:41 +03:00
Info (12128): Elaborating entity "ram32" for hierarchy "ram32:ram1"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram32:ram1|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram32:ram1|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram32:ram1|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "32768"
Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "widthad_a" = "15"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf
Info (12023): Found entity 1: altsyncram_g9i1
Info (12128): Elaborating entity "altsyncram_g9i1" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
Info (12023): Found entity 1: decode_msa
Info (12128): Elaborating entity "decode_msa" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf
Info (12023): Found entity 1: decode_f8a
Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf
Info (12023): Found entity 1: mux_6nb
Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2"
2022-04-02 14:56:02 +03:00
Info (12128): Elaborating entity "sdram_controller" for hierarchy "sdram_controller:sdram_"
Info (12128): Elaborating entity "sdram_clk_gen" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll"
Info (12128): Elaborating entity "altpll" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component"
Info (12133): Instantiated megafunction "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" with the following parameter:
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "1"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "2"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "1"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "2"
Info (12134): Parameter "clk1_phase_shift" = "3000"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=sdram_clk_gen"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_UNUSED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v
Info (12023): Found entity 1: sdram_clk_gen_altpll
Info (12128): Elaborating entity "sdram_clk_gen_altpll" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated"
2022-03-31 14:13:34 +03:00
Info (12128): Elaborating entity "ula" for hierarchy "ula:ula_"
Info (12128): Elaborating entity "pll" for hierarchy "ula:ula_|pll:pll_"
Info (12128): Elaborating entity "altpll" for hierarchy "ula:ula_|pll:pll_|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "ula:ula_|pll:pll_|altpll:altpll_component"
Info (12133): Instantiated megafunction "ula:ula_|pll:pll_|altpll:altpll_component" with the following parameter:
Info (12134): Parameter "bandwidth_type" = "AUTO"
2022-04-01 18:58:14 +03:00
Info (12134): Parameter "clk0_divide_by" = "2000"
2022-03-31 14:13:34 +03:00
Info (12134): Parameter "clk0_duty_cycle" = "50"
2022-04-01 18:58:14 +03:00
Info (12134): Parameter "clk0_multiply_by" = "1007"
2022-03-31 14:13:34 +03:00
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "25"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "7"
Info (12134): Parameter "clk1_phase_shift" = "0"
Info (12134): Parameter "clk2_divide_by" = "25"
Info (12134): Parameter "clk2_duty_cycle" = "50"
Info (12134): Parameter "clk2_multiply_by" = "12"
Info (12134): Parameter "clk2_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_USED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_USED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "self_reset_on_loss_lock" = "OFF"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v
Info (12023): Found entity 1: pll_altpll
Info (12128): Elaborating entity "pll_altpll" for hierarchy "ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated"
Info (12128): Elaborating entity "clocks" for hierarchy "ula:ula_|clocks:clocks_"
Info (12128): Elaborating entity "i2c_loader" for hierarchy "ula:ula_|i2c_loader:i2c_loader_"
Info (12128): Elaborating entity "i2s_intf" for hierarchy "ula:ula_|i2s_intf:i2s_intf_"
Info (12128): Elaborating entity "video" for hierarchy "ula:ula_|video:video_"
Info (12128): Elaborating entity "ps2_keyboard" for hierarchy "ula:ula_|ps2_keyboard:ps2_keyboard_"
Info (12128): Elaborating entity "zx_keyboard" for hierarchy "ula:ula_|zx_keyboard:zx_keyboard_"
Info (12128): Elaborating entity "z80_top_direct_n" for hierarchy "z80_top_direct_n:z80_"
Info (12128): Elaborating entity "clk_delay" for hierarchy "z80_top_direct_n:z80_|clk_delay:clk_delay_"
Info (12128): Elaborating entity "decode_state" for hierarchy "z80_top_direct_n:z80_|decode_state:decode_state_"
Info (12128): Elaborating entity "execute" for hierarchy "z80_top_direct_n:z80_|execute:execute_"
Info (12128): Elaborating entity "interrupts" for hierarchy "z80_top_direct_n:z80_|interrupts:interrupts_"
Info (12128): Elaborating entity "ir" for hierarchy "z80_top_direct_n:z80_|ir:ir_"
Info (12128): Elaborating entity "pin_control" for hierarchy "z80_top_direct_n:z80_|pin_control:pin_control_"
Info (12128): Elaborating entity "pla_decode" for hierarchy "z80_top_direct_n:z80_|pla_decode:pla_decode_"
Info (12128): Elaborating entity "resets" for hierarchy "z80_top_direct_n:z80_|resets:resets_"
Info (12128): Elaborating entity "memory_ifc" for hierarchy "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
Info (12128): Elaborating entity "sequencer" for hierarchy "z80_top_direct_n:z80_|sequencer:sequencer_"
Info (12128): Elaborating entity "alu_control" for hierarchy "z80_top_direct_n:z80_|alu_control:alu_control_"
Info (12128): Elaborating entity "alu_mux_4" for hierarchy "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_4:b2v_inst_cond_mux"
Info (12128): Elaborating entity "alu_mux_8" for hierarchy "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
Info (12128): Elaborating entity "alu_select" for hierarchy "z80_top_direct_n:z80_|alu_select:alu_select_"
Info (12128): Elaborating entity "alu_flags" for hierarchy "z80_top_direct_n:z80_|alu_flags:alu_flags_"
Info (12128): Elaborating entity "alu_mux_2" for hierarchy "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_2:b2v_inst_mux_cf"
Info (12128): Elaborating entity "alu" for hierarchy "z80_top_direct_n:z80_|alu:alu_"
Info (12128): Elaborating entity "alu_core" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core"
Info (12128): Elaborating entity "alu_slice" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0"
Info (12128): Elaborating entity "alu_bit_select" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select"
Info (12128): Elaborating entity "alu_shifter_core" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift"
Info (12128): Elaborating entity "alu_mux_2z" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high"
Info (12128): Elaborating entity "alu_mux_3z" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low"
Info (12128): Elaborating entity "alu_prep_daa" for hierarchy "z80_top_direct_n:z80_|alu:alu_|alu_prep_daa:b2v_prep_daa"
Info (12128): Elaborating entity "reg_file" for hierarchy "z80_top_direct_n:z80_|reg_file:reg_file_"
Info (12128): Elaborating entity "reg_latch" for hierarchy "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi"
Info (12128): Elaborating entity "reg_control" for hierarchy "z80_top_direct_n:z80_|reg_control:reg_control_"
Info (12128): Elaborating entity "address_latch" for hierarchy "z80_top_direct_n:z80_|address_latch:address_latch_"
Info (12128): Elaborating entity "address_mux" for hierarchy "z80_top_direct_n:z80_|address_latch:address_latch_|address_mux:b2v_inst7"
Info (12128): Elaborating entity "inc_dec" for hierarchy "z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec"
Info (12128): Elaborating entity "inc_dec_2bit" for hierarchy "z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0"
Info (12128): Elaborating entity "bus_control" for hierarchy "z80_top_direct_n:z80_|bus_control:bus_control_"
Info (12128): Elaborating entity "bus_switch" for hierarchy "z80_top_direct_n:z80_|bus_switch:bus_switch_"
Info (12128): Elaborating entity "data_switch" for hierarchy "z80_top_direct_n:z80_|data_switch:sw2_"
Info (12128): Elaborating entity "data_switch_mask" for hierarchy "z80_top_direct_n:z80_|data_switch_mask:sw1_"
Info (12128): Elaborating entity "address_pins" for hierarchy "z80_top_direct_n:z80_|address_pins:address_pins_"
Info (12128): Elaborating entity "data_pins" for hierarchy "z80_top_direct_n:z80_|data_pins:data_pins_"
Info (12128): Elaborating entity "control_pins_n" for hierarchy "z80_top_direct_n:z80_|control_pins_n:control_pins_"
Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]" to the node "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]" into an OR gate
2022-04-02 14:56:02 +03:00
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "RamWE" into an OR gate
2022-03-31 14:13:34 +03:00
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nWR" to the node "RamWE" into an OR gate
2022-04-02 14:56:02 +03:00
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal1" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal1" into an OR gate
2022-03-31 14:13:34 +03:00
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[0]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[7]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[7]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[6]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[6]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[5]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[4]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[3]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[2]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[1]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_high[3]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_1" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_high[2]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|SYNTHESIZED_WIRE_2[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_high[1]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_13" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_high[0]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|SYNTHESIZED_WIRE_2[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_low[3]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_17" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_low[2]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|SYNTHESIZED_WIRE_3[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_low[1]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|SYNTHESIZED_WIRE_3[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db_low[0]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|SYNTHESIZED_WIRE_3[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[3]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[4]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[4]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[5]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[5]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[6]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[6]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[7]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[8]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[9]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[10]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[11]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[12]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[13]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[14]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]" to the node "z80_top_direct_n:z80_|address_latch:address_latch_|abusz[15]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[6]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_12" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[7]" to the node "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[0]" to the node "z80_top_direct_n:z80_|alu_control:alu_control_|shift_cf_out" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[0]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_22" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[7]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_10" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[5]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_14" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[4]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_16" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[3]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_18" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[2]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_20" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu_control:alu_control_|db[1]" to the node "z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_2" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[6]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_high[3]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[5]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_high[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[4]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_high[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[3]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_high[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[2]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_low[3]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|alu:alu_|db[1]" to the node "z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift|out_low[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[3]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[4]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[5]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[6]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo|latch[7]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[0]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[1]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[2]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[3]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[4]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[5]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[6]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]" to the node "z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi|latch[7]" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[0]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[1]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[2]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[3]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[4]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[5]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[6]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6" into an OR gate
Warning (13047): Converted the fan-out from the tri-state buffer "D[7]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7" into an OR gate
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
2022-03-30 14:57:41 +03:00
Warning (13024): Output pins are stuck at VCC or GND
2022-03-31 14:13:34 +03:00
Warning (13410): Pin "LED[1]" is stuck at GND
Warning (13410): Pin "LED[4]" is stuck at GND
Warning (13410): Pin "LED[5]" is stuck at GND
Warning (13410): Pin "LED[6]" is stuck at GND
Warning (13410): Pin "LED[7]" is stuck at GND
Warning (13410): Pin "GPIO_1[24]" is stuck at VCC
Warning (13410): Pin "GPIO_1[32]" is stuck at GND
Warning (13410): Pin "GPIO_1[33]" is stuck at GND
2022-04-02 14:56:02 +03:00
Warning (13410): Pin "DRAM_CKE" is stuck at VCC
Warning (13410): Pin "DRAM_CS_N" is stuck at GND
2022-03-30 11:53:01 +03:00
Info (286030): Timing-Driven Synthesis is running
2022-03-31 14:13:34 +03:00
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
2022-03-30 11:53:01 +03:00
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
2022-04-02 14:56:02 +03:00
Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
2022-03-31 14:13:34 +03:00
Warning (21074): Design contains 2 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "SW[0]"
Warning (15610): No output dependent on input pin "SW[3]"
2022-04-02 14:56:02 +03:00
Info (21057): Implemented 3006 device resources after synthesis - the final resource count might be different
2022-04-01 18:58:14 +03:00
Info (21058): Implemented 11 input pins
2022-04-02 14:56:02 +03:00
Info (21059): Implemented 85 output pins
Info (21060): Implemented 18 bidirectional pins
Info (21061): Implemented 2826 logic cells
2022-03-30 14:57:41 +03:00
Info (21064): Implemented 64 RAM segments
2022-04-02 14:56:02 +03:00
Info (21065): Implemented 2 PLLs
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings
Info: Peak virtual memory: 446 megabytes
Info: Processing ended: Sat Apr 2 14:50:45 2022
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all processors): 00:00:15
2022-03-31 14:13:34 +03:00
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg.
2022-03-30 11:53:01 +03:00
