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de0-zx-spectrum/output_files/spectrum.map.rpt
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Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Analysis & Synthesis report for spectrum
Added RAM16
2022-03-30 14:23:28 +03:00
Wed Mar 30 13:47:09 2022
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
Added RAM16
2022-03-30 14:23:28 +03:00
10. Registers Removed During Synthesis
11. Removed Registers Triggering Further Register Optimizations
12. General Register Statistics
13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
17. altsyncram Parameter Settings by Entity Instance
18. Port Connectivity Checks: "ram16:ram0"
19. Port Connectivity Checks: "rom0:rom"
20. Elapsed Time Per Partition
21. Analysis & Synthesis Messages
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
Added RAM16
2022-03-30 14:23:28 +03:00
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ;
Initial import. Counter to leds
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; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
Added RAM16
2022-03-30 14:23:28 +03:00
; Total logic elements ; 50 ;
; Total combinational functions ; 48 ;
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; Dedicated logic registers ; 38 ;
; Total registers ; 38 ;
Initial import. Counter to leds
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; Total pins ; 9 ;
; Total virtual pins ; 0 ;
Added RAM16
2022-03-30 14:23:28 +03:00
; Total memory bits ; 98,304 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+
Option : Device
Setting : EP4CE22F17C6
Default Value :
Option : Top-level entity name
Setting : spectrum
Default Value : spectrum
Option : Family name
Setting : Cyclone IV E
Default Value : Cyclone IV GX
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting : On
Default Value : On
Option : Enable compact report table
Setting : Off
Default Value : Off
Option : Restructure Multiplexers
Setting : Auto
Default Value : Auto
Option : Create Debugging Nodes for IP Cores
Setting : Off
Default Value : Off
Option : Preserve fewer node names
Setting : On
Default Value : On
Option : Disable OpenCore Plus hardware evaluation
Setting : Off
Default Value : Off
Option : Verilog Version
Setting : Verilog_2001
Default Value : Verilog_2001
Option : VHDL Version
Setting : VHDL_1993
Default Value : VHDL_1993
Option : State Machine Processing
Setting : Auto
Default Value : Auto
Option : Safe State Machine
Setting : Off
Default Value : Off
Option : Extract Verilog State Machines
Setting : On
Default Value : On
Option : Extract VHDL State Machines
Setting : On
Default Value : On
Option : Ignore Verilog initial constructs
Setting : Off
Default Value : Off
Option : Iteration limit for constant Verilog loops
Setting : 5000
Default Value : 5000
Option : Iteration limit for non-constant Verilog loops
Setting : 250
Default Value : 250
Option : Add Pass-Through Logic to Inferred RAMs
Setting : On
Default Value : On
Option : Infer RAMs from Raw Logic
Setting : On
Default Value : On
Option : Parallel Synthesis
Setting : On
Default Value : On
Option : DSP Block Balancing
Setting : Auto
Default Value : Auto
Option : NOT Gate Push-Back
Setting : On
Default Value : On
Option : Power-Up Don't Care
Setting : On
Default Value : On
Option : Remove Redundant Logic Cells
Setting : Off
Default Value : Off
Option : Remove Duplicate Registers
Setting : On
Default Value : On
Option : Ignore CARRY Buffers
Setting : Off
Default Value : Off
Option : Ignore CASCADE Buffers
Setting : Off
Default Value : Off
Option : Ignore GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore ROW GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore LCELL Buffers
Setting : Off
Default Value : Off
Option : Ignore SOFT Buffers
Setting : On
Default Value : On
Option : Limit AHDL Integers to 32 Bits
Setting : Off
Default Value : Off
Option : Optimization Technique
Setting : Balanced
Default Value : Balanced
Option : Carry Chain Length
Setting : 70
Default Value : 70
Option : Auto Carry Chains
Setting : On
Default Value : On
Option : Auto Open-Drain Pins
Setting : On
Default Value : On
Option : Perform WYSIWYG Primitive Resynthesis
Setting : Off
Default Value : Off
Option : Auto ROM Replacement
Setting : On
Default Value : On
Option : Auto RAM Replacement
Setting : On
Default Value : On
Option : Auto DSP Block Replacement
Setting : On
Default Value : On
Option : Auto Shift Register Replacement
Setting : Auto
Default Value : Auto
Option : Allow Shift Register Merging across Hierarchies
Setting : Auto
Default Value : Auto
Option : Auto Clock Enable Replacement
Setting : On
Default Value : On
Option : Strict RAM Replacement
Setting : Off
Default Value : Off
Option : Allow Synchronous Control Signals
Setting : On
Default Value : On
Option : Force Use of Synchronous Clear Signals
Setting : Off
Default Value : Off
Option : Auto RAM Block Balancing
Setting : On
Default Value : On
Option : Auto RAM to Logic Cell Conversion
Setting : Off
Default Value : Off
Option : Auto Resource Sharing
Setting : Off
Default Value : Off
Option : Allow Any RAM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any ROM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any Shift Register Size For Recognition
Setting : Off
Default Value : Off
Option : Use LogicLock Constraints during Resource Balancing
Setting : On
Default Value : On
Option : Ignore translate_off and synthesis_off directives
Setting : Off
Default Value : Off
Option : Timing-Driven Synthesis
Setting : On
Default Value : On
Option : Report Parameter Settings
Setting : On
Default Value : On
Option : Report Source Assignments
Setting : On
Default Value : On
Option : Report Connectivity Checks
Setting : On
Default Value : On
Option : Ignore Maximum Fan-Out Assignments
Setting : Off
Default Value : Off
Option : Synchronization Register Chain Length
Setting : 2
Default Value : 2
Option : PowerPlay Power Optimization
Setting : Normal compilation
Default Value : Normal compilation
Option : HDL message level
Setting : Level2
Default Value : Level2
Option : Suppress Register Optimization Related Messages
Setting : Off
Default Value : Off
Option : Number of Removed Registers Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Swept Nodes Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Inverted Registers Reported in Synthesis Report
Setting : 100
Default Value : 100
Option : Clock MUX Protection
Setting : On
Default Value : On
Option : Auto Gated Clock Conversion
Setting : Off
Default Value : Off
Option : Block Design Naming
Setting : Auto
Default Value : Auto
Option : SDC constraint protection
Setting : Off
Default Value : Off
Option : Synthesis Effort
Setting : Auto
Default Value : Auto
Option : Shift Register Replacement - Allow Asynchronous Clear Signal
Setting : On
Default Value : On
Option : Pre-Mapping Resynthesis Optimization
Setting : Off
Default Value : Off
Option : Analysis & Synthesis Message Level
Setting : Medium
Default Value : Medium
Option : Disable Register Merging Across Hierarchies
Setting : Auto
Default Value : Auto
Option : Resource Aware Inference For Block RAM
Setting : On
Default Value : On
Option : Synthesis Seed
Setting : 1
Default Value : 1
+--------------------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------------------------+
File Name with User-Entered Path : spectrum.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Added RAM16
2022-03-30 14:23:28 +03:00
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v
Library :
Added RAM16
2022-03-30 14:23:28 +03:00
File Name with User-Entered Path : ram16.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
Library :
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
Library :
File Name with User-Entered Path : stratix_ram_block.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
Library :
File Name with User-Entered Path : lpm_mux.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc
Library :
File Name with User-Entered Path : lpm_decode.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc
Library :
File Name with User-Entered Path : aglobal131.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc
Library :
File Name with User-Entered Path : a_rdenreg.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
Library :
File Name with User-Entered Path : altrom.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc
Library :
File Name with User-Entered Path : altram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
Library :
File Name with User-Entered Path : altdpram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library :
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
File Name with User-Entered Path : db/altsyncram_qh91.tdf
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Used in Netlist : yes
File Type : Auto-Generated Megafunction
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf
Library :
File Name with User-Entered Path : rom/gw03.hex
Used in Netlist : yes
File Type : Auto-Found Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom/gw03.hex
Library :
File Name with User-Entered Path : db/decode_c8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_c8a.tdf
Library :
File Name with User-Entered Path : db/mux_3nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Library :
Added RAM16
2022-03-30 14:23:28 +03:00
File Name with User-Entered Path : db/altsyncram_bui2.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf
Library :
File Name with User-Entered Path : db/decode_jsa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
Library :
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
Added RAM16
2022-03-30 14:23:28 +03:00
; Estimated Total logic elements ; 50 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; ; ;
Added RAM16
2022-03-30 14:23:28 +03:00
; Total combinational functions ; 48 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; Logic element usage by number of LUT inputs ; ;
Added RAM16
2022-03-30 14:23:28 +03:00
; -- 4 input functions ; 7 ;
; -- 3 input functions ; 6 ;
; -- <=2 input functions ; 35 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; ; ;
; Logic elements by mode ; ;
Added RAM16
2022-03-30 14:23:28 +03:00
; -- normal mode ; 16 ;
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; -- arithmetic mode ; 32 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; ; ;
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; Total registers ; 38 ;
; -- Dedicated logic registers ; 38 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
Added RAM16
2022-03-30 14:23:28 +03:00
; Total memory bits ; 98304 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
Added RAM16
2022-03-30 14:23:28 +03:00
; Maximum fan-out ; 50 ;
; Total fan-out ; 401 ;
; Average fan-out ; 3.46 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
+---------------------------------------------+----------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
Added RAM16
2022-03-30 14:23:28 +03:00
LC Combinationals : 48 (44)
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
LC Registers : 38 (36)
Added RAM16
2022-03-30 14:23:28 +03:00
Memory Bits : 98304
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 9
Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Added RAM16
2022-03-30 14:23:28 +03:00
Compilation Hierarchy Node : |ram16:ram0|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
Library Name : work
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Compilation Hierarchy Node : |rom0:rom|
Added RAM16
2022-03-30 14:23:28 +03:00
LC Combinationals : 4 (0)
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
LC Registers : 2 (0)
Added RAM16
2022-03-30 14:23:28 +03:00
Memory Bits : 65536
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
Added RAM16
2022-03-30 14:23:28 +03:00
LC Combinationals : 4 (0)
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
LC Registers : 2 (0)
Added RAM16
2022-03-30 14:23:28 +03:00
Memory Bits : 65536
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
Added RAM16
2022-03-30 14:23:28 +03:00
LC Combinationals : 4 (0)
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
LC Registers : 2 (2)
Added RAM16
2022-03-30 14:23:28 +03:00
Memory Bits : 65536
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2|
Added RAM16
2022-03-30 14:23:28 +03:00
LC Combinationals : 4 (4)
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
LC Registers : 0 (0)
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Memory Bits : 0
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Library Name : work
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Added RAM16
2022-03-30 14:23:28 +03:00
Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : True Dual Port
Port A Depth : 16384
Port A Width : 8
Port B Depth : 16384
Port B Width : 8
Size : 131072
MIF : led_patterns.mif
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Type : AUTO
Mode : ROM
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Port A Depth : 16384
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Port A Width : 8
Port B Depth : --
Port B Width : --
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Size : 131072
MIF : ./rom/gw03.hex
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+
Added RAM16
2022-03-30 14:23:28 +03:00
Vendor : Altera
IP Core Name : RAM: 2-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram16:ram0
IP Include File : /home/benny/work/fpga/projects/ram16.v
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Vendor : Altera
IP Core Name : ROM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|rom0:rom
IP Include File : /home/benny/work/fpga/projects/rom0.v
+--------------------------------------------------------------------------------+
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Added RAM16
2022-03-30 14:23:28 +03:00
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; address[0] ; Merged with A[0] ;
; address[1] ; Merged with A[1] ;
; address[2] ; Merged with A[2] ;
; address[3] ; Merged with A[3] ;
; address[4] ; Merged with A[4] ;
; address[5] ; Merged with A[5] ;
; address[6] ; Merged with A[6] ;
; address[7] ; Merged with A[7] ;
; address[8] ; Merged with A[8] ;
; address[9] ; Merged with A[9] ;
; address[10] ; Merged with A[10] ;
; address[11] ; Merged with A[11] ;
; address[12] ; Merged with A[12] ;
; address[13] ; Merged with A[13] ;
; A[14,15] ; Lost fanout ;
; Total Number of Removed Registers = 18 ; ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------+
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
+--------------------------------------------------------------------------------+
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; Total registers ; 38 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; Number of registers using Clock Enable ; 13 ;
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
+--------------------------------------------------------------------------------+
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated ;
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
Added RAM16
2022-03-30 14:23:28 +03:00
+--------------------------------------------------------------------------------+
; Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : ROM
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Value : 14
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Type : Signed Integer
Parameter Name : NUMWORDS_A
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Value : 16384
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Value : ./rom/gw03.hex
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Value : altsyncram_qh91
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
Added RAM16
2022-03-30 14:23:28 +03:00
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : BIDIR_DUAL_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_B
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_B
Value : 16384
Type : Signed Integer
Parameter Name : INDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Signed Integer
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_bui2
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+--------------------------------------------+
; Name ; Value ;
+-------------------------------------------+--------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; ram16:ram0|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; BIDIR_DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 16384 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; CLOCK0 ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram16:ram0" ;
+--------------------------------------------------------------------------------+
Port : address_a
Type : Input
Severity : Warning
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : address_a[13..3]
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_a[7..4]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_a
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_a[-1]
Type : Input
Severity : Info
Details : Stuck at GND
Port : data_b
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_b
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_b
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_b[-1]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "rom0:rom" ;
+--------------------------------------------------------------------------------+
Port : q[3..0]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Added RAM16
2022-03-30 14:23:28 +03:00
Info: Processing started: Wed Mar 30 13:47:07 2022
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
Added RAM16
2022-03-30 14:23:28 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
Info (12023): Found entity 1: ram16
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Added RAM16
2022-03-30 14:23:28 +03:00
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "init_file" = "./rom/gw03.hex"
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "numwords_a" = "16384"
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Info (12134): Parameter "widthad_a" = "14"
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf
Info (12023): Found entity 1: altsyncram_qh91
Info (12128): Elaborating entity "altsyncram_qh91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
Info (12023): Found entity 1: decode_c8a
Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
Added RAM16
2022-03-30 14:23:28 +03:00
Info (12128): Elaborating entity "ram16" for hierarchy "ram16:ram0"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram16:ram0|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram16:ram0|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram16:ram0|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_reg_b" = "CLOCK0"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
Info (12134): Parameter "indata_reg_b" = "CLOCK0"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "numwords_b" = "16384"
Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_aclr_b" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "widthad_b" = "14"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_b" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12134): Parameter "width_byteena_b" = "1"
Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf
Info (12023): Found entity 1: altsyncram_bui2
Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Info (286030): Timing-Driven Synthesis is running
Added RAM16
2022-03-30 14:23:28 +03:00
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Added RAM16
2022-03-30 14:23:28 +03:00
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Added RAM16
2022-03-30 14:23:28 +03:00
Info (21061): Implemented 50 logic cells
Info (21064): Implemented 12 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings
Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 13:47:09 2022
Added ROM based LED patterns
2022-03-30 12:47:42 +03:00
Info: Elapsed time: 00:00:02
ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00
Info: Total CPU time (on all processors): 00:00:02
Initial import. Counter to leds
2022-03-30 11:53:01 +03:00
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