de0-zx-spectrum/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "spectrum")
  (DATE "03/30/2022 14:56:19")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 32-bit")
  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (DELAY
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (INSTANCE CLOCK_50\~inputclkctrl)
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  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[0\]\~63)
    (DELAY
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  )
  (CELL
    (CELLTYPE "dffeas")
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        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[2\]\~23)
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      (ABSOLUTE
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        (IOPATH datad combout (68:68:68) (63:63:63))
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        (IOPATH datab combout (192:192:192) (177:177:177))
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        (IOPATH datad combout (68:68:68) (63:63:63))
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      (ABSOLUTE
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  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[4\]\~27)
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      (ABSOLUTE
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        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
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    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
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        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
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    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[5\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (189:189:189))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
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      )
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  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
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    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
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      (ABSOLUTE
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        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[7\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (134:134:134) (183:183:183))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[8\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (135:135:135) (188:188:188))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[9\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (133:133:133) (183:183:183))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[10\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (133:133:133) (186:186:186))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[11\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (140:140:140) (189:189:189))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[12\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (213:213:213) (265:265:265))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[13\]\~45)
    (DELAY
      (ABSOLUTE
        (PORT dataa (211:211:211) (270:270:270))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[14\]\~47)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136:136:136) (189:189:189))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[15\]\~49)
    (DELAY
      (ABSOLUTE
        (PORT datab (135:135:135) (184:184:184))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[16\]\~51)
    (DELAY
      (ABSOLUTE
        (PORT dataa (135:135:135) (187:187:187))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[17\]\~53)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136:136:136) (188:188:188))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[18\]\~55)
    (DELAY
      (ABSOLUTE
        (PORT datab (135:135:135) (185:185:185))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[19\]\~57)
    (DELAY
      (ABSOLUTE
        (PORT datab (135:135:135) (185:185:185))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[20\]\~59)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[20\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[21\]\~61)
    (DELAY
      (ABSOLUTE
        (PORT datad (129:129:129) (166:166:166))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (908:908:908) (912:912:912))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (382:382:382) (459:459:459))
        (PORT datac (371:371:371) (449:449:449))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datac combout (120:120:120) (125:125:125))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (137:137:137) (191:191:191))
        (PORT datab (135:135:135) (185:185:185))
        (PORT datac (122:122:122) (165:165:165))
        (PORT datad (123:123:123) (163:163:163))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136:136:136) (189:189:189))
        (PORT datab (134:134:134) (184:184:184))
        (PORT datac (121:121:121) (164:164:164))
        (PORT datad (123:123:123) (162:162:162))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (137:137:137) (191:191:191))
        (PORT datab (136:136:136) (187:187:187))
        (PORT datac (200:200:200) (245:245:245))
        (PORT datad (122:122:122) (162:162:162))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (138:138:138) (192:192:192))
        (PORT datab (137:137:137) (188:188:188))
        (PORT datac (124:124:124) (168:168:168))
        (PORT datad (202:202:202) (246:246:246))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (139:139:139) (193:193:193))
        (PORT datab (138:138:138) (188:188:188))
        (PORT datac (131:131:131) (173:173:173))
        (PORT datad (132:132:132) (170:170:170))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (197:197:197) (238:238:238))
        (PORT datab (180:180:180) (221:221:221))
        (PORT datac (177:177:177) (213:213:213))
        (PORT datad (325:325:325) (379:379:379))
        (IOPATH dataa combout (159:159:159) (163:163:163))
        (IOPATH datab combout (161:161:161) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[0\]\~40)
    (DELAY
      (ABSOLUTE
        (PORT dataa (104:104:104) (135:135:135))
        (PORT datab (336:336:336) (393:393:393))
        (PORT datad (185:185:185) (214:214:214))
        (IOPATH dataa combout (158:158:158) (173:173:173))
        (IOPATH datab combout (160:160:160) (176:176:176))
        (IOPATH datac combout (190:190:190) (195:195:195))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (910:910:910))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[1\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (238:238:238) (301:301:301))
        (PORT datab (231:231:231) (296:296:296))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (479:479:479) (564:564:564))
        (PORT datab (363:363:363) (441:441:441))
        (PORT datac (307:307:307) (359:359:359))
        (PORT datad (102:102:102) (119:119:119))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[2\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (189:189:189))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[3\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[4\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (911:911:911))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (430:430:430) (463:463:463))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[5\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT datab (154:154:154) (201:201:201))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[6\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (155:155:155) (205:205:205))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[7\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (155:155:155) (204:204:204))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[8\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT datab (154:154:154) (202:202:202))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[9\]\~30)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[10\]\~32)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[11\]\~34)
    (DELAY
      (ABSOLUTE
        (PORT datab (155:155:155) (202:202:202))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[12\]\~36)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (415:415:415) (438:438:438))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[13\]\~38)
    (DELAY
      (ABSOLUTE
        (PORT datab (154:154:154) (202:202:202))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (911:911:911))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (430:430:430) (463:463:463))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1192:1192:1192) (1412:1412:1412))
        (PORT d[1] (1138:1138:1138) (1353:1353:1353))
        (PORT d[2] (1044:1044:1044) (1226:1226:1226))
        (PORT d[3] (1415:1415:1415) (1648:1648:1648))
        (PORT d[4] (1258:1258:1258) (1477:1477:1477))
        (PORT d[5] (1215:1215:1215) (1410:1410:1410))
        (PORT d[6] (1211:1211:1211) (1418:1418:1418))
        (PORT d[7] (1193:1193:1193) (1406:1406:1406))
        (PORT d[8] (1316:1316:1316) (1533:1533:1533))
        (PORT d[9] (1224:1224:1224) (1442:1442:1442))
        (PORT d[10] (1311:1311:1311) (1559:1559:1559))
        (PORT d[11] (1306:1306:1306) (1521:1521:1521))
        (PORT d[12] (1339:1339:1339) (1574:1574:1574))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (1041:1041:1041) (1194:1194:1194))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datac (922:922:922) (1074:1074:1074))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (117:117:117) (154:154:154))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1208:1208:1208) (1437:1437:1437))
        (PORT d[1] (1134:1134:1134) (1341:1341:1341))
        (PORT d[2] (1240:1240:1240) (1449:1449:1449))
        (PORT d[3] (1286:1286:1286) (1506:1506:1506))
        (PORT d[4] (1225:1225:1225) (1436:1436:1436))
        (PORT d[5] (1206:1206:1206) (1396:1396:1396))
        (PORT d[6] (1205:1205:1205) (1409:1409:1409))
        (PORT d[7] (1199:1199:1199) (1418:1418:1418))
        (PORT d[8] (1323:1323:1323) (1536:1536:1536))
        (PORT d[9] (1195:1195:1195) (1406:1406:1406))
        (PORT d[10] (1154:1154:1154) (1375:1375:1375))
        (PORT d[11] (1301:1301:1301) (1516:1516:1516))
        (PORT d[12] (1296:1296:1296) (1520:1520:1520))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (1107:1107:1107) (981:981:981))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (508:508:508) (582:582:582))
        (PORT datab (1432:1432:1432) (1679:1679:1679))
        (PORT datac (506:506:506) (569:569:569))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (190:190:190) (188:188:188))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1186:1186:1186) (1411:1411:1411))
        (PORT d[1] (1084:1084:1084) (1282:1282:1282))
        (PORT d[2] (1165:1165:1165) (1364:1364:1364))
        (PORT d[3] (1260:1260:1260) (1484:1484:1484))
        (PORT d[4] (1245:1245:1245) (1460:1460:1460))
        (PORT d[5] (1046:1046:1046) (1223:1223:1223))
        (PORT d[6] (1046:1046:1046) (1226:1226:1226))
        (PORT d[7] (1254:1254:1254) (1475:1475:1475))
        (PORT d[8] (978:978:978) (1152:1152:1152))
        (PORT d[9] (1262:1262:1262) (1470:1470:1470))
        (PORT d[10] (933:933:933) (1116:1116:1116))
        (PORT d[11] (1320:1320:1320) (1538:1538:1538))
        (PORT d[12] (1122:1122:1122) (1324:1324:1324))
        (PORT clk (1085:1085:1085) (1103:1103:1103))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (PORT d[0] (1103:1103:1103) (977:977:977))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1086:1086:1086) (1104:1104:1104))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1067:1067:1067) (1084:1084:1084))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (617:617:617))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (617:617:617))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1186:1186:1186) (1406:1406:1406))
        (PORT d[1] (1091:1091:1091) (1296:1296:1296))
        (PORT d[2] (1235:1235:1235) (1445:1445:1445))
        (PORT d[3] (1260:1260:1260) (1479:1479:1479))
        (PORT d[4] (1232:1232:1232) (1447:1447:1447))
        (PORT d[5] (905:905:905) (1064:1064:1064))
        (PORT d[6] (1206:1206:1206) (1396:1396:1396))
        (PORT d[7] (1231:1231:1231) (1440:1440:1440))
        (PORT d[8] (1236:1236:1236) (1422:1422:1422))
        (PORT d[9] (1290:1290:1290) (1507:1507:1507))
        (PORT d[10] (947:947:947) (1130:1130:1130))
        (PORT d[11] (1263:1263:1263) (1460:1460:1460))
        (PORT d[12] (1234:1234:1234) (1462:1462:1462))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (PORT d[0] (954:954:954) (1076:1076:1076))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1086:1086:1086))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (534:534:534) (619:619:619))
        (PORT datac (533:533:533) (611:611:611))
        (PORT datad (1552:1552:1552) (1817:1817:1817))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1224:1224:1224) (1454:1454:1454))
        (PORT d[1] (960:960:960) (1146:1146:1146))
        (PORT d[2] (1209:1209:1209) (1416:1416:1416))
        (PORT d[3] (1289:1289:1289) (1514:1514:1514))
        (PORT d[4] (1217:1217:1217) (1426:1426:1426))
        (PORT d[5] (1071:1071:1071) (1255:1255:1255))
        (PORT d[6] (1210:1210:1210) (1397:1397:1397))
        (PORT d[7] (1206:1206:1206) (1421:1421:1421))
        (PORT d[8] (1242:1242:1242) (1425:1425:1425))
        (PORT d[9] (1207:1207:1207) (1418:1418:1418))
        (PORT d[10] (996:996:996) (1198:1198:1198))
        (PORT d[11] (1315:1315:1315) (1532:1532:1532))
        (PORT d[12] (1264:1264:1264) (1499:1499:1499))
        (PORT clk (1084:1084:1084) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1084:1084:1084) (1102:1102:1102))
        (PORT d[0] (1126:1126:1126) (995:995:995))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1066:1066:1066) (1083:1083:1083))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (606:606:606) (615:615:615))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1195:1195:1195) (1416:1416:1416))
        (PORT d[1] (1142:1142:1142) (1357:1357:1357))
        (PORT d[2] (1109:1109:1109) (1305:1305:1305))
        (PORT d[3] (1408:1408:1408) (1641:1641:1641))
        (PORT d[4] (1246:1246:1246) (1474:1474:1474))
        (PORT d[5] (1090:1090:1090) (1274:1274:1274))
        (PORT d[6] (1236:1236:1236) (1449:1449:1449))
        (PORT d[7] (1200:1200:1200) (1414:1414:1414))
        (PORT d[8] (1301:1301:1301) (1516:1516:1516))
        (PORT d[9] (1236:1236:1236) (1458:1458:1458))
        (PORT d[10] (1330:1330:1330) (1577:1577:1577))
        (PORT d[11] (1309:1309:1309) (1524:1524:1524))
        (PORT d[12] (1262:1262:1262) (1482:1482:1482))
        (PORT clk (1099:1099:1099) (1116:1116:1116))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (PORT d[0] (1087:1087:1087) (1240:1240:1240))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1117:1117:1117))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1081:1081:1081) (1097:1097:1097))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (621:621:621) (629:629:629))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (622:622:622) (630:630:630))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (622:622:622) (630:630:630))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (622:622:622) (630:630:630))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (552:552:552) (633:633:633))
        (PORT datac (1367:1367:1367) (1600:1600:1600))
        (PORT datad (187:187:187) (219:219:219))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1011:1011:1011) (1209:1209:1209))
        (PORT d[1] (1109:1109:1109) (1318:1318:1318))
        (PORT d[2] (1220:1220:1220) (1430:1430:1430))
        (PORT d[3] (1258:1258:1258) (1480:1480:1480))
        (PORT d[4] (1197:1197:1197) (1385:1385:1385))
        (PORT d[5] (1081:1081:1081) (1249:1249:1249))
        (PORT d[6] (1051:1051:1051) (1213:1213:1213))
        (PORT d[7] (1051:1051:1051) (1239:1239:1239))
        (PORT d[8] (1061:1061:1061) (1222:1222:1222))
        (PORT d[9] (1099:1099:1099) (1293:1293:1293))
        (PORT d[10] (1003:1003:1003) (1205:1205:1205))
        (PORT d[11] (1063:1063:1063) (1230:1230:1230))
        (PORT d[12] (1143:1143:1143) (1325:1325:1325))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (960:960:960) (1086:1086:1086))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1145:1145:1145) (1355:1355:1355))
        (PORT d[1] (1077:1077:1077) (1274:1274:1274))
        (PORT d[2] (1228:1228:1228) (1438:1438:1438))
        (PORT d[3] (1255:1255:1255) (1474:1474:1474))
        (PORT d[4] (1223:1223:1223) (1423:1423:1423))
        (PORT d[5] (1033:1033:1033) (1207:1207:1207))
        (PORT d[6] (1034:1034:1034) (1202:1202:1202))
        (PORT d[7] (1087:1087:1087) (1283:1283:1283))
        (PORT d[8] (1078:1078:1078) (1241:1241:1241))
        (PORT d[9] (1273:1273:1273) (1486:1486:1486))
        (PORT d[10] (1224:1224:1224) (1455:1455:1455))
        (PORT d[11] (1078:1078:1078) (1244:1244:1244))
        (PORT d[12] (1209:1209:1209) (1443:1443:1443))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (1104:1104:1104) (974:974:974))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (404:404:404) (475:475:475))
        (PORT datac (1090:1090:1090) (1296:1296:1296))
        (PORT datad (187:187:187) (219:219:219))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1249:1249:1249) (1436:1436:1436))
        (PORT clk (1096:1096:1096) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1192:1192:1192) (1416:1416:1416))
        (PORT d[1] (1238:1238:1238) (1442:1442:1442))
        (PORT d[2] (1268:1268:1268) (1483:1483:1483))
        (PORT d[3] (1317:1317:1317) (1536:1536:1536))
        (PORT d[4] (1248:1248:1248) (1464:1464:1464))
        (PORT d[5] (1240:1240:1240) (1440:1440:1440))
        (PORT d[6] (1206:1206:1206) (1406:1406:1406))
        (PORT d[7] (1201:1201:1201) (1420:1420:1420))
        (PORT d[8] (1335:1335:1335) (1556:1556:1556))
        (PORT d[9] (1208:1208:1208) (1422:1422:1422))
        (PORT d[10] (1171:1171:1171) (1400:1400:1400))
        (PORT d[11] (1335:1335:1335) (1558:1558:1558))
        (PORT d[12] (1333:1333:1333) (1563:1563:1563))
        (PORT clk (1094:1094:1094) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1114:1114:1114))
        (PORT d[0] (1246:1246:1246) (1090:1090:1090))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1253:1253:1253) (1440:1440:1440))
        (PORT clk (1097:1097:1097) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1183:1183:1183) (1403:1403:1403))
        (PORT d[1] (1259:1259:1259) (1469:1469:1469))
        (PORT d[2] (1220:1220:1220) (1431:1431:1431))
        (PORT d[3] (1318:1318:1318) (1536:1536:1536))
        (PORT d[4] (1258:1258:1258) (1476:1476:1476))
        (PORT d[5] (1241:1241:1241) (1440:1440:1440))
        (PORT d[6] (1207:1207:1207) (1406:1406:1406))
        (PORT d[7] (1202:1202:1202) (1420:1420:1420))
        (PORT d[8] (1336:1336:1336) (1556:1556:1556))
        (PORT d[9] (1209:1209:1209) (1422:1422:1422))
        (PORT d[10] (1172:1172:1172) (1400:1400:1400))
        (PORT d[11] (1336:1336:1336) (1558:1558:1558))
        (PORT d[12] (1334:1334:1334) (1563:1563:1563))
        (PORT clk (1096:1096:1096) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (PORT d[0] (1246:1246:1246) (1090:1090:1090))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1776:1776:1776) (2025:2025:2025))
        (PORT clk (1099:1099:1099) (1117:1117:1117))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1104:1104:1104) (1288:1288:1288))
        (PORT d[1] (1300:1300:1300) (1538:1538:1538))
        (PORT d[2] (1113:1113:1113) (1299:1299:1299))
        (PORT d[3] (1008:1008:1008) (1183:1183:1183))
        (PORT d[4] (1254:1254:1254) (1467:1467:1467))
        (PORT d[5] (912:912:912) (1074:1074:1074))
        (PORT d[6] (1026:1026:1026) (1213:1213:1213))
        (PORT d[7] (1011:1011:1011) (1192:1192:1192))
        (PORT d[8] (1099:1099:1099) (1292:1292:1292))
        (PORT d[9] (995:995:995) (1159:1159:1159))
        (PORT d[10] (975:975:975) (1149:1149:1149))
        (PORT d[11] (1135:1135:1135) (1317:1317:1317))
        (PORT d[12] (1192:1192:1192) (1396:1396:1396))
        (PORT clk (1097:1097:1097) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1117:1117:1117))
        (PORT d[0] (739:739:739) (832:832:832))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1118:1118:1118))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1118:1118:1118))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1118:1118:1118))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1118:1118:1118))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1079:1079:1079) (1096:1096:1096))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1780:1780:1780) (2029:2029:2029))
        (PORT clk (1100:1100:1100) (1118:1118:1118))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1111:1111:1111) (1289:1289:1289))
        (PORT d[1] (1301:1301:1301) (1538:1538:1538))
        (PORT d[2] (1093:1093:1093) (1271:1271:1271))
        (PORT d[3] (1009:1009:1009) (1183:1183:1183))
        (PORT d[4] (1272:1272:1272) (1498:1498:1498))
        (PORT d[5] (913:913:913) (1074:1074:1074))
        (PORT d[6] (1027:1027:1027) (1213:1213:1213))
        (PORT d[7] (1012:1012:1012) (1192:1192:1192))
        (PORT d[8] (1100:1100:1100) (1292:1292:1292))
        (PORT d[9] (996:996:996) (1159:1159:1159))
        (PORT d[10] (976:976:976) (1149:1149:1149))
        (PORT d[11] (1136:1136:1136) (1317:1317:1317))
        (PORT d[12] (1193:1193:1193) (1396:1396:1396))
        (PORT clk (1099:1099:1099) (1117:1117:1117))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1100:1100:1100) (1118:1118:1118))
        (PORT d[0] (739:739:739) (832:832:832))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1101:1101:1101) (1119:1119:1119))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1101:1101:1101) (1119:1119:1119))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1101:1101:1101) (1119:1119:1119))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1101:1101:1101) (1119:1119:1119))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1080:1080:1080) (1097:1097:1097))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1532:1532:1532) (1797:1797:1797))
        (PORT datac (350:350:350) (394:394:394))
        (PORT datad (597:597:597) (684:684:684))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1757:1757:1757) (2009:2009:2009))
        (PORT clk (1102:1102:1102) (1119:1119:1119))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (946:946:946) (1114:1114:1114))
        (PORT d[1] (1098:1098:1098) (1285:1285:1285))
        (PORT d[2] (1113:1113:1113) (1299:1299:1299))
        (PORT d[3] (1011:1011:1011) (1190:1190:1190))
        (PORT d[4] (1146:1146:1146) (1339:1339:1339))
        (PORT d[5] (1091:1091:1091) (1279:1279:1279))
        (PORT d[6] (1109:1109:1109) (1300:1300:1300))
        (PORT d[7] (1182:1182:1182) (1383:1383:1383))
        (PORT d[8] (1113:1113:1113) (1312:1312:1312))
        (PORT d[9] (1176:1176:1176) (1375:1375:1375))
        (PORT d[10] (1007:1007:1007) (1189:1189:1189))
        (PORT d[11] (1125:1125:1125) (1298:1298:1298))
        (PORT d[12] (1173:1173:1173) (1378:1378:1378))
        (PORT clk (1100:1100:1100) (1117:1117:1117))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1119:1119:1119))
        (PORT d[0] (990:990:990) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1082:1082:1082) (1098:1098:1098))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1761:1761:1761) (2013:2013:2013))
        (PORT clk (1103:1103:1103) (1120:1120:1120))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (952:952:952) (1112:1112:1112))
        (PORT d[1] (1111:1111:1111) (1297:1297:1297))
        (PORT d[2] (1094:1094:1094) (1272:1272:1272))
        (PORT d[3] (1012:1012:1012) (1190:1190:1190))
        (PORT d[4] (1135:1135:1135) (1323:1323:1323))
        (PORT d[5] (1092:1092:1092) (1279:1279:1279))
        (PORT d[6] (1110:1110:1110) (1300:1300:1300))
        (PORT d[7] (1183:1183:1183) (1383:1383:1383))
        (PORT d[8] (1114:1114:1114) (1312:1312:1312))
        (PORT d[9] (1177:1177:1177) (1375:1375:1375))
        (PORT d[10] (1008:1008:1008) (1189:1189:1189))
        (PORT d[11] (1126:1126:1126) (1298:1298:1298))
        (PORT d[12] (1174:1174:1174) (1378:1378:1378))
        (PORT clk (1102:1102:1102) (1119:1119:1119))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1120:1120:1120))
        (PORT d[0] (990:990:990) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1099:1099:1099))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1780:1780:1780) (2036:2036:2036))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (955:955:955) (1126:1126:1126))
        (PORT d[1] (1112:1112:1112) (1301:1301:1301))
        (PORT d[2] (937:937:937) (1088:1088:1088))
        (PORT d[3] (987:987:987) (1160:1160:1160))
        (PORT d[4] (1114:1114:1114) (1320:1320:1320))
        (PORT d[5] (898:898:898) (1053:1053:1053))
        (PORT d[6] (1179:1179:1179) (1379:1379:1379))
        (PORT d[7] (1007:1007:1007) (1188:1188:1188))
        (PORT d[8] (1092:1092:1092) (1283:1283:1283))
        (PORT d[9] (1174:1174:1174) (1370:1370:1370))
        (PORT d[10] (1273:1273:1273) (1534:1534:1534))
        (PORT d[11] (1140:1140:1140) (1314:1314:1314))
        (PORT d[12] (1184:1184:1184) (1386:1386:1386))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (739:739:739) (832:832:832))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1784:1784:1784) (2040:2040:2040))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (946:946:946) (1112:1112:1112))
        (PORT d[1] (1112:1112:1112) (1301:1301:1301))
        (PORT d[2] (945:945:945) (1106:1106:1106))
        (PORT d[3] (988:988:988) (1160:1160:1160))
        (PORT d[4] (1117:1117:1117) (1315:1315:1315))
        (PORT d[5] (899:899:899) (1053:1053:1053))
        (PORT d[6] (1180:1180:1180) (1379:1379:1379))
        (PORT d[7] (1008:1008:1008) (1188:1188:1188))
        (PORT d[8] (1093:1093:1093) (1283:1283:1283))
        (PORT d[9] (1175:1175:1175) (1370:1370:1370))
        (PORT d[10] (1274:1274:1274) (1534:1534:1534))
        (PORT d[11] (1141:1141:1141) (1314:1314:1314))
        (PORT d[12] (1185:1185:1185) (1386:1386:1386))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (739:739:739) (832:832:832))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (147:147:147) (198:198:198))
        (PORT datac (371:371:371) (434:434:434))
        (PORT datad (187:187:187) (219:219:219))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (515:515:515) (593:593:593))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (921:921:921) (1072:1072:1072))
        (PORT d[1] (940:940:940) (1111:1111:1111))
        (PORT d[2] (912:912:912) (1062:1062:1062))
        (PORT d[3] (969:969:969) (1130:1130:1130))
        (PORT d[4] (969:969:969) (1139:1139:1139))
        (PORT d[5] (851:851:851) (998:998:998))
        (PORT d[6] (944:944:944) (1091:1091:1091))
        (PORT d[7] (1103:1103:1103) (1276:1276:1276))
        (PORT d[8] (982:982:982) (1139:1139:1139))
        (PORT d[9] (1010:1010:1010) (1175:1175:1175))
        (PORT d[10] (830:830:830) (996:996:996))
        (PORT d[11] (1080:1080:1080) (1241:1241:1241))
        (PORT d[12] (1001:1001:1001) (1178:1178:1178))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (796:796:796) (707:707:707))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (519:519:519) (597:597:597))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (933:933:933) (1086:1086:1086))
        (PORT d[1] (934:934:934) (1096:1096:1096))
        (PORT d[2] (923:923:923) (1065:1065:1065))
        (PORT d[3] (970:970:970) (1130:1130:1130))
        (PORT d[4] (969:969:969) (1138:1138:1138))
        (PORT d[5] (852:852:852) (998:998:998))
        (PORT d[6] (945:945:945) (1091:1091:1091))
        (PORT d[7] (1104:1104:1104) (1276:1276:1276))
        (PORT d[8] (983:983:983) (1139:1139:1139))
        (PORT d[9] (1011:1011:1011) (1175:1175:1175))
        (PORT d[10] (831:831:831) (996:996:996))
        (PORT d[11] (1081:1081:1081) (1241:1241:1241))
        (PORT d[12] (1002:1002:1002) (1178:1178:1178))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (796:796:796) (707:707:707))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (507:507:507) (583:583:583))
        (PORT clk (1096:1096:1096) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1100:1100:1100) (1288:1288:1288))
        (PORT d[1] (949:949:949) (1121:1121:1121))
        (PORT d[2] (1081:1081:1081) (1253:1253:1253))
        (PORT d[3] (967:967:967) (1129:1129:1129))
        (PORT d[4] (978:978:978) (1150:1150:1150))
        (PORT d[5] (856:856:856) (1003:1003:1003))
        (PORT d[6] (1068:1068:1068) (1239:1239:1239))
        (PORT d[7] (964:964:964) (1133:1133:1133))
        (PORT d[8] (1005:1005:1005) (1171:1171:1171))
        (PORT d[9] (1008:1008:1008) (1169:1169:1169))
        (PORT d[10] (1001:1001:1001) (1185:1185:1185))
        (PORT d[11] (1075:1075:1075) (1233:1233:1233))
        (PORT d[12] (1001:1001:1001) (1187:1187:1187))
        (PORT clk (1094:1094:1094) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1114:1114:1114))
        (PORT d[0] (699:699:699) (786:786:786))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (511:511:511) (587:587:587))
        (PORT clk (1097:1097:1097) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1101:1101:1101) (1288:1288:1288))
        (PORT d[1] (940:940:940) (1108:1108:1108))
        (PORT d[2] (931:931:931) (1074:1074:1074))
        (PORT d[3] (968:968:968) (1129:1129:1129))
        (PORT d[4] (973:973:973) (1133:1133:1133))
        (PORT d[5] (857:857:857) (1003:1003:1003))
        (PORT d[6] (1069:1069:1069) (1239:1239:1239))
        (PORT d[7] (965:965:965) (1133:1133:1133))
        (PORT d[8] (1006:1006:1006) (1171:1171:1171))
        (PORT d[9] (1009:1009:1009) (1169:1169:1169))
        (PORT d[10] (1002:1002:1002) (1185:1185:1185))
        (PORT d[11] (1076:1076:1076) (1233:1233:1233))
        (PORT d[12] (1002:1002:1002) (1187:1187:1187))
        (PORT clk (1096:1096:1096) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (PORT d[0] (699:699:699) (786:786:786))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (561:561:561) (650:650:650))
        (PORT datac (404:404:404) (493:493:493))
        (PORT datad (545:545:545) (630:630:630))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1943:1943:1943) (2218:2218:2218))
        (PORT clk (1091:1091:1091) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (948:948:948) (1115:1115:1115))
        (PORT d[1] (1092:1092:1092) (1278:1278:1278))
        (PORT d[2] (927:927:927) (1085:1085:1085))
        (PORT d[3] (968:968:968) (1135:1135:1135))
        (PORT d[4] (1145:1145:1145) (1338:1338:1338))
        (PORT d[5] (864:864:864) (1020:1020:1020))
        (PORT d[6] (1209:1209:1209) (1415:1415:1415))
        (PORT d[7] (1143:1143:1143) (1337:1337:1337))
        (PORT d[8] (1174:1174:1174) (1360:1360:1360))
        (PORT d[9] (1186:1186:1186) (1389:1389:1389))
        (PORT d[10] (1132:1132:1132) (1327:1327:1327))
        (PORT d[11] (969:969:969) (1134:1134:1134))
        (PORT d[12] (1029:1029:1029) (1213:1213:1213))
        (PORT clk (1089:1089:1089) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (PORT d[0] (792:792:792) (702:702:702))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1088:1088:1088))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1947:1947:1947) (2222:2222:2222))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (953:953:953) (1112:1112:1112))
        (PORT d[1] (1083:1083:1083) (1264:1264:1264))
        (PORT d[2] (947:947:947) (1110:1110:1110))
        (PORT d[3] (969:969:969) (1135:1135:1135))
        (PORT d[4] (1140:1140:1140) (1323:1323:1323))
        (PORT d[5] (865:865:865) (1020:1020:1020))
        (PORT d[6] (1210:1210:1210) (1415:1415:1415))
        (PORT d[7] (1144:1144:1144) (1337:1337:1337))
        (PORT d[8] (1175:1175:1175) (1360:1360:1360))
        (PORT d[9] (1187:1187:1187) (1389:1389:1389))
        (PORT d[10] (1133:1133:1133) (1327:1327:1327))
        (PORT d[11] (970:970:970) (1134:1134:1134))
        (PORT d[12] (1030:1030:1030) (1213:1213:1213))
        (PORT clk (1091:1091:1091) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (792:792:792) (702:702:702))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1931:1931:1931) (2203:2203:2203))
        (PORT clk (1089:1089:1089) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1082:1082:1082) (1265:1265:1265))
        (PORT d[1] (1084:1084:1084) (1267:1267:1267))
        (PORT d[2] (946:946:946) (1109:1109:1109))
        (PORT d[3] (984:984:984) (1156:1156:1156))
        (PORT d[4] (1149:1149:1149) (1345:1345:1345))
        (PORT d[5] (879:879:879) (1033:1033:1033))
        (PORT d[6] (1211:1211:1211) (1419:1419:1419))
        (PORT d[7] (994:994:994) (1168:1168:1168))
        (PORT d[8] (910:910:910) (1074:1074:1074))
        (PORT d[9] (1181:1181:1181) (1382:1382:1382))
        (PORT d[10] (998:998:998) (1180:1180:1180))
        (PORT d[11] (1143:1143:1143) (1314:1314:1314))
        (PORT d[12] (1180:1180:1180) (1382:1382:1382))
        (PORT clk (1087:1087:1087) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1107:1107:1107))
        (PORT d[0] (729:729:729) (824:824:824))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1069:1069:1069) (1086:1086:1086))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1935:1935:1935) (2207:2207:2207))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1100:1100:1100) (1289:1289:1289))
        (PORT d[1] (1101:1101:1101) (1292:1292:1292))
        (PORT d[2] (947:947:947) (1109:1109:1109))
        (PORT d[3] (985:985:985) (1156:1156:1156))
        (PORT d[4] (1150:1150:1150) (1345:1345:1345))
        (PORT d[5] (880:880:880) (1033:1033:1033))
        (PORT d[6] (1212:1212:1212) (1419:1419:1419))
        (PORT d[7] (995:995:995) (1168:1168:1168))
        (PORT d[8] (911:911:911) (1074:1074:1074))
        (PORT d[9] (1182:1182:1182) (1382:1382:1382))
        (PORT d[10] (999:999:999) (1180:1180:1180))
        (PORT d[11] (1144:1144:1144) (1314:1314:1314))
        (PORT d[12] (1181:1181:1181) (1382:1382:1382))
        (PORT clk (1089:1089:1089) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (729:729:729) (824:824:824))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (420:420:420) (513:513:513))
        (PORT datac (363:363:363) (428:428:428))
        (PORT datad (188:188:188) (220:220:220))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1026:1026:1026) (1230:1230:1230))
        (PORT d[1] (1066:1066:1066) (1262:1262:1262))
        (PORT d[2] (1194:1194:1194) (1394:1394:1394))
        (PORT d[3] (1244:1244:1244) (1457:1457:1457))
        (PORT d[4] (1231:1231:1231) (1430:1430:1430))
        (PORT d[5] (1064:1064:1064) (1247:1247:1247))
        (PORT d[6] (1019:1019:1019) (1175:1175:1175))
        (PORT d[7] (1076:1076:1076) (1269:1269:1269))
        (PORT d[8] (1083:1083:1083) (1251:1251:1251))
        (PORT d[9] (1100:1100:1100) (1289:1289:1289))
        (PORT d[10] (1006:1006:1006) (1204:1204:1204))
        (PORT d[11] (1070:1070:1070) (1234:1234:1234))
        (PORT d[12] (1266:1266:1266) (1505:1505:1505))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (1090:1090:1090) (964:964:964))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1218:1218:1218) (1448:1448:1448))
        (PORT d[1] (1092:1092:1092) (1290:1290:1290))
        (PORT d[2] (1231:1231:1231) (1441:1441:1441))
        (PORT d[3] (1282:1282:1282) (1504:1504:1504))
        (PORT d[4] (1249:1249:1249) (1465:1465:1465))
        (PORT d[5] (1088:1088:1088) (1277:1277:1277))
        (PORT d[6] (1180:1180:1180) (1378:1378:1378))
        (PORT d[7] (1198:1198:1198) (1413:1413:1413))
        (PORT d[8] (1151:1151:1151) (1346:1346:1346))
        (PORT d[9] (1219:1219:1219) (1437:1437:1437))
        (PORT d[10] (1144:1144:1144) (1363:1363:1363))
        (PORT d[11] (1299:1299:1299) (1510:1510:1510))
        (PORT d[12] (1149:1149:1149) (1360:1360:1360))
        (PORT clk (1086:1086:1086) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1086:1086:1086) (1104:1104:1104))
        (PORT d[0] (975:975:975) (1100:1100:1100))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1068:1068:1068) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (646:646:646) (750:750:750))
        (PORT datac (1426:1426:1426) (1680:1680:1680))
        (PORT datad (186:186:186) (218:218:218))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1193:1193:1193) (1414:1414:1414))
        (PORT d[1] (1111:1111:1111) (1316:1316:1316))
        (PORT d[2] (1192:1192:1192) (1395:1395:1395))
        (PORT d[3] (1250:1250:1250) (1457:1457:1457))
        (PORT d[4] (1233:1233:1233) (1447:1447:1447))
        (PORT d[5] (1075:1075:1075) (1257:1257:1257))
        (PORT d[6] (1216:1216:1216) (1416:1416:1416))
        (PORT d[7] (1216:1216:1216) (1434:1434:1434))
        (PORT d[8] (1007:1007:1007) (1188:1188:1188))
        (PORT d[9] (1225:1225:1225) (1442:1442:1442))
        (PORT d[10] (990:990:990) (1192:1192:1192))
        (PORT d[11] (1304:1304:1304) (1520:1520:1520))
        (PORT d[12] (1145:1145:1145) (1354:1354:1354))
        (PORT clk (1081:1081:1081) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1081:1081:1081) (1100:1100:1100))
        (PORT d[0] (964:964:964) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1082:1082:1082) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1063:1063:1063) (1081:1081:1081))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (603:603:603) (613:613:613))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (604:604:604) (614:614:614))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (604:604:604) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (604:604:604) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1198:1198:1198) (1423:1423:1423))
        (PORT d[1] (981:981:981) (1164:1164:1164))
        (PORT d[2] (1247:1247:1247) (1461:1461:1461))
        (PORT d[3] (1261:1261:1261) (1481:1481:1481))
        (PORT d[4] (1234:1234:1234) (1447:1447:1447))
        (PORT d[5] (913:913:913) (1074:1074:1074))
        (PORT d[6] (1204:1204:1204) (1391:1391:1391))
        (PORT d[7] (1103:1103:1103) (1308:1308:1308))
        (PORT d[8] (994:994:994) (1172:1172:1172))
        (PORT d[9] (1281:1281:1281) (1494:1494:1494))
        (PORT d[10] (979:979:979) (1178:1178:1178))
        (PORT d[11] (1258:1258:1258) (1452:1452:1452))
        (PORT d[12] (1245:1245:1245) (1474:1474:1474))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (PORT d[0] (1089:1089:1089) (965:965:965))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1069:1069:1069) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (446:446:446))
        (PORT datac (533:533:533) (610:610:610))
        (PORT datad (1535:1535:1535) (1793:1793:1793))
        (IOPATH dataa combout (166:166:166) (163:163:163))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1123:1123:1123) (1330:1330:1330))
        (PORT d[1] (930:930:930) (1089:1089:1089))
        (PORT d[2] (1069:1069:1069) (1239:1239:1239))
        (PORT d[3] (1064:1064:1064) (1247:1247:1247))
        (PORT d[4] (1036:1036:1036) (1204:1204:1204))
        (PORT d[5] (941:941:941) (1099:1099:1099))
        (PORT d[6] (1067:1067:1067) (1238:1238:1238))
        (PORT d[7] (893:893:893) (1045:1045:1045))
        (PORT d[8] (899:899:899) (1041:1041:1041))
        (PORT d[9] (886:886:886) (1039:1039:1039))
        (PORT d[10] (1008:1008:1008) (1210:1210:1210))
        (PORT d[11] (912:912:912) (1055:1055:1055))
        (PORT d[12] (995:995:995) (1161:1161:1161))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (PORT d[0] (1064:1064:1064) (941:941:941))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1088:1088:1088))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (975:975:975) (1160:1160:1160))
        (PORT d[1] (924:924:924) (1082:1082:1082))
        (PORT d[2] (1030:1030:1030) (1201:1201:1201))
        (PORT d[3] (1006:1006:1006) (1164:1164:1164))
        (PORT d[4] (1020:1020:1020) (1188:1188:1188))
        (PORT d[5] (910:910:910) (1057:1057:1057))
        (PORT d[6] (869:869:869) (1008:1008:1008))
        (PORT d[7] (857:857:857) (1010:1010:1010))
        (PORT d[8] (876:876:876) (1014:1014:1014))
        (PORT d[9] (862:862:862) (1009:1009:1009))
        (PORT d[10] (1027:1027:1027) (1232:1232:1232))
        (PORT d[11] (879:879:879) (1020:1020:1020))
        (PORT d[12] (977:977:977) (1140:1140:1140))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (PORT d[0] (925:925:925) (1027:1027:1027))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1086:1086:1086))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (403:403:403) (473:473:473))
        (PORT datac (1064:1064:1064) (1265:1265:1265))
        (PORT datad (544:544:544) (627:627:627))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1178:1178:1178) (1398:1398:1398))
        (PORT d[1] (1102:1102:1102) (1303:1303:1303))
        (PORT d[2] (1262:1262:1262) (1476:1476:1476))
        (PORT d[3] (1293:1293:1293) (1514:1514:1514))
        (PORT d[4] (1256:1256:1256) (1472:1472:1472))
        (PORT d[5] (1236:1236:1236) (1438:1438:1438))
        (PORT d[6] (1211:1211:1211) (1416:1416:1416))
        (PORT d[7] (1213:1213:1213) (1429:1429:1429))
        (PORT d[8] (1322:1322:1322) (1535:1535:1535))
        (PORT d[9] (1057:1057:1057) (1251:1251:1251))
        (PORT d[10] (1166:1166:1166) (1397:1397:1397))
        (PORT d[11] (1309:1309:1309) (1522:1522:1522))
        (PORT d[12] (1321:1321:1321) (1552:1552:1552))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (1123:1123:1123) (993:993:993))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1074:1074:1074) (1091:1091:1091))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (614:614:614) (623:623:623))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (624:624:624))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (624:624:624))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (624:624:624))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1182:1182:1182) (1401:1401:1401))
        (PORT d[1] (1255:1255:1255) (1465:1465:1465))
        (PORT d[2] (1303:1303:1303) (1532:1532:1532))
        (PORT d[3] (1282:1282:1282) (1501:1501:1501))
        (PORT d[4] (1259:1259:1259) (1469:1469:1469))
        (PORT d[5] (1203:1203:1203) (1397:1397:1397))
        (PORT d[6] (1106:1106:1106) (1302:1302:1302))
        (PORT d[7] (1199:1199:1199) (1413:1413:1413))
        (PORT d[8] (1140:1140:1140) (1333:1333:1333))
        (PORT d[9] (1222:1222:1222) (1437:1437:1437))
        (PORT d[10] (1157:1157:1157) (1370:1370:1370))
        (PORT d[11] (1327:1327:1327) (1548:1548:1548))
        (PORT d[12] (1273:1273:1273) (1497:1497:1497))
        (PORT clk (1097:1097:1097) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1115:1115:1115))
        (PORT d[0] (1089:1089:1089) (1245:1245:1245))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1079:1079:1079) (1096:1096:1096))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (628:628:628))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (620:620:620) (629:629:629))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (620:620:620) (629:629:629))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (620:620:620) (629:629:629))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT datab (1561:1561:1561) (1837:1837:1837))
        (PORT datac (295:295:295) (334:334:334))
        (PORT datad (360:360:360) (415:415:415))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1960:1960:1960) (2239:2239:2239))
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1124:1124:1124) (1309:1309:1309))
        (PORT d[1] (965:965:965) (1143:1143:1143))
        (PORT d[2] (972:972:972) (1130:1130:1130))
        (PORT d[3] (995:995:995) (1161:1161:1161))
        (PORT d[4] (1145:1145:1145) (1338:1338:1338))
        (PORT d[5] (844:844:844) (987:987:987))
        (PORT d[6] (983:983:983) (1155:1155:1155))
        (PORT d[7] (1282:1282:1282) (1481:1481:1481))
        (PORT d[8] (1161:1161:1161) (1341:1341:1341))
        (PORT d[9] (996:996:996) (1159:1159:1159))
        (PORT d[10] (829:829:829) (993:993:993))
        (PORT d[11] (1245:1245:1245) (1427:1427:1427))
        (PORT d[12] (1004:1004:1004) (1179:1179:1179))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (PORT d[0] (806:806:806) (718:718:718))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1073:1073:1073) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1964:1964:1964) (2243:2243:2243))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1130:1130:1130) (1325:1325:1325))
        (PORT d[1] (956:956:956) (1129:1129:1129))
        (PORT d[2] (983:983:983) (1142:1142:1142))
        (PORT d[3] (996:996:996) (1161:1161:1161))
        (PORT d[4] (1139:1139:1139) (1323:1323:1323))
        (PORT d[5] (845:845:845) (987:987:987))
        (PORT d[6] (984:984:984) (1155:1155:1155))
        (PORT d[7] (1283:1283:1283) (1481:1481:1481))
        (PORT d[8] (1162:1162:1162) (1341:1341:1341))
        (PORT d[9] (997:997:997) (1159:1159:1159))
        (PORT d[10] (830:830:830) (993:993:993))
        (PORT d[11] (1246:1246:1246) (1427:1427:1427))
        (PORT d[12] (1005:1005:1005) (1179:1179:1179))
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (PORT d[0] (806:806:806) (718:718:718))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1074:1074:1074) (1090:1090:1090))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1961:1961:1961) (2240:2240:2240))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1083:1083:1083) (1266:1266:1266))
        (PORT d[1] (1098:1098:1098) (1290:1290:1290))
        (PORT d[2] (1095:1095:1095) (1268:1268:1268))
        (PORT d[3] (1021:1021:1021) (1203:1203:1203))
        (PORT d[4] (1136:1136:1136) (1329:1329:1329))
        (PORT d[5] (854:854:854) (1000:1000:1000))
        (PORT d[6] (1166:1166:1166) (1365:1365:1365))
        (PORT d[7] (997:997:997) (1177:1177:1177))
        (PORT d[8] (915:915:915) (1080:1080:1080))
        (PORT d[9] (1172:1172:1172) (1367:1367:1367))
        (PORT d[10] (1138:1138:1138) (1333:1333:1333))
        (PORT d[11] (1258:1258:1258) (1444:1444:1444))
        (PORT d[12] (1009:1009:1009) (1188:1188:1188))
        (PORT clk (1093:1093:1093) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (PORT d[0] (717:717:717) (806:806:806))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1075:1075:1075) (1091:1091:1091))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1965:1965:1965) (2244:2244:2244))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1105:1105:1105) (1295:1295:1295))
        (PORT d[1] (1105:1105:1105) (1291:1291:1291))
        (PORT d[2] (1117:1117:1117) (1290:1290:1290))
        (PORT d[3] (1022:1022:1022) (1203:1203:1203))
        (PORT d[4] (1137:1137:1137) (1328:1328:1328))
        (PORT d[5] (855:855:855) (1000:1000:1000))
        (PORT d[6] (1167:1167:1167) (1365:1365:1365))
        (PORT d[7] (998:998:998) (1177:1177:1177))
        (PORT d[8] (916:916:916) (1080:1080:1080))
        (PORT d[9] (1173:1173:1173) (1367:1367:1367))
        (PORT d[10] (1139:1139:1139) (1333:1333:1333))
        (PORT d[11] (1259:1259:1259) (1444:1444:1444))
        (PORT d[12] (1010:1010:1010) (1188:1188:1188))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (717:717:717) (806:806:806))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1092:1092:1092))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (146:146:146) (196:196:196))
        (PORT datac (367:367:367) (429:429:429))
        (PORT datad (540:540:540) (622:622:622))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1553:1553:1553) (1772:1772:1772))
        (PORT clk (1105:1105:1105) (1123:1123:1123))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1121:1121:1121) (1309:1309:1309))
        (PORT d[1] (1119:1119:1119) (1307:1307:1307))
        (PORT d[2] (1115:1115:1115) (1298:1298:1298))
        (PORT d[3] (1010:1010:1010) (1184:1184:1184))
        (PORT d[4] (1245:1245:1245) (1459:1459:1459))
        (PORT d[5] (1075:1075:1075) (1254:1254:1254))
        (PORT d[6] (1179:1179:1179) (1380:1380:1380))
        (PORT d[7] (1183:1183:1183) (1388:1388:1388))
        (PORT d[8] (1071:1071:1071) (1255:1255:1255))
        (PORT d[9] (1181:1181:1181) (1377:1377:1377))
        (PORT d[10] (1284:1284:1284) (1529:1529:1529))
        (PORT d[11] (1157:1157:1157) (1333:1333:1333))
        (PORT d[12] (1190:1190:1190) (1396:1396:1396))
        (PORT clk (1103:1103:1103) (1121:1121:1121))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1123:1123:1123))
        (PORT d[0] (864:864:864) (974:974:974))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1102:1102:1102))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1557:1557:1557) (1776:1776:1776))
        (PORT clk (1106:1106:1106) (1124:1124:1124))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1121:1121:1121) (1307:1307:1307))
        (PORT d[1] (1131:1131:1131) (1323:1323:1323))
        (PORT d[2] (1116:1116:1116) (1298:1298:1298))
        (PORT d[3] (1011:1011:1011) (1184:1184:1184))
        (PORT d[4] (1267:1267:1267) (1486:1486:1486))
        (PORT d[5] (1076:1076:1076) (1254:1254:1254))
        (PORT d[6] (1180:1180:1180) (1380:1380:1380))
        (PORT d[7] (1184:1184:1184) (1388:1388:1388))
        (PORT d[8] (1072:1072:1072) (1255:1255:1255))
        (PORT d[9] (1182:1182:1182) (1377:1377:1377))
        (PORT d[10] (1285:1285:1285) (1529:1529:1529))
        (PORT d[11] (1158:1158:1158) (1333:1333:1333))
        (PORT d[12] (1191:1191:1191) (1396:1396:1396))
        (PORT clk (1105:1105:1105) (1123:1123:1123))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (PORT d[0] (864:864:864) (974:974:974))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1086:1086:1086) (1103:1103:1103))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1543:1543:1543) (1761:1761:1761))
        (PORT clk (1106:1106:1106) (1124:1124:1124))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1106:1106:1106) (1283:1283:1283))
        (PORT d[1] (1132:1132:1132) (1325:1325:1325))
        (PORT d[2] (1120:1120:1120) (1296:1296:1296))
        (PORT d[3] (1022:1022:1022) (1200:1200:1200))
        (PORT d[4] (1244:1244:1244) (1461:1461:1461))
        (PORT d[5] (1005:1005:1005) (1167:1167:1167))
        (PORT d[6] (1155:1155:1155) (1348:1348:1348))
        (PORT d[7] (1187:1187:1187) (1391:1391:1391))
        (PORT d[8] (1288:1288:1288) (1509:1509:1509))
        (PORT d[9] (1195:1195:1195) (1396:1396:1396))
        (PORT d[10] (957:957:957) (1125:1125:1125))
        (PORT d[11] (1147:1147:1147) (1319:1319:1319))
        (PORT d[12] (1203:1203:1203) (1413:1413:1413))
        (PORT clk (1104:1104:1104) (1122:1122:1122))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1124:1124:1124))
        (PORT d[0] (973:973:973) (865:865:865))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1086:1086:1086) (1103:1103:1103))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1547:1547:1547) (1765:1765:1765))
        (PORT clk (1107:1107:1107) (1125:1125:1125))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1114:1114:1114) (1299:1299:1299))
        (PORT d[1] (1122:1122:1122) (1309:1309:1309))
        (PORT d[2] (1292:1292:1292) (1484:1484:1484))
        (PORT d[3] (1023:1023:1023) (1200:1200:1200))
        (PORT d[4] (1122:1122:1122) (1325:1325:1325))
        (PORT d[5] (1006:1006:1006) (1167:1167:1167))
        (PORT d[6] (1156:1156:1156) (1348:1348:1348))
        (PORT d[7] (1188:1188:1188) (1391:1391:1391))
        (PORT d[8] (1289:1289:1289) (1509:1509:1509))
        (PORT d[9] (1196:1196:1196) (1396:1396:1396))
        (PORT d[10] (958:958:958) (1125:1125:1125))
        (PORT d[11] (1148:1148:1148) (1319:1319:1319))
        (PORT d[12] (1204:1204:1204) (1413:1413:1413))
        (PORT clk (1106:1106:1106) (1124:1124:1124))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1125:1125:1125))
        (PORT d[0] (973:973:973) (865:865:865))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datab (347:347:347) (396:396:396))
        (PORT datac (551:551:551) (655:655:655))
        (PORT datad (500:500:500) (562:562:562))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1185:1185:1185) (1367:1367:1367))
        (PORT clk (1101:1101:1101) (1119:1119:1119))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1218:1218:1218) (1437:1437:1437))
        (PORT d[1] (1132:1132:1132) (1335:1335:1335))
        (PORT d[2] (1052:1052:1052) (1229:1229:1229))
        (PORT d[3] (1405:1405:1405) (1639:1639:1639))
        (PORT d[4] (1439:1439:1439) (1682:1682:1682))
        (PORT d[5] (1192:1192:1192) (1383:1383:1383))
        (PORT d[6] (1278:1278:1278) (1495:1495:1495))
        (PORT d[7] (1272:1272:1272) (1483:1483:1483))
        (PORT d[8] (1268:1268:1268) (1492:1492:1492))
        (PORT d[9] (1259:1259:1259) (1477:1477:1477))
        (PORT d[10] (1165:1165:1165) (1379:1379:1379))
        (PORT d[11] (1312:1312:1312) (1526:1526:1526))
        (PORT d[12] (1254:1254:1254) (1473:1473:1473))
        (PORT clk (1099:1099:1099) (1117:1117:1117))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1101:1101:1101) (1119:1119:1119))
        (PORT d[0] (1093:1093:1093) (1246:1246:1246))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1120:1120:1120))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1081:1081:1081) (1098:1098:1098))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1189:1189:1189) (1371:1371:1371))
        (PORT clk (1102:1102:1102) (1120:1120:1120))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1214:1214:1214) (1439:1439:1439))
        (PORT d[1] (1143:1143:1143) (1349:1349:1349))
        (PORT d[2] (1050:1050:1050) (1233:1233:1233))
        (PORT d[3] (1406:1406:1406) (1639:1639:1639))
        (PORT d[4] (1325:1325:1325) (1542:1542:1542))
        (PORT d[5] (1193:1193:1193) (1383:1383:1383))
        (PORT d[6] (1279:1279:1279) (1495:1495:1495))
        (PORT d[7] (1273:1273:1273) (1483:1483:1483))
        (PORT d[8] (1269:1269:1269) (1492:1492:1492))
        (PORT d[9] (1260:1260:1260) (1477:1477:1477))
        (PORT d[10] (1166:1166:1166) (1379:1379:1379))
        (PORT d[11] (1313:1313:1313) (1526:1526:1526))
        (PORT d[12] (1255:1255:1255) (1473:1473:1473))
        (PORT clk (1101:1101:1101) (1119:1119:1119))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1102:1102:1102) (1120:1120:1120))
        (PORT d[0] (1093:1093:1093) (1246:1246:1246))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1103:1103:1103) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1082:1082:1082) (1099:1099:1099))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1781:1781:1781) (2037:2037:2037))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (961:961:961) (1132:1132:1132))
        (PORT d[1] (1124:1124:1124) (1320:1320:1320))
        (PORT d[2] (980:980:980) (1145:1145:1145))
        (PORT d[3] (990:990:990) (1162:1162:1162))
        (PORT d[4] (1145:1145:1145) (1337:1337:1337))
        (PORT d[5] (879:879:879) (1030:1030:1030))
        (PORT d[6] (1204:1204:1204) (1411:1411:1411))
        (PORT d[7] (1175:1175:1175) (1379:1379:1379))
        (PORT d[8] (1080:1080:1080) (1259:1259:1259))
        (PORT d[9] (1152:1152:1152) (1345:1345:1345))
        (PORT d[10] (966:966:966) (1140:1140:1140))
        (PORT d[11] (1138:1138:1138) (1308:1308:1308))
        (PORT d[12] (1177:1177:1177) (1376:1376:1376))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (PORT d[0] (839:839:839) (742:742:742))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1074:1074:1074) (1090:1090:1090))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1785:1785:1785) (2041:2041:2041))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (951:951:951) (1118:1118:1118))
        (PORT d[1] (1119:1119:1119) (1303:1303:1303))
        (PORT d[2] (1100:1100:1100) (1282:1282:1282))
        (PORT d[3] (991:991:991) (1162:1162:1162))
        (PORT d[4] (1146:1146:1146) (1337:1337:1337))
        (PORT d[5] (880:880:880) (1030:1030:1030))
        (PORT d[6] (1205:1205:1205) (1411:1411:1411))
        (PORT d[7] (1176:1176:1176) (1379:1379:1379))
        (PORT d[8] (1081:1081:1081) (1259:1259:1259))
        (PORT d[9] (1153:1153:1153) (1345:1345:1345))
        (PORT d[10] (967:967:967) (1140:1140:1140))
        (PORT d[11] (1139:1139:1139) (1308:1308:1308))
        (PORT d[12] (1178:1178:1178) (1376:1376:1376))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (PORT d[0] (839:839:839) (742:742:742))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1075:1075:1075) (1091:1091:1091))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1279:1279:1279) (1512:1512:1512))
        (PORT datac (512:512:512) (580:580:580))
        (PORT datad (714:714:714) (815:815:815))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1613:1613:1613) (1842:1842:1842))
        (PORT clk (1104:1104:1104) (1120:1120:1120))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1091:1091:1091) (1279:1279:1279))
        (PORT d[1] (1128:1128:1128) (1320:1320:1320))
        (PORT d[2] (1120:1120:1120) (1310:1310:1310))
        (PORT d[3] (1014:1014:1014) (1191:1191:1191))
        (PORT d[4] (1114:1114:1114) (1313:1313:1313))
        (PORT d[5] (1085:1085:1085) (1268:1268:1268))
        (PORT d[6] (1179:1179:1179) (1379:1379:1379))
        (PORT d[7] (1124:1124:1124) (1311:1311:1311))
        (PORT d[8] (1271:1271:1271) (1485:1485:1485))
        (PORT d[9] (1175:1175:1175) (1370:1370:1370))
        (PORT d[10] (1296:1296:1296) (1547:1547:1547))
        (PORT d[11] (1282:1282:1282) (1476:1476:1476))
        (PORT d[12] (1184:1184:1184) (1390:1390:1390))
        (PORT clk (1102:1102:1102) (1118:1118:1118))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1120:1120:1120))
        (PORT d[0] (872:872:872) (980:980:980))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1121:1121:1121))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1084:1084:1084) (1099:1099:1099))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1617:1617:1617) (1846:1846:1846))
        (PORT clk (1105:1105:1105) (1121:1121:1121))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1080:1080:1080) (1263:1263:1263))
        (PORT d[1] (1124:1124:1124) (1303:1303:1303))
        (PORT d[2] (1087:1087:1087) (1267:1267:1267))
        (PORT d[3] (1015:1015:1015) (1191:1191:1191))
        (PORT d[4] (1105:1105:1105) (1300:1300:1300))
        (PORT d[5] (1086:1086:1086) (1268:1268:1268))
        (PORT d[6] (1180:1180:1180) (1379:1379:1379))
        (PORT d[7] (1125:1125:1125) (1311:1311:1311))
        (PORT d[8] (1272:1272:1272) (1485:1485:1485))
        (PORT d[9] (1176:1176:1176) (1370:1370:1370))
        (PORT d[10] (1297:1297:1297) (1547:1547:1547))
        (PORT d[11] (1283:1283:1283) (1476:1476:1476))
        (PORT d[12] (1185:1185:1185) (1390:1390:1390))
        (PORT clk (1104:1104:1104) (1120:1120:1120))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1105:1105:1105) (1121:1121:1121))
        (PORT d[0] (872:872:872) (980:980:980))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1122:1122:1122))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1122:1122:1122))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1122:1122:1122))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1106:1106:1106) (1122:1122:1122))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1100:1100:1100))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1284:1284:1284) (1472:1472:1472))
        (PORT clk (1107:1107:1107) (1124:1124:1124))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1110:1110:1110) (1300:1300:1300))
        (PORT d[1] (1122:1122:1122) (1310:1310:1310))
        (PORT d[2] (1078:1078:1078) (1245:1245:1245))
        (PORT d[3] (1164:1164:1164) (1353:1353:1353))
        (PORT d[4] (1277:1277:1277) (1496:1496:1496))
        (PORT d[5] (1022:1022:1022) (1190:1190:1190))
        (PORT d[6] (1163:1163:1163) (1359:1359:1359))
        (PORT d[7] (1175:1175:1175) (1371:1371:1371))
        (PORT d[8] (1057:1057:1057) (1233:1233:1233))
        (PORT d[9] (1176:1176:1176) (1371:1371:1371))
        (PORT d[10] (1326:1326:1326) (1546:1546:1546))
        (PORT d[11] (1123:1123:1123) (1309:1309:1309))
        (PORT d[12] (1196:1196:1196) (1401:1401:1401))
        (PORT clk (1105:1105:1105) (1122:1122:1122))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1107:1107:1107) (1124:1124:1124))
        (PORT d[0] (990:990:990) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1125:1125:1125))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1103:1103:1103))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1288:1288:1288) (1476:1476:1476))
        (PORT clk (1108:1108:1108) (1125:1125:1125))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1101:1101:1101) (1286:1286:1286))
        (PORT d[1] (1123:1123:1123) (1310:1310:1310))
        (PORT d[2] (1085:1085:1085) (1261:1261:1261))
        (PORT d[3] (1165:1165:1165) (1353:1353:1353))
        (PORT d[4] (1288:1288:1288) (1510:1510:1510))
        (PORT d[5] (1023:1023:1023) (1190:1190:1190))
        (PORT d[6] (1164:1164:1164) (1359:1359:1359))
        (PORT d[7] (1176:1176:1176) (1371:1371:1371))
        (PORT d[8] (1058:1058:1058) (1233:1233:1233))
        (PORT d[9] (1177:1177:1177) (1371:1371:1371))
        (PORT d[10] (1327:1327:1327) (1546:1546:1546))
        (PORT d[11] (1124:1124:1124) (1309:1309:1309))
        (PORT d[12] (1197:1197:1197) (1401:1401:1401))
        (PORT clk (1107:1107:1107) (1124:1124:1124))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1108:1108:1108) (1125:1125:1125))
        (PORT d[0] (990:990:990) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1109:1109:1109) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1109:1109:1109) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1109:1109:1109) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1109:1109:1109) (1126:1126:1126))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1104:1104:1104))
        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (314:314:314) (361:361:361))
        (PORT datac (474:474:474) (563:563:563))
        (PORT datad (364:364:364) (420:420:420))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[14\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT dataa (155:155:155) (205:205:205))
        (IOPATH dataa combout (195:195:195) (203:203:203))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (911:911:911))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (430:430:430) (463:463:463))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (324:324:324) (385:385:385))
        (PORT datad (240:240:240) (296:296:296))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1222:1222:1222) (1373:1373:1373))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (750:750:750) (881:881:881))
        (PORT d[1] (752:752:752) (885:885:885))
        (PORT d[2] (759:759:759) (883:883:883))
        (PORT d[3] (751:751:751) (877:877:877))
        (PORT d[4] (740:740:740) (858:858:858))
        (PORT d[5] (693:693:693) (792:792:792))
        (PORT d[6] (739:739:739) (858:858:858))
        (PORT d[7] (848:848:848) (971:971:971))
        (PORT d[8] (777:777:777) (904:904:904))
        (PORT d[9] (754:754:754) (868:868:868))
        (PORT d[10] (752:752:752) (879:879:879))
        (PORT d[11] (760:760:760) (877:877:877))
        (PORT d[12] (782:782:782) (915:915:915))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (556:556:556) (593:593:593))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datac (325:325:325) (386:386:386))
        (PORT datad (241:241:241) (297:297:297))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (488:488:488) (559:559:559))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (901:901:901) (1054:1054:1054))
        (PORT d[1] (745:745:745) (868:868:868))
        (PORT d[2] (911:911:911) (1062:1062:1062))
        (PORT d[3] (983:983:983) (1160:1160:1160))
        (PORT d[4] (960:960:960) (1131:1131:1131))
        (PORT d[5] (853:853:853) (1005:1005:1005))
        (PORT d[6] (959:959:959) (1109:1109:1109))
        (PORT d[7] (1074:1074:1074) (1240:1240:1240))
        (PORT d[8] (953:953:953) (1104:1104:1104))
        (PORT d[9] (973:973:973) (1129:1129:1129))
        (PORT d[10] (1014:1014:1014) (1196:1196:1196))
        (PORT d[11] (1083:1083:1083) (1249:1249:1249))
        (PORT d[12] (1013:1013:1013) (1198:1198:1198))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (762:762:762) (841:841:841))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (325:325:325) (385:385:385))
        (PORT datad (240:240:240) (296:296:296))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1463:1463:1463) (1668:1668:1668))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (997:997:997) (1166:1166:1166))
        (PORT d[1] (1057:1057:1057) (1227:1227:1227))
        (PORT d[2] (827:827:827) (962:962:962))
        (PORT d[3] (821:821:821) (948:948:948))
        (PORT d[4] (855:855:855) (1004:1004:1004))
        (PORT d[5] (728:728:728) (850:850:850))
        (PORT d[6] (881:881:881) (1023:1023:1023))
        (PORT d[7] (1001:1001:1001) (1155:1155:1155))
        (PORT d[8] (710:710:710) (835:835:835))
        (PORT d[9] (691:691:691) (815:815:815))
        (PORT d[10] (697:697:697) (823:823:823))
        (PORT d[11] (725:725:725) (846:846:846))
        (PORT d[12] (664:664:664) (776:776:776))
        (PORT clk (1085:1085:1085) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (PORT d[0] (595:595:595) (646:646:646))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1067:1067:1067) (1083:1083:1083))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (615:615:615))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datac (322:322:322) (383:383:383))
        (PORT datad (238:238:238) (294:294:294))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1373:1373:1373) (1553:1553:1553))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (584:584:584) (682:682:682))
        (PORT d[1] (594:594:594) (705:705:705))
        (PORT d[2] (599:599:599) (706:706:706))
        (PORT d[3] (592:592:592) (698:698:698))
        (PORT d[4] (882:882:882) (1016:1016:1016))
        (PORT d[5] (593:593:593) (694:694:694))
        (PORT d[6] (626:626:626) (736:736:736))
        (PORT d[7] (714:714:714) (825:825:825))
        (PORT d[8] (754:754:754) (873:873:873))
        (PORT d[9] (625:625:625) (732:732:732))
        (PORT d[10] (762:762:762) (891:891:891))
        (PORT d[11] (634:634:634) (743:743:743))
        (PORT d[12] (706:706:706) (823:823:823))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (475:475:475) (507:507:507))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (339:339:339) (400:400:400))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1104:1104:1104) (1133:1133:1133))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (120:120:120) (157:157:157))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (906:906:906) (911:911:911))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1053:1053:1053) (1237:1237:1237))
        (PORT datab (633:633:633) (714:714:714))
        (PORT datac (471:471:471) (542:542:542))
        (PORT datad (151:151:151) (195:195:195))
        (IOPATH dataa combout (188:188:188) (179:179:179))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (656:656:656) (751:751:751))
        (PORT datab (811:811:811) (924:924:924))
        (PORT datac (88:88:88) (110:110:110))
        (PORT datad (151:151:151) (195:195:195))
        (IOPATH dataa combout (165:165:165) (163:163:163))
        (IOPATH datab combout (167:167:167) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1081:1081:1081) (1229:1229:1229))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1232:1232:1232) (1446:1446:1446))
        (PORT d[1] (887:887:887) (1040:1040:1040))
        (PORT d[2] (977:977:977) (1123:1123:1123))
        (PORT d[3] (981:981:981) (1125:1125:1125))
        (PORT d[4] (973:973:973) (1125:1125:1125))
        (PORT d[5] (874:874:874) (1008:1008:1008))
        (PORT d[6] (858:858:858) (1004:1004:1004))
        (PORT d[7] (815:815:815) (944:944:944))
        (PORT d[8] (867:867:867) (1006:1006:1006))
        (PORT d[9] (831:831:831) (969:969:969))
        (PORT d[10] (840:840:840) (980:980:980))
        (PORT d[11] (872:872:872) (1005:1005:1005))
        (PORT d[12] (968:968:968) (1124:1124:1124))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (717:717:717) (782:782:782))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1267:1267:1267) (1445:1445:1445))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1129:1129:1129) (1330:1330:1330))
        (PORT d[1] (864:864:864) (1008:1008:1008))
        (PORT d[2] (976:976:976) (1124:1124:1124))
        (PORT d[3] (978:978:978) (1122:1122:1122))
        (PORT d[4] (968:968:968) (1120:1120:1120))
        (PORT d[5] (884:884:884) (1020:1020:1020))
        (PORT d[6] (866:866:866) (1015:1015:1015))
        (PORT d[7] (806:806:806) (934:934:934))
        (PORT d[8] (863:863:863) (1002:1002:1002))
        (PORT d[9] (838:838:838) (979:979:979))
        (PORT d[10] (847:847:847) (990:990:990))
        (PORT d[11] (882:882:882) (1017:1017:1017))
        (PORT d[12] (951:951:951) (1104:1104:1104))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (PORT d[0] (686:686:686) (747:747:747))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1110:1110:1110))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1088:1088:1088))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1548:1548:1548) (1749:1749:1749))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (583:583:583) (695:695:695))
        (PORT d[1] (605:605:605) (721:721:721))
        (PORT d[2] (575:575:575) (678:678:678))
        (PORT d[3] (732:732:732) (858:858:858))
        (PORT d[4] (738:738:738) (863:863:863))
        (PORT d[5] (580:580:580) (680:680:680))
        (PORT d[6] (573:573:573) (669:669:669))
        (PORT d[7] (681:681:681) (785:785:785))
        (PORT d[8] (591:591:591) (691:691:691))
        (PORT d[9] (613:613:613) (721:721:721))
        (PORT d[10] (602:602:602) (715:715:715))
        (PORT d[11] (611:611:611) (717:717:717))
        (PORT d[12] (598:598:598) (704:704:704))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (449:449:449) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (860:860:860) (1035:1035:1035))
        (PORT datab (839:839:839) (965:965:965))
        (PORT datac (732:732:732) (828:828:828))
        (PORT datad (538:538:538) (635:635:635))
        (IOPATH dataa combout (188:188:188) (184:184:184))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (490:490:490) (557:557:557))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (993:993:993) (1187:1187:1187))
        (PORT d[1] (971:971:971) (1169:1169:1169))
        (PORT d[2] (1235:1235:1235) (1439:1439:1439))
        (PORT d[3] (1035:1035:1035) (1200:1200:1200))
        (PORT d[4] (1182:1182:1182) (1366:1366:1366))
        (PORT d[5] (887:887:887) (1045:1045:1045))
        (PORT d[6] (1050:1050:1050) (1212:1212:1212))
        (PORT d[7] (1252:1252:1252) (1469:1469:1469))
        (PORT d[8] (886:886:886) (1022:1022:1022))
        (PORT d[9] (881:881:881) (1028:1028:1028))
        (PORT d[10] (1019:1019:1019) (1221:1221:1221))
        (PORT d[11] (912:912:912) (1056:1056:1056))
        (PORT d[12] (1006:1006:1006) (1176:1176:1176))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (655:655:655) (737:737:737))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (866:866:866) (979:979:979))
        (PORT datab (104:104:104) (134:134:134))
        (PORT datac (609:609:609) (680:680:680))
        (PORT datad (543:543:543) (641:641:641))
        (IOPATH dataa combout (166:166:166) (159:159:159))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1390:1390:1390) (1575:1575:1575))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (588:588:588) (688:688:688))
        (PORT d[1] (599:599:599) (709:709:709))
        (PORT d[2] (599:599:599) (705:705:705))
        (PORT d[3] (735:735:735) (857:857:857))
        (PORT d[4] (596:596:596) (708:708:708))
        (PORT d[5] (595:595:595) (695:695:695))
        (PORT d[6] (604:604:604) (713:713:713))
        (PORT d[7] (714:714:714) (824:824:824))
        (PORT d[8] (614:614:614) (723:723:723))
        (PORT d[9] (624:624:624) (731:731:731))
        (PORT d[10] (611:611:611) (725:725:725))
        (PORT d[11] (633:633:633) (742:742:742))
        (PORT d[12] (634:634:634) (751:751:751))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (430:430:430) (457:457:457))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1092:1092:1092))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (616:616:616) (624:624:624))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1288:1288:1288) (1469:1469:1469))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (827:827:827) (974:974:974))
        (PORT d[1] (1056:1056:1056) (1226:1226:1226))
        (PORT d[2] (856:856:856) (1000:1000:1000))
        (PORT d[3] (835:835:835) (964:964:964))
        (PORT d[4] (835:835:835) (974:974:974))
        (PORT d[5] (729:729:729) (847:847:847))
        (PORT d[6] (880:880:880) (1024:1024:1024))
        (PORT d[7] (1001:1001:1001) (1154:1154:1154))
        (PORT d[8] (723:723:723) (850:850:850))
        (PORT d[9] (695:695:695) (817:817:817))
        (PORT d[10] (700:700:700) (825:825:825))
        (PORT d[11] (725:725:725) (842:842:842))
        (PORT d[12] (828:828:828) (974:974:974))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (593:593:593) (641:641:641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1069:1069:1069) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1280:1280:1280) (1460:1460:1460))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (981:981:981) (1140:1140:1140))
        (PORT d[1] (1048:1048:1048) (1220:1220:1220))
        (PORT d[2] (863:863:863) (1007:1007:1007))
        (PORT d[3] (843:843:843) (989:989:989))
        (PORT d[4] (865:865:865) (1013:1013:1013))
        (PORT d[5] (738:738:738) (857:857:857))
        (PORT d[6] (878:878:878) (1022:1022:1022))
        (PORT d[7] (969:969:969) (1115:1115:1115))
        (PORT d[8] (718:718:718) (840:840:840))
        (PORT d[9] (717:717:717) (847:847:847))
        (PORT d[10] (708:708:708) (834:834:834))
        (PORT d[11] (746:746:746) (870:870:870))
        (PORT d[12] (683:683:683) (795:795:795))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (588:588:588) (644:644:644))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (646:646:646) (729:729:729))
        (PORT datab (164:164:164) (218:218:218))
        (PORT datac (861:861:861) (1014:1014:1014))
        (PORT datad (642:642:642) (717:717:717))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (188:188:188) (193:193:193))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1568:1568:1568) (1779:1779:1779))
        (PORT clk (1087:1087:1087) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (416:416:416) (498:498:498))
        (PORT d[1] (409:409:409) (486:486:486))
        (PORT d[2] (549:549:549) (642:642:642))
        (PORT d[3] (731:731:731) (855:855:855))
        (PORT d[4] (591:591:591) (702:702:702))
        (PORT d[5] (741:741:741) (852:852:852))
        (PORT d[6] (564:564:564) (658:658:658))
        (PORT d[7] (689:689:689) (797:797:797))
        (PORT d[8] (582:582:582) (679:679:679))
        (PORT d[9] (593:593:593) (694:694:694))
        (PORT d[10] (694:694:694) (805:805:805))
        (PORT d[11] (702:702:702) (817:817:817))
        (PORT d[12] (675:675:675) (785:785:785))
        (PORT clk (1085:1085:1085) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1106:1106:1106))
        (PORT d[0] (447:447:447) (475:475:475))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1067:1067:1067) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (461:461:461) (533:533:533))
        (PORT datab (164:164:164) (219:219:219))
        (PORT datac (89:89:89) (109:109:109))
        (PORT datad (446:446:446) (503:503:503))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (190:190:190) (205:205:205))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1083:1083:1083) (1252:1252:1252))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1171:1171:1171) (1388:1388:1388))
        (PORT d[1] (967:967:967) (1155:1155:1155))
        (PORT d[2] (1205:1205:1205) (1409:1409:1409))
        (PORT d[3] (1293:1293:1293) (1521:1521:1521))
        (PORT d[4] (1211:1211:1211) (1407:1407:1407))
        (PORT d[5] (1077:1077:1077) (1262:1262:1262))
        (PORT d[6] (1029:1029:1029) (1186:1186:1186))
        (PORT d[7] (1225:1225:1225) (1433:1433:1433))
        (PORT d[8] (1091:1091:1091) (1260:1260:1260))
        (PORT d[9] (1091:1091:1091) (1276:1276:1276))
        (PORT d[10] (1012:1012:1012) (1210:1210:1210))
        (PORT d[11] (1078:1078:1078) (1243:1243:1243))
        (PORT d[12] (1173:1173:1173) (1363:1363:1363))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (758:758:758) (846:846:846))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1740:1740:1740) (1971:1971:1971))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (579:579:579) (684:684:684))
        (PORT d[1] (573:573:573) (676:676:676))
        (PORT d[2] (724:724:724) (841:841:841))
        (PORT d[3] (775:775:775) (903:903:903))
        (PORT d[4] (776:776:776) (917:917:917))
        (PORT d[5] (854:854:854) (1000:1000:1000))
        (PORT d[6] (771:771:771) (895:895:895))
        (PORT d[7] (890:890:890) (1031:1031:1031))
        (PORT d[8] (764:764:764) (888:888:888))
        (PORT d[9] (784:784:784) (913:913:913))
        (PORT d[10] (776:776:776) (917:917:917))
        (PORT d[11] (883:883:883) (1021:1021:1021))
        (PORT d[12] (745:745:745) (862:862:862))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (627:627:627) (674:674:674))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1092:1092:1092))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (616:616:616) (624:624:624))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (857:857:857) (1032:1032:1032))
        (PORT datab (562:562:562) (667:667:667))
        (PORT datac (804:804:804) (914:914:914))
        (PORT datad (583:583:583) (663:663:663))
        (IOPATH dataa combout (188:188:188) (184:184:184))
        (IOPATH datab combout (190:190:190) (188:188:188))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1470:1470:1470) (1676:1676:1676))
        (PORT clk (1084:1084:1084) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1010:1010:1010) (1181:1181:1181))
        (PORT d[1] (569:569:569) (674:674:674))
        (PORT d[2] (676:676:676) (793:793:793))
        (PORT d[3] (641:641:641) (749:749:749))
        (PORT d[4] (680:680:680) (805:805:805))
        (PORT d[5] (580:580:580) (680:680:680))
        (PORT d[6] (897:897:897) (1042:1042:1042))
        (PORT d[7] (864:864:864) (1012:1012:1012))
        (PORT d[8] (544:544:544) (645:645:645))
        (PORT d[9] (517:517:517) (616:616:616))
        (PORT d[10] (576:576:576) (681:681:681))
        (PORT d[11] (534:534:534) (631:631:631))
        (PORT d[12] (516:516:516) (613:613:613))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1084:1084:1084) (1102:1102:1102))
        (PORT d[0] (437:437:437) (463:463:463))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1064:1064:1064) (1081:1081:1081))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (604:604:604) (613:613:613))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1729:1729:1729) (1957:1957:1957))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (567:567:567) (672:672:672))
        (PORT d[1] (552:552:552) (651:651:651))
        (PORT d[2] (570:570:570) (663:663:663))
        (PORT d[3] (594:594:594) (702:702:702))
        (PORT d[4] (584:584:584) (689:689:689))
        (PORT d[5] (869:869:869) (1027:1027:1027))
        (PORT d[6] (595:595:595) (700:700:700))
        (PORT d[7] (717:717:717) (834:834:834))
        (PORT d[8] (596:596:596) (696:696:696))
        (PORT d[9] (618:618:618) (725:725:725))
        (PORT d[10] (706:706:706) (819:819:819))
        (PORT d[11] (743:743:743) (854:854:854))
        (PORT d[12] (587:587:587) (688:688:688))
        (PORT clk (1088:1088:1088) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (457:457:457) (490:490:490))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (105:105:105) (136:136:136))
        (PORT datab (559:559:559) (663:663:663))
        (PORT datac (607:607:607) (686:686:686))
        (PORT datad (574:574:574) (641:641:641))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH datab combout (167:167:167) (158:158:158))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1289:1289:1289) (1470:1470:1470))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (813:813:813) (952:952:952))
        (PORT d[1] (709:709:709) (837:837:837))
        (PORT d[2] (863:863:863) (1007:1007:1007))
        (PORT d[3] (848:848:848) (987:987:987))
        (PORT d[4] (865:865:865) (1012:1012:1012))
        (PORT d[5] (750:750:750) (876:876:876))
        (PORT d[6] (703:703:703) (828:828:828))
        (PORT d[7] (671:671:671) (780:780:780))
        (PORT d[8] (718:718:718) (839:839:839))
        (PORT d[9] (716:716:716) (846:846:846))
        (PORT d[10] (707:707:707) (833:833:833))
        (PORT d[11] (732:732:732) (850:850:850))
        (PORT d[12] (695:695:695) (814:814:814))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (PORT d[0] (594:594:594) (647:647:647))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1086:1086:1086))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (669:669:669) (771:771:771))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (986:986:986) (1173:1173:1173))
        (PORT d[1] (763:763:763) (902:902:902))
        (PORT d[2] (860:860:860) (999:999:999))
        (PORT d[3] (902:902:902) (1063:1063:1063))
        (PORT d[4] (1024:1024:1024) (1193:1193:1193))
        (PORT d[5] (757:757:757) (885:885:885))
        (PORT d[6] (868:868:868) (1007:1007:1007))
        (PORT d[7] (1054:1054:1054) (1237:1237:1237))
        (PORT d[8] (705:705:705) (819:819:819))
        (PORT d[9] (701:701:701) (825:825:825))
        (PORT d[10] (1015:1015:1015) (1213:1213:1213))
        (PORT d[11] (711:711:711) (829:829:829))
        (PORT d[12] (822:822:822) (966:966:966))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (626:626:626) (689:689:689))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1069:1069:1069) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1898:1898:1898) (2144:2144:2144))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (779:779:779) (916:916:916))
        (PORT d[1] (739:739:739) (862:862:862))
        (PORT d[2] (769:769:769) (899:899:899))
        (PORT d[3] (783:783:783) (913:913:913))
        (PORT d[4] (780:780:780) (918:918:918))
        (PORT d[5] (845:845:845) (993:993:993))
        (PORT d[6] (939:939:939) (1083:1083:1083))
        (PORT d[7] (922:922:922) (1073:1073:1073))
        (PORT d[8] (792:792:792) (925:925:925))
        (PORT d[9] (816:816:816) (952:952:952))
        (PORT d[10] (773:773:773) (908:908:908))
        (PORT d[11] (1050:1050:1050) (1208:1208:1208))
        (PORT d[12] (996:996:996) (1170:1170:1170))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (600:600:600) (648:648:648))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (859:859:859) (1034:1034:1034))
        (PORT datab (560:560:560) (665:665:665))
        (PORT datac (459:459:459) (521:521:521))
        (PORT datad (690:690:690) (800:800:800))
        (IOPATH dataa combout (170:170:170) (165:165:165))
        (IOPATH datab combout (169:169:169) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (509:509:509) (592:592:592))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (927:927:927) (1075:1075:1075))
        (PORT d[1] (1116:1116:1116) (1310:1310:1310))
        (PORT d[2] (923:923:923) (1076:1076:1076))
        (PORT d[3] (975:975:975) (1149:1149:1149))
        (PORT d[4] (1083:1083:1083) (1262:1262:1262))
        (PORT d[5] (849:849:849) (994:994:994))
        (PORT d[6] (954:954:954) (1111:1111:1111))
        (PORT d[7] (1086:1086:1086) (1254:1254:1254))
        (PORT d[8] (984:984:984) (1140:1140:1140))
        (PORT d[9] (1014:1014:1014) (1180:1180:1180))
        (PORT d[10] (990:990:990) (1170:1170:1170))
        (PORT d[11] (904:904:904) (1036:1036:1036))
        (PORT d[12] (1014:1014:1014) (1193:1193:1193))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (746:746:746) (815:815:815))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (797:797:797) (900:900:900))
        (PORT datab (103:103:103) (131:131:131))
        (PORT datac (759:759:759) (861:861:861))
        (PORT datad (542:542:542) (640:640:640))
        (IOPATH dataa combout (166:166:166) (159:159:159))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1743:1743:1743) (1973:1973:1973))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (589:589:589) (699:699:699))
        (PORT d[1] (688:688:688) (800:800:800))
        (PORT d[2] (575:575:575) (669:669:669))
        (PORT d[3] (608:608:608) (720:720:720))
        (PORT d[4] (594:594:594) (701:701:701))
        (PORT d[5] (868:868:868) (1020:1020:1020))
        (PORT d[6] (597:597:597) (698:698:698))
        (PORT d[7] (737:737:737) (859:859:859))
        (PORT d[8] (619:619:619) (727:727:727))
        (PORT d[9] (617:617:617) (721:721:721))
        (PORT d[10] (713:713:713) (827:827:827))
        (PORT d[11] (712:712:712) (826:826:826))
        (PORT d[12] (607:607:607) (714:714:714))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (PORT d[0] (445:445:445) (479:479:479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1074:1074:1074) (1090:1090:1090))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (614:614:614) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (855:855:855) (984:984:984))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (982:982:982) (1165:1165:1165))
        (PORT d[1] (751:751:751) (885:885:885))
        (PORT d[2] (899:899:899) (1052:1052:1052))
        (PORT d[3] (830:830:830) (966:966:966))
        (PORT d[4] (832:832:832) (969:969:969))
        (PORT d[5] (743:743:743) (864:864:864))
        (PORT d[6] (861:861:861) (999:999:999))
        (PORT d[7] (1059:1059:1059) (1243:1243:1243))
        (PORT d[8] (717:717:717) (837:837:837))
        (PORT d[9] (710:710:710) (837:837:837))
        (PORT d[10] (743:743:743) (884:884:884))
        (PORT d[11] (740:740:740) (866:866:866))
        (PORT d[12] (811:811:811) (951:951:951))
        (PORT clk (1085:1085:1085) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (PORT d[0] (608:608:608) (664:664:664))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1067:1067:1067) (1083:1083:1083))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (615:615:615))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1728:1728:1728) (1953:1953:1953))
        (PORT clk (1092:1092:1092) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (575:575:575) (673:673:673))
        (PORT d[1] (565:565:565) (667:667:667))
        (PORT d[2] (613:613:613) (722:722:722))
        (PORT d[3] (596:596:596) (702:702:702))
        (PORT d[4] (594:594:594) (700:700:700))
        (PORT d[5] (855:855:855) (1006:1006:1006))
        (PORT d[6] (762:762:762) (888:888:888))
        (PORT d[7] (726:726:726) (844:844:844))
        (PORT d[8] (605:605:605) (706:706:706))
        (PORT d[9] (627:627:627) (734:734:734))
        (PORT d[10] (700:700:700) (807:807:807))
        (PORT d[11] (757:757:757) (876:876:876))
        (PORT d[12] (690:690:690) (801:801:801))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1110:1110:1110))
        (PORT d[0] (478:478:478) (506:506:506))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1093:1093:1093) (1111:1111:1111))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (528:528:528) (605:605:605))
        (PORT datab (564:564:564) (669:669:669))
        (PORT datac (575:575:575) (653:653:653))
        (PORT datad (842:842:842) (1003:1003:1003))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1900:1900:1900) (2148:2148:2148))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (761:761:761) (893:893:893))
        (PORT d[1] (728:728:728) (851:851:851))
        (PORT d[2] (747:747:747) (864:864:864))
        (PORT d[3] (781:781:781) (910:910:910))
        (PORT d[4] (770:770:770) (906:906:906))
        (PORT d[5] (861:861:861) (1012:1012:1012))
        (PORT d[6] (784:784:784) (915:915:915))
        (PORT d[7] (911:911:911) (1059:1059:1059))
        (PORT d[8] (776:776:776) (900:900:900))
        (PORT d[9] (808:808:808) (942:942:942))
        (PORT d[10] (911:911:911) (1071:1071:1071))
        (PORT d[11] (901:901:901) (1045:1045:1045))
        (PORT d[12] (756:756:756) (873:873:873))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (631:631:631) (678:678:678))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (436:436:436) (499:499:499))
        (PORT datab (560:560:560) (664:664:664))
        (PORT datac (91:91:91) (113:113:113))
        (PORT datad (592:592:592) (671:671:671))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (190:190:190) (205:205:205))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (847:847:847) (972:972:972))
        (PORT clk (1084:1084:1084) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1028:1028:1028) (1203:1203:1203))
        (PORT d[1] (754:754:754) (892:892:892))
        (PORT d[2] (829:829:829) (964:964:964))
        (PORT d[3] (829:829:829) (964:964:964))
        (PORT d[4] (824:824:824) (958:958:958))
        (PORT d[5] (735:735:735) (855:855:855))
        (PORT d[6] (861:861:861) (1003:1003:1003))
        (PORT d[7] (693:693:693) (818:818:818))
        (PORT d[8] (858:858:858) (996:996:996))
        (PORT d[9] (705:705:705) (834:834:834))
        (PORT d[10] (883:883:883) (1037:1037:1037))
        (PORT d[11] (704:704:704) (820:820:820))
        (PORT d[12] (816:816:816) (960:960:960))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1084:1084:1084) (1102:1102:1102))
        (PORT d[0] (608:608:608) (666:666:666))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1064:1064:1064) (1081:1081:1081))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (604:604:604) (613:613:613))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (605:605:605) (614:614:614))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1459:1459:1459) (1662:1662:1662))
        (PORT clk (1082:1082:1082) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1017:1017:1017) (1188:1188:1188))
        (PORT d[1] (846:846:846) (991:991:991))
        (PORT d[2] (843:843:843) (974:974:974))
        (PORT d[3] (831:831:831) (969:969:969))
        (PORT d[4] (816:816:816) (941:941:941))
        (PORT d[5] (712:712:712) (826:826:826))
        (PORT d[6] (694:694:694) (815:815:815))
        (PORT d[7] (854:854:854) (1001:1001:1001))
        (PORT d[8] (695:695:695) (810:810:810))
        (PORT d[9] (676:676:676) (795:795:795))
        (PORT d[10] (916:916:916) (1080:1080:1080))
        (PORT d[11] (707:707:707) (824:824:824))
        (PORT d[12] (790:790:790) (928:928:928))
        (PORT clk (1080:1080:1080) (1098:1098:1098))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1082:1082:1082) (1100:1100:1100))
        (PORT d[0] (581:581:581) (635:635:635))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1083:1083:1083) (1101:1101:1101))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1062:1062:1062) (1079:1079:1079))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (602:602:602) (611:611:611))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (603:603:603) (612:612:612))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (603:603:603) (612:612:612))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (603:603:603) (612:612:612))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (506:506:506) (608:608:608))
        (PORT datab (480:480:480) (542:542:542))
        (PORT datac (626:626:626) (702:702:702))
        (PORT datad (956:956:956) (1121:1121:1121))
        (IOPATH dataa combout (166:166:166) (159:159:159))
        (IOPATH datab combout (167:167:167) (158:158:158))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (662:662:662) (763:763:763))
        (PORT clk (1091:1091:1091) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (924:924:924) (1097:1097:1097))
        (PORT d[1] (922:922:922) (1079:1079:1079))
        (PORT d[2] (1040:1040:1040) (1211:1211:1211))
        (PORT d[3] (1002:1002:1002) (1157:1157:1157))
        (PORT d[4] (1035:1035:1035) (1203:1203:1203))
        (PORT d[5] (928:928:928) (1079:1079:1079))
        (PORT d[6] (1044:1044:1044) (1210:1210:1210))
        (PORT d[7] (883:883:883) (1043:1043:1043))
        (PORT d[8] (891:891:891) (1033:1033:1033))
        (PORT d[9] (887:887:887) (1040:1040:1040))
        (PORT d[10] (1007:1007:1007) (1205:1205:1205))
        (PORT d[11] (942:942:942) (1101:1101:1101))
        (PORT d[12] (997:997:997) (1166:1166:1166))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (PORT d[0] (720:720:720) (813:813:813))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1092:1092:1092) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1563:1563:1563) (1768:1768:1768))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (403:403:403) (480:480:480))
        (PORT d[1] (403:403:403) (480:480:480))
        (PORT d[2] (412:412:412) (478:478:478))
        (PORT d[3] (435:435:435) (514:514:514))
        (PORT d[4] (740:740:740) (866:866:866))
        (PORT d[5] (478:478:478) (564:564:564))
        (PORT d[6] (741:741:741) (862:862:862))
        (PORT d[7] (417:417:417) (488:488:488))
        (PORT d[8] (416:416:416) (489:489:489))
        (PORT d[9] (421:421:421) (498:498:498))
        (PORT d[10] (431:431:431) (512:512:512))
        (PORT d[11] (443:443:443) (519:519:519))
        (PORT d[12] (999:999:999) (1182:1182:1182))
        (PORT clk (1088:1088:1088) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (377:377:377) (394:394:394))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (504:504:504) (605:605:605))
        (PORT datab (104:104:104) (133:133:133))
        (PORT datac (634:634:634) (718:718:718))
        (PORT datad (562:562:562) (634:634:634))
        (IOPATH dataa combout (188:188:188) (179:179:179))
        (IOPATH datab combout (196:196:196) (192:192:192))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1549:1549:1549) (1753:1753:1753))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (591:591:591) (704:704:704))
        (PORT d[1] (598:598:598) (715:715:715))
        (PORT d[2] (600:600:600) (709:709:709))
        (PORT d[3] (604:604:604) (716:716:716))
        (PORT d[4] (590:590:590) (696:696:696))
        (PORT d[5] (1038:1038:1038) (1216:1216:1216))
        (PORT d[6] (744:744:744) (864:864:864))
        (PORT d[7] (695:695:695) (802:802:802))
        (PORT d[8] (602:602:602) (704:704:704))
        (PORT d[9] (616:616:616) (723:723:723))
        (PORT d[10] (591:591:591) (700:700:700))
        (PORT d[11] (612:612:612) (713:713:713))
        (PORT d[12] (637:637:637) (756:756:756))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
        (PORT d[0] (457:457:457) (484:484:484))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1074:1074:1074) (1090:1090:1090))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (614:614:614) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (615:615:615) (623:623:623))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (668:668:668) (768:768:768))
        (PORT clk (1096:1096:1096) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (916:916:916) (1068:1068:1068))
        (PORT d[1] (944:944:944) (1116:1116:1116))
        (PORT d[2] (1090:1090:1090) (1262:1262:1262))
        (PORT d[3] (970:970:970) (1138:1138:1138))
        (PORT d[4] (1093:1093:1093) (1273:1273:1273))
        (PORT d[5] (842:842:842) (985:985:985))
        (PORT d[6] (967:967:967) (1137:1137:1137))
        (PORT d[7] (1247:1247:1247) (1435:1435:1435))
        (PORT d[8] (1166:1166:1166) (1353:1353:1353))
        (PORT d[9] (1166:1166:1166) (1359:1359:1359))
        (PORT d[10] (820:820:820) (978:978:978))
        (PORT d[11] (1231:1231:1231) (1411:1411:1411))
        (PORT d[12] (1024:1024:1024) (1207:1207:1207))
        (PORT clk (1094:1094:1094) (1110:1110:1110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1112:1112:1112))
        (PORT d[0] (596:596:596) (654:654:654))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1113:1113:1113))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1076:1076:1076) (1091:1091:1091))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (616:616:616) (623:623:623))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (624:624:624))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (624:624:624))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (624:624:624))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (488:488:488) (559:559:559))
        (PORT datab (165:165:165) (222:222:222))
        (PORT datac (859:859:859) (1011:1011:1011))
        (PORT datad (823:823:823) (949:949:949))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1914:1914:1914) (2164:2164:2164))
        (PORT clk (1098:1098:1098) (1115:1115:1115))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (769:769:769) (901:901:901))
        (PORT d[1] (747:747:747) (873:873:873))
        (PORT d[2] (883:883:883) (1016:1016:1016))
        (PORT d[3] (983:983:983) (1158:1158:1158))
        (PORT d[4] (781:781:781) (919:919:919))
        (PORT d[5] (834:834:834) (979:979:979))
        (PORT d[6] (945:945:945) (1090:1090:1090))
        (PORT d[7] (901:901:901) (1043:1043:1043))
        (PORT d[8] (796:796:796) (928:928:928))
        (PORT d[9] (807:807:807) (939:939:939))
        (PORT d[10] (787:787:787) (940:940:940))
        (PORT d[11] (891:891:891) (1027:1027:1027))
        (PORT d[12] (1017:1017:1017) (1205:1205:1205))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (PORT d[0] (637:637:637) (684:684:684))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1099:1099:1099) (1116:1116:1116))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1372:1372:1372) (1553:1553:1553))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (745:745:745) (876:876:876))
        (PORT d[1] (748:748:748) (880:880:880))
        (PORT d[2] (743:743:743) (864:864:864))
        (PORT d[3] (792:792:792) (929:929:929))
        (PORT d[4] (882:882:882) (1021:1021:1021))
        (PORT d[5] (732:732:732) (845:845:845))
        (PORT d[6] (734:734:734) (852:852:852))
        (PORT d[7] (843:843:843) (967:967:967))
        (PORT d[8] (763:763:763) (884:884:884))
        (PORT d[9] (760:760:760) (878:878:878))
        (PORT d[10] (747:747:747) (874:874:874))
        (PORT d[11] (769:769:769) (889:889:889))
        (PORT d[12] (754:754:754) (880:880:880))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (PORT d[0] (561:561:561) (601:601:601))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1077:1077:1077) (1093:1093:1093))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (617:617:617) (625:625:625))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (103:103:103) (134:134:134))
        (PORT datab (164:164:164) (222:222:222))
        (PORT datac (643:643:643) (739:739:739))
        (PORT datad (597:597:597) (678:678:678))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH datab combout (167:167:167) (158:158:158))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (515:515:515) (594:594:594))
        (PORT datac (393:393:393) (475:475:475))
        (PORT datad (346:346:346) (400:400:400))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (566:566:566) (674:674:674))
        (PORT datac (336:336:336) (382:382:382))
        (PORT datad (184:184:184) (213:213:213))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (538:538:538) (622:622:622))
        (PORT datab (564:564:564) (672:672:672))
        (PORT datad (865:865:865) (1021:1021:1021))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (167:167:167) (158:158:158))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (566:566:566) (675:675:675))
        (PORT datac (358:358:358) (408:408:408))
        (PORT datad (350:350:350) (403:403:403))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (568:568:568) (676:676:676))
        (PORT datac (740:740:740) (826:826:826))
        (PORT datad (352:352:352) (402:402:402))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datab (368:368:368) (425:425:425))
        (PORT datac (552:552:552) (656:656:656))
        (PORT datad (361:361:361) (417:417:417))
        (IOPATH datab combout (168:168:168) (167:167:167))
        (IOPATH datac combout (119:119:119) (125:125:125))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT datab (1104:1104:1104) (1288:1288:1288))
        (PORT datac (358:358:358) (413:413:413))
        (PORT datad (185:185:185) (215:215:215))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (530:530:530) (609:609:609))
        (PORT datac (548:548:548) (651:651:651))
        (PORT datad (614:614:614) (693:693:693))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
)