de0-zx-spectrum/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "spectrum")
  (DATE "03/30/2022 13:47:24")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 32-bit")
  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

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        (IOPATH datad combout (68:68:68) (63:63:63))
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      (ABSOLUTE
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      (ABSOLUTE
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    (CELLTYPE "dffeas")
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[14\]\~47)
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      (ABSOLUTE
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  (CELL
    (CELLTYPE "dffeas")
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    (DELAY
      (ABSOLUTE
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[15\]\~49)
    (DELAY
      (ABSOLUTE
        (PORT dataa (211:211:211) (270:270:270))
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      )
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  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
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        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
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    (TIMINGCHECK
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  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[16\]\~51)
    (DELAY
      (ABSOLUTE
        (PORT dataa (135:135:135) (187:187:187))
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        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
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    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[17\]\~53)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136:136:136) (188:188:188))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[18\]\~55)
    (DELAY
      (ABSOLUTE
        (PORT datab (135:135:135) (185:185:185))
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        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[19\]\~57)
    (DELAY
      (ABSOLUTE
        (PORT datab (135:135:135) (185:185:185))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (912:912:912) (916:916:916))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[20\]\~59)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[20\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1110:1110:1110) (1138:1138:1138))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[21\]\~61)
    (DELAY
      (ABSOLUTE
        (PORT datad (129:129:129) (166:166:166))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1110:1110:1110) (1138:1138:1138))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (137:137:137) (191:191:191))
        (PORT datab (135:135:135) (185:185:185))
        (PORT datac (122:122:122) (165:165:165))
        (PORT datad (123:123:123) (163:163:163))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136:136:136) (189:189:189))
        (PORT datab (134:134:134) (184:184:184))
        (PORT datac (121:121:121) (164:164:164))
        (PORT datad (123:123:123) (162:162:162))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (137:137:137) (191:191:191))
        (PORT datab (136:136:136) (186:186:186))
        (PORT datac (200:200:200) (246:246:246))
        (PORT datad (123:123:123) (162:162:162))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (232:232:232) (289:289:289))
        (PORT datab (213:213:213) (270:270:270))
        (PORT datac (296:296:296) (349:349:349))
        (PORT datad (300:300:300) (354:354:354))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (139:139:139) (193:193:193))
        (PORT datab (144:144:144) (193:193:193))
        (PORT datac (131:131:131) (173:173:173))
        (PORT datad (125:125:125) (165:165:165))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (120:120:120) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (197:197:197) (238:238:238))
        (PORT datab (177:177:177) (218:218:218))
        (PORT datac (89:89:89) (111:111:111))
        (PORT datad (336:336:336) (394:394:394))
        (IOPATH dataa combout (159:159:159) (163:163:163))
        (IOPATH datab combout (161:161:161) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (472:472:472) (559:559:559))
        (PORT datab (488:488:488) (576:576:576))
        (PORT datac (327:327:327) (384:384:384))
        (PORT datad (89:89:89) (107:107:107))
        (IOPATH dataa combout (158:158:158) (157:157:157))
        (IOPATH datab combout (160:160:160) (156:156:156))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[0\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT datad (172:172:172) (198:198:198))
        (IOPATH datac combout (190:190:190) (195:195:195))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[1\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (233:233:233) (295:295:295))
        (PORT datab (320:320:320) (389:389:389))
        (IOPATH dataa combout (186:186:186) (180:180:180))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datab combout (190:190:190) (181:181:181))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[2\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (189:189:189))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[3\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (141:141:141) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[4\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[5\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[6\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[7\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (186:186:186) (175:175:175))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[8\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (211:211:211) (271:271:271))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[9\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (154:154:154) (202:202:202))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[10\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[11\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (142:142:142) (190:190:190))
        (IOPATH datab combout (192:192:192) (177:177:177))
        (IOPATH datab cout (227:227:227) (175:175:175))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[12\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (143:143:143) (193:193:193))
        (IOPATH dataa combout (165:165:165) (173:173:173))
        (IOPATH dataa cout (226:226:226) (171:171:171))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
        (IOPATH cin cout (34:34:34) (34:34:34))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[13\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datad (141:141:141) (177:177:177))
        (IOPATH datad combout (68:68:68) (63:63:63))
        (IOPATH cin combout (187:187:187) (204:204:204))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1111:1111:1111) (1139:1139:1139))
        (PORT d (37:37:37) (50:50:50))
        (PORT ena (422:422:422) (442:442:442))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
      (HOLD ena (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (575:575:575) (672:672:672))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (590:590:590) (696:696:696))
        (PORT d[1] (817:817:817) (948:948:948))
        (PORT d[2] (530:530:530) (622:622:622))
        (PORT d[3] (567:567:567) (666:666:666))
        (PORT d[4] (567:567:567) (666:666:666))
        (PORT d[5] (440:440:440) (515:515:515))
        (PORT d[6] (440:440:440) (515:515:515))
        (PORT d[7] (440:440:440) (515:515:515))
        (PORT d[8] (440:440:440) (515:515:515))
        (PORT d[9] (440:440:440) (515:515:515))
        (PORT d[10] (440:440:440) (515:515:515))
        (PORT d[11] (440:440:440) (515:515:515))
        (PORT d[12] (440:440:440) (515:515:515))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1070:1070:1070))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (579:579:579) (676:676:676))
        (PORT clk (1056:1056:1056) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (581:581:581) (685:685:685))
        (PORT d[1] (818:818:818) (948:948:948))
        (PORT d[2] (541:541:541) (634:634:634))
        (PORT d[3] (677:677:677) (784:784:784))
        (PORT d[4] (537:537:537) (629:629:629))
        (PORT d[5] (882:882:882) (1013:1013:1013))
        (PORT d[6] (689:689:689) (790:790:790))
        (PORT d[7] (709:709:709) (819:819:819))
        (PORT d[8] (674:674:674) (787:787:787))
        (PORT d[9] (692:692:692) (792:792:792))
        (PORT d[10] (701:701:701) (805:805:805))
        (PORT d[11] (685:685:685) (787:787:787))
        (PORT d[12] (719:719:719) (829:829:829))
        (PORT clk (1053:1053:1053) (1072:1072:1072))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1056:1056:1056) (1073:1073:1073))
        (PORT d[0] (542:542:542) (498:498:498))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (564:564:564) (651:651:651))
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (587:587:587) (692:692:692))
        (PORT d[1] (673:673:673) (782:782:782))
        (PORT d[2] (535:535:535) (629:629:629))
        (PORT d[3] (576:576:576) (669:669:669))
        (PORT d[4] (576:576:576) (669:669:669))
        (PORT d[5] (461:461:461) (543:543:543))
        (PORT d[6] (461:461:461) (543:543:543))
        (PORT d[7] (461:461:461) (543:543:543))
        (PORT d[8] (461:461:461) (543:543:543))
        (PORT d[9] (461:461:461) (543:543:543))
        (PORT d[10] (461:461:461) (543:543:543))
        (PORT d[11] (461:461:461) (543:543:543))
        (PORT d[12] (461:461:461) (543:543:543))
        (PORT clk (1092:1092:1092) (1109:1109:1109))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1094:1094:1094) (1111:1111:1111))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1095:1095:1095) (1112:1112:1112))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1049:1049:1049) (1068:1068:1068))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (568:568:568) (655:655:655))
        (PORT clk (1054:1054:1054) (1071:1071:1071))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (599:599:599) (705:705:705))
        (PORT d[1] (536:536:536) (629:629:629))
        (PORT d[2] (711:711:711) (827:827:827))
        (PORT d[3] (679:679:679) (777:777:777))
        (PORT d[4] (529:529:529) (615:615:615))
        (PORT d[5] (871:871:871) (1002:1002:1002))
        (PORT d[6] (708:708:708) (816:816:816))
        (PORT d[7] (714:714:714) (824:824:824))
        (PORT d[8] (809:809:809) (929:929:929))
        (PORT d[9] (698:698:698) (799:799:799))
        (PORT d[10] (710:710:710) (818:818:818))
        (PORT d[11] (692:692:692) (794:794:794))
        (PORT d[12] (713:713:713) (817:817:817))
        (PORT clk (1051:1051:1051) (1070:1070:1070))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1054:1054:1054) (1071:1071:1071))
        (PORT d[0] (549:549:549) (504:504:504))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1072:1072:1072))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1055:1055:1055) (1072:1072:1072))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (749:749:749) (870:870:870))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (590:590:590) (703:703:703))
        (PORT d[1] (511:511:511) (605:605:605))
        (PORT d[2] (843:843:843) (978:978:978))
        (PORT d[3] (749:749:749) (871:871:871))
        (PORT d[4] (749:749:749) (871:871:871))
        (PORT d[5] (426:426:426) (499:499:499))
        (PORT d[6] (426:426:426) (499:499:499))
        (PORT d[7] (426:426:426) (499:499:499))
        (PORT d[8] (426:426:426) (499:499:499))
        (PORT d[9] (426:426:426) (499:499:499))
        (PORT d[10] (426:426:426) (499:499:499))
        (PORT d[11] (426:426:426) (499:499:499))
        (PORT d[12] (426:426:426) (499:499:499))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (753:753:753) (874:874:874))
        (PORT clk (1057:1057:1057) (1074:1074:1074))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (581:581:581) (689:689:689))
        (PORT d[1] (829:829:829) (959:959:959))
        (PORT d[2] (505:505:505) (587:587:587))
        (PORT d[3] (808:808:808) (929:929:929))
        (PORT d[4] (517:517:517) (601:601:601))
        (PORT d[5] (584:584:584) (688:688:688))
        (PORT d[6] (687:687:687) (792:792:792))
        (PORT d[7] (579:579:579) (678:678:678))
        (PORT d[8] (830:830:830) (959:959:959))
        (PORT d[9] (693:693:693) (797:797:797))
        (PORT d[10] (688:688:688) (792:792:792))
        (PORT d[11] (686:686:686) (792:792:792))
        (PORT d[12] (694:694:694) (796:796:796))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
        (PORT d[0] (528:528:528) (485:485:485))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (760:760:760) (881:881:881))
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (420:420:420) (491:491:491))
        (PORT d[1] (350:350:350) (416:416:416))
        (PORT d[2] (851:851:851) (986:986:986))
        (PORT d[3] (362:362:362) (421:421:421))
        (PORT d[4] (362:362:362) (421:421:421))
        (PORT d[5] (263:263:263) (312:312:312))
        (PORT d[6] (263:263:263) (312:312:312))
        (PORT d[7] (263:263:263) (312:312:312))
        (PORT d[8] (263:263:263) (312:312:312))
        (PORT d[9] (263:263:263) (312:312:312))
        (PORT d[10] (263:263:263) (312:312:312))
        (PORT d[11] (263:263:263) (312:312:312))
        (PORT d[12] (263:263:263) (312:312:312))
        (PORT clk (1095:1095:1095) (1112:1112:1112))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1098:1098:1098) (1115:1115:1115))
        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1052:1052:1052) (1071:1071:1071))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (764:764:764) (885:885:885))
        (PORT clk (1057:1057:1057) (1074:1074:1074))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (408:408:408) (481:481:481))
        (PORT d[1] (845:845:845) (980:980:980))
        (PORT d[2] (851:851:851) (985:985:985))
        (PORT d[3] (360:360:360) (420:420:420))
        (PORT d[4] (363:363:363) (426:426:426))
        (PORT d[5] (397:397:397) (470:470:470))
        (PORT d[6] (422:422:422) (497:497:497))
        (PORT d[7] (416:416:416) (491:491:491))
        (PORT d[8] (853:853:853) (987:987:987))
        (PORT d[9] (417:417:417) (487:487:487))
        (PORT d[10] (536:536:536) (626:626:626))
        (PORT d[11] (407:407:407) (476:476:476))
        (PORT d[12] (520:520:520) (600:600:600))
        (PORT clk (1054:1054:1054) (1073:1073:1073))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1057:1057:1057) (1074:1074:1074))
        (PORT d[0] (367:367:367) (342:342:342))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1058:1058:1058) (1075:1075:1075))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (890:890:890) (1046:1046:1046))
        (PORT d[1] (707:707:707) (833:833:833))
        (PORT d[2] (698:698:698) (814:814:814))
        (PORT d[3] (700:700:700) (816:816:816))
        (PORT d[4] (716:716:716) (835:835:835))
        (PORT d[5] (893:893:893) (1047:1047:1047))
        (PORT d[6] (685:685:685) (805:805:805))
        (PORT d[7] (683:683:683) (802:802:802))
        (PORT d[8] (697:697:697) (821:821:821))
        (PORT d[9] (699:699:699) (813:813:813))
        (PORT d[10] (705:705:705) (827:827:827))
        (PORT d[11] (695:695:695) (816:816:816))
        (PORT d[12] (868:868:868) (1002:1002:1002))
        (PORT clk (1089:1089:1089) (1106:1106:1106))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (PORT d[0] (652:652:652) (726:726:726))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1071:1071:1071) (1087:1087:1087))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (741:741:741) (882:882:882))
        (PORT d[1] (710:710:710) (834:834:834))
        (PORT d[2] (710:710:710) (834:834:834))
        (PORT d[3] (737:737:737) (861:861:861))
        (PORT d[4] (737:737:737) (864:864:864))
        (PORT d[5] (885:885:885) (1039:1039:1039))
        (PORT d[6] (687:687:687) (804:804:804))
        (PORT d[7] (695:695:695) (814:814:814))
        (PORT d[8] (713:713:713) (841:841:841))
        (PORT d[9] (698:698:698) (807:807:807))
        (PORT d[10] (704:704:704) (821:821:821))
        (PORT d[11] (708:708:708) (830:830:830))
        (PORT d[12] (709:709:709) (830:830:830))
        (PORT clk (1088:1088:1088) (1105:1105:1105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (PORT d[0] (754:754:754) (674:674:674))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1089:1089:1089) (1106:1106:1106))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1070:1070:1070) (1086:1086:1086))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (611:611:611) (619:619:619))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datac (343:343:343) (405:405:405))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (918:918:918))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (119:119:119) (156:156:156))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (913:913:913) (918:918:918))
        (PORT d (37:37:37) (50:50:50))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (342:342:342) (390:390:390))
        (PORT datac (503:503:503) (576:576:576))
        (PORT datad (534:534:534) (639:639:639))
        (IOPATH datab combout (167:167:167) (167:167:167))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (902:902:902) (1061:1061:1061))
        (PORT d[1] (541:541:541) (647:647:647))
        (PORT d[2] (549:549:549) (652:652:652))
        (PORT d[3] (570:570:570) (678:678:678))
        (PORT d[4] (543:543:543) (639:639:639))
        (PORT d[5] (894:894:894) (1048:1048:1048))
        (PORT d[6] (530:530:530) (631:631:631))
        (PORT d[7] (520:520:520) (620:620:620))
        (PORT d[8] (555:555:555) (661:661:661))
        (PORT d[9] (827:827:827) (956:956:956))
        (PORT d[10] (807:807:807) (932:932:932))
        (PORT d[11] (518:518:518) (615:615:615))
        (PORT d[12] (549:549:549) (649:649:649))
        (PORT clk (1090:1090:1090) (1107:1107:1107))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1107:1107:1107))
        (PORT d[0] (497:497:497) (552:552:552))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1108:1108:1108))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1088:1088:1088))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (620:620:620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (621:621:621))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (709:709:709) (831:831:831))
        (PORT d[1] (717:717:717) (841:841:841))
        (PORT d[2] (701:701:701) (817:817:817))
        (PORT d[3] (729:729:729) (850:850:850))
        (PORT d[4] (722:722:722) (844:844:844))
        (PORT d[5] (871:871:871) (1018:1018:1018))
        (PORT d[6] (705:705:705) (825:825:825))
        (PORT d[7] (701:701:701) (821:821:821))
        (PORT d[8] (720:720:720) (849:849:849))
        (PORT d[9] (704:704:704) (814:814:814))
        (PORT d[10] (710:710:710) (828:828:828))
        (PORT d[11] (701:701:701) (817:817:817))
        (PORT d[12] (850:850:850) (983:983:983))
        (PORT clk (1087:1087:1087) (1104:1104:1104))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1087:1087:1087) (1104:1104:1104))
        (PORT d[0] (715:715:715) (641:641:641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1088:1088:1088) (1105:1105:1105))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1069:1069:1069) (1085:1085:1085))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (609:609:609) (617:617:617))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (610:610:610) (618:618:618))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (343:343:343) (396:396:396))
        (PORT datab (391:391:391) (482:482:482))
        (PORT datac (509:509:509) (578:578:578))
        (IOPATH dataa combout (170:170:170) (163:163:163))
        (IOPATH datab combout (190:190:190) (188:188:188))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1062:1062:1062) (1240:1240:1240))
        (PORT d[1] (678:678:678) (795:795:795))
        (PORT d[2] (707:707:707) (825:825:825))
        (PORT d[3] (722:722:722) (850:850:850))
        (PORT d[4] (698:698:698) (818:818:818))
        (PORT d[5] (1071:1071:1071) (1252:1252:1252))
        (PORT d[6] (680:680:680) (794:794:794))
        (PORT d[7] (766:766:766) (911:911:911))
        (PORT d[8] (671:671:671) (789:789:789))
        (PORT d[9] (687:687:687) (798:798:798))
        (PORT d[10] (701:701:701) (824:824:824))
        (PORT d[11] (668:668:668) (774:774:774))
        (PORT d[12] (699:699:699) (819:819:819))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (706:706:706) (636:636:636))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (418:418:418) (498:498:498))
        (PORT d[1] (350:350:350) (416:416:416))
        (PORT d[2] (841:841:841) (972:972:972))
        (PORT d[3] (659:659:659) (763:763:763))
        (PORT d[4] (523:523:523) (608:608:608))
        (PORT d[5] (581:581:581) (682:682:682))
        (PORT d[6] (662:662:662) (762:762:762))
        (PORT d[7] (686:686:686) (794:794:794))
        (PORT d[8] (846:846:846) (974:974:974))
        (PORT d[9] (689:689:689) (796:796:796))
        (PORT d[10] (686:686:686) (791:791:791))
        (PORT d[11] (665:665:665) (765:765:765))
        (PORT d[12] (681:681:681) (783:783:783))
        (PORT clk (1096:1096:1096) (1113:1113:1113))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1096:1096:1096) (1113:1113:1113))
        (PORT d[0] (487:487:487) (531:531:531))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1097:1097:1097) (1114:1114:1114))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1078:1078:1078) (1094:1094:1094))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (618:618:618) (626:626:626))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (619:619:619) (627:627:627))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (527:527:527) (627:627:627))
        (PORT datac (326:326:326) (367:367:367))
        (PORT datad (559:559:559) (635:635:635))
        (IOPATH datab combout (166:166:166) (176:176:176))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (870:870:870) (1017:1017:1017))
        (PORT d[1] (729:729:729) (858:858:858))
        (PORT d[2] (709:709:709) (832:832:832))
        (PORT d[3] (754:754:754) (885:885:885))
        (PORT d[4] (892:892:892) (1033:1033:1033))
        (PORT d[5] (722:722:722) (857:857:857))
        (PORT d[6] (718:718:718) (845:845:845))
        (PORT d[7] (702:702:702) (822:822:822))
        (PORT d[8] (708:708:708) (830:830:830))
        (PORT d[9] (718:718:718) (834:834:834))
        (PORT d[10] (724:724:724) (848:848:848))
        (PORT d[11] (702:702:702) (818:818:818))
        (PORT d[12] (705:705:705) (820:820:820))
        (PORT clk (1085:1085:1085) (1102:1102:1102))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1085:1085:1085) (1102:1102:1102))
        (PORT d[0] (637:637:637) (711:711:711))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1086:1086:1086) (1103:1103:1103))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1067:1067:1067) (1083:1083:1083))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (607:607:607) (615:615:615))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (608:608:608) (616:616:616))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (579:579:579) (682:682:682))
        (PORT d[1] (520:520:520) (610:610:610))
        (PORT d[2] (520:520:520) (605:605:605))
        (PORT d[3] (679:679:679) (778:778:778))
        (PORT d[4] (859:859:859) (988:988:988))
        (PORT d[5] (729:729:729) (849:849:849))
        (PORT d[6] (694:694:694) (798:798:798))
        (PORT d[7] (731:731:731) (845:845:845))
        (PORT d[8] (827:827:827) (954:954:954))
        (PORT d[9] (711:711:711) (819:819:819))
        (PORT d[10] (710:710:710) (819:819:819))
        (PORT d[11] (704:704:704) (814:814:814))
        (PORT d[12] (713:713:713) (817:817:817))
        (PORT clk (1090:1090:1090) (1108:1108:1108))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (104:104:104))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1090:1090:1090) (1108:1108:1108))
        (PORT d[0] (549:549:549) (505:505:505))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1091:1091:1091) (1109:1109:1109))
        (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1072:1072:1072) (1089:1089:1089))
        (IOPATH (posedge clk) q (164:164:164) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (25:25:25))
      (HOLD d (posedge clk) (90:90:90))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (612:612:612) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (613:613:613) (622:622:622))
        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (554:554:554) (662:662:662))
        (PORT datac (330:330:330) (371:371:371))
        (PORT datad (564:564:564) (639:639:639))
        (IOPATH datab combout (188:188:188) (177:177:177))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
)