85 lines
2.4 KiB
Verilog
85 lines
2.4 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:04:13 2014"
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module alu_mux_8(
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in0,
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in1,
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in2,
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in3,
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in4,
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in5,
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in6,
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in7,
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sel,
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out
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);
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input wire in0;
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input wire in1;
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input wire in2;
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input wire in3;
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input wire in4;
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input wire in5;
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input wire in6;
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input wire in7;
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input wire [2:0] sel;
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output wire out;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_17;
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wire SYNTHESIZED_WIRE_18;
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wire SYNTHESIZED_WIRE_19;
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assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0;
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assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1;
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assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2;
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assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3;
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assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4;
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assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5;
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assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6;
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assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7;
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assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
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assign SYNTHESIZED_WIRE_20 = ~sel[0];
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assign SYNTHESIZED_WIRE_21 = ~sel[1];
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assign SYNTHESIZED_WIRE_22 = ~sel[2];
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endmodule
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