56 lines
1.9 KiB
Verilog
56 lines
1.9 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:33:19 2014"
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module data_switch(
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sw_up_en,
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sw_down_en,
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db_down,
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db_up
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);
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input wire sw_up_en;
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input wire sw_down_en;
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inout wire [7:0] db_down;
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inout wire [7:0] db_up;
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assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
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assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
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assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
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assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
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assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
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assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
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assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
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assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
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assign db_down[7] = sw_down_en ? db_up[7] : 1'bz;
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assign db_down[6] = sw_down_en ? db_up[6] : 1'bz;
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assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
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assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
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assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
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assign db_down[2] = sw_down_en ? db_up[2] : 1'bz;
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assign db_down[1] = sw_down_en ? db_up[1] : 1'bz;
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assign db_down[0] = sw_down_en ? db_up[0] : 1'bz;
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endmodule
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