87 lines
3.0 KiB
Tcl
87 lines
3.0 KiB
Tcl
#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name "CLOCK_50" -period 50MHz [get_ports {CLOCK_50}]
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create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
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create_clock -name beep -period 10.000 [get_registers {ula:ula_|beep}]
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derive_pll_clocks -create_base_clocks
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -clock CLOCK_50 -max 2 [all_inputs]
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set_input_delay -clock CLOCK_50 -min 1 [all_inputs]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {CLOCK_50}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -clock CLOCK_50 10 [all_outputs]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous \
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-group [get_clocks {CLOCK_50}] \
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-group [get_clocks {clk_cpu}] \
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-group [get_clocks {KEY1}] \
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-group [get_clocks {beep}] \
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-group ula_|pll_|altpll_component|pll|clk[0] \
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-group ula_|pll_|altpll_component|pll|clk[1] \
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-group ula_|pll_|altpll_component|pll|clk[2]
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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