64 lines
1.7 KiB
Verilog
64 lines
1.7 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:01:36 2014"
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module alu_prep_daa(
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high,
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low,
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low_gt_9,
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high_eq_9,
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high_gt_9
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);
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input wire [3:0] high;
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input wire [3:0] low;
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output wire low_gt_9;
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output wire high_eq_9;
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output wire high_gt_9;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_5;
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assign SYNTHESIZED_WIRE_4 = ~high[2];
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assign SYNTHESIZED_WIRE_1 = low[3] & low[2];
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assign SYNTHESIZED_WIRE_3 = high[3] & high[2];
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assign SYNTHESIZED_WIRE_0 = low[3] & low[1];
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assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
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assign SYNTHESIZED_WIRE_2 = high[3] & high[1];
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assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
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assign SYNTHESIZED_WIRE_5 = ~high[1];
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assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
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endmodule
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