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de0-zx-spectrum/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP4CE22F17C6 Package FBGA256
//
//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "spectrum")
(DATE "03/30/2022 14:56:19")
(VENDOR "Altera")
(PROGRAM "Quartus II 32-bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[0\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1079:1079:1079) (1118:1118:1118))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[1\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1927:1927:1927) (1971:1971:1971))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[2\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1553:1553:1553) (1570:1570:1570))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[3\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2547:2547:2547) (2782:2782:2782))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[4\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1256:1256:1256) (1326:1326:1326))
(IOPATH i o (2582:2582:2582) (2502:2502:2502))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[5\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1315:1315:1315) (1355:1355:1355))
(IOPATH i o (4477:4477:4477) (4127:4127:4127))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[6\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1625:1625:1625) (1695:1695:1695))
(IOPATH i o (2455:2455:2455) (2378:2378:2378))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[7\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1490:1490:1490) (1603:1603:1603))
(IOPATH i o (4477:4477:4477) (4127:4127:4127))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[0\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1423:1423:1423) (1461:1461:1461))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[1\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1507:1507:1507) (1522:1522:1522))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[2\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1054:1054:1054) (1041:1041:1041))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[3\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1986:1986:1986) (2103:2103:2103))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[4\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1427:1427:1427) (1432:1432:1432))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[5\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1282:1282:1282) (1273:1273:1273))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[6\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1710:1710:1710) (1721:1721:1721))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[7\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1242:1242:1242) (1238:1238:1238))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[8\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1805:1805:1805) (1868:1868:1868))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[9\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1456:1456:1456) (1507:1507:1507))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[10\]\~output)
(DELAY
(ABSOLUTE
(PORT i (985:985:985) (976:976:976))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[11\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1324:1324:1324) (1362:1362:1362))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[12\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1106:1106:1106) (1123:1123:1123))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[13\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1331:1331:1331) (1387:1387:1387))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[14\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1729:1729:1729) (1767:1767:1767))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[15\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1595:1595:1595) (1671:1671:1671))
(IOPATH i o (4557:4557:4557) (4190:4190:4190))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[16\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2420:2420:2420) (2529:2529:2529))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[17\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2351:2351:2351) (2435:2435:2435))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[18\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2730:2730:2730) (2802:2802:2802))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[19\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1903:1903:1903) (1989:1989:1989))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[20\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1900:1900:1900) (1959:1959:1959))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[21\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2199:2199:2199) (2286:2286:2286))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[22\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2004:2004:2004) (2002:2002:2002))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[23\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2135:2135:2135) (2240:2240:2240))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[24\]\~output)
(DELAY
(ABSOLUTE
(PORT i (845:845:845) (883:883:883))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[25\]\~output)
(DELAY
(ABSOLUTE
(PORT i (812:812:812) (809:809:809))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[26\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1171:1171:1171) (1139:1139:1139))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[27\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1042:1042:1042) (1061:1061:1061))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[28\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1020:1020:1020) (1007:1007:1007))
(IOPATH i o (4557:4557:4557) (4190:4190:4190))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[29\]\~output)
(DELAY
(ABSOLUTE
(PORT i (988:988:988) (994:994:994))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[30\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1458:1458:1458) (1462:1462:1462))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE GPIO_0\[31\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1426:1426:1426) (1430:1430:1430))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_ibuf")
(INSTANCE CLOCK_50\~input)
(DELAY
(ABSOLUTE
(IOPATH i o (479:479:479) (732:732:732))
)
)
)
(CELL
(CELLTYPE "cycloneive_clkctrl")
(INSTANCE CLOCK_50\~inputclkctrl)
(DELAY
(ABSOLUTE
(PORT inclk[0] (154:154:154) (138:138:138))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[0\]\~63)
(DELAY
(ABSOLUTE
(IOPATH datac combout (353:353:353) (369:369:369))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[1\]\~21)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (345:345:345))
(PORT datab (251:251:251) (336:336:336))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[2\]\~23)
(DELAY
(ABSOLUTE
(PORT datab (251:251:251) (336:336:336))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[3\]\~25)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[4\]\~27)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[5\]\~29)
(DELAY
(ABSOLUTE
(PORT datab (263:263:263) (346:346:346))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[6\]\~31)
(DELAY
(ABSOLUTE
(PORT dataa (252:252:252) (342:342:342))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[7\]\~33)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[8\]\~35)
(DELAY
(ABSOLUTE
(PORT dataa (251:251:251) (341:341:341))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[9\]\~37)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (334:334:334))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[10\]\~39)
(DELAY
(ABSOLUTE
(PORT dataa (252:252:252) (340:340:340))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[11\]\~41)
(DELAY
(ABSOLUTE
(PORT datab (261:261:261) (343:343:343))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[12\]\~43)
(DELAY
(ABSOLUTE
(PORT datab (409:409:409) (473:473:473))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[13\]\~45)
(DELAY
(ABSOLUTE
(PORT dataa (403:403:403) (479:479:479))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[14\]\~47)
(DELAY
(ABSOLUTE
(PORT dataa (251:251:251) (342:342:342))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[14\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[15\]\~49)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (336:336:336))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[15\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[16\]\~51)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (343:343:343))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[16\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[17\]\~53)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (345:345:345))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[17\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[18\]\~55)
(DELAY
(ABSOLUTE
(PORT datab (252:252:252) (338:338:338))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[18\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[19\]\~57)
(DELAY
(ABSOLUTE
(PORT datab (252:252:252) (338:338:338))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[19\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[20\]\~59)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[20\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[21\]\~61)
(DELAY
(ABSOLUTE
(PORT datad (239:239:239) (309:309:309))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[21\])
(DELAY
(ABSOLUTE
(PORT clk (1525:1525:1525) (1538:1538:1538))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~7)
(DELAY
(ABSOLUTE
(PORT dataa (712:712:712) (771:771:771))
(PORT datac (699:699:699) (751:751:751))
(IOPATH dataa combout (371:371:371) (376:376:376))
(IOPATH datac combout (241:241:241) (241:241:241))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~5)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (343:343:343))
(PORT datab (251:251:251) (335:335:335))
(PORT datac (224:224:224) (303:303:303))
(PORT datad (225:225:225) (298:298:298))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~0)
(DELAY
(ABSOLUTE
(PORT dataa (252:252:252) (342:342:342))
(PORT datab (250:250:250) (335:335:335))
(PORT datac (223:223:223) (301:301:301))
(PORT datad (225:225:225) (297:297:297))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~1)
(DELAY
(ABSOLUTE
(PORT dataa (254:254:254) (346:346:346))
(PORT datab (253:253:253) (338:338:338))
(PORT datac (380:380:380) (441:441:441))
(PORT datad (226:226:226) (299:299:299))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~2)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (344:344:344))
(PORT datab (252:252:252) (337:337:337))
(PORT datac (224:224:224) (306:306:306))
(PORT datad (382:382:382) (438:438:438))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~3)
(DELAY
(ABSOLUTE
(PORT dataa (255:255:255) (346:346:346))
(PORT datab (253:253:253) (339:339:339))
(PORT datac (239:239:239) (316:316:316))
(PORT datad (240:240:240) (310:310:310))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~4)
(DELAY
(ABSOLUTE
(PORT dataa (388:388:388) (416:416:416))
(PORT datab (348:348:348) (385:385:385))
(PORT datac (348:348:348) (372:372:372))
(PORT datad (612:612:612) (622:622:622))
(IOPATH dataa combout (300:300:300) (307:307:307))
(IOPATH datab combout (300:300:300) (308:308:308))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[0\]\~40)
(DELAY
(ABSOLUTE
(PORT dataa (201:201:201) (245:245:245))
(PORT datab (634:634:634) (650:650:650))
(PORT datad (356:356:356) (373:373:373))
(IOPATH dataa combout (324:324:324) (328:328:328))
(IOPATH datab combout (333:333:333) (332:332:332))
(IOPATH datac combout (353:353:353) (369:369:369))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[1\]\~14)
(DELAY
(ABSOLUTE
(PORT dataa (454:454:454) (533:533:533))
(PORT datab (446:446:446) (522:522:522))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~6)
(DELAY
(ABSOLUTE
(PORT dataa (891:891:891) (951:951:951))
(PORT datab (672:672:672) (743:743:743))
(PORT datac (574:574:574) (595:595:595))
(PORT datad (195:195:195) (220:220:220))
(IOPATH dataa combout (301:301:301) (299:299:299))
(IOPATH datab combout (300:300:300) (308:308:308))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[2\]\~16)
(DELAY
(ABSOLUTE
(PORT datab (261:261:261) (343:343:343))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[3\]\~18)
(DELAY
(ABSOLUTE
(PORT datab (262:262:262) (344:344:344))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[4\]\~20)
(DELAY
(ABSOLUTE
(PORT dataa (264:264:264) (351:351:351))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(PORT ena (830:830:830) (846:846:846))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[5\]\~22)
(DELAY
(ABSOLUTE
(PORT datab (283:283:283) (365:365:365))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[6\]\~24)
(DELAY
(ABSOLUTE
(PORT dataa (285:285:285) (373:373:373))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[7\]\~26)
(DELAY
(ABSOLUTE
(PORT dataa (285:285:285) (373:373:373))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[8\]\~28)
(DELAY
(ABSOLUTE
(PORT datab (284:284:284) (367:367:367))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[9\]\~30)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[10\]\~32)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[11\]\~34)
(DELAY
(ABSOLUTE
(PORT datab (284:284:284) (368:368:368))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[12\]\~36)
(DELAY
(ABSOLUTE
(PORT dataa (266:266:266) (352:352:352))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(PORT ena (803:803:803) (805:805:805))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[13\]\~38)
(DELAY
(ABSOLUTE
(PORT datab (283:283:283) (366:366:366))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(PORT ena (830:830:830) (846:846:846))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2043:2043:2043) (2263:2263:2263))
(PORT d[1] (2019:2019:2019) (2202:2202:2202))
(PORT d[2] (1854:1854:1854) (2009:2009:2009))
(PORT d[3] (2468:2468:2468) (2633:2633:2633))
(PORT d[4] (2187:2187:2187) (2357:2357:2357))
(PORT d[5] (2172:2172:2172) (2317:2317:2317))
(PORT d[6] (2138:2138:2138) (2285:2285:2285))
(PORT d[7] (2050:2050:2050) (2279:2279:2279))
(PORT d[8] (2347:2347:2347) (2486:2486:2486))
(PORT d[9] (2169:2169:2169) (2346:2346:2346))
(PORT d[10] (2278:2278:2278) (2456:2456:2456))
(PORT d[11] (2295:2295:2295) (2429:2429:2429))
(PORT d[12] (2349:2349:2349) (2504:2504:2504))
(PORT clk (1857:1857:1857) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1882:1882:1882))
(PORT d[0] (1825:1825:1825) (1943:1943:1943))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1008:1008:1008))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datac (1619:1619:1619) (1769:1769:1769))
(IOPATH datac combout (243:243:243) (242:242:242))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1531:1531:1531) (1544:1544:1544))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (217:217:217) (286:286:286))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1531:1531:1531) (1544:1544:1544))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2095:2095:2095) (2299:2299:2299))
(PORT d[1] (1981:1981:1981) (2171:2171:2171))
(PORT d[2] (2178:2178:2178) (2333:2333:2333))
(PORT d[3] (2235:2235:2235) (2394:2394:2394))
(PORT d[4] (2150:2150:2150) (2298:2298:2298))
(PORT d[5] (2138:2138:2138) (2260:2260:2260))
(PORT d[6] (2153:2153:2153) (2309:2309:2309))
(PORT d[7] (2077:2077:2077) (2297:2297:2297))
(PORT d[8] (2333:2333:2333) (2484:2484:2484))
(PORT d[9] (2128:2128:2128) (2284:2284:2284))
(PORT d[10] (1989:1989:1989) (2169:2169:2169))
(PORT d[11] (2292:2292:2292) (2429:2429:2429))
(PORT d[12] (2279:2279:2279) (2438:2438:2438))
(PORT clk (1849:1849:1849) (1876:1876:1876))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(PORT d[0] (1788:1788:1788) (1705:1705:1705))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1839:1839:1839))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1003:1003:1003))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1003:1003:1003))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1003:1003:1003))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
(DELAY
(ABSOLUTE
(PORT dataa (925:925:925) (930:930:930))
(PORT datab (2498:2498:2498) (2712:2712:2712))
(PORT datac (903:903:903) (906:906:906))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datac combout (243:243:243) (242:242:242))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2065:2065:2065) (2268:2268:2268))
(PORT d[1] (1940:1940:1940) (2074:2074:2074))
(PORT d[2] (2079:2079:2079) (2206:2206:2206))
(PORT d[3] (2222:2222:2222) (2377:2377:2377))
(PORT d[4] (2175:2175:2175) (2348:2348:2348))
(PORT d[5] (1890:1890:1890) (2010:2010:2010))
(PORT d[6] (1854:1854:1854) (1985:1985:1985))
(PORT d[7] (2198:2198:2198) (2368:2368:2368))
(PORT d[8] (1757:1757:1757) (1867:1867:1867))
(PORT d[9] (2154:2154:2154) (2298:2298:2298))
(PORT d[10] (1641:1641:1641) (1806:1806:1806))
(PORT d[11] (2317:2317:2317) (2449:2449:2449))
(PORT d[12] (1976:1976:1976) (2131:2131:2131))
(PORT clk (1845:1845:1845) (1872:1872:1872))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1845:1845:1845) (1872:1872:1872))
(PORT d[0] (1789:1789:1789) (1707:1707:1707))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1873:1873:1873))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1808:1808:1808) (1835:1835:1835))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2019:2019:2019) (2227:2227:2227))
(PORT d[1] (1947:1947:1947) (2115:2115:2115))
(PORT d[2] (2170:2170:2170) (2334:2334:2334))
(PORT d[3] (2218:2218:2218) (2359:2359:2359))
(PORT d[4] (2158:2158:2158) (2329:2329:2329))
(PORT d[5] (1630:1630:1630) (1742:1742:1742))
(PORT d[6] (2095:2095:2095) (2239:2239:2239))
(PORT d[7] (2150:2150:2150) (2292:2292:2292))
(PORT d[8] (2149:2149:2149) (2291:2291:2291))
(PORT d[9] (2220:2220:2220) (2350:2350:2350))
(PORT d[10] (1655:1655:1655) (1834:1834:1834))
(PORT d[11] (2184:2184:2184) (2353:2353:2353))
(PORT d[12] (2144:2144:2144) (2362:2362:2362))
(PORT clk (1847:1847:1847) (1874:1874:1874))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1874:1874:1874))
(PORT d[0] (1680:1680:1680) (1746:1746:1746))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1810:1810:1810) (1837:1837:1837))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
(DELAY
(ABSOLUTE
(PORT datab (956:956:956) (993:993:993))
(PORT datac (927:927:927) (988:988:988))
(PORT datad (2737:2737:2737) (2929:2929:2929))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2114:2114:2114) (2311:2311:2311))
(PORT d[1] (1686:1686:1686) (1848:1848:1848))
(PORT d[2] (2168:2168:2168) (2314:2314:2314))
(PORT d[3] (2251:2251:2251) (2410:2410:2410))
(PORT d[4] (2142:2142:2142) (2284:2284:2284))
(PORT d[5] (1925:1925:1925) (2063:2063:2063))
(PORT d[6] (2081:2081:2081) (2241:2241:2241))
(PORT d[7] (2063:2063:2063) (2296:2296:2296))
(PORT d[8] (2131:2131:2131) (2296:2296:2296))
(PORT d[9] (2131:2131:2131) (2289:2289:2289))
(PORT d[10] (1732:1732:1732) (1913:1913:1913))
(PORT d[11] (2308:2308:2308) (2449:2449:2449))
(PORT d[12] (2190:2190:2190) (2407:2407:2407))
(PORT clk (1843:1843:1843) (1871:1871:1871))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1843:1843:1843) (1871:1871:1871))
(PORT d[0] (1818:1818:1818) (1733:1733:1733))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1806:1806:1806) (1834:1834:1834))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (997:997:997))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (992:992:992) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (992:992:992) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (992:992:992) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2045:2045:2045) (2260:2260:2260))
(PORT d[1] (2023:2023:2023) (2209:2209:2209))
(PORT d[2] (1962:1962:1962) (2121:2121:2121))
(PORT d[3] (2465:2465:2465) (2628:2628:2628))
(PORT d[4] (2184:2184:2184) (2381:2381:2381))
(PORT d[5] (1958:1958:1958) (2089:2089:2089))
(PORT d[6] (2196:2196:2196) (2345:2345:2345))
(PORT d[7] (2053:2053:2053) (2286:2286:2286))
(PORT d[8] (2335:2335:2335) (2452:2452:2452))
(PORT d[9] (2180:2180:2180) (2364:2364:2364))
(PORT d[10] (2313:2313:2313) (2485:2485:2485))
(PORT d[11] (2298:2298:2298) (2430:2430:2430))
(PORT d[12] (2225:2225:2225) (2392:2392:2392))
(PORT clk (1859:1859:1859) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1884:1884:1884))
(PORT d[0] (1894:1894:1894) (2005:2005:2005))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1007:1007:1007) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
(DELAY
(ABSOLUTE
(PORT dataa (964:964:964) (1029:1029:1029))
(PORT datac (2401:2401:2401) (2590:2590:2590))
(PORT datad (348:348:348) (364:364:364))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1733:1733:1733) (1922:1922:1922))
(PORT d[1] (1970:1970:1970) (2131:2131:2131))
(PORT d[2] (2159:2159:2159) (2306:2306:2306))
(PORT d[3] (2219:2219:2219) (2360:2360:2360))
(PORT d[4] (2084:2084:2084) (2195:2195:2195))
(PORT d[5] (1896:1896:1896) (1993:1993:1993))
(PORT d[6] (1827:1827:1827) (1951:1951:1951))
(PORT d[7] (1862:1862:1862) (1984:1984:1984))
(PORT d[8] (1868:1868:1868) (1994:1994:1994))
(PORT d[9] (1908:1908:1908) (2030:2030:2030))
(PORT d[10] (1767:1767:1767) (1972:1972:1972))
(PORT d[11] (1868:1868:1868) (1996:1996:1996))
(PORT d[12] (2048:2048:2048) (2130:2130:2130))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1685:1685:1685) (1767:1767:1767))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1982:1982:1982) (2177:2177:2177))
(PORT d[1] (1928:1928:1928) (2063:2063:2063))
(PORT d[2] (2166:2166:2166) (2327:2327:2327))
(PORT d[3] (2210:2210:2210) (2351:2351:2351))
(PORT d[4] (2129:2129:2129) (2252:2252:2252))
(PORT d[5] (1872:1872:1872) (1985:1985:1985))
(PORT d[6] (1796:1796:1796) (1941:1941:1941))
(PORT d[7] (1902:1902:1902) (2083:2083:2083))
(PORT d[8] (1861:1861:1861) (2011:2011:2011))
(PORT d[9] (2186:2186:2186) (2333:2333:2333))
(PORT d[10] (2118:2118:2118) (2300:2300:2300))
(PORT d[11] (1858:1858:1858) (2006:2006:2006))
(PORT d[12] (2105:2105:2105) (2343:2343:2343))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1792:1792:1792) (1727:1727:1727))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
(DELAY
(ABSOLUTE
(PORT dataa (726:726:726) (773:773:773))
(PORT datac (1897:1897:1897) (2091:2091:2091))
(PORT datad (348:348:348) (363:363:363))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2186:2186:2186) (2285:2285:2285))
(PORT clk (1857:1857:1857) (1885:1885:1885))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2065:2065:2065) (2268:2268:2268))
(PORT d[1] (2187:2187:2187) (2316:2316:2316))
(PORT d[2] (2211:2211:2211) (2384:2384:2384))
(PORT d[3] (2281:2281:2281) (2440:2440:2440))
(PORT d[4] (2169:2169:2169) (2344:2344:2344))
(PORT d[5] (2210:2210:2210) (2364:2364:2364))
(PORT d[6] (2149:2149:2149) (2283:2283:2283))
(PORT d[7] (2077:2077:2077) (2302:2302:2302))
(PORT d[8] (2367:2367:2367) (2522:2522:2522))
(PORT d[9] (2150:2150:2150) (2314:2314:2314))
(PORT d[10] (2027:2027:2027) (2231:2231:2231))
(PORT d[11] (2348:2348:2348) (2486:2486:2486))
(PORT d[12] (2333:2333:2333) (2496:2496:2496))
(PORT clk (1854:1854:1854) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1885:1885:1885))
(PORT d[0] (2022:2022:2022) (1911:1911:1911))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1817:1817:1817) (1844:1844:1844))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2191:2191:2191) (2290:2290:2290))
(PORT clk (1859:1859:1859) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2044:2044:2044) (2243:2243:2243))
(PORT d[1] (2233:2233:2233) (2365:2365:2365))
(PORT d[2] (2159:2159:2159) (2330:2330:2330))
(PORT d[3] (2282:2282:2282) (2440:2440:2440))
(PORT d[4] (2187:2187:2187) (2356:2356:2356))
(PORT d[5] (2211:2211:2211) (2364:2364:2364))
(PORT d[6] (2150:2150:2150) (2283:2283:2283))
(PORT d[7] (2078:2078:2078) (2302:2302:2302))
(PORT d[8] (2368:2368:2368) (2522:2522:2522))
(PORT d[9] (2151:2151:2151) (2314:2314:2314))
(PORT d[10] (2028:2028:2028) (2231:2231:2231))
(PORT d[11] (2349:2349:2349) (2486:2486:2486))
(PORT d[12] (2334:2334:2334) (2496:2496:2496))
(PORT clk (1855:1855:1855) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1886:1886:1886))
(PORT d[0] (2022:2022:2022) (1911:1911:1911))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3174:3174:3174) (3285:3285:3285))
(PORT clk (1864:1864:1864) (1891:1891:1891))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1967:1967:1967) (2086:2086:2086))
(PORT d[1] (2293:2293:2293) (2486:2486:2486))
(PORT d[2] (1954:1954:1954) (2112:2112:2112))
(PORT d[3] (1742:1742:1742) (1900:1900:1900))
(PORT d[4] (2207:2207:2207) (2364:2364:2364))
(PORT d[5] (1570:1570:1570) (1733:1733:1733))
(PORT d[6] (1787:1787:1787) (1945:1945:1945))
(PORT d[7] (1752:1752:1752) (1914:1914:1914))
(PORT d[8] (1950:1950:1950) (2065:2065:2065))
(PORT d[9] (1769:1769:1769) (1880:1880:1880))
(PORT d[10] (1682:1682:1682) (1838:1838:1838))
(PORT d[11] (2015:2015:2015) (2121:2121:2121))
(PORT d[12] (2067:2067:2067) (2250:2250:2250))
(PORT clk (1861:1861:1861) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1864:1864:1864) (1891:1891:1891))
(PORT d[0] (1283:1283:1283) (1352:1352:1352))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1892:1892:1892))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1892:1892:1892))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1892:1892:1892))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1892:1892:1892))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1824:1824:1824) (1850:1850:1850))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3179:3179:3179) (3290:3290:3290))
(PORT clk (1866:1866:1866) (1892:1892:1892))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1976:1976:1976) (2082:2082:2082))
(PORT d[1] (2294:2294:2294) (2486:2486:2486))
(PORT d[2] (1911:1911:1911) (2064:2064:2064))
(PORT d[3] (1743:1743:1743) (1900:1900:1900))
(PORT d[4] (2244:2244:2244) (2421:2421:2421))
(PORT d[5] (1571:1571:1571) (1733:1733:1733))
(PORT d[6] (1788:1788:1788) (1945:1945:1945))
(PORT d[7] (1753:1753:1753) (1914:1914:1914))
(PORT d[8] (1951:1951:1951) (2065:2065:2065))
(PORT d[9] (1770:1770:1770) (1880:1880:1880))
(PORT d[10] (1683:1683:1683) (1838:1838:1838))
(PORT d[11] (2016:2016:2016) (2121:2121:2121))
(PORT d[12] (2068:2068:2068) (2250:2250:2250))
(PORT clk (1862:1862:1862) (1889:1889:1889))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1866:1866:1866) (1892:1892:1892))
(PORT d[0] (1283:1283:1283) (1352:1352:1352))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1893:1893:1893))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1893:1893:1893))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1893:1893:1893))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1893:1893:1893))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1826:1826:1826) (1851:1851:1851))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0)
(DELAY
(ABSOLUTE
(PORT dataa (2697:2697:2697) (2912:2912:2912))
(PORT datac (642:642:642) (662:662:662))
(PORT datad (1091:1091:1091) (1109:1109:1109))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3157:3157:3157) (3259:3259:3259))
(PORT clk (1866:1866:1866) (1893:1893:1893))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1684:1684:1684) (1814:1814:1814))
(PORT d[1] (1912:1912:1912) (2072:2072:2072))
(PORT d[2] (1954:1954:1954) (2112:2112:2112))
(PORT d[3] (1766:1766:1766) (1915:1915:1915))
(PORT d[4] (1998:1998:1998) (2150:2150:2150))
(PORT d[5] (1881:1881:1881) (2064:2064:2064))
(PORT d[6] (1954:1954:1954) (2093:2093:2093))
(PORT d[7] (2034:2034:2034) (2198:2198:2198))
(PORT d[8] (1978:1978:1978) (2097:2097:2097))
(PORT d[9] (2037:2037:2037) (2220:2220:2220))
(PORT d[10] (1742:1742:1742) (1908:1908:1908))
(PORT d[11] (1966:1966:1966) (2088:2088:2088))
(PORT d[12] (2052:2052:2052) (2237:2237:2237))
(PORT clk (1863:1863:1863) (1889:1889:1889))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1866:1866:1866) (1893:1893:1893))
(PORT d[0] (1617:1617:1617) (1549:1549:1549))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1894:1894:1894))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1894:1894:1894))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1894:1894:1894))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1867:1867:1867) (1894:1894:1894))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1826:1826:1826) (1852:1852:1852))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3162:3162:3162) (3264:3264:3264))
(PORT clk (1868:1868:1868) (1894:1894:1894))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1694:1694:1694) (1812:1812:1812))
(PORT d[1] (1917:1917:1917) (2089:2089:2089))
(PORT d[2] (1911:1911:1911) (2064:2064:2064))
(PORT d[3] (1767:1767:1767) (1915:1915:1915))
(PORT d[4] (1977:1977:1977) (2126:2126:2126))
(PORT d[5] (1882:1882:1882) (2064:2064:2064))
(PORT d[6] (1955:1955:1955) (2093:2093:2093))
(PORT d[7] (2035:2035:2035) (2198:2198:2198))
(PORT d[8] (1979:1979:1979) (2097:2097:2097))
(PORT d[9] (2038:2038:2038) (2220:2220:2220))
(PORT d[10] (1743:1743:1743) (1908:1908:1908))
(PORT d[11] (1967:1967:1967) (2088:2088:2088))
(PORT d[12] (2053:2053:2053) (2237:2237:2237))
(PORT clk (1864:1864:1864) (1891:1891:1891))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1868:1868:1868) (1894:1894:1894))
(PORT d[0] (1617:1617:1617) (1549:1549:1549))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1869:1869:1869) (1895:1895:1895))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1869:1869:1869) (1895:1895:1895))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1869:1869:1869) (1895:1895:1895))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1869:1869:1869) (1895:1895:1895))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1828:1828:1828) (1853:1853:1853))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3172:3172:3172) (3285:3285:3285))
(PORT clk (1860:1860:1860) (1888:1888:1888))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1706:1706:1706) (1842:1842:1842))
(PORT d[1] (1974:1974:1974) (2127:2127:2127))
(PORT d[2] (1651:1651:1651) (1764:1764:1764))
(PORT d[3] (1724:1724:1724) (1872:1872:1872))
(PORT d[4] (1952:1952:1952) (2127:2127:2127))
(PORT d[5] (1542:1542:1542) (1700:1700:1700))
(PORT d[6] (2052:2052:2052) (2207:2207:2207))
(PORT d[7] (1747:1747:1747) (1911:1911:1911))
(PORT d[8] (1938:1938:1938) (2069:2069:2069))
(PORT d[9] (2028:2028:2028) (2200:2200:2200))
(PORT d[10] (2188:2188:2188) (2417:2417:2417))
(PORT d[11] (2008:2008:2008) (2111:2111:2111))
(PORT d[12] (2045:2045:2045) (2242:2242:2242))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1888:1888:1888))
(PORT d[0] (1283:1283:1283) (1352:1352:1352))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3177:3177:3177) (3290:3290:3290))
(PORT clk (1862:1862:1862) (1889:1889:1889))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1685:1685:1685) (1817:1817:1817))
(PORT d[1] (1975:1975:1975) (2132:2132:2132))
(PORT d[2] (1665:1665:1665) (1796:1796:1796))
(PORT d[3] (1725:1725:1725) (1872:1872:1872))
(PORT d[4] (1960:1960:1960) (2115:2115:2115))
(PORT d[5] (1543:1543:1543) (1700:1700:1700))
(PORT d[6] (2053:2053:2053) (2207:2207:2207))
(PORT d[7] (1748:1748:1748) (1911:1911:1911))
(PORT d[8] (1939:1939:1939) (2069:2069:2069))
(PORT d[9] (2029:2029:2029) (2200:2200:2200))
(PORT d[10] (2189:2189:2189) (2417:2417:2417))
(PORT d[11] (2009:2009:2009) (2111:2111:2111))
(PORT d[12] (2046:2046:2046) (2242:2242:2242))
(PORT clk (1858:1858:1858) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1862:1862:1862) (1889:1889:1889))
(PORT d[0] (1283:1283:1283) (1352:1352:1352))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1848:1848:1848))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1)
(DELAY
(ABSOLUTE
(PORT datab (271:271:271) (357:357:357))
(PORT datac (681:681:681) (694:694:694))
(PORT datad (348:348:348) (364:364:364))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (929:929:929) (968:968:968))
(PORT clk (1860:1860:1860) (1888:1888:1888))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1594:1594:1594) (1715:1715:1715))
(PORT d[1] (1702:1702:1702) (1831:1831:1831))
(PORT d[2] (1596:1596:1596) (1703:1703:1703))
(PORT d[3] (1706:1706:1706) (1830:1830:1830))
(PORT d[4] (1670:1670:1670) (1826:1826:1826))
(PORT d[5] (1479:1479:1479) (1627:1627:1627))
(PORT d[6] (1631:1631:1631) (1770:1770:1770))
(PORT d[7] (1937:1937:1937) (2048:2048:2048))
(PORT d[8] (1681:1681:1681) (1829:1829:1829))
(PORT d[9] (1735:1735:1735) (1889:1889:1889))
(PORT d[10] (1456:1456:1456) (1610:1610:1610))
(PORT d[11] (1888:1888:1888) (2010:2010:2010))
(PORT d[12] (1744:1744:1744) (1905:1905:1905))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1888:1888:1888))
(PORT d[0] (1312:1312:1312) (1246:1246:1246))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (934:934:934) (973:973:973))
(PORT clk (1862:1862:1862) (1889:1889:1889))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1617:1617:1617) (1734:1734:1734))
(PORT d[1] (1689:1689:1689) (1799:1799:1799))
(PORT d[2] (1610:1610:1610) (1731:1731:1731))
(PORT d[3] (1707:1707:1707) (1830:1830:1830))
(PORT d[4] (1671:1671:1671) (1832:1832:1832))
(PORT d[5] (1480:1480:1480) (1627:1627:1627))
(PORT d[6] (1632:1632:1632) (1770:1770:1770))
(PORT d[7] (1938:1938:1938) (2048:2048:2048))
(PORT d[8] (1682:1682:1682) (1829:1829:1829))
(PORT d[9] (1736:1736:1736) (1889:1889:1889))
(PORT d[10] (1457:1457:1457) (1610:1610:1610))
(PORT d[11] (1889:1889:1889) (2010:2010:2010))
(PORT d[12] (1745:1745:1745) (1905:1905:1905))
(PORT clk (1858:1858:1858) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1862:1862:1862) (1889:1889:1889))
(PORT d[0] (1312:1312:1312) (1246:1246:1246))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1848:1848:1848))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (901:901:901) (948:948:948))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1970:1970:1970) (2104:2104:2104))
(PORT d[1] (1716:1716:1716) (1847:1847:1847))
(PORT d[2] (1895:1895:1895) (2002:2002:2002))
(PORT d[3] (1692:1692:1692) (1826:1826:1826))
(PORT d[4] (1680:1680:1680) (1846:1846:1846))
(PORT d[5] (1484:1484:1484) (1636:1636:1636))
(PORT d[6] (1880:1880:1880) (2002:2002:2002))
(PORT d[7] (1679:1679:1679) (1844:1844:1844))
(PORT d[8] (1716:1716:1716) (1877:1877:1877))
(PORT d[9] (1718:1718:1718) (1874:1874:1874))
(PORT d[10] (1753:1753:1753) (1899:1899:1899))
(PORT d[11] (1880:1880:1880) (1999:1999:1999))
(PORT d[12] (1753:1753:1753) (1919:1919:1919))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1244:1244:1244) (1290:1290:1290))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (906:906:906) (953:953:953))
(PORT clk (1862:1862:1862) (1888:1888:1888))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1971:1971:1971) (2104:2104:2104))
(PORT d[1] (1695:1695:1695) (1822:1822:1822))
(PORT d[2] (1615:1615:1615) (1740:1740:1740))
(PORT d[3] (1693:1693:1693) (1826:1826:1826))
(PORT d[4] (1667:1667:1667) (1814:1814:1814))
(PORT d[5] (1485:1485:1485) (1636:1636:1636))
(PORT d[6] (1881:1881:1881) (2002:2002:2002))
(PORT d[7] (1680:1680:1680) (1844:1844:1844))
(PORT d[8] (1717:1717:1717) (1877:1877:1877))
(PORT d[9] (1719:1719:1719) (1874:1874:1874))
(PORT d[10] (1754:1754:1754) (1899:1899:1899))
(PORT d[11] (1881:1881:1881) (1999:1999:1999))
(PORT d[12] (1754:1754:1754) (1919:1919:1919))
(PORT clk (1858:1858:1858) (1885:1885:1885))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1862:1862:1862) (1888:1888:1888))
(PORT d[0] (1244:1244:1244) (1290:1290:1290))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2)
(DELAY
(ABSOLUTE
(PORT datab (992:992:992) (1034:1034:1034))
(PORT datac (735:735:735) (831:831:831))
(PORT datad (969:969:969) (1010:1010:1010))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3451:3451:3451) (3568:3568:3568))
(PORT clk (1855:1855:1855) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1695:1695:1695) (1821:1821:1821))
(PORT d[1] (1961:1961:1961) (2101:2101:2101))
(PORT d[2] (1635:1635:1635) (1763:1763:1763))
(PORT d[3] (1691:1691:1691) (1829:1829:1829))
(PORT d[4] (1958:1958:1958) (2143:2143:2143))
(PORT d[5] (1514:1514:1514) (1654:1654:1654))
(PORT d[6] (2088:2088:2088) (2262:2262:2262))
(PORT d[7] (1969:1969:1969) (2129:2129:2129))
(PORT d[8] (1996:1996:1996) (2177:2177:2177))
(PORT d[9] (2062:2062:2062) (2258:2258:2258))
(PORT d[10] (1974:1974:1974) (2129:2129:2129))
(PORT d[11] (1732:1732:1732) (1851:1851:1851))
(PORT d[12] (1780:1780:1780) (1964:1964:1964))
(PORT clk (1852:1852:1852) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1883:1883:1883))
(PORT d[0] (1309:1309:1309) (1248:1248:1248))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1815:1815:1815) (1842:1842:1842))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3456:3456:3456) (3573:3573:3573))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1705:1705:1705) (1819:1819:1819))
(PORT d[1] (1940:1940:1940) (2077:2077:2077))
(PORT d[2] (1677:1677:1677) (1808:1808:1808))
(PORT d[3] (1692:1692:1692) (1829:1829:1829))
(PORT d[4] (1945:1945:1945) (2111:2111:2111))
(PORT d[5] (1515:1515:1515) (1654:1654:1654))
(PORT d[6] (2089:2089:2089) (2262:2262:2262))
(PORT d[7] (1970:1970:1970) (2129:2129:2129))
(PORT d[8] (1997:1997:1997) (2177:2177:2177))
(PORT d[9] (2063:2063:2063) (2258:2258:2258))
(PORT d[10] (1975:1975:1975) (2129:2129:2129))
(PORT d[11] (1733:1733:1733) (1851:1851:1851))
(PORT d[12] (1781:1781:1781) (1964:1964:1964))
(PORT clk (1853:1853:1853) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(PORT d[0] (1309:1309:1309) (1248:1248:1248))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1817:1817:1817) (1843:1843:1843))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3433:3433:3433) (3533:3533:3533))
(PORT clk (1853:1853:1853) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1935:1935:1935) (2059:2059:2059))
(PORT d[1] (1879:1879:1879) (2055:2055:2055))
(PORT d[2] (1673:1673:1673) (1806:1806:1806))
(PORT d[3] (1719:1719:1719) (1862:1862:1862))
(PORT d[4] (2011:2011:2011) (2162:2162:2162))
(PORT d[5] (1532:1532:1532) (1674:1674:1674))
(PORT d[6] (2091:2091:2091) (2267:2267:2267))
(PORT d[7] (1723:1723:1723) (1889:1889:1889))
(PORT d[8] (1623:1623:1623) (1738:1738:1738))
(PORT d[9] (2043:2043:2043) (2237:2237:2237))
(PORT d[10] (1745:1745:1745) (1889:1889:1889))
(PORT d[11] (1993:1993:1993) (2111:2111:2111))
(PORT d[12] (2047:2047:2047) (2224:2224:2224))
(PORT clk (1850:1850:1850) (1877:1877:1877))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1881:1881:1881))
(PORT d[0] (1291:1291:1291) (1343:1343:1343))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1813:1813:1813) (1840:1840:1840))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3438:3438:3438) (3538:3538:3538))
(PORT clk (1855:1855:1855) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1990:1990:1990) (2109:2109:2109))
(PORT d[1] (1965:1965:1965) (2111:2111:2111))
(PORT d[2] (1674:1674:1674) (1806:1806:1806))
(PORT d[3] (1720:1720:1720) (1862:1862:1862))
(PORT d[4] (2012:2012:2012) (2162:2162:2162))
(PORT d[5] (1533:1533:1533) (1674:1674:1674))
(PORT d[6] (2092:2092:2092) (2267:2267:2267))
(PORT d[7] (1724:1724:1724) (1889:1889:1889))
(PORT d[8] (1624:1624:1624) (1738:1738:1738))
(PORT d[9] (2044:2044:2044) (2237:2237:2237))
(PORT d[10] (1746:1746:1746) (1889:1889:1889))
(PORT d[11] (1994:1994:1994) (2111:2111:2111))
(PORT d[12] (2048:2048:2048) (2224:2224:2224))
(PORT clk (1851:1851:1851) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(PORT d[0] (1291:1291:1291) (1343:1343:1343))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1815:1815:1815) (1841:1841:1841))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3)
(DELAY
(ABSOLUTE
(PORT datab (767:767:767) (864:864:864))
(PORT datac (674:674:674) (687:687:687))
(PORT datad (349:349:349) (365:365:365))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1759:1759:1759) (1954:1954:1954))
(PORT d[1] (1921:1921:1921) (2055:2055:2055))
(PORT d[2] (2115:2115:2115) (2262:2262:2262))
(PORT d[3] (2204:2204:2204) (2339:2339:2339))
(PORT d[4] (2144:2144:2144) (2260:2260:2260))
(PORT d[5] (1918:1918:1918) (2036:2036:2036))
(PORT d[6] (1770:1770:1770) (1893:1893:1893))
(PORT d[7] (1884:1884:1884) (2012:2012:2012))
(PORT d[8] (1882:1882:1882) (2030:2030:2030))
(PORT d[9] (1891:1891:1891) (2020:2020:2020))
(PORT d[10] (1752:1752:1752) (1953:1953:1953))
(PORT d[11] (1851:1851:1851) (1994:1994:1994))
(PORT d[12] (2201:2201:2201) (2421:2421:2421))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1875:1875:1875))
(PORT d[0] (1773:1773:1773) (1689:1689:1689))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2105:2105:2105) (2311:2311:2311))
(PORT d[1] (1947:1947:1947) (2084:2084:2084))
(PORT d[2] (2166:2166:2166) (2324:2324:2324))
(PORT d[3] (2248:2248:2248) (2396:2396:2396))
(PORT d[4] (2176:2176:2176) (2348:2348:2348))
(PORT d[5] (1952:1952:1952) (2095:2095:2095))
(PORT d[6] (2117:2117:2117) (2251:2251:2251))
(PORT d[7] (2058:2058:2058) (2288:2288:2288))
(PORT d[8] (2060:2060:2060) (2177:2177:2177))
(PORT d[9] (2163:2163:2163) (2322:2322:2322))
(PORT d[10] (1982:1982:1982) (2160:2160:2160))
(PORT d[11] (2269:2269:2269) (2403:2403:2403))
(PORT d[12] (2020:2020:2020) (2182:2182:2182))
(PORT clk (1846:1846:1846) (1873:1873:1873))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1873:1873:1873))
(PORT d[0] (1701:1701:1701) (1783:1783:1783))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1809:1809:1809) (1836:1836:1836))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
(DELAY
(ABSOLUTE
(PORT dataa (1172:1172:1172) (1214:1214:1214))
(PORT datac (2506:2506:2506) (2721:2721:2721))
(PORT datad (346:346:346) (361:361:361))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2054:2054:2054) (2271:2271:2271))
(PORT d[1] (1989:1989:1989) (2131:2131:2131))
(PORT d[2] (2133:2133:2133) (2280:2280:2280))
(PORT d[3] (2185:2185:2185) (2313:2313:2313))
(PORT d[4] (2173:2173:2173) (2323:2323:2323))
(PORT d[5] (1924:1924:1924) (2063:2063:2063))
(PORT d[6] (2151:2151:2151) (2279:2279:2279))
(PORT d[7] (2084:2084:2084) (2320:2320:2320))
(PORT d[8] (1814:1814:1814) (1935:1935:1935))
(PORT d[9] (2164:2164:2164) (2343:2343:2343))
(PORT d[10] (1715:1715:1715) (1899:1899:1899))
(PORT d[11] (2299:2299:2299) (2432:2432:2432))
(PORT d[12] (2017:2017:2017) (2181:2181:2181))
(PORT clk (1841:1841:1841) (1869:1869:1869))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1841:1841:1841) (1869:1869:1869))
(PORT d[0] (1694:1694:1694) (1761:1761:1761))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1842:1842:1842) (1870:1870:1870))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1804:1804:1804) (1832:1832:1832))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (995:995:995))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (990:990:990) (996:996:996))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (990:990:990) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (990:990:990) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2042:2042:2042) (2251:2251:2251))
(PORT d[1] (1726:1726:1726) (1880:1880:1880))
(PORT d[2] (2193:2193:2193) (2359:2359:2359))
(PORT d[3] (2213:2213:2213) (2374:2374:2374))
(PORT d[4] (2158:2158:2158) (2320:2320:2320))
(PORT d[5] (1641:1641:1641) (1756:1756:1756))
(PORT d[6] (2078:2078:2078) (2220:2220:2220))
(PORT d[7] (1942:1942:1942) (2112:2112:2112))
(PORT d[8] (1789:1789:1789) (1911:1911:1911))
(PORT d[9] (2199:2199:2199) (2326:2326:2326))
(PORT d[10] (1702:1702:1702) (1882:1882:1882))
(PORT d[11] (2172:2172:2172) (2318:2318:2318))
(PORT d[12] (2153:2153:2153) (2388:2388:2388))
(PORT clk (1846:1846:1846) (1873:1873:1873))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1873:1873:1873))
(PORT d[0] (1766:1766:1766) (1700:1700:1700))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1809:1809:1809) (1836:1836:1836))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
(DELAY
(ABSOLUTE
(PORT dataa (693:693:693) (733:733:733))
(PORT datac (925:925:925) (989:989:989))
(PORT datad (2699:2699:2699) (2890:2890:2890))
(IOPATH dataa combout (304:304:304) (308:308:308))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1958:1958:1958) (2119:2119:2119))
(PORT d[1] (1627:1627:1627) (1734:1734:1734))
(PORT d[2] (1870:1870:1870) (2003:2003:2003))
(PORT d[3] (1889:1889:1889) (1979:1979:1979))
(PORT d[4] (1810:1810:1810) (1926:1926:1926))
(PORT d[5] (1669:1669:1669) (1774:1774:1774))
(PORT d[6] (1873:1873:1873) (2001:2001:2001))
(PORT d[7] (1570:1570:1570) (1685:1685:1685))
(PORT d[8] (1579:1579:1579) (1703:1703:1703))
(PORT d[9] (1542:1542:1542) (1637:1637:1637))
(PORT d[10] (1774:1774:1774) (1984:1984:1984))
(PORT d[11] (1616:1616:1616) (1719:1719:1719))
(PORT d[12] (1777:1777:1777) (1896:1896:1896))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1741:1741:1741) (1677:1677:1677))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1696:1696:1696) (1855:1855:1855))
(PORT d[1] (1624:1624:1624) (1716:1716:1716))
(PORT d[2] (1829:1829:1829) (1941:1941:1941))
(PORT d[3] (1799:1799:1799) (1866:1866:1866))
(PORT d[4] (1795:1795:1795) (1904:1904:1904))
(PORT d[5] (1607:1607:1607) (1721:1721:1721))
(PORT d[6] (1527:1527:1527) (1632:1632:1632))
(PORT d[7] (1539:1539:1539) (1667:1667:1667))
(PORT d[8] (1561:1561:1561) (1665:1665:1665))
(PORT d[9] (1507:1507:1507) (1599:1599:1599))
(PORT d[10] (1787:1787:1787) (2014:2014:2014))
(PORT d[11] (1560:1560:1560) (1657:1657:1657))
(PORT d[12] (1765:1765:1765) (1857:1857:1857))
(PORT clk (1846:1846:1846) (1872:1872:1872))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1872:1872:1872))
(PORT d[0] (1628:1628:1628) (1667:1667:1667))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1873:1873:1873))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1809:1809:1809) (1835:1835:1835))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
(DELAY
(ABSOLUTE
(PORT dataa (726:726:726) (771:771:771))
(PORT datac (1862:1862:1862) (2046:2046:2046))
(PORT datad (959:959:959) (1001:1001:1001))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2034:2034:2034) (2233:2233:2233))
(PORT d[1] (1965:1965:1965) (2106:2106:2106))
(PORT d[2] (2209:2209:2209) (2367:2367:2367))
(PORT d[3] (2240:2240:2240) (2404:2404:2404))
(PORT d[4] (2184:2184:2184) (2357:2357:2357))
(PORT d[5] (2204:2204:2204) (2358:2358:2358))
(PORT d[6] (2164:2164:2164) (2290:2290:2290))
(PORT d[7] (2094:2094:2094) (2301:2301:2301))
(PORT d[8] (2332:2332:2332) (2483:2483:2483))
(PORT d[9] (1879:1879:1879) (2041:2041:2041))
(PORT d[10] (2031:2031:2031) (2222:2222:2222))
(PORT d[11] (2277:2277:2277) (2430:2430:2430))
(PORT d[12] (2315:2315:2315) (2497:2497:2497))
(PORT clk (1852:1852:1852) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1879:1879:1879))
(PORT d[0] (1813:1813:1813) (1728:1728:1728))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1815:1815:1815) (1842:1842:1842))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1005:1005:1005))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1001:1001:1001) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1001:1001:1001) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1001:1001:1001) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2036:2036:2036) (2238:2238:2238))
(PORT d[1] (2208:2208:2208) (2355:2355:2355))
(PORT d[2] (2290:2290:2290) (2482:2482:2482))
(PORT d[3] (2227:2227:2227) (2392:2392:2392))
(PORT d[4] (2188:2188:2188) (2350:2350:2350))
(PORT d[5] (2163:2163:2163) (2296:2296:2296))
(PORT d[6] (1938:1938:1938) (2096:2096:2096))
(PORT d[7] (2053:2053:2053) (2285:2285:2285))
(PORT d[8] (2038:2038:2038) (2172:2172:2172))
(PORT d[9] (2152:2152:2152) (2331:2331:2331))
(PORT d[10] (2012:2012:2012) (2207:2207:2207))
(PORT d[11] (2331:2331:2331) (2476:2476:2476))
(PORT d[12] (2240:2240:2240) (2416:2416:2416))
(PORT clk (1859:1859:1859) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1884:1884:1884))
(PORT d[0] (1909:1909:1909) (2020:2020:2020))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1007:1007:1007) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1008:1008:1008) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
(DELAY
(ABSOLUTE
(PORT datab (2760:2760:2760) (2963:2963:2963))
(PORT datac (556:556:556) (558:558:558))
(PORT datad (649:649:649) (676:676:676))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3478:3478:3478) (3599:3599:3599))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2019:2019:2019) (2126:2126:2126))
(PORT d[1] (1744:1744:1744) (1872:1872:1872))
(PORT d[2] (1727:1727:1727) (1824:1824:1824))
(PORT d[3] (1724:1724:1724) (1879:1879:1879))
(PORT d[4] (1958:1958:1958) (2143:2143:2143))
(PORT d[5] (1471:1471:1471) (1597:1597:1597))
(PORT d[6] (1707:1707:1707) (1863:1863:1863))
(PORT d[7] (2243:2243:2243) (2372:2372:2372))
(PORT d[8] (1971:1971:1971) (2145:2145:2145))
(PORT d[9] (1769:1769:1769) (1882:1882:1882))
(PORT d[10] (1445:1445:1445) (1602:1602:1602))
(PORT d[11] (2162:2162:2162) (2306:2306:2306))
(PORT d[12] (1740:1740:1740) (1899:1899:1899))
(PORT clk (1854:1854:1854) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(PORT d[0] (1319:1319:1319) (1255:1255:1255))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1817:1817:1817) (1843:1843:1843))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3483:3483:3483) (3604:3604:3604))
(PORT clk (1859:1859:1859) (1885:1885:1885))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2034:2034:2034) (2152:2152:2152))
(PORT d[1] (1723:1723:1723) (1848:1848:1848))
(PORT d[2] (1752:1752:1752) (1847:1847:1847))
(PORT d[3] (1725:1725:1725) (1879:1879:1879))
(PORT d[4] (1945:1945:1945) (2111:2111:2111))
(PORT d[5] (1472:1472:1472) (1597:1597:1597))
(PORT d[6] (1708:1708:1708) (1863:1863:1863))
(PORT d[7] (2244:2244:2244) (2372:2372:2372))
(PORT d[8] (1972:1972:1972) (2145:2145:2145))
(PORT d[9] (1770:1770:1770) (1882:1882:1882))
(PORT d[10] (1446:1446:1446) (1602:1602:1602))
(PORT d[11] (2163:2163:2163) (2306:2306:2306))
(PORT d[12] (1741:1741:1741) (1899:1899:1899))
(PORT clk (1855:1855:1855) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(PORT d[0] (1319:1319:1319) (1255:1255:1255))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1844:1844:1844))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3478:3478:3478) (3600:3600:3600))
(PORT clk (1858:1858:1858) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1943:1943:1943) (2073:2073:2073))
(PORT d[1] (1998:1998:1998) (2125:2125:2125))
(PORT d[2] (1904:1904:1904) (2028:2028:2028))
(PORT d[3] (1782:1782:1782) (1923:1923:1923))
(PORT d[4] (1950:1950:1950) (2124:2124:2124))
(PORT d[5] (1477:1477:1477) (1622:1622:1622))
(PORT d[6] (2045:2045:2045) (2181:2181:2181))
(PORT d[7] (1737:1737:1737) (1896:1896:1896))
(PORT d[8] (1640:1640:1640) (1754:1754:1754))
(PORT d[9] (2015:2015:2015) (2206:2206:2206))
(PORT d[10] (1977:1977:1977) (2149:2149:2149))
(PORT d[11] (2188:2188:2188) (2337:2337:2337))
(PORT d[12] (1746:1746:1746) (1924:1924:1924))
(PORT clk (1855:1855:1855) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(PORT d[0] (1256:1256:1256) (1318:1318:1318))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1818:1818:1818) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3483:3483:3483) (3605:3605:3605))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1989:1989:1989) (2122:2122:2122))
(PORT d[1] (2007:2007:2007) (2122:2122:2122))
(PORT d[2] (1944:1944:1944) (2065:2065:2065))
(PORT d[3] (1783:1783:1783) (1923:1923:1923))
(PORT d[4] (1951:1951:1951) (2130:2130:2130))
(PORT d[5] (1478:1478:1478) (1622:1622:1622))
(PORT d[6] (2046:2046:2046) (2181:2181:2181))
(PORT d[7] (1738:1738:1738) (1896:1896:1896))
(PORT d[8] (1641:1641:1641) (1754:1754:1754))
(PORT d[9] (2016:2016:2016) (2206:2206:2206))
(PORT d[10] (1978:1978:1978) (2149:2149:2149))
(PORT d[11] (2189:2189:2189) (2337:2337:2337))
(PORT d[12] (1747:1747:1747) (1924:1924:1924))
(PORT clk (1856:1856:1856) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1256:1256:1256) (1318:1318:1318))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4)
(DELAY
(ABSOLUTE
(PORT datab (270:270:270) (355:355:355))
(PORT datac (649:649:649) (696:696:696))
(PORT datad (965:965:965) (1003:1003:1003))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2795:2795:2795) (2881:2881:2881))
(PORT clk (1870:1870:1870) (1896:1896:1896))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1986:1986:1986) (2096:2096:2096))
(PORT d[1] (1924:1924:1924) (2104:2104:2104))
(PORT d[2] (1955:1955:1955) (2104:2104:2104))
(PORT d[3] (1736:1736:1736) (1899:1899:1899))
(PORT d[4] (2176:2176:2176) (2350:2350:2350))
(PORT d[5] (1843:1843:1843) (2000:2000:2000))
(PORT d[6] (2047:2047:2047) (2218:2218:2218))
(PORT d[7] (2035:2035:2035) (2190:2190:2190))
(PORT d[8] (1909:1909:1909) (2029:2029:2029))
(PORT d[9] (2025:2025:2025) (2217:2217:2217))
(PORT d[10] (2173:2173:2173) (2412:2412:2412))
(PORT d[11] (2021:2021:2021) (2147:2147:2147))
(PORT d[12] (2070:2070:2070) (2251:2251:2251))
(PORT clk (1867:1867:1867) (1892:1892:1892))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1896:1896:1896))
(PORT d[0] (1526:1526:1526) (1593:1593:1593))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1830:1830:1830) (1855:1855:1855))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2800:2800:2800) (2886:2886:2886))
(PORT clk (1872:1872:1872) (1897:1897:1897))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1987:1987:1987) (2103:2103:2103))
(PORT d[1] (1947:1947:1947) (2127:2127:2127))
(PORT d[2] (1956:1956:1956) (2104:2104:2104))
(PORT d[3] (1737:1737:1737) (1899:1899:1899))
(PORT d[4] (2222:2222:2222) (2399:2399:2399))
(PORT d[5] (1844:1844:1844) (2000:2000:2000))
(PORT d[6] (2048:2048:2048) (2218:2218:2218))
(PORT d[7] (2036:2036:2036) (2190:2190:2190))
(PORT d[8] (1910:1910:1910) (2029:2029:2029))
(PORT d[9] (2026:2026:2026) (2217:2217:2217))
(PORT d[10] (2174:2174:2174) (2412:2412:2412))
(PORT d[11] (2022:2022:2022) (2147:2147:2147))
(PORT d[12] (2071:2071:2071) (2251:2251:2251))
(PORT clk (1868:1868:1868) (1894:1894:1894))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1897:1897:1897))
(PORT d[0] (1526:1526:1526) (1593:1593:1593))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1832:1832:1832) (1856:1856:1856))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2785:2785:2785) (2862:2862:2862))
(PORT clk (1870:1870:1870) (1897:1897:1897))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1953:1953:1953) (2079:2079:2079))
(PORT d[1] (1947:1947:1947) (2130:2130:2130))
(PORT d[2] (1994:1994:1994) (2095:2095:2095))
(PORT d[3] (1760:1760:1760) (1926:1926:1926))
(PORT d[4] (2185:2185:2185) (2357:2357:2357))
(PORT d[5] (1741:1741:1741) (1881:1881:1881))
(PORT d[6] (2007:2007:2007) (2161:2161:2161))
(PORT d[7] (2039:2039:2039) (2194:2194:2194))
(PORT d[8] (2281:2281:2281) (2397:2397:2397))
(PORT d[9] (2052:2052:2052) (2249:2249:2249))
(PORT d[10] (1662:1662:1662) (1830:1830:1830))
(PORT d[11] (1999:1999:1999) (2122:2122:2122))
(PORT d[12] (2091:2091:2091) (2299:2299:2299))
(PORT clk (1867:1867:1867) (1893:1893:1893))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1897:1897:1897))
(PORT d[0] (1591:1591:1591) (1526:1526:1526))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1830:1830:1830) (1856:1856:1856))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2790:2790:2790) (2867:2867:2867))
(PORT clk (1872:1872:1872) (1898:1898:1898))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1967:1967:1967) (2105:2105:2105))
(PORT d[1] (1926:1926:1926) (2106:2106:2106))
(PORT d[2] (2313:2313:2313) (2399:2399:2399))
(PORT d[3] (1761:1761:1761) (1926:1926:1926))
(PORT d[4] (1962:1962:1962) (2131:2131:2131))
(PORT d[5] (1742:1742:1742) (1881:1881:1881))
(PORT d[6] (2008:2008:2008) (2161:2161:2161))
(PORT d[7] (2040:2040:2040) (2194:2194:2194))
(PORT d[8] (2282:2282:2282) (2397:2397:2397))
(PORT d[9] (2053:2053:2053) (2249:2249:2249))
(PORT d[10] (1663:1663:1663) (1830:1830:1830))
(PORT d[11] (2000:2000:2000) (2122:2122:2122))
(PORT d[12] (2092:2092:2092) (2299:2299:2299))
(PORT clk (1868:1868:1868) (1895:1895:1895))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1898:1898:1898))
(PORT d[0] (1591:1591:1591) (1526:1526:1526))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1832:1832:1832) (1857:1857:1857))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5)
(DELAY
(ABSOLUTE
(PORT datab (635:635:635) (645:645:645))
(PORT datac (993:993:993) (1070:1070:1070))
(PORT datad (902:902:902) (910:910:910))
(IOPATH datab combout (342:342:342) (342:342:342))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2129:2129:2129) (2209:2209:2209))
(PORT clk (1862:1862:1862) (1889:1889:1889))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2080:2080:2080) (2290:2290:2290))
(PORT d[1] (1984:1984:1984) (2161:2161:2161))
(PORT d[2] (1864:1864:1864) (2019:2019:2019))
(PORT d[3] (2469:2469:2469) (2619:2619:2619))
(PORT d[4] (2505:2505:2505) (2677:2677:2677))
(PORT d[5] (2155:2155:2155) (2279:2279:2279))
(PORT d[6] (2240:2240:2240) (2392:2392:2392))
(PORT d[7] (2203:2203:2203) (2386:2386:2386))
(PORT d[8] (2230:2230:2230) (2405:2405:2405))
(PORT d[9] (2206:2206:2206) (2378:2378:2378))
(PORT d[10] (2026:2026:2026) (2221:2221:2221))
(PORT d[11] (2288:2288:2288) (2426:2426:2426))
(PORT d[12] (2218:2218:2218) (2381:2381:2381))
(PORT clk (1859:1859:1859) (1885:1885:1885))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1862:1862:1862) (1889:1889:1889))
(PORT d[0] (1896:1896:1896) (2026:2026:2026))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1863:1863:1863) (1890:1890:1890))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1848:1848:1848))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2134:2134:2134) (2214:2214:2214))
(PORT clk (1864:1864:1864) (1890:1890:1890))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2073:2073:2073) (2293:2293:2293))
(PORT d[1] (2007:2007:2007) (2186:2186:2186))
(PORT d[2] (1860:1860:1860) (2030:2030:2030))
(PORT d[3] (2470:2470:2470) (2619:2619:2619))
(PORT d[4] (2337:2337:2337) (2481:2481:2481))
(PORT d[5] (2156:2156:2156) (2279:2279:2279))
(PORT d[6] (2241:2241:2241) (2392:2392:2392))
(PORT d[7] (2204:2204:2204) (2386:2386:2386))
(PORT d[8] (2231:2231:2231) (2405:2405:2405))
(PORT d[9] (2207:2207:2207) (2378:2378:2378))
(PORT d[10] (2027:2027:2027) (2221:2221:2221))
(PORT d[11] (2289:2289:2289) (2426:2426:2426))
(PORT d[12] (2219:2219:2219) (2381:2381:2381))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1864:1864:1864) (1890:1890:1890))
(PORT d[0] (1896:1896:1896) (2026:2026:2026))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1891:1891:1891))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1891:1891:1891))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1891:1891:1891))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1865:1865:1865) (1891:1891:1891))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1824:1824:1824) (1849:1849:1849))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3173:3173:3173) (3286:3286:3286))
(PORT clk (1857:1857:1857) (1885:1885:1885))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1718:1718:1718) (1848:1848:1848))
(PORT d[1] (2002:2002:2002) (2154:2154:2154))
(PORT d[2] (1745:1745:1745) (1851:1851:1851))
(PORT d[3] (1732:1732:1732) (1875:1875:1875))
(PORT d[4] (1993:1993:1993) (2145:2145:2145))
(PORT d[5] (1514:1514:1514) (1664:1664:1664))
(PORT d[6] (2087:2087:2087) (2261:2261:2261))
(PORT d[7] (2026:2026:2026) (2179:2179:2179))
(PORT d[8] (1911:1911:1911) (2044:2044:2044))
(PORT d[9] (2000:2000:2000) (2165:2165:2165))
(PORT d[10] (1691:1691:1691) (1849:1849:1849))
(PORT d[11] (1991:1991:1991) (2092:2092:2092))
(PORT d[12] (2025:2025:2025) (2206:2206:2206))
(PORT clk (1854:1854:1854) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1885:1885:1885))
(PORT d[0] (1365:1365:1365) (1299:1299:1299))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1886:1886:1886))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1817:1817:1817) (1844:1844:1844))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3178:3178:3178) (3291:3291:3291))
(PORT clk (1859:1859:1859) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1697:1697:1697) (1824:1824:1824))
(PORT d[1] (1990:1990:1990) (2122:2122:2122))
(PORT d[2] (1947:1947:1947) (2080:2080:2080))
(PORT d[3] (1733:1733:1733) (1875:1875:1875))
(PORT d[4] (1994:1994:1994) (2145:2145:2145))
(PORT d[5] (1515:1515:1515) (1664:1664:1664))
(PORT d[6] (2088:2088:2088) (2261:2261:2261))
(PORT d[7] (2027:2027:2027) (2179:2179:2179))
(PORT d[8] (1912:1912:1912) (2044:2044:2044))
(PORT d[9] (2001:2001:2001) (2165:2165:2165))
(PORT d[10] (1692:1692:1692) (1849:1849:1849))
(PORT d[11] (1992:1992:1992) (2092:2092:2092))
(PORT d[12] (2026:2026:2026) (2206:2206:2206))
(PORT clk (1855:1855:1855) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1886:1886:1886))
(PORT d[0] (1365:1365:1365) (1299:1299:1299))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6)
(DELAY
(ABSOLUTE
(PORT dataa (2229:2229:2229) (2452:2452:2452))
(PORT datac (917:917:917) (935:935:935))
(PORT datad (1306:1306:1306) (1332:1332:1332))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2883:2883:2883) (2988:2988:2988))
(PORT clk (1869:1869:1869) (1895:1895:1895))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1960:1960:1960) (2086:2086:2086))
(PORT d[1] (1945:1945:1945) (2125:2125:2125))
(PORT d[2] (1971:1971:1971) (2132:2132:2132))
(PORT d[3] (1766:1766:1766) (1913:1913:1913))
(PORT d[4] (1945:1945:1945) (2126:2126:2126))
(PORT d[5] (1865:1865:1865) (2025:2025:2025))
(PORT d[6] (2059:2059:2059) (2199:2199:2199))
(PORT d[7] (1959:1959:1959) (2120:2120:2120))
(PORT d[8] (2245:2245:2245) (2378:2378:2378))
(PORT d[9] (2021:2021:2021) (2210:2210:2210))
(PORT d[10] (2196:2196:2196) (2442:2442:2442))
(PORT d[11] (2254:2254:2254) (2367:2367:2367))
(PORT d[12] (2061:2061:2061) (2263:2263:2263))
(PORT clk (1866:1866:1866) (1891:1891:1891))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1869:1869:1869) (1895:1895:1895))
(PORT d[0] (1539:1539:1539) (1603:1603:1603))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1896:1896:1896))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1896:1896:1896))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1896:1896:1896))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1870:1870:1870) (1896:1896:1896))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1829:1829:1829) (1854:1854:1854))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2888:2888:2888) (2993:2993:2993))
(PORT clk (1871:1871:1871) (1896:1896:1896))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1939:1939:1939) (2062:2062:2062))
(PORT d[1] (1933:1933:1933) (2100:2100:2100))
(PORT d[2] (1928:1928:1928) (2069:2069:2069))
(PORT d[3] (1767:1767:1767) (1913:1913:1913))
(PORT d[4] (1924:1924:1924) (2101:2101:2101))
(PORT d[5] (1866:1866:1866) (2025:2025:2025))
(PORT d[6] (2060:2060:2060) (2199:2199:2199))
(PORT d[7] (1960:1960:1960) (2120:2120:2120))
(PORT d[8] (2246:2246:2246) (2378:2378:2378))
(PORT d[9] (2022:2022:2022) (2210:2210:2210))
(PORT d[10] (2197:2197:2197) (2442:2442:2442))
(PORT d[11] (2255:2255:2255) (2367:2367:2367))
(PORT d[12] (2062:2062:2062) (2263:2263:2263))
(PORT clk (1867:1867:1867) (1893:1893:1893))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1896:1896:1896))
(PORT d[0] (1539:1539:1539) (1603:1603:1603))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1897:1897:1897))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1831:1831:1831) (1855:1855:1855))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2303:2303:2303) (2389:2389:2389))
(PORT clk (1871:1871:1871) (1898:1898:1898))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1974:1974:1974) (2117:2117:2117))
(PORT d[1] (1926:1926:1926) (2107:2107:2107))
(PORT d[2] (1892:1892:1892) (2023:2023:2023))
(PORT d[3] (2018:2018:2018) (2177:2177:2177))
(PORT d[4] (2218:2218:2218) (2413:2413:2413))
(PORT d[5] (1772:1772:1772) (1925:1925:1925))
(PORT d[6] (2015:2015:2015) (2155:2155:2155))
(PORT d[7] (2023:2023:2023) (2199:2199:2199))
(PORT d[8] (1873:1873:1873) (2013:2013:2013))
(PORT d[9] (2016:2016:2016) (2205:2205:2205))
(PORT d[10] (2301:2301:2301) (2478:2478:2478))
(PORT d[11] (2004:2004:2004) (2138:2138:2138))
(PORT d[12] (2070:2070:2070) (2273:2273:2273))
(PORT clk (1868:1868:1868) (1894:1894:1894))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1871:1871:1871) (1898:1898:1898))
(PORT d[0] (1618:1618:1618) (1535:1535:1535))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1872:1872:1872) (1899:1899:1899))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1831:1831:1831) (1857:1857:1857))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2308:2308:2308) (2394:2394:2394))
(PORT clk (1873:1873:1873) (1899:1899:1899))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1952:1952:1952) (2092:2092:2092))
(PORT d[1] (1927:1927:1927) (2107:2107:2107))
(PORT d[2] (1907:1907:1907) (2055:2055:2055))
(PORT d[3] (2019:2019:2019) (2177:2177:2177))
(PORT d[4] (2241:2241:2241) (2431:2431:2431))
(PORT d[5] (1773:1773:1773) (1925:1925:1925))
(PORT d[6] (2016:2016:2016) (2155:2155:2155))
(PORT d[7] (2024:2024:2024) (2199:2199:2199))
(PORT d[8] (1874:1874:1874) (2013:2013:2013))
(PORT d[9] (2017:2017:2017) (2205:2205:2205))
(PORT d[10] (2302:2302:2302) (2478:2478:2478))
(PORT d[11] (2005:2005:2005) (2138:2138:2138))
(PORT d[12] (2071:2071:2071) (2273:2273:2273))
(PORT clk (1869:1869:1869) (1896:1896:1896))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1873:1873:1873) (1899:1899:1899))
(PORT d[0] (1618:1618:1618) (1535:1535:1535))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1874:1874:1874) (1900:1900:1900))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1874:1874:1874) (1900:1900:1900))
(IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1874:1874:1874) (1900:1900:1900))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1874:1874:1874) (1900:1900:1900))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1833:1833:1833) (1858:1858:1858))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7)
(DELAY
(ABSOLUTE
(PORT dataa (591:591:591) (604:604:604))
(PORT datac (867:867:867) (931:931:931))
(PORT datad (655:655:655) (682:682:682))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE A\[14\]\~41)
(DELAY
(ABSOLUTE
(PORT dataa (286:286:286) (374:374:374))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH cin combout (455:455:455) (437:437:437))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE A\[14\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(PORT ena (830:830:830) (846:846:846))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0)
(DELAY
(ABSOLUTE
(PORT datac (612:612:612) (670:670:670))
(PORT datad (450:450:450) (522:522:522))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2168:2168:2168) (2212:2212:2212))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1337:1337:1337) (1420:1420:1420))
(PORT d[1] (1328:1328:1328) (1430:1430:1430))
(PORT d[2] (1364:1364:1364) (1439:1439:1439))
(PORT d[3] (1355:1355:1355) (1417:1417:1417))
(PORT d[4] (1299:1299:1299) (1403:1403:1403))
(PORT d[5] (1278:1278:1278) (1332:1332:1332))
(PORT d[6] (1295:1295:1295) (1405:1405:1405))
(PORT d[7] (1499:1499:1499) (1598:1598:1598))
(PORT d[8] (1363:1363:1363) (1461:1461:1461))
(PORT d[9] (1332:1332:1332) (1422:1422:1422))
(PORT d[10] (1336:1336:1336) (1423:1423:1423))
(PORT d[11] (1346:1346:1346) (1428:1428:1428))
(PORT d[12] (1391:1391:1391) (1503:1503:1503))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (982:982:982) (966:966:966))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2)
(DELAY
(ABSOLUTE
(PORT datac (611:611:611) (671:671:671))
(PORT datad (452:452:452) (521:521:521))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (905:905:905) (924:924:924))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1580:1580:1580) (1688:1688:1688))
(PORT d[1] (1302:1302:1302) (1409:1409:1409))
(PORT d[2] (1611:1611:1611) (1712:1712:1712))
(PORT d[3] (1734:1734:1734) (1874:1874:1874))
(PORT d[4] (1682:1682:1682) (1815:1815:1815))
(PORT d[5] (1491:1491:1491) (1641:1641:1641))
(PORT d[6] (1673:1673:1673) (1775:1775:1775))
(PORT d[7] (1894:1894:1894) (1992:1992:1992))
(PORT d[8] (1660:1660:1660) (1786:1786:1786))
(PORT d[9] (1691:1691:1691) (1820:1820:1820))
(PORT d[10] (1748:1748:1748) (1931:1931:1931))
(PORT d[11] (1900:1900:1900) (2024:2024:2024))
(PORT d[12] (1764:1764:1764) (1943:1943:1943))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1353:1353:1353) (1332:1332:1332))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\])
(DELAY
(ABSOLUTE
(PORT datac (612:612:612) (671:671:671))
(PORT datad (451:451:451) (521:521:521))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2579:2579:2579) (2676:2676:2676))
(PORT clk (1845:1845:1845) (1873:1873:1873))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1784:1784:1784) (1877:1877:1877))
(PORT d[1] (1842:1842:1842) (1972:1972:1972))
(PORT d[2] (1490:1490:1490) (1579:1579:1579))
(PORT d[3] (1483:1483:1483) (1540:1540:1540))
(PORT d[4] (1539:1539:1539) (1619:1619:1619))
(PORT d[5] (1318:1318:1318) (1397:1397:1397))
(PORT d[6] (1554:1554:1554) (1660:1660:1660))
(PORT d[7] (1764:1764:1764) (1873:1873:1873))
(PORT d[8] (1286:1286:1286) (1377:1377:1377))
(PORT d[9] (1242:1242:1242) (1310:1310:1310))
(PORT d[10] (1262:1262:1262) (1360:1360:1360))
(PORT d[11] (1317:1317:1317) (1401:1401:1401))
(PORT d[12] (1190:1190:1190) (1255:1255:1255))
(PORT clk (1842:1842:1842) (1869:1869:1869))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1845:1845:1845) (1873:1873:1873))
(PORT d[0] (1069:1069:1069) (1039:1039:1039))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1805:1805:1805) (1832:1832:1832))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (990:990:990) (995:995:995))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1)
(DELAY
(ABSOLUTE
(PORT datac (610:610:610) (668:668:668))
(PORT datad (448:448:448) (518:518:518))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2427:2427:2427) (2508:2508:2508))
(PORT clk (1859:1859:1859) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1028:1028:1028) (1117:1117:1117))
(PORT d[1] (1049:1049:1049) (1160:1160:1160))
(PORT d[2] (1086:1086:1086) (1148:1148:1148))
(PORT d[3] (1062:1062:1062) (1134:1134:1134))
(PORT d[4] (1559:1559:1559) (1650:1650:1650))
(PORT d[5] (1057:1057:1057) (1151:1151:1151))
(PORT d[6] (1108:1108:1108) (1213:1213:1213))
(PORT d[7] (1269:1269:1269) (1366:1366:1366))
(PORT d[8] (1333:1333:1333) (1424:1424:1424))
(PORT d[9] (1102:1102:1102) (1207:1207:1207))
(PORT d[10] (1349:1349:1349) (1437:1437:1437))
(PORT d[11] (1129:1129:1129) (1210:1210:1210))
(PORT d[12] (1284:1284:1284) (1360:1360:1360))
(PORT clk (1856:1856:1856) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1886:1886:1886))
(PORT d[0] (846:846:846) (828:828:828))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1008:1008:1008))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (657:657:657) (705:705:705))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1889:1889:1889) (1911:1911:1911))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (220:220:220) (290:290:290))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1523:1523:1523) (1536:1536:1536))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
(DELAY
(ABSOLUTE
(PORT dataa (1852:1852:1852) (1977:1977:1977))
(PORT datab (1135:1135:1135) (1147:1147:1147))
(PORT datac (855:855:855) (891:891:891))
(PORT datad (274:274:274) (357:357:357))
(IOPATH dataa combout (371:371:371) (376:376:376))
(IOPATH datab combout (355:355:355) (349:349:349))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1)
(DELAY
(ABSOLUTE
(PORT dataa (1172:1172:1172) (1209:1209:1209))
(PORT datab (1425:1425:1425) (1483:1483:1483))
(PORT datac (170:170:170) (203:203:203))
(PORT datad (274:274:274) (357:357:357))
(IOPATH dataa combout (303:303:303) (308:308:308))
(IOPATH datab combout (306:306:306) (308:308:308))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1911:1911:1911) (1992:1992:1992))
(PORT clk (1851:1851:1851) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2172:2172:2172) (2339:2339:2339))
(PORT d[1] (1564:1564:1564) (1694:1694:1694))
(PORT d[2] (1725:1725:1725) (1839:1839:1839))
(PORT d[3] (1747:1747:1747) (1811:1811:1811))
(PORT d[4] (1741:1741:1741) (1810:1810:1810))
(PORT d[5] (1548:1548:1548) (1644:1644:1644))
(PORT d[6] (1530:1530:1530) (1633:1633:1633))
(PORT d[7] (1459:1459:1459) (1557:1557:1557))
(PORT d[8] (1541:1541:1541) (1649:1649:1649))
(PORT d[9] (1471:1471:1471) (1529:1529:1529))
(PORT d[10] (1489:1489:1489) (1593:1593:1593))
(PORT d[11] (1557:1557:1557) (1641:1641:1641))
(PORT d[12] (1770:1770:1770) (1827:1827:1827))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(PORT d[0] (1273:1273:1273) (1267:1267:1267))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2250:2250:2250) (2330:2330:2330))
(PORT clk (1851:1851:1851) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1978:1978:1978) (2147:2147:2147))
(PORT d[1] (1517:1517:1517) (1633:1633:1633))
(PORT d[2] (1736:1736:1736) (1836:1836:1836))
(PORT d[3] (1746:1746:1746) (1798:1798:1798))
(PORT d[4] (1738:1738:1738) (1807:1807:1807))
(PORT d[5] (1573:1573:1573) (1658:1658:1658))
(PORT d[6] (1555:1555:1555) (1647:1647:1647))
(PORT d[7] (1442:1442:1442) (1529:1529:1529))
(PORT d[8] (1539:1539:1539) (1634:1634:1634))
(PORT d[9] (1492:1492:1492) (1553:1553:1553))
(PORT d[10] (1509:1509:1509) (1617:1617:1617))
(PORT d[11] (1582:1582:1582) (1654:1654:1654))
(PORT d[12] (1740:1740:1740) (1798:1798:1798))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(PORT d[0] (1245:1245:1245) (1209:1209:1209))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2717:2717:2717) (2805:2805:2805))
(PORT clk (1854:1854:1854) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1059:1059:1059) (1142:1142:1142))
(PORT d[1] (1091:1091:1091) (1165:1165:1165))
(PORT d[2] (1060:1060:1060) (1123:1123:1123))
(PORT d[3] (1344:1344:1344) (1418:1418:1418))
(PORT d[4] (1302:1302:1302) (1409:1409:1409))
(PORT d[5] (1050:1050:1050) (1118:1118:1118))
(PORT d[6] (1031:1031:1031) (1111:1111:1111))
(PORT d[7] (1231:1231:1231) (1307:1307:1307))
(PORT d[8] (1068:1068:1068) (1146:1146:1146))
(PORT d[9] (1109:1109:1109) (1198:1198:1198))
(PORT d[10] (1092:1092:1092) (1176:1176:1176))
(PORT d[11] (1106:1106:1106) (1187:1187:1187))
(PORT d[12] (1080:1080:1080) (1183:1183:1183))
(PORT clk (1851:1851:1851) (1877:1877:1877))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1881:1881:1881))
(PORT d[0] (829:829:829) (786:786:786))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1814:1814:1814) (1840:1840:1840))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (999:999:999) (1003:1003:1003))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2)
(DELAY
(ABSOLUTE
(PORT dataa (1538:1538:1538) (1685:1685:1685))
(PORT datab (1502:1502:1502) (1574:1574:1574))
(PORT datac (1307:1307:1307) (1329:1329:1329))
(PORT datad (983:983:983) (1060:1060:1060))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (898:898:898) (917:917:917))
(PORT clk (1851:1851:1851) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1708:1708:1708) (1889:1889:1889))
(PORT d[1] (1738:1738:1738) (1912:1912:1912))
(PORT d[2] (2173:2173:2173) (2306:2306:2306))
(PORT d[3] (1836:1836:1836) (1931:1931:1931))
(PORT d[4] (2057:2057:2057) (2182:2182:2182))
(PORT d[5] (1610:1610:1610) (1719:1719:1719))
(PORT d[6] (1827:1827:1827) (1950:1950:1950))
(PORT d[7] (2186:2186:2186) (2317:2317:2317))
(PORT d[8] (1553:1553:1553) (1673:1673:1673))
(PORT d[9] (1518:1518:1518) (1627:1627:1627))
(PORT d[10] (1791:1791:1791) (1987:1987:1987))
(PORT d[11] (1616:1616:1616) (1720:1720:1720))
(PORT d[12] (1800:1800:1800) (1921:1921:1921))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(PORT d[0] (1172:1172:1172) (1177:1177:1177))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3)
(DELAY
(ABSOLUTE
(PORT dataa (1504:1504:1504) (1573:1573:1573))
(PORT datab (200:200:200) (239:239:239))
(PORT datac (1093:1093:1093) (1101:1101:1101))
(PORT datad (983:983:983) (1067:1067:1067))
(IOPATH dataa combout (304:304:304) (299:299:299))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2453:2453:2453) (2542:2542:2542))
(PORT clk (1858:1858:1858) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1037:1037:1037) (1128:1128:1128))
(PORT d[1] (1054:1054:1054) (1160:1160:1160))
(PORT d[2] (1085:1085:1085) (1147:1147:1147))
(PORT d[3] (1322:1322:1322) (1383:1383:1383))
(PORT d[4] (1063:1063:1063) (1161:1161:1161))
(PORT d[5] (1060:1060:1060) (1155:1155:1155))
(PORT d[6] (1070:1070:1070) (1162:1162:1162))
(PORT d[7] (1268:1268:1268) (1365:1365:1365))
(PORT d[8] (1092:1092:1092) (1181:1181:1181))
(PORT d[9] (1101:1101:1101) (1206:1206:1206))
(PORT d[10] (1084:1084:1084) (1184:1184:1184))
(PORT d[11] (1128:1128:1128) (1209:1209:1209))
(PORT d[12] (1125:1125:1125) (1247:1247:1247))
(PORT clk (1855:1855:1855) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(PORT d[0] (769:769:769) (752:752:752))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1818:1818:1818) (1843:1843:1843))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1003:1003:1003) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2274:2274:2274) (2350:2350:2350))
(PORT clk (1847:1847:1847) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1485:1485:1485) (1583:1583:1583))
(PORT d[1] (1841:1841:1841) (1971:1971:1971))
(PORT d[2] (1529:1529:1529) (1647:1647:1647))
(PORT d[3] (1494:1494:1494) (1568:1568:1568))
(PORT d[4] (1502:1502:1502) (1598:1598:1598))
(PORT d[5] (1300:1300:1300) (1387:1387:1387))
(PORT d[6] (1569:1569:1569) (1676:1676:1676))
(PORT d[7] (1763:1763:1763) (1873:1873:1873))
(PORT d[8] (1295:1295:1295) (1399:1399:1399))
(PORT d[9] (1229:1229:1229) (1312:1312:1312))
(PORT d[10] (1248:1248:1248) (1357:1357:1357))
(PORT d[11] (1299:1299:1299) (1395:1395:1395))
(PORT d[12] (1524:1524:1524) (1618:1618:1618))
(PORT clk (1844:1844:1844) (1871:1871:1871))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1875:1875:1875))
(PORT d[0] (1054:1054:1054) (1024:1024:1024))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1807:1807:1807) (1834:1834:1834))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (992:992:992) (997:997:997))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2261:2261:2261) (2357:2357:2357))
(PORT clk (1850:1850:1850) (1878:1878:1878))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1737:1737:1737) (1843:1843:1843))
(PORT d[1] (1850:1850:1850) (1966:1966:1966))
(PORT d[2] (1540:1540:1540) (1643:1643:1643))
(PORT d[3] (1525:1525:1525) (1596:1596:1596))
(PORT d[4] (1540:1540:1540) (1614:1614:1614))
(PORT d[5] (1306:1306:1306) (1402:1402:1402))
(PORT d[6] (1565:1565:1565) (1672:1672:1672))
(PORT d[7] (1724:1724:1724) (1812:1812:1812))
(PORT d[8] (1273:1273:1273) (1378:1378:1378))
(PORT d[9] (1270:1270:1270) (1341:1341:1341))
(PORT d[10] (1253:1253:1253) (1367:1367:1367))
(PORT d[11] (1339:1339:1339) (1422:1422:1422))
(PORT d[12] (1201:1201:1201) (1283:1283:1283))
(PORT clk (1847:1847:1847) (1874:1874:1874))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1878:1878:1878))
(PORT d[0] (1041:1041:1041) (1051:1051:1051))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1810:1810:1810) (1837:1837:1837))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4)
(DELAY
(ABSOLUTE
(PORT dataa (1156:1156:1156) (1166:1166:1166))
(PORT datab (302:302:302) (396:396:396))
(PORT datac (1519:1519:1519) (1629:1629:1629))
(PORT datad (1138:1138:1138) (1148:1148:1148))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2749:2749:2749) (2863:2863:2863))
(PORT clk (1850:1850:1850) (1877:1877:1877))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (760:760:760) (843:843:843))
(PORT d[1] (738:738:738) (819:819:819))
(PORT d[2] (1007:1007:1007) (1067:1067:1067))
(PORT d[3] (1327:1327:1327) (1409:1409:1409))
(PORT d[4] (1070:1070:1070) (1153:1153:1153))
(PORT d[5] (1291:1291:1291) (1393:1393:1393))
(PORT d[6] (1016:1016:1016) (1096:1096:1096))
(PORT d[7] (1254:1254:1254) (1327:1327:1327))
(PORT d[8] (1046:1046:1046) (1125:1125:1125))
(PORT d[9] (1067:1067:1067) (1150:1150:1150))
(PORT d[10] (1263:1263:1263) (1344:1344:1344))
(PORT d[11] (1288:1288:1288) (1365:1365:1365))
(PORT d[12] (1238:1238:1238) (1306:1306:1306))
(PORT clk (1847:1847:1847) (1873:1873:1873))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(PORT d[0] (821:821:821) (785:785:785))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1878:1878:1878))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1878:1878:1878))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1878:1878:1878))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1878:1878:1878))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1810:1810:1810) (1836:1836:1836))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1000:1000:1000))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5)
(DELAY
(ABSOLUTE
(PORT dataa (826:826:826) (865:865:865))
(PORT datab (301:301:301) (396:396:396))
(PORT datac (171:171:171) (203:203:203))
(PORT datad (818:818:818) (827:827:827))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1913:1913:1913) (1986:1986:1986))
(PORT clk (1852:1852:1852) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1995:1995:1995) (2182:2182:2182))
(PORT d[1] (1708:1708:1708) (1871:1871:1871))
(PORT d[2] (2135:2135:2135) (2280:2280:2280))
(PORT d[3] (2271:2271:2271) (2418:2418:2418))
(PORT d[4] (2106:2106:2106) (2226:2226:2226))
(PORT d[5] (1944:1944:1944) (2065:2065:2065))
(PORT d[6] (1778:1778:1778) (1904:1904:1904))
(PORT d[7] (2147:2147:2147) (2267:2267:2267))
(PORT d[8] (1887:1887:1887) (2041:2041:2041))
(PORT d[9] (1870:1870:1870) (1997:1997:1997))
(PORT d[10] (1754:1754:1754) (1977:1977:1977))
(PORT d[11] (1857:1857:1857) (2005:2005:2005))
(PORT d[12] (2069:2069:2069) (2211:2211:2211))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1879:1879:1879))
(PORT d[0] (1357:1357:1357) (1388:1388:1388))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3031:3031:3031) (3166:3166:3166))
(PORT clk (1858:1858:1858) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1049:1049:1049) (1114:1114:1114))
(PORT d[1] (1017:1017:1017) (1109:1109:1109))
(PORT d[2] (1297:1297:1297) (1378:1378:1378))
(PORT d[3] (1362:1362:1362) (1466:1466:1466))
(PORT d[4] (1376:1376:1376) (1484:1484:1484))
(PORT d[5] (1483:1483:1483) (1628:1628:1628))
(PORT d[6] (1357:1357:1357) (1437:1437:1437))
(PORT d[7] (1587:1587:1587) (1682:1682:1682))
(PORT d[8] (1344:1344:1344) (1446:1446:1446))
(PORT d[9] (1376:1376:1376) (1485:1485:1485))
(PORT d[10] (1367:1367:1367) (1486:1486:1486))
(PORT d[11] (1591:1591:1591) (1672:1672:1672))
(PORT d[12] (1328:1328:1328) (1396:1396:1396))
(PORT clk (1855:1855:1855) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(PORT d[0] (1101:1101:1101) (1098:1098:1098))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1818:1818:1818) (1843:1843:1843))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1003:1003:1003) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6)
(DELAY
(ABSOLUTE
(PORT dataa (1536:1536:1536) (1683:1683:1683))
(PORT datab (1027:1027:1027) (1106:1106:1106))
(PORT datac (1437:1437:1437) (1486:1486:1486))
(PORT datad (1069:1069:1069) (1080:1080:1080))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2589:2589:2589) (2663:2663:2663))
(PORT clk (1843:1843:1843) (1871:1871:1871))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1794:1794:1794) (1905:1905:1905))
(PORT d[1] (1026:1026:1026) (1096:1096:1096))
(PORT d[2] (1216:1216:1216) (1322:1322:1322))
(PORT d[3] (1156:1156:1156) (1234:1234:1234))
(PORT d[4] (1228:1228:1228) (1312:1312:1312))
(PORT d[5] (1039:1039:1039) (1118:1118:1118))
(PORT d[6] (1579:1579:1579) (1705:1705:1705))
(PORT d[7] (1556:1556:1556) (1623:1623:1623))
(PORT d[8] (999:999:999) (1083:1083:1083))
(PORT d[9] (931:931:931) (997:997:997))
(PORT d[10] (1049:1049:1049) (1130:1130:1130))
(PORT d[11] (974:974:974) (1054:1054:1054))
(PORT d[12] (938:938:938) (1003:1003:1003))
(PORT clk (1840:1840:1840) (1867:1867:1867))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1843:1843:1843) (1871:1871:1871))
(PORT d[0] (785:785:785) (764:764:764))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1803:1803:1803) (1830:1830:1830))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (988:988:988) (993:993:993))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3027:3027:3027) (3141:3141:3141))
(PORT clk (1852:1852:1852) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1048:1048:1048) (1116:1116:1116))
(PORT d[1] (1003:1003:1003) (1076:1076:1076))
(PORT d[2] (1015:1015:1015) (1094:1094:1094))
(PORT d[3] (1075:1075:1075) (1152:1152:1152))
(PORT d[4] (1040:1040:1040) (1142:1142:1142))
(PORT d[5] (1523:1523:1523) (1680:1680:1680))
(PORT d[6] (1060:1060:1060) (1132:1132:1132))
(PORT d[7] (1290:1290:1290) (1385:1385:1385))
(PORT d[8] (1054:1054:1054) (1146:1146:1146))
(PORT d[9] (1098:1098:1098) (1199:1199:1199))
(PORT d[10] (1272:1272:1272) (1371:1371:1371))
(PORT d[11] (1344:1344:1344) (1414:1414:1414))
(PORT d[12] (1049:1049:1049) (1145:1145:1145))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1879:1879:1879))
(PORT d[0] (821:821:821) (781:781:781))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7)
(DELAY
(ABSOLUTE
(PORT dataa (201:201:201) (245:245:245))
(PORT datab (1022:1022:1022) (1100:1100:1100))
(PORT datac (1108:1108:1108) (1131:1131:1131))
(PORT datad (1030:1030:1030) (1028:1028:1028))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2272:2272:2272) (2349:2349:2349))
(PORT clk (1849:1849:1849) (1876:1876:1876))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1442:1442:1442) (1554:1554:1554))
(PORT d[1] (1253:1253:1253) (1367:1367:1367))
(PORT d[2] (1540:1540:1540) (1642:1642:1642))
(PORT d[3] (1521:1521:1521) (1596:1596:1596))
(PORT d[4] (1539:1539:1539) (1613:1613:1613))
(PORT d[5] (1333:1333:1333) (1432:1432:1432))
(PORT d[6] (1253:1253:1253) (1364:1364:1364))
(PORT d[7] (1206:1206:1206) (1279:1279:1279))
(PORT d[8] (1272:1272:1272) (1377:1377:1377))
(PORT d[9] (1269:1269:1269) (1340:1340:1340))
(PORT d[10] (1253:1253:1253) (1366:1366:1366))
(PORT d[11] (1311:1311:1311) (1390:1390:1390))
(PORT d[12] (1228:1228:1228) (1314:1314:1314))
(PORT clk (1846:1846:1846) (1872:1872:1872))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(PORT d[0] (1050:1050:1050) (1057:1057:1057))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1877:1877:1877))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1809:1809:1809) (1835:1835:1835))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1205:1205:1205) (1259:1259:1259))
(PORT clk (1847:1847:1847) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1704:1704:1704) (1863:1863:1863))
(PORT d[1] (1350:1350:1350) (1444:1444:1444))
(PORT d[2] (1524:1524:1524) (1626:1626:1626))
(PORT d[3] (1609:1609:1609) (1701:1701:1701))
(PORT d[4] (1816:1816:1816) (1915:1915:1915))
(PORT d[5] (1349:1349:1349) (1449:1449:1449))
(PORT d[6] (1526:1526:1526) (1631:1631:1631))
(PORT d[7] (1868:1868:1868) (2005:2005:2005))
(PORT d[8] (1256:1256:1256) (1354:1354:1354))
(PORT d[9] (1222:1222:1222) (1313:1313:1313))
(PORT d[10] (1760:1760:1760) (1983:1983:1983))
(PORT d[11] (1260:1260:1260) (1360:1360:1360))
(PORT d[12] (1497:1497:1497) (1594:1594:1594))
(PORT clk (1844:1844:1844) (1871:1871:1871))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1875:1875:1875))
(PORT d[0] (1136:1136:1136) (1101:1101:1101))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1807:1807:1807) (1834:1834:1834))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (992:992:992) (997:997:997))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (993:993:993) (998:998:998))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3295:3295:3295) (3430:3430:3430))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1400:1400:1400) (1465:1465:1465))
(PORT d[1] (1299:1299:1299) (1392:1392:1392))
(PORT d[2] (1360:1360:1360) (1457:1457:1457))
(PORT d[3] (1366:1366:1366) (1473:1473:1473))
(PORT d[4] (1357:1357:1357) (1492:1492:1492))
(PORT d[5] (1494:1494:1494) (1624:1624:1624))
(PORT d[6] (1642:1642:1642) (1736:1736:1736))
(PORT d[7] (1649:1649:1649) (1735:1735:1735))
(PORT d[8] (1394:1394:1394) (1494:1494:1494))
(PORT d[9] (1413:1413:1413) (1542:1542:1542))
(PORT d[10] (1353:1353:1353) (1458:1458:1458))
(PORT d[11] (1865:1865:1865) (1964:1964:1964))
(PORT d[12] (1729:1729:1729) (1881:1881:1881))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1059:1059:1059) (1056:1056:1056))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8)
(DELAY
(ABSOLUTE
(PORT dataa (1536:1536:1536) (1685:1685:1685))
(PORT datab (1024:1024:1024) (1105:1105:1105))
(PORT datac (844:844:844) (864:864:864))
(PORT datad (1224:1224:1224) (1255:1255:1255))
(IOPATH dataa combout (341:341:341) (367:367:367))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (913:913:913) (963:963:963))
(PORT clk (1860:1860:1860) (1888:1888:1888))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1599:1599:1599) (1720:1720:1720))
(PORT d[1] (2019:2019:2019) (2145:2145:2145))
(PORT d[2] (1619:1619:1619) (1729:1729:1729))
(PORT d[3] (1723:1723:1723) (1862:1862:1862))
(PORT d[4] (1885:1885:1885) (2025:2025:2025))
(PORT d[5] (1472:1472:1472) (1621:1621:1621))
(PORT d[6] (1660:1660:1660) (1786:1786:1786))
(PORT d[7] (1903:1903:1903) (2010:2010:2010))
(PORT d[8] (1677:1677:1677) (1831:1831:1831))
(PORT d[9] (1733:1733:1733) (1891:1891:1891))
(PORT d[10] (1717:1717:1717) (1862:1862:1862))
(PORT d[11] (1563:1563:1563) (1687:1687:1687))
(PORT d[12] (1762:1762:1762) (1918:1918:1918))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1888:1888:1888))
(PORT d[0] (1302:1302:1302) (1308:1308:1308))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1889:1889:1889))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9)
(DELAY
(ABSOLUTE
(PORT dataa (1439:1439:1439) (1460:1460:1460))
(PORT datab (198:198:198) (238:238:238))
(PORT datac (1360:1360:1360) (1372:1372:1372))
(PORT datad (988:988:988) (1066:1066:1066))
(IOPATH dataa combout (304:304:304) (299:299:299))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3036:3036:3036) (3166:3166:3166))
(PORT clk (1856:1856:1856) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1070:1070:1070) (1137:1137:1137))
(PORT d[1] (1268:1268:1268) (1329:1329:1329))
(PORT d[2] (1017:1017:1017) (1100:1100:1100))
(PORT d[3] (1083:1083:1083) (1176:1176:1176))
(PORT d[4] (1049:1049:1049) (1156:1156:1156))
(PORT d[5] (1511:1511:1511) (1661:1661:1661))
(PORT d[6] (1059:1059:1059) (1156:1156:1156))
(PORT d[7] (1328:1328:1328) (1409:1409:1409))
(PORT d[8] (1088:1088:1088) (1193:1193:1193))
(PORT d[9] (1082:1082:1082) (1187:1187:1187))
(PORT d[10] (1284:1284:1284) (1353:1353:1353))
(PORT d[11] (1286:1286:1286) (1362:1362:1362))
(PORT d[12] (1088:1088:1088) (1169:1169:1169))
(PORT clk (1853:1853:1853) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(PORT d[0] (790:790:790) (777:777:777))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1816:1816:1816) (1842:1842:1842))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1001:1001:1001) (1005:1005:1005))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1515:1515:1515) (1590:1590:1590))
(PORT clk (1845:1845:1845) (1873:1873:1873))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1684:1684:1684) (1856:1856:1856))
(PORT d[1] (1327:1327:1327) (1417:1417:1417))
(PORT d[2] (1593:1593:1593) (1712:1712:1712))
(PORT d[3] (1482:1482:1482) (1558:1558:1558))
(PORT d[4] (1470:1470:1470) (1568:1568:1568))
(PORT d[5] (1321:1321:1321) (1416:1416:1416))
(PORT d[6] (1522:1522:1522) (1622:1622:1622))
(PORT d[7] (1877:1877:1877) (1993:1993:1993))
(PORT d[8] (1283:1283:1283) (1385:1385:1385))
(PORT d[9] (1243:1243:1243) (1337:1337:1337))
(PORT d[10] (1317:1317:1317) (1437:1437:1437))
(PORT d[11] (1330:1330:1330) (1417:1417:1417))
(PORT d[12] (1474:1474:1474) (1569:1569:1569))
(PORT clk (1842:1842:1842) (1869:1869:1869))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1845:1845:1845) (1873:1873:1873))
(PORT d[0] (1079:1079:1079) (1084:1084:1084))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1874:1874:1874))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1805:1805:1805) (1832:1832:1832))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (990:990:990) (995:995:995))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (991:991:991) (996:996:996))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3013:3013:3013) (3126:3126:3126))
(PORT clk (1854:1854:1854) (1881:1881:1881))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1025:1025:1025) (1101:1101:1101))
(PORT d[1] (1011:1011:1011) (1098:1098:1098))
(PORT d[2] (1092:1092:1092) (1187:1187:1187))
(PORT d[3] (1057:1057:1057) (1145:1145:1145))
(PORT d[4] (1049:1049:1049) (1156:1156:1156))
(PORT d[5] (1495:1495:1495) (1647:1647:1647))
(PORT d[6] (1359:1359:1359) (1441:1441:1441))
(PORT d[7] (1304:1304:1304) (1384:1384:1384))
(PORT d[8] (1061:1061:1061) (1161:1161:1161))
(PORT d[9] (1104:1104:1104) (1210:1210:1210))
(PORT d[10] (1256:1256:1256) (1330:1330:1330))
(PORT d[11] (1374:1374:1374) (1438:1438:1438))
(PORT d[12] (1252:1252:1252) (1325:1325:1325))
(PORT clk (1851:1851:1851) (1877:1877:1877))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1854:1854:1854) (1881:1881:1881))
(PORT d[0] (853:853:853) (827:827:827))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1882:1882:1882))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1814:1814:1814) (1840:1840:1840))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (999:999:999) (1003:1003:1003))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1000:1000:1000) (1004:1004:1004))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10)
(DELAY
(ABSOLUTE
(PORT dataa (962:962:962) (991:991:991))
(PORT datab (1027:1027:1027) (1101:1101:1101))
(PORT datac (1043:1043:1043) (1062:1062:1062))
(PORT datad (1508:1508:1508) (1635:1635:1635))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3309:3309:3309) (3445:3445:3445))
(PORT clk (1859:1859:1859) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1367:1367:1367) (1451:1451:1451))
(PORT d[1] (1291:1291:1291) (1383:1383:1383))
(PORT d[2] (1315:1315:1315) (1397:1397:1397))
(PORT d[3] (1366:1366:1366) (1472:1472:1472))
(PORT d[4] (1347:1347:1347) (1474:1474:1474))
(PORT d[5] (1507:1507:1507) (1654:1654:1654))
(PORT d[6] (1385:1385:1385) (1469:1469:1469))
(PORT d[7] (1626:1626:1626) (1709:1709:1709))
(PORT d[8] (1351:1351:1351) (1468:1468:1468))
(PORT d[9] (1407:1407:1407) (1530:1530:1530))
(PORT d[10] (1617:1617:1617) (1719:1719:1719))
(PORT d[11] (1604:1604:1604) (1709:1709:1709))
(PORT d[12] (1333:1333:1333) (1405:1405:1405))
(PORT clk (1856:1856:1856) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1886:1886:1886))
(PORT d[0] (1122:1122:1122) (1077:1077:1077))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1008:1008:1008))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11)
(DELAY
(ABSOLUTE
(PORT dataa (797:797:797) (828:828:828))
(PORT datab (1022:1022:1022) (1101:1101:1101))
(PORT datac (173:173:173) (206:206:206))
(PORT datad (1084:1084:1084) (1093:1093:1093))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1484:1484:1484) (1567:1567:1567))
(PORT clk (1843:1843:1843) (1871:1871:1871))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1829:1829:1829) (1926:1926:1926))
(PORT d[1] (1342:1342:1342) (1428:1428:1428))
(PORT d[2] (1473:1473:1473) (1582:1582:1582))
(PORT d[3] (1480:1480:1480) (1573:1573:1573))
(PORT d[4] (1466:1466:1466) (1557:1557:1557))
(PORT d[5] (1316:1316:1316) (1406:1406:1406))
(PORT d[6] (1540:1540:1540) (1631:1631:1631))
(PORT d[7] (1258:1258:1258) (1325:1325:1325))
(PORT d[8] (1542:1542:1542) (1637:1637:1637))
(PORT d[9] (1242:1242:1242) (1329:1329:1329))
(PORT d[10] (1550:1550:1550) (1667:1667:1667))
(PORT d[11] (1256:1256:1256) (1351:1351:1351))
(PORT d[12] (1498:1498:1498) (1566:1566:1566))
(PORT clk (1840:1840:1840) (1867:1867:1867))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1843:1843:1843) (1871:1871:1871))
(PORT d[0] (1103:1103:1103) (1091:1091:1091))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1844:1844:1844) (1872:1872:1872))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1803:1803:1803) (1830:1830:1830))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (988:988:988) (993:993:993))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (989:989:989) (994:994:994))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2568:2568:2568) (2646:2646:2646))
(PORT clk (1841:1841:1841) (1869:1869:1869))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1806:1806:1806) (1901:1901:1901))
(PORT d[1] (1552:1552:1552) (1632:1632:1632))
(PORT d[2] (1513:1513:1513) (1599:1599:1599))
(PORT d[3] (1504:1504:1504) (1580:1580:1580))
(PORT d[4] (1464:1464:1464) (1525:1525:1525))
(PORT d[5] (1285:1285:1285) (1359:1359:1359))
(PORT d[6] (1247:1247:1247) (1334:1334:1334))
(PORT d[7] (1543:1543:1543) (1606:1606:1606))
(PORT d[8] (1265:1265:1265) (1346:1346:1346))
(PORT d[9] (1205:1205:1205) (1275:1275:1275))
(PORT d[10] (1613:1613:1613) (1730:1730:1730))
(PORT d[11] (1283:1283:1283) (1364:1364:1364))
(PORT d[12] (1460:1460:1460) (1536:1536:1536))
(PORT clk (1838:1838:1838) (1865:1865:1865))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1841:1841:1841) (1869:1869:1869))
(PORT d[0] (1059:1059:1059) (1032:1032:1032))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1842:1842:1842) (1870:1870:1870))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1842:1842:1842) (1870:1870:1870))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1842:1842:1842) (1870:1870:1870))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1842:1842:1842) (1870:1870:1870))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1801:1801:1801) (1828:1828:1828))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (986:986:986) (991:991:991))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (987:987:987) (992:992:992))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (987:987:987) (992:992:992))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (987:987:987) (992:992:992))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12)
(DELAY
(ABSOLUTE
(PORT dataa (949:949:949) (1022:1022:1022))
(PORT datab (882:882:882) (892:892:892))
(PORT datac (1128:1128:1128) (1124:1124:1124))
(PORT datad (1708:1708:1708) (1801:1801:1801))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH datab combout (306:306:306) (308:308:308))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1201:1201:1201) (1251:1251:1251))
(PORT clk (1850:1850:1850) (1878:1878:1878))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1610:1610:1610) (1758:1758:1758))
(PORT d[1] (1621:1621:1621) (1712:1712:1712))
(PORT d[2] (1839:1839:1839) (1958:1958:1958))
(PORT d[3] (1774:1774:1774) (1842:1842:1842))
(PORT d[4] (1809:1809:1809) (1925:1925:1925))
(PORT d[5] (1642:1642:1642) (1742:1742:1742))
(PORT d[6] (1842:1842:1842) (1953:1953:1953))
(PORT d[7] (1571:1571:1571) (1692:1692:1692))
(PORT d[8] (1574:1574:1574) (1694:1694:1694))
(PORT d[9] (1542:1542:1542) (1654:1654:1654))
(PORT d[10] (1756:1756:1756) (1975:1975:1975))
(PORT d[11] (1677:1677:1677) (1772:1772:1772))
(PORT d[12] (1793:1793:1793) (1908:1908:1908))
(PORT clk (1847:1847:1847) (1874:1874:1874))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1878:1878:1878))
(PORT d[0] (1243:1243:1243) (1306:1306:1306))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1851:1851:1851) (1879:1879:1879))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1810:1810:1810) (1837:1837:1837))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2741:2741:2741) (2845:2845:2845))
(PORT clk (1852:1852:1852) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (732:732:732) (812:812:812))
(PORT d[1] (730:730:730) (809:809:809))
(PORT d[2] (748:748:748) (807:807:807))
(PORT d[3] (798:798:798) (865:865:865))
(PORT d[4] (1302:1302:1302) (1410:1410:1410))
(PORT d[5] (857:857:857) (940:940:940))
(PORT d[6] (1335:1335:1335) (1404:1404:1404))
(PORT d[7] (754:754:754) (826:826:826))
(PORT d[8] (751:751:751) (827:827:827))
(PORT d[9] (765:765:765) (842:842:842))
(PORT d[10] (781:781:781) (864:864:864))
(PORT d[11] (801:801:801) (859:859:859))
(PORT d[12] (1765:1765:1765) (1920:1920:1920))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1852:1852:1852) (1879:1879:1879))
(PORT d[0] (714:714:714) (664:664:664))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1853:1853:1853) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13)
(DELAY
(ABSOLUTE
(PORT dataa (947:947:947) (1020:1020:1020))
(PORT datab (200:200:200) (239:239:239))
(PORT datac (1145:1145:1145) (1151:1151:1151))
(PORT datad (1040:1040:1040) (1038:1038:1038))
(IOPATH dataa combout (371:371:371) (376:376:376))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2732:2732:2732) (2820:2820:2820))
(PORT clk (1856:1856:1856) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1061:1061:1061) (1156:1156:1156))
(PORT d[1] (1068:1068:1068) (1164:1164:1164))
(PORT d[2] (1093:1093:1093) (1176:1176:1176))
(PORT d[3] (1101:1101:1101) (1184:1184:1184))
(PORT d[4] (1051:1051:1051) (1154:1154:1154))
(PORT d[5] (1803:1803:1803) (1981:1981:1981))
(PORT d[6] (1321:1321:1321) (1401:1401:1401))
(PORT d[7] (1240:1240:1240) (1328:1328:1328))
(PORT d[8] (1072:1072:1072) (1167:1167:1167))
(PORT d[9] (1096:1096:1096) (1195:1195:1195))
(PORT d[10] (1053:1053:1053) (1146:1146:1146))
(PORT d[11] (1088:1088:1088) (1182:1182:1182))
(PORT d[12] (1139:1139:1139) (1250:1250:1250))
(PORT clk (1853:1853:1853) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1883:1883:1883))
(PORT d[0] (820:820:820) (798:798:798))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1816:1816:1816) (1842:1842:1842))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1001:1001:1001) (1005:1005:1005))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1002:1002:1002) (1006:1006:1006))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1186:1186:1186) (1254:1254:1254))
(PORT clk (1859:1859:1859) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1633:1633:1633) (1730:1730:1730))
(PORT d[1] (1706:1706:1706) (1835:1835:1835))
(PORT d[2] (1902:1902:1902) (2011:2011:2011))
(PORT d[3] (1689:1689:1689) (1841:1841:1841))
(PORT d[4] (1895:1895:1895) (2039:2039:2039))
(PORT d[5] (1462:1462:1462) (1587:1587:1587))
(PORT d[6] (1692:1692:1692) (1844:1844:1844))
(PORT d[7] (2176:2176:2176) (2279:2279:2279))
(PORT d[8] (2000:2000:2000) (2161:2161:2161))
(PORT d[9] (2005:2005:2005) (2193:2193:2193))
(PORT d[10] (1430:1430:1430) (1590:1590:1590))
(PORT d[11] (2146:2146:2146) (2285:2285:2285))
(PORT d[12] (1786:1786:1786) (1943:1943:1943))
(PORT clk (1856:1856:1856) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1859:1859:1859) (1886:1886:1886))
(PORT d[0] (1074:1074:1074) (1078:1078:1078))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1008:1008:1008))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14)
(DELAY
(ABSOLUTE
(PORT dataa (900:900:900) (906:906:906))
(PORT datab (302:302:302) (396:396:396))
(PORT datac (1517:1517:1517) (1627:1627:1627))
(PORT datad (1452:1452:1452) (1515:1515:1515))
(IOPATH dataa combout (341:341:341) (319:319:319))
(IOPATH datab combout (342:342:342) (325:325:325))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (3319:3319:3319) (3470:3470:3470))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1379:1379:1379) (1448:1448:1448))
(PORT d[1] (1321:1321:1321) (1413:1413:1413))
(PORT d[2] (1557:1557:1557) (1658:1658:1658))
(PORT d[3] (1719:1719:1719) (1851:1851:1851))
(PORT d[4] (1357:1357:1357) (1492:1492:1492))
(PORT d[5] (1462:1462:1462) (1589:1589:1589))
(PORT d[6] (1645:1645:1645) (1743:1743:1743))
(PORT d[7] (1604:1604:1604) (1700:1700:1700))
(PORT d[8] (1383:1383:1383) (1508:1508:1508))
(PORT d[9] (1391:1391:1391) (1519:1519:1519))
(PORT d[10] (1384:1384:1384) (1542:1542:1542))
(PORT d[11] (1581:1581:1581) (1677:1677:1677))
(PORT d[12] (1786:1786:1786) (1940:1940:1940))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1124:1124:1124) (1095:1095:1095))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2440:2440:2440) (2510:2510:2510))
(PORT clk (1860:1860:1860) (1887:1887:1887))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1328:1328:1328) (1418:1418:1418))
(PORT d[1] (1327:1327:1327) (1415:1415:1415))
(PORT d[2] (1338:1338:1338) (1400:1400:1400))
(PORT d[3] (1424:1424:1424) (1493:1493:1493))
(PORT d[4] (1571:1571:1571) (1657:1657:1657))
(PORT d[5] (1300:1300:1300) (1371:1371:1371))
(PORT d[6] (1293:1293:1293) (1389:1389:1389))
(PORT d[7] (1497:1497:1497) (1583:1583:1583))
(PORT d[8] (1339:1339:1339) (1429:1429:1429))
(PORT d[9] (1353:1353:1353) (1446:1446:1446))
(PORT d[10] (1332:1332:1332) (1421:1421:1421))
(PORT d[11] (1372:1372:1372) (1441:1441:1441))
(PORT d[12] (1339:1339:1339) (1448:1448:1448))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1860:1860:1860) (1887:1887:1887))
(PORT d[0] (1003:1003:1003) (985:985:985))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1861:1861:1861) (1888:1888:1888))
(IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15)
(DELAY
(ABSOLUTE
(PORT dataa (200:200:200) (244:244:244))
(PORT datab (303:303:303) (400:400:400))
(PORT datac (1160:1160:1160) (1176:1176:1176))
(PORT datad (1074:1074:1074) (1066:1066:1066))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0)
(DELAY
(ABSOLUTE
(PORT dataa (949:949:949) (952:952:952))
(PORT datac (702:702:702) (800:800:800))
(PORT datad (645:645:645) (654:654:654))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1)
(DELAY
(ABSOLUTE
(PORT datab (1021:1021:1021) (1105:1105:1105))
(PORT datac (616:616:616) (620:620:620))
(PORT datad (342:342:342) (355:355:355))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2)
(DELAY
(ABSOLUTE
(PORT dataa (983:983:983) (996:996:996))
(PORT datab (1022:1022:1022) (1101:1101:1101))
(PORT datad (1506:1506:1506) (1591:1591:1591))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3)
(DELAY
(ABSOLUTE
(PORT datab (1021:1021:1021) (1105:1105:1105))
(PORT datac (646:646:646) (656:656:656))
(PORT datad (652:652:652) (658:658:658))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4)
(DELAY
(ABSOLUTE
(PORT datab (1024:1024:1024) (1103:1103:1103))
(PORT datac (1317:1317:1317) (1316:1316:1316))
(PORT datad (631:631:631) (658:658:658))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5)
(DELAY
(ABSOLUTE
(PORT datab (664:664:664) (697:697:697))
(PORT datac (994:994:994) (1070:1070:1070))
(PORT datad (660:660:660) (670:670:670))
(IOPATH datab combout (342:342:342) (342:342:342))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6)
(DELAY
(ABSOLUTE
(PORT datab (1989:1989:1989) (2097:2097:2097))
(PORT datac (635:635:635) (654:654:654))
(PORT datad (343:343:343) (356:356:356))
(IOPATH datab combout (342:342:342) (342:342:342))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7)
(DELAY
(ABSOLUTE
(PORT dataa (937:937:937) (981:981:981))
(PORT datac (989:989:989) (1063:1063:1063))
(PORT datad (1104:1104:1104) (1106:1106:1106))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
)
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