125 lines
4.5 KiB
Python
125 lines
4.5 KiB
Python
#!/usr/bin/env python3
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#
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# This script reads and parses all top-level modules and generates a core block
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# file containing instantiation of these modules. This generated file is included
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# by core.vh
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2016 Goran Devic
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import os
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# Define a set of module cross-connections. These are the chip's internal buses
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# which we inject as connections as we generate a list of module instances
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xconnections = [
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['interrupts', 'db', 'db0[4:3]'],
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['ir', 'db', 'db0[7:0]'],
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['alu_control', 'db', 'db1[7:0]'],
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['alu_control', 'op543', '{pla[104],pla[103],pla[102]}'],
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['alu_flags', 'db', 'db1[7:0]'],
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['alu', 'db', 'db2[7:0]'],
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['alu', 'bsel', 'db0[5:3]'],
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['reg_file', 'db_hi_ds', 'db2[7:0]'],
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['reg_file', 'db_lo_ds', 'db1[7:0]'],
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['reg_file', 'db_hi_as', 'db_hi_as[7:0]'],
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['reg_file', 'db_lo_as', 'db_lo_as[7:0]'],
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['address_latch', 'abus', '{db_hi_as[7:0], db_lo_as[7:0]}'],
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['bus_control', 'db', 'db0[7:0]']
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]
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# Define a list of modules that are not used (but listed in 'top-level-files.txt' )
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skip_modules = ['address_pins', 'data_pins', 'control_pins_n']
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# For error-checking, make sure every xconnection entry has been utilized
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xcount = len(xconnections)
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def connect(module, wire):
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global xcount
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for xconnection in xconnections:
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m, w, xcon = xconnection
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if module==m and wire==w:
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print("Cross-connecting:", module, wire, "->", xcon)
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xcount -= 1
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return xcon
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return wire
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def parse(wires, lines):
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while(len(lines)>0 and lines[0].startswith(');')==False):
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line = lines[0].strip()
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lines.pop(0)
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if len(line)==0 or line[0]=='(' or line[0]=='/':
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continue
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tokens = line.split()
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if len(tokens)>=3 and tokens[0] in ['input', 'output']:
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tokens.pop(0)
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if len(tokens)>=2 and tokens[0] in ['wire', 'reg']:
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tokens.pop(0)
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if len(tokens)>=2 and tokens[0].startswith('['):
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tokens.pop(0)
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if len(tokens)>=2 and tokens[0]=='`include':
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include_file = tokens[1].replace('"', '')
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with open('../control/' + include_file) as f:
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included_lines = f.read().splitlines()
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parse(wires, included_lines)
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continue
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name = tokens[0]
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if name.endswith(','):
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name = name[:-1]
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wires.append(name)
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with open('../top-level-files.txt') as f:
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files = f.read().splitlines()
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# Create a file that should be included in the top-level core source
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with open('coremodules.vh', 'w') as file1:
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file1.write("// Automatically generated by gencoremodules.py\n")
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# Read and parse each file from the list of input files
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for infile in files:
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if not os.path.isfile('../' + infile):
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continue
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with open('../' + infile, "r") as f:
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lines = f.read().splitlines()
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# Find 'module' section; read and generate instantiation statement
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while(len(lines)>0 and lines[0].startswith('module ')==False):
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lines.pop(0)
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if len(lines)==0:
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continue
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module_name = lines[0].split()[1]
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lines.pop(0)
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if module_name.endswith('('):
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module_name = module_name[:-1]
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if module_name in skip_modules:
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continue
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# Read a list of input/output wires, one per line
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wires = []
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parse(wires, lines)
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# Print the names of all parsed signals in a module instantiation format
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with open('coremodules.vh', 'a') as file1:
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file1.write("\n" + module_name + " " + module_name + "_(\n")
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while(len(wires)>0):
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wire = wires.pop(0)
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terminator = ','
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if len(wires)==0:
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terminator = "\n);"
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file1.write(" ." + wire + " (" + connect(module_name, wire) + ")" + terminator + "\n")
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assert(xcount==0)
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# Touch files that include 'coremodules.vh' to ensure it will recompile correctly
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os.utime("core.vh", None)
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