71 lines
2.4 KiB
Python
71 lines
2.4 KiB
Python
#!/usr/bin/env python3
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#
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# Run this script to export necessary CPU files away and into your project.
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014,2018 Goran Devic, www.baltazarstudios.com
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import sys
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import os
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from shutil import copyfile
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if len(sys.argv) != 2:
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print ("\nUsage: export.py <destination-folder>\n")
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print ("Exports all necessary A-Z80 Verilog files to a project folder of your choice.")
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exit(-1)
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dest = sys.argv[1]
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total = 0
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if not os.path.exists(dest):
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print ("ERROR: Destination folder does not exist!")
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exit(-1)
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if not os.path.isdir(dest):
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print ("ERROR: Destination is not a directory!")
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exit(-1)
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with open('top-level-files.txt') as f:
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files = f.read().splitlines()
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with open('copyleft.txt') as f:
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copyleft = f.read()
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# Read and copy each file from the list of input files
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for infile in files:
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if infile.startswith('+'):
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infile = infile[2:]
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if infile.startswith('Files='):
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files = int(infile[6:])
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if total != files:
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print ("ERROR: Incorrect number of files copied!")
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exit(-1)
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else:
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print ("\nDone copying {0} files.\n".format(files))
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if not os.path.isfile(infile):
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continue
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name = os.path.basename(infile)
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print ('Copying', infile)
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with open(dest + '/' + name, 'wt') as f:
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f.write(copyleft)
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with open(infile) as g:
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f.write(g.read())
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total += 1
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print ("All necessary A-Z80 CPU files are copied to", dest)
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print ("Add all Verilog files (*.v) to your project and ensure that Verilog include")
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print ("files (*.vh) are on the include path.\n")
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print ("Use z80_top_direct_n.v as your top-level interface file.\n")
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print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
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print ("copy and use data_pins_lattice.v file instead.")
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