54 lines
1.7 KiB
Verilog
54 lines
1.7 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Fri Feb 26 22:25:37 2016"
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module bus_control(
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ctl_bus_ff_oe,
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ctl_bus_zero_oe,
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db
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);
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input wire ctl_bus_ff_oe;
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input wire ctl_bus_zero_oe;
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inout wire [7:0] db;
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wire [7:0] bus;
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wire [7:0] vcc;
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wire SYNTHESIZED_WIRE_0;
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assign db[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz;
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assign db[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz;
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assign db[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz;
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assign db[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz;
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assign db[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz;
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assign db[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz;
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assign db[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz;
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assign db[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz;
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assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc;
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assign SYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe;
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assign vcc = 8'b11111111;
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endmodule
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