60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Fri Oct 31 21:08:42 2014"
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module alu_mux_3z(
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sel_zero,
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sel_a,
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sel_b,
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a,
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b,
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ena,
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Q
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);
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input wire sel_zero;
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input wire sel_a;
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input wire sel_b;
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input wire [3:0] a;
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input wire [3:0] b;
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output wire ena;
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output wire [3:0] Q;
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wire [3:0] SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire [3:0] SYNTHESIZED_WIRE_2;
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wire [3:0] SYNTHESIZED_WIRE_3;
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assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a};
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assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
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assign SYNTHESIZED_WIRE_1 = ~sel_zero;
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assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
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assign ena = sel_a | sel_b | sel_zero;
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assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b};
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endmodule
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