--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=49152 NUMWORDS_B=49152 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=16 WIDTHAD_B=16 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION decode_psa (data[2..0], enable) RETURNS ( eq[5..0]); FUNCTION decode_i8a (data[2..0]) RETURNS ( eq[5..0]); FUNCTION mux_9nb (data[47..0], sel[2..0]) RETURNS ( result[7..0]); FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = lut 112 M9K 48 reg 12 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_dui2 ( address_a[15..0] : input; address_b[15..0] : input; clock0 : input; data_a[7..0] : input; data_b[7..0] : input; q_a[7..0] : output; q_b[7..0] : output; wren_a : input; wren_b : input; ) VARIABLE address_reg_a[2..0] : dffe; address_reg_b[2..0] : dffe; out_address_reg_a[2..0] : dffe; out_address_reg_b[2..0] : dffe; decode2 : decode_psa; decode3 : decode_psa; rden_decode_a : decode_i8a; rden_decode_b : decode_i8a; mux4 : mux_9nb; mux5 : mux_9nb; ram_block1a0 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a1 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a2 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a3 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a4 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a5 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a6 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a7 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a8 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a9 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a10 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a11 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a12 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a13 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a14 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a15 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a16 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a17 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a18 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a19 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a20 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a21 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a22 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a23 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a24 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a25 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a26 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a27 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a28 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a29 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a30 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a31 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 32767, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a32 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a33 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a34 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a35 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a36 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a37 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a38 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a39 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 32768, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 40959, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a40 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a41 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a42 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a43 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a44 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a45 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a46 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a47 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "ena1", CLK1_INPUT_CLOCK_ENABLE = "none", CLK1_OUTPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "led_patterns.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 13, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock1", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 40960, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 49151, PORT_A_LOGICAL_RAM_DEPTH = 49152, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 13, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 49152, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", PORT_B_READ_ENABLE_CLOCK = "clock1", PORT_B_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); address_a_sel[2..0] : WIRE; address_a_wire[15..0] : WIRE; address_b_sel[2..0] : WIRE; address_b_wire[15..0] : WIRE; w_addr_val_b4w[2..0] : WIRE; w_addr_val_b8w[2..0] : WIRE; wren_decode_addr_sel_a[2..0] : WIRE; wren_decode_addr_sel_b[2..0] : WIRE; BEGIN address_reg_a[].clk = clock0; address_reg_a[].d = address_a_sel[]; address_reg_b[].clk = clock0; address_reg_b[].d = address_b_sel[]; out_address_reg_a[].clk = clock0; out_address_reg_a[].d = address_reg_a[].q; out_address_reg_b[].clk = clock0; out_address_reg_b[].d = address_reg_b[].q; decode2.data[2..0] = address_a_wire[15..13]; decode2.enable = wren_a; decode3.data[] = w_addr_val_b4w[]; decode3.enable = wren_b; rden_decode_a.data[] = wren_decode_addr_sel_a[]; rden_decode_b.data[] = w_addr_val_b8w[]; mux4.data[] = ( ram_block1a[47..0].portadataout[0..0]); mux4.sel[] = out_address_reg_a[].q; mux5.data[] = ( ram_block1a[47..0].portbdataout[0..0]); mux5.sel[] = out_address_reg_b[].q; ram_block1a[47..0].clk0 = clock0; ram_block1a[47..0].clk1 = clock0; ram_block1a[47..0].ena0 = ( rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..5], rden_decode_a.eq[5..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..4], rden_decode_a.eq[4..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..3], rden_decode_a.eq[3..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..2], rden_decode_a.eq[2..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]); ram_block1a[47..0].ena1 = ( rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..5], rden_decode_b.eq[5..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..4], rden_decode_b.eq[4..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..3], rden_decode_b.eq[3..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..2], rden_decode_b.eq[2..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]); ram_block1a[47..0].portaaddr[] = ( address_a_wire[12..0]); ram_block1a[0].portadatain[] = ( data_a[0..0]); ram_block1a[1].portadatain[] = ( data_a[1..1]); ram_block1a[2].portadatain[] = ( data_a[2..2]); ram_block1a[3].portadatain[] = ( data_a[3..3]); ram_block1a[4].portadatain[] = ( data_a[4..4]); ram_block1a[5].portadatain[] = ( data_a[5..5]); ram_block1a[6].portadatain[] = ( data_a[6..6]); ram_block1a[7].portadatain[] = ( data_a[7..7]); ram_block1a[8].portadatain[] = ( data_a[0..0]); ram_block1a[9].portadatain[] = ( data_a[1..1]); ram_block1a[10].portadatain[] = ( data_a[2..2]); ram_block1a[11].portadatain[] = ( data_a[3..3]); ram_block1a[12].portadatain[] = ( data_a[4..4]); ram_block1a[13].portadatain[] = ( data_a[5..5]); ram_block1a[14].portadatain[] = ( data_a[6..6]); ram_block1a[15].portadatain[] = ( data_a[7..7]); ram_block1a[16].portadatain[] = ( data_a[0..0]); ram_block1a[17].portadatain[] = ( data_a[1..1]); ram_block1a[18].portadatain[] = ( data_a[2..2]); ram_block1a[19].portadatain[] = ( data_a[3..3]); ram_block1a[20].portadatain[] = ( data_a[4..4]); ram_block1a[21].portadatain[] = ( data_a[5..5]); ram_block1a[22].portadatain[] = ( data_a[6..6]); ram_block1a[23].portadatain[] = ( data_a[7..7]); ram_block1a[24].portadatain[] = ( data_a[0..0]); ram_block1a[25].portadatain[] = ( data_a[1..1]); ram_block1a[26].portadatain[] = ( data_a[2..2]); ram_block1a[27].portadatain[] = ( data_a[3..3]); ram_block1a[28].portadatain[] = ( data_a[4..4]); ram_block1a[29].portadatain[] = ( data_a[5..5]); ram_block1a[30].portadatain[] = ( data_a[6..6]); ram_block1a[31].portadatain[] = ( data_a[7..7]); ram_block1a[32].portadatain[] = ( data_a[0..0]); ram_block1a[33].portadatain[] = ( data_a[1..1]); ram_block1a[34].portadatain[] = ( data_a[2..2]); ram_block1a[35].portadatain[] = ( data_a[3..3]); ram_block1a[36].portadatain[] = ( data_a[4..4]); ram_block1a[37].portadatain[] = ( data_a[5..5]); ram_block1a[38].portadatain[] = ( data_a[6..6]); ram_block1a[39].portadatain[] = ( data_a[7..7]); ram_block1a[40].portadatain[] = ( data_a[0..0]); ram_block1a[41].portadatain[] = ( data_a[1..1]); ram_block1a[42].portadatain[] = ( data_a[2..2]); ram_block1a[43].portadatain[] = ( data_a[3..3]); ram_block1a[44].portadatain[] = ( data_a[4..4]); ram_block1a[45].portadatain[] = ( data_a[5..5]); ram_block1a[46].portadatain[] = ( data_a[6..6]); ram_block1a[47].portadatain[] = ( data_a[7..7]); ram_block1a[47..0].portare = B"111111111111111111111111111111111111111111111111"; ram_block1a[47..0].portawe = ( decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); ram_block1a[47..0].portbaddr[] = ( address_b_wire[12..0]); ram_block1a[0].portbdatain[] = ( data_b[0..0]); ram_block1a[1].portbdatain[] = ( data_b[1..1]); ram_block1a[2].portbdatain[] = ( data_b[2..2]); ram_block1a[3].portbdatain[] = ( data_b[3..3]); ram_block1a[4].portbdatain[] = ( data_b[4..4]); ram_block1a[5].portbdatain[] = ( data_b[5..5]); ram_block1a[6].portbdatain[] = ( data_b[6..6]); ram_block1a[7].portbdatain[] = ( data_b[7..7]); ram_block1a[8].portbdatain[] = ( data_b[0..0]); ram_block1a[9].portbdatain[] = ( data_b[1..1]); ram_block1a[10].portbdatain[] = ( data_b[2..2]); ram_block1a[11].portbdatain[] = ( data_b[3..3]); ram_block1a[12].portbdatain[] = ( data_b[4..4]); ram_block1a[13].portbdatain[] = ( data_b[5..5]); ram_block1a[14].portbdatain[] = ( data_b[6..6]); ram_block1a[15].portbdatain[] = ( data_b[7..7]); ram_block1a[16].portbdatain[] = ( data_b[0..0]); ram_block1a[17].portbdatain[] = ( data_b[1..1]); ram_block1a[18].portbdatain[] = ( data_b[2..2]); ram_block1a[19].portbdatain[] = ( data_b[3..3]); ram_block1a[20].portbdatain[] = ( data_b[4..4]); ram_block1a[21].portbdatain[] = ( data_b[5..5]); ram_block1a[22].portbdatain[] = ( data_b[6..6]); ram_block1a[23].portbdatain[] = ( data_b[7..7]); ram_block1a[24].portbdatain[] = ( data_b[0..0]); ram_block1a[25].portbdatain[] = ( data_b[1..1]); ram_block1a[26].portbdatain[] = ( data_b[2..2]); ram_block1a[27].portbdatain[] = ( data_b[3..3]); ram_block1a[28].portbdatain[] = ( data_b[4..4]); ram_block1a[29].portbdatain[] = ( data_b[5..5]); ram_block1a[30].portbdatain[] = ( data_b[6..6]); ram_block1a[31].portbdatain[] = ( data_b[7..7]); ram_block1a[32].portbdatain[] = ( data_b[0..0]); ram_block1a[33].portbdatain[] = ( data_b[1..1]); ram_block1a[34].portbdatain[] = ( data_b[2..2]); ram_block1a[35].portbdatain[] = ( data_b[3..3]); ram_block1a[36].portbdatain[] = ( data_b[4..4]); ram_block1a[37].portbdatain[] = ( data_b[5..5]); ram_block1a[38].portbdatain[] = ( data_b[6..6]); ram_block1a[39].portbdatain[] = ( data_b[7..7]); ram_block1a[40].portbdatain[] = ( data_b[0..0]); ram_block1a[41].portbdatain[] = ( data_b[1..1]); ram_block1a[42].portbdatain[] = ( data_b[2..2]); ram_block1a[43].portbdatain[] = ( data_b[3..3]); ram_block1a[44].portbdatain[] = ( data_b[4..4]); ram_block1a[45].portbdatain[] = ( data_b[5..5]); ram_block1a[46].portbdatain[] = ( data_b[6..6]); ram_block1a[47].portbdatain[] = ( data_b[7..7]); ram_block1a[47..0].portbre = B"111111111111111111111111111111111111111111111111"; ram_block1a[47..0].portbwe = ( decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); address_a_sel[2..0] = address_a[15..13]; address_a_wire[] = address_a[]; address_b_sel[2..0] = address_b[15..13]; address_b_wire[] = address_b[]; q_a[] = mux4.result[]; q_b[] = mux5.result[]; w_addr_val_b4w[2..0] = address_b_wire[15..13]; w_addr_val_b8w[] = wren_decode_addr_sel_b[]; wren_decode_addr_sel_a[2..0] = address_a_wire[15..13]; wren_decode_addr_sel_b[2..0] = address_b_wire[15..13]; END; --VALID FILE