A-Z80 Timing Table	M_	T_	Function	valid	nextM	setM1	A:reg rd	A:reg wr	inc/dec	A:latch	D:reg rd	D:reg wr	Reg gate	SW2	SW1	DB pads	FLAGT	ALU	ALU bus	op2 latch	op1 latch	nibble	operation		SZ	XY	HF	PF	NF	CF	CF2		Special	Comments
																																		
// 8-bit Load Group																																		
																																		
"#if pla[17] & ~pla[50] : ld r,n"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									r8	<	d	<	R																		
#002H T2  AB:000 DB:46  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC		 	W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead			Y																												
#end																																		
																																		
"#if pla[61] & ~pla[58] & ~pla[59] : ld r,r'"			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									r8	<	u				<	op1															
#002H T2  AB:000 DB:05  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-				>s0			bus													
#end																																		
																																		
"#if use_ixiy & pla[58] : ld r,(ix+d)"			"4,3,5,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									r8	<	d	<	R																		
#006H T2  AB:001 DB:4E  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead	 	Y																													
#012H T8  AB:002 DB:--	3	1																															WZ=IX+d	
#013H T9  AB:002 DB:--	3	2																															WZ=IX+d	
#014H T10 AB:002 DB:--	3	3																															WZ=IX+d	
#015H T11 AB:002 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:002 DB:--	3	5			mr																												WZ=IX+d	Clears the IX/IY and ...
#end																																		
																																		
"#if ~use_ixiy & pla[58] : ld r,(hl)"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									r8	<	d	<	R																		
#002H T2  AB:000 DB:46  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:003 DB:--	2	1	fMRead				HL			W																								
#006H T6  AB:003 DB:03          MREQ RD	2	2	fMRead																															
#007H T7  AB:003 DB:03          MREQ RD	2	3	fMRead			Y																												
																																		
#017H T13 AB:001 DB:--	4	1	fMRead							R																								...continues here
#018H T14 AB:001 DB:4E          MREQ RD	4	2	fMRead																															
#019H T15 AB:001 DB:4E          MREQ RD	4	3	fMRead			Y																												
#end																																		
																																		
"#if use_ixiy & pla[59] : ld (ix+d),r"			"4,3,5,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:70  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead	 	Y																													
#012H T8  AB:002 DB:--	3	1																															WZ=IX+d	
#013H T9  AB:002 DB:--	3	2																															WZ=IX+d	
#014H T10 AB:002 DB:--	3	3																															WZ=IX+d	
#015H T11 AB:002 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:002 DB:--	3	5			mw																												WZ=IX+d	Clears the IX/IY and ...
#end																																		
																																		
"#if ~use_ixiy & pla[59] : ld (hl),r"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:70  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mw						r8		>r8	-	>	W																		
#005H T5  AB:001 DB:--	2	1	fMWrite				HL			W																								
#006H T6  AB:001 DB:01          MREQ	2	2	fMWrite																															
#007H T7  AB:001 DB:01          MREQ    WR	2	3	fMWrite			Y																												
																																		
#017H T13 AB:000 DB:--	4	1	fMWrite							R	r8		>r8	-	>	W																		...continues here
#018H T14 AB:000 DB:46          MREQ	4	2	fMWrite																															
#019H T15 AB:000 DB:46          MREQ    WR	4	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[40] : ld (ix+d),n"			"4,3,5,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:36  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead	 	mr																													
#012H T8  AB:003 DB:--	3	1	fMRead				PC			W																							WZ=IX+d	
#013H T9  AB:003 DB:02          MREQ RD	3	2	fMRead					PC	+	R																							WZ=IX+d	
#014H T10 AB:003 DB:02          MREQ RD	3	3	fMRead																														WZ=IX+d	"Reads ""n"" at the same time"
#015H T11 AB:003 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:003 DB:--	3	5			mw																												WZ=IX+d	Clears the IX/IY and ...
#end																																		
																																		
"#if pla[50] & ~pla[40] : ld (hl),n"			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:36  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead	 	mw																													
#008H T8  AB:001 DB:--	3	1	fMWrite				HL			W																								
#009H T9  AB:001 DB:01          MREQ	3	2	fMWrite																															
#010H T10 AB:001 DB:01          MREQ    WR	3	3	fMWrite			Y																												
																																		
#017H T13 AB:002 DB:--	4	1	fMWrite							R																								...continues here
#018H T14 AB:002 DB:02          MREQ	4	2	fMWrite																															
#019H T15 AB:002 DB:02          MREQ    WR	4	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[8] & pla[13] : ld (rr),a"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:02  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mw						A		>h	u	>	W																		
#005H T5  AB:001 DB:--	2	1	fMWrite				r16			W																								
#006H T6  AB:001 DB:FF          MREQ	2	2	fMWrite					WZ	+	R																								
#007H T7  AB:001 DB:FF          MREQ    WR	2	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[8] & ~pla[13] : ld a,(rr)"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<	d	<	R																		
#002H T2  AB:000 DB:0A  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:002 DB:--	2	1	fMRead				r16			W																								
#006H T6  AB:002 DB:02          MREQ RD	2	2	fMRead					WZ	+	R																								
#007H T7  AB:002 DB:02          MREQ RD	2	3	fMRead			Y																												
#end																																		
																																		
"#if pla[38] & pla[13] : ld (nn),a"			"4,3,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:32  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead		mw		WZ			W		W	<h	d	<	R																		
#011H T11 AB:001 DB:--	4	1	fMWrite							R	A		>h	u	>	W																		
#012H T12 AB:001 DB:FE          MREQ	4	2	fMWrite					WZ	+	R																								
#013H T13 AB:001 DB:FE          MREQ    WR	4	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[38] & ~pla[13] : ld a,(nn)"			"4,3,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<	d	<	R																		
#002H T2  AB:000 DB:3A  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead		mr							W	<h	d	<	R																		
#011H T11 AB:001 DB:--	4	1	fMRead				WZ			W																								
#012H T12 AB:001 DB:01          MREQ RD	4	2	fMRead					WZ	+	R																								
#013H T13 AB:001 DB:01          MREQ RD	4	3	fMRead			Y																												
#end																																		
																																		
"#if pla[83] : ld a,i/a,r"			5																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	OR		*	*	*	iff2	0					
#006H T2  AB:001 DB:57  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y							I/R		>r8'	-			alu	>s0		bus	bus	L	OR		*	*	*		0					
#009H T5  AB:001 DB:--	1	5				Y																												
#end																																		
																																		
"#if pla[57] : ld i,a/r,a"			5																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:47  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y								I/R	<	u				<	op1															
#009H T5  AB:001 DB:--	1	5				Y																												
#end																																		
																																		
// 16-bit Load Group																																		
																																		
"#if pla[7] : ld rr,nn"			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									rh	<	d	<	R																	USE_SP	
#002H T2  AB:000 DB:01  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr																													
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W		rl	<	d	<	R																	USE_SP	
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead			Y																												
#end																																		
																																		
"#if pla[30] & pla[13] : ld (nn),hl"			"4,3,3,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:22  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead		mw		WZ			W		W	<h	d	<	R																		
#011H T11 AB:001 DB:--	4	1	fMWrite							R	rl		>l		>	W																		
#012H T12 AB:001 DB:01          MREQ	4	2	fMWrite					WZ	+	R																								
#013H T13 AB:001 DB:01          MREQ    WR	4	3	fMWrite		mw		WZ			W																								
#014H T14 AB:002 DB:--	5	1	fMWrite							R	rh		>h	u	>	W																		
#015H T15 AB:002 DB:02          MREQ	5	2	fMWrite					WZ	+	R																								
#016H T16 AB:002 DB:02          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[30] & ~pla[13] : ld hl,(nn)"			"4,3,3,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:2A  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead		mr							W	<h	d	<	R																		
#011H T11 AB:001 DB:--	4	1	fMRead				WZ			W																								
#012H T12 AB:001 DB:01          MREQ RD	4	2	fMRead					WZ	+	R																								
#013H T13 AB:001 DB:01          MREQ RD	4	3	fMRead		mr							rl	<	d	<	R																		
#014H T14 AB:002 DB:--	5	1	fMRead				WZ			W																								
#015H T15 AB:002 DB:02          MREQ RD	5	2	fMRead					WZ	+	R																								
#016H T16 AB:002 DB:02          MREQ RD	5	3	fMRead			Y						rh	<	d	<	R																		
#end																																		
																																		
"#if pla[31] & pla[33] : ld (nn),rr"			"4,3,3,3,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:43  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#012H T8  AB:003 DB:--	3	1	fMRead				PC			W																								
#013H T9  AB:003 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#014H T10 AB:003 DB:02          MREQ RD	3	3	fMRead		mw		WZ			W		W	<h	d	<	R																		
#015H T11 AB:001 DB:--	4	1	fMWrite							R	rl		>l		>	W																	USE_SP	
#016H T12 AB:001 DB:FF          MREQ	4	2	fMWrite					WZ	+	R																								
#017H T13 AB:001 DB:FF          MREQ    WR	4	3	fMWrite		mw		WZ			W																								
#018H T14 AB:002 DB:--	5	1	fMWrite							R	rh		>h	u	>	W																	USE_SP	
#019H T15 AB:002 DB:C3          MREQ	5	2	fMWrite					WZ	+	R																								
#020H T16 AB:002 DB:C3          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
"#if pla[31] & ~pla[33] : ld rr,(nn)"			"4,3,3,3,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:43  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#012H T8  AB:003 DB:--	3	1	fMRead				PC			W																								
#013H T9  AB:003 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#014H T10 AB:003 DB:02          MREQ RD	3	3	fMRead		mr							W	<h	d	<	R																		
#015H T11 AB:001 DB:--	4	1	fMRead				WZ			W																								
#016H T12 AB:001 DB:FF          MREQ RD	4	2	fMRead					WZ	+	R																								
#017H T13 AB:001 DB:FF          MREQ RD	4	3	fMRead		mr							rl	<	d	<	R																	USE_SP	
#018H T14 AB:002 DB:--	5	1	fMRead				WZ			W																								
#019H T15 AB:002 DB:C3          MREQ RD	5	2	fMRead					WZ	+	R																								
#020H T16 AB:002 DB:C3          MREQ RD	5	3	fMRead			Y						rh	<	d	<	R																	USE_SP	
#end																																		
																																		
"#if pla[5] : ld sp,hl"			6																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:F9  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y			HL			W																								
#005H T5  AB:000 DB:--	1	5						SP		R																								
#006H T6  AB:000 DB:--	1	6				Y																												
#end																																		
																																		
#if pla[23] & pla[16] : push qq			"5,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C5  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y																														
#005H T5  AB:000 DB:--	1	5			mw		SP		-	W																								
#006H T6  AB:002 DB:--	2	1	fMWrite						-	P	rh		>h	u	>	W																		
#007H T7  AB:002 DB:02          MREQ	2	2	fMWrite					SP	-	R																								
#008H T8  AB:002 DB:02          MREQ    WR	2	3	fMWrite		mw		SP		-	W																								
#009H T9  AB:001 DB:--	3	1	fMWrite						-	P	rl		>l		>	W																		
#010H T10 AB:001 DB:01          MREQ	3	2	fMWrite					SP	-	R																								
#011H T11 AB:001 DB:01          MREQ    WR	3	3	fMWrite			Y																												
#end																																		
																																		
#if pla[23] & ~pla[16] : pop qq			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C1  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				SP			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					SP	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							rl	<	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				SP			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					SP	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead			Y						rh	<	d	<	R																		
#end																																		
																																		
"// Exchange, Block Transfer and Search Groups"																																		
																																		
"#if pla[2] : ex de,hl"			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:EB  M1      MREQ RD	1	2	fMFetch																														Ex_DE_HL	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																												
#end																																		
																																		
"#if pla[39] : ex af,af'"			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:08  M1      MREQ RD	1	2	fMFetch																														Ex_AF_AF'	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																												
#end																																		
																																		
#if pla[1] : exx			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:D9  M1      MREQ RD	1	2	fMFetch																														EXX	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																												
#end																																		
																																		
"#if pla[10] : ex (sp),hl"			"4,3,4,3,5"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:E3  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:0FD DB:--	2	1	fMRead				SP			W																								
#006H T6  AB:0FD DB:03          MREQ RD	2	2	fMRead					SP	+	R																								
#007H T7  AB:0FD DB:03          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:0FE DB:--	3	1	fMRead				SP			W																								
#009H T9  AB:0FE DB:D1          MREQ RD	3	2	fMRead					SP	+	R																								
#010H T10 AB:0FE DB:D1          MREQ RD	3	3	fMRead									W	<h	d	<	R																		
#011H T11 AB:0FE DB:-- 	3	4			mw		SP		-	W																								
#012H T12 AB:0FE DB:--	4	1	fMWrite						-	P	rh		>h	u	>	W																		
#013H T13 AB:0FE DB:00          MREQ	4	2	fMWrite					SP	-	R																								
#014H T14 AB:0FE DB:00          MREQ    WR	4	3	fMWrite		mw		SP		-	W																								
#015H T15 AB:0FD DB:--	5	1	fMWrite						-	P	rl		>l		>	W																		
#016H T16 AB:0FD DB:01          MREQ	5	2	fMWrite					SP	-	R																								
#017H T17 AB:0FD DB:01          MREQ    WR 	5	3	fMWrite				WZ			W																								
#018H T18 AB:0FD DB:01	5	4						HL		R																								
#019H T19 AB:0FD DB:01	5	5				Y																												
#end																																		
																																		
#if pla[0] : Non-repeating version of a block instruction			"4,3,5,(5)"																															
#always																																	NonRep	
#end																																		
																																		
#if pla[12] : ldi/ldir/ldd/lddr			"4,3,5,(5)"																															
#035H T1  AB:00A DB:--  M1	1	1	fMFetch														alu		res			H	OR			*	*	REP	0		R			
#036H T2  AB:00A DB:B0  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#037H T3  AB:004 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#038H T4  AB:004 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#039H T5  AB:000 DB:--	2	1	fMRead				HL			W																								
#040H T6  AB:000 DB:21          MREQ RD	2	2	fMRead					HL	op3	R																								
#041H T7  AB:000 DB:21          MREQ RD	2	3	fMRead		mw									d	<	R	alu	>s0		bus		L	ADD				*				W			
#042H T8  AB:000 DB:--	3	1	fMWrite				DE			W							alu	<	res			H	ADD								R			
#043H T9  AB:000 DB:21          MREQ	3	2	fMWrite					DE	op3	R																								
#044H T10 AB:000 DB:21          MREQ    WR	3	3	fMWrite				BC			W																								
#045H T11 AB:000 DB:21	3	4						BC	-	R																							WriteBC=1	Update repeat flag latch
#046H T12 AB:000 DB:21	3	5			Y	BR																												
#047H T13 AB:000 DB:--	4	1					PC			W																								
#048H T14 AB:000 DB:--	4	2						PC	-	R																								
#049H T15 AB:000 DB:--	4	3					PC			W																								
#050H T16 AB:000 DB:--	4	4						PC	-	R																								
#051H T17 AB:000 DB:--	4	5				Y																												
#end																																		
																																		
#if pla[11] : cpi/cpir/cpd/cpdr			"4,3,5,(5)"																															
#035H T1  AB:00A DB:--  M1	1	1	fMFetch														alu	<	res		0	H	SUB			*		REP	1		R			
#036H T2  AB:00A DB:B1  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF	
#037H T3  AB:004 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#038H T4  AB:004 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#039H T5  AB:000 DB:--	2	1	fMRead				HL			W																								
#040H T6  AB:000 DB:21          MREQ RD	2	2	fMRead					HL	op3	R																								
#041H T7  AB:000 DB:21          MREQ RD	2	3	fMRead		Y									d	<	R	alu	>s0		bus		L	SUB				*				W			
#042H T8  AB:000 DB:--	3	1															alu	<	res			H	SUB		*						R			
#043H T9  AB:000 DB:--	3	2																																
#044H T10 AB:000 DB:--	3	3					BC			W																								
#045H T11 AB:000 DB:--	3	4						BC	-	R																							WriteBC=1	Update repeat flag latch
#046H T12 AB:000 DB:--	3	5			Y	BRZ																												
#047H T13 AB:000 DB:--	4	1					PC			W																								
#048H T14 AB:000 DB:--	4	2						PC	-	R																								
#049H T15 AB:000 DB:--	4	3					PC			W																								
#050H T16 AB:000 DB:--	4	4						PC	-	R																								
#051H T17 AB:000 DB:--	4	5				Y																												
#end																																		
																																		
// 8-bit Arithmetic and Logic Group																																		
																																		
"#if pla[65] & ~pla[52] : add/sub/and/or/xor/cmp a,r"			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									?	<	u			alu	<	res			H	PLA		*	?		?	?	*				A is stored in each ALU PLA below
#002H T2  AB:000 DB:80  M1      MREQ RD	1	2	fMFetch									F	<				<						PLA										?NF_HF_CF	"If (NF), complement HF, CF"
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-			alu	>s0		bus		L	PLA		*	*	*		?					
#end																																		
																																		
"#if pla[64] : add/sub/and/or/xor/cmp a,n"			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									?	<	u			alu	<	res			H	PLA		*	?		?	?	*				A is stored in each ALU PLA below
#002H T2  AB:000 DB:C6  M1      MREQ RD	1	2	fMFetch									F	<				<						PLA										?NF_HF_CF	"If (NF), complement HF, CF"
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr						r8		>r8	-			alu	>s0		bus		L	PLA		*	*	*		?					
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W													PLA											
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead			Y								d	<	R	alu	>s0		bus		L	PLA		*	*	*		?					
#end																																		
																																		
#if use_ixiy & pla[52] : add/sub/and/or/xor/cp (ix+d)			"4,3,5,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:86  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead		Y																													
#012H T8  AB:002 DB:--	3	1																															WZ=IX+d	
#013H T9  AB:002 DB:--	3	2																															WZ=IX+d	
#014H T10 AB:002 DB:--	3	3																															WZ=IX+d	"Reads ""n"" at the same time"
#015H T11 AB:002 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:002 DB:--	3	5			mr																												WZ=IX+d	Clears the IX/IY and ...
#end																																		
																																		
#if ~use_ixiy & pla[52] : add/sub/and/or/xor/cp (hl)			"4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									?	<	u			alu	<	res			H	PLA		*	?		?	?	*				A is stored in each ALU PLA below
#002H T2  AB:000 DB:86  M1      MREQ RD	1	2	fMFetch									F	<				<						PLA										?NF_HF_CF	"If (NF), complement HF, CF"
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				HL			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					WZ	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead			Y								d	<	R	alu	>s0		bus		L	PLA		*	*	*		?					
																																		
#017H T13 AB:000 DB:--	4	1	fMRead							R																								...continues here
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead								AF		>				>	>s0		bus	bus				*	*	*		*	*				Reloads AF since (IX+d) used ALU core
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead			Y								d	<	R	alu	>s0		bus		L	PLA		*	*	*		?					
#end																																		
																																		
#if pla[66] & ~pla[53] : inc/dec r			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									r8	<	u			alu	<	res			H	ADC		*	*		V			R			
#002H T2  AB:000 DB:05  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF	"If (NF), complement HF"
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8'		>r8'	-			alu	>s0		0	bus	L	ADC		*	*	*		0	1	W			
#end																																		
																																		
#if pla[75] : dec																																		
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																										1	0			NEG_OP2	
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch																										1	0			NEG_OP2	
#end																																		
																																		
#if (M2 | M4) & pla[75] : dec																																		
#always																													1	0			NEG_OP2	
#end																																		
																																		
#if use_ixiy & pla[53] : inc/dec (ix+d)			"4,3,5,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:34  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead		Y																													
#012H T8  AB:002 DB:--	3	1																															WZ=IX+d	
#013H T9  AB:002 DB:--	3	2																															WZ=IX+d	
#014H T10 AB:002 DB:--	3	3																															WZ=IX+d	
#015H T11 AB:002 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:002 DB:--	3	5			mr																												WZ=IX+d	Clears the IX/IY and ...
#end																																		
																																		
#if ~use_ixiy & pla[53] : inc/dec (hl)			"4,4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:34  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF	"If (NF), complement HF"
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				HL			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead																															
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead											d	<	R	alu	>s0		0	bus	L	ADC				*		0	1	W			
#008H T8  AB:001 DB:--	2	4			mw									u	>	W	alu	<	res			H	ADC		*	*		V			R			
#009H T9  AB:001 DB:--	3	1	fMWrite							R																								
#010H T10 AB:001 DB:02          MREQ	3	2	fMWrite																															
#011H T11 AB:001 DB:02          MREQ    WR	3	3	fMWrite			Y																												
																																		
#017H T13 AB:002 DB:--	4	1	fMRead							R																								...continues here
#018H T14 AB:002 DB:01          MREQ RD	4	2	fMRead																															
#019H T15 AB:002 DB:01          MREQ RD	4	3	fMRead											d	<	R	alu	>s0		0	bus	L	ADC				*		0	1	W			
#020H T16 AB:002 DB:--	4	4			mw									u	>	W	alu	<	res			H	ADC		*	*		V			R			
#021H T17 AB:002 DB:--	5	1	fMWrite							R																								
#022H T18 AB:002 DB:02          MREQ	5	2	fMWrite																															
#023H T19 AB:002 DB:02          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
// 16-bit Arithmetic Group																																		
																																		
"#if pla[69] : add hl,ss"			"4,4,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:09  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	0	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	Y						L		>l	d				>s0			bus													
#005H T5  AB:000 DB:--	2	1									rl		>l	d			alu	>s0		bus		L	ADD				*						USE_SP	
#006H T6  AB:000 DB:--	2	2										Z	<l	u			alu	<	res			H	ADC			*				*				
#007H T7  AB:000 DB:--	2	3									H		>					>s0			bus													
#008H T8  AB:000 DB:--	2	4			Y						rh		>				alu	>s0		bus		L	ADC				*						USE_SP	
#009H T9  AB:000 DB:--	3	1					WZ			W		W	<h	u			alu	<	res			H	ADC			*				*				
#010H T10 AB:000 DB:--	3	2						HL		R																								
#011H T11 AB:000 DB:--	3	3				Y																												
#end																																		
																																		
"#if op3 & pla[68] : adc hl,ss"			"4,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:42  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	0	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	Y						L		>l	d				>s0			bus													
#009H T5  AB:001 DB:--	2	1									rl		>l	d			alu	>s0		bus		L	ADC				*						USE_SP	
#010H T6  AB:001 DB:--	2	2										Z	<l	u			alu	<	res			H	ADC		*	*				*				
#011H T7  AB:001 DB:--	2	3									H		>					>s0			bus													
#012H T8  AB:001 DB:--	2	4			Y						rh		>				alu	>s0		bus		L	ADC				*						USE_SP	
#013H T9  AB:001 DB:--	3	1					WZ			W		W	<h	u			alu	<	res			H	ADC		*	*		V		*			ZERO_16BIT	
#014H T10 AB:001 DB:--	3	2						HL		R																								
#015H T11 AB:001 DB:--	3	3				Y																												
#end																																		
																																		
"#if ~op3 & pla[68] : sbc hl,ss"			"4,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:42  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF_CF	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	1	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	Y						L		>l	d				>s0			bus													
#009H T5  AB:001 DB:--	2	1									rl		>l	d			alu	>s0		bus		L	SBC				*						USE_SP	
#010H T6  AB:001 DB:--	2	2										Z	<l	u			alu	<	res			H	SBC		*	*				*				
#011H T7  AB:001 DB:--	2	3									H		>					>s0			bus													
#012H T8  AB:001 DB:--	2	4			Y						rh		>				alu	>s0		bus		L	SBCh				*						USE_SP	
#013H T9  AB:001 DB:--	3	1					WZ			W		W	<h	u			alu	<	res			H	SBC		*	*		V		*			ZERO_16BIT	
#014H T10 AB:001 DB:--	3	2						HL		R																								
#015H T11 AB:001 DB:--	3	3				Y																												
#end																																		
																																		
#if pla[9] : inc/dec ss			6																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:03  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y			r16			W																							USE_SP	
#005H T5  AB:000 DB:--	1	5						r16	op3	R																							USE_SP	
#006H T6  AB:000 DB:--	1	6				Y																												
#end																																		
																																		
// General Purpose Arithmetic and CPU Control Groups																																		
																																		
#if pla[77] : daa			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	ADC		*	*		P		*			?NF_SUB	
#002H T2  AB:000 DB:27  M1      MREQ RD	1	2	fMFetch									F	<				<														R		?NF_HF	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	W2	*	*	*				"Only for DAA, write HF2 flag"
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y								d			alu	>s0		bus		L	ADC		*	*	*			1	W.daa		"DAA,?NF_SUB"	
#end																																		
																																		
#if pla[81] : cpl			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	OR			*			1				NEG_OP2	
#002H T2  AB:000 DB:2F  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y											alu				0	L	OR			*	*		1				NEG_OP2	
#end																																		
																																		
#if pla[82] : neg			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	SUB		*	*		V	1	*				
#006H T2  AB:001 DB:44  M1      MREQ RD	1	2	fMFetch									F	<				<																?NF_HF_CF	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y											alu				0	L	SUB		*	*	*		1	*				
#end																																		
																																		
#if pla[89] : ccf			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch														alu	<	res			H	OR			*			0					
#002H T2  AB:000 DB:3F  M1      MREQ RD	1	2	fMFetch									F	<				<													^			?~CF_HF	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y											alu					L	OR			*	*		0					
#end																																		
																																		
#if pla[92] : scf			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch														alu	<	res			H	OR			*			0					
#002H T2  AB:000 DB:37  M1      MREQ RD	1	2	fMFetch									F	<				<													1				
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y											alu					L	OR			*	*		0					
#end																																		
																																		
#if pla[95] : halt			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:76  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																														HALT	
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																												
#end																																		
																																		
#if pla[97] : di/ei			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:F3  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																														DI_EI	
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																											NO_INTS	"At last M/T, inhibit interrupts"
#end																																		
																																		
#if pla[96] : im n			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:46  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch												<	R																	IM	M1/T3 reads in mode # from opcode[4:3]
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																												
#end																																		
																																		
// Rotate and Shift Group																																		
																																		
#if pla[25] : rlca/rla/rrca/rra			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	OR			*	*		0	*				
#002H T2  AB:000 DB:07  M1      MREQ RD	1	2	fMFetch									F	<				<														R			
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					A		>				alu	>s1		bus	bus	L	OR			*	*		0		W.sh			
#end																																		
																																		
#if ~use_ixiy & pla[70] & ~pla[55] : rlc r			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									r8'	<	u			alu	<	res			H	OR		*	*	*	P	0	*				
#006H T2  AB:001 DB:00  M1      MREQ RD	1	2	fMFetch									F	<				<														R			
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-			alu	>s1		bus	bus	L	OR		*	*	*		0		W.sh			
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R																	OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s1		bus	bus	L	OR						0		W.sh			
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W	alu	<	res			H	OR		*	*	*	P	0	*				
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
#if ~use_ixiy & pla[70] & pla[55] : rlc (hl)			"4,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:00  M1      MREQ RD	1	2	fMFetch									F	<				<														R			
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:006 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:006 DB:05          MREQ RD	2	2	fMRead																															
#011H T7  AB:006 DB:05          MREQ RD	2	3	fMRead																															
#012H T8  AB:006 DB:--	2	4			mw									d	<	R	alu	>s1		bus	bus	L	OR						0		W.sh			
#013H T9  AB:006 DB:--	3	1	fMWrite							R				u	>	W	alu	<	res			H	OR		*	*	*	P	0	*				
#014H T10 AB:006 DB:0A          MREQ	3	2	fMWrite																															
#015H T11 AB:006 DB:0A          MREQ    WR	3	3	fMWrite			Y																												
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R																	OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s1		bus	bus	L	OR						0		W.sh			
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W	alu	<	res			H	OR		*	*	*	P	0	*				
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
#if pla[15] & op3 : rld			"4,3,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	OR		*	*		P	0					
#006H T2  AB:001 DB:67  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:000 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:000 DB:ED          MREQ RD	2	2	fMRead					WZ	+	R																								
#011H T7  AB:000 DB:ED          MREQ RD	2	3	fMRead		Y																													
#012H T8  AB:000 DB:--	3	1												d	<	R		>s0		lq		L												
#013H T9  AB:000 DB:--	3	2																																
#014H T10 AB:000 DB:--	3	3																																
#015H T11 AB:000 DB:--	3	4			mw									d	<	R		>s0			low	H												
#016H T12 AB:000 DB:--	4	1	fMWrite							R				u	>	W		<	op2															
#017H T13 AB:000 DB:EE          MREQ	4	2	fMWrite																op1	bus														
#018H T14 AB:000 DB:EE          MREQ    WR	4	3	fMWrite			Y											alu					L	OR		*	*	*		0					
#end																																		
																																		
#if pla[15] & ~op3 : rrd			"4,3,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									A	<				alu	<	res			H	OR		*	*		P	0					
#006H T2  AB:001 DB:67  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:000 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:000 DB:ED          MREQ RD	2	2	fMRead					WZ	+	R																								
#011H T7  AB:000 DB:ED          MREQ RD	2	3	fMRead		Y																													
#012H T8  AB:000 DB:--	3	1												d	<	R		>s0		lq	low	L												
#013H T9  AB:000 DB:--	3	2												u	>	W		<	op2															
#014H T10 AB:000 DB:--	3	3									A		>					>s0		lq		L												
#015H T11 AB:000 DB:--	3	4			mw									d	<	R		>s0			low	H												
#016H T12 AB:000 DB:--	4	1	fMWrite							R				u	>	W		<	op2															
#017H T13 AB:000 DB:EE          MREQ	4	2	fMWrite																op1	bus														
#018H T14 AB:000 DB:EE          MREQ    WR	4	3	fMWrite			Y											alu					L	OR		*	*	*		0					
#end																																		
																																		
// Bit Manipulation Group																																		
																																		
"#if ~use_ixiy & pla[72] & ~pla[55] : bit b,r"			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch														alu	<	res			H	AND		*		*	P	0					
#006H T2  AB:001 DB:40  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-			alu	>s0			bus	L	AND		*	*	*		0					
																																		
#017H T13 AB:000 DB:--	4	1	fMRead							R						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead																															
#020H T16 AB:000 DB:--	4	4				Y								d	<	R	alu	>s0			bus	L	AND		*		*		0					
#end																																		
																																		
"#if ~use_ixiy & pla[72] & pla[55] : bit b,(hl)"			"4,4"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch														alu	<	res			H	AND		*		*	P	0					
#006H T2  AB:001 DB:06  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:006 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:006 DB:05          MREQ RD	2	2	fMRead																															
#011H T7  AB:006 DB:05          MREQ RD	2	3	fMRead								WZ		>				>									*								"BIT n,(HL) saves WZ in X,Y (""MEMPTR"")"
#012H T8  AB:006 DB:--	2	4				Y								d	<	R	alu	>s0			bus	L	AND		*		*		0					
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead																															
#020H T16 AB:000 DB:--	4	4				Y								d	<	R	alu	>s0			bus	L	AND		*		*		0					
#end																																		
																																		
"#if ~use_ixiy & pla[74] & ~pla[55] : set b,r"			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									r8'	<	u				<	res			H	OR											
#006H T2  AB:001 DB:40  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-				>s0			bus	L	OR											
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s0			bus	L	OR											
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W		<	res			H	OR											
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
"#if ~use_ixiy & pla[74] & pla[55] : set b,(hl)"			"4,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:06  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:006 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:006 DB:05          MREQ RD	2	2	fMRead																															
#011H T7  AB:006 DB:05          MREQ RD	2	3	fMRead											d	<	R		>s0			bus	L	OR											
#012H T8  AB:006 DB:--	2	4			mw									u	>	W		<	res			H	OR											
#013H T9  AB:006 DB:--	3	1	fMWrite							R																								
#014H T10 AB:006 DB:0A          MREQ	3	2	fMWrite																															
#015H T11 AB:006 DB:0A          MREQ    WR	3	3	fMWrite			Y																												
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s0			bus	L	OR											
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W		<	res			H	OR											
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
"#if ~use_ixiy & pla[73] & ~pla[55] : res b,r"			4																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									r8'	<	u				<	res			H	NAND											
#006H T2  AB:001 DB:40  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y					r8		>r8	-				>s0			bus	L	NAND											
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s0			bus	L	NAND											
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W		<	res			H	NAND											
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
"#if ~use_ixiy & pla[73] & pla[55] : res b,(hl)"			"4,4,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:06  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>			R	>	>bs		bus	bus				*	*	*	*	*	*				Override M1/T3 load with a bit select
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:006 DB:--	2	1	fMRead				HL			W																								
#010H T6  AB:006 DB:05          MREQ RD	2	2	fMRead																															
#011H T7  AB:006 DB:05          MREQ RD	2	3	fMRead											d	<	R		>s0			bus	L	NAND											
#012H T8  AB:006 DB:--	2	4			mw									u	>	W		<	res			H	NAND											
#013H T9  AB:006 DB:--	3	1	fMWrite							R																								
#014H T10 AB:006 DB:0A          MREQ	3	2	fMWrite																															
#015H T11 AB:006 DB:0A          MREQ    WR	3	3	fMWrite			Y																												
																																		
#017H T13 AB:000 DB:--	4	1	fMRead				WZ			W						R		>bs		bus	bus												OpcodeToIR	...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD          MREQ RD	4	2	fMRead																															
#019H T15 AB:000 DB:DD          MREQ RD	4	3	fMRead		mw									d	<	R	alu	>s0			bus	L	NAND											
#029H T17 AB:002 DB:--	5	1	fMWrite							R				u	>	W		<	res			H	NAND											
#030H T18 AB:002 DB:BB          MREQ	5	2	fMWrite																															
#031H T19 AB:002 DB:BB          MREQ    WR	5	3	fMWrite			Y																												
#end																																		
																																		
// Input and Output Groups																																		
																																		
"#if pla[37] & ~pla[28] : in a,(n)"			"4,3,4"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<	d	<	R																		
#002H T2  AB:000 DB:DB  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		ior																													
#008H T8  AB:001 DB:--	3	1	fIORead				A			W		?	<		<	R																		
#009H T9  AB:001 DB:--               RD    IORQ	3	2	fIORead																															
#010H T10 AB:001 DB:--               RD    IORQ	3	3	fIORead																															
#011H T11 AB:001 DB:--               RD    IORQ	3	4	fIORead			Y																												
#end																																		
																																		
"#if pla[27] & ~pla[34] : in r,(c)"			"4,4"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch									r8	<	d	<	R	alu		res			H	OR		*	*		P	0					
#006H T2  AB:001 DB:40  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	ior																													
#009H T5  AB:0FF DB:--	2	1	fIORead				BC			W																								
#010H T6  AB:0FF DB:--               RD    IORQ	2	2	fIORead																															
#011H T7  AB:0FF DB:--               RD    IORQ	2	3	fIORead																															
#012H T8  AB:0FF DB:--               RD    IORQ	2	4	fIORead			Y								d	<	R	alu	>s0		bus	bus	L	OR		*	*	*		0					
#end																																		
																																		
"#if pla[37] & pla[28] : out (n),a"			"4,3,4"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:D3  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		iow		A			W			<l		<	R																		
#008H T8  AB:001 DB:--	3	1	fIOWrite							R	A		>h	u	>	W																		
#009H T9  AB:001 DB:03                  WR IORQ	3	2	fIOWrite																															
#010H T10 AB:001 DB:03                  WR IORQ	3	3	fIOWrite																															
#011H T11 AB:001 DB:03                  WR IORQ	3	4	fIOWrite			Y																												
#end																																		
																																		
"#if pla[27] & pla[34] : out (c),r"			"4,4"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:41  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	iow						r8'		>r8'	-	>	W																		
#009H T5  AB:0FF DB:--	2	1	fIOWrite				BC			W																								
#010H T6  AB:0FF DB:C3                  WR IORQ	2	2	fIOWrite																															
#011H T7  AB:0FF DB:C3                  WR IORQ	2	3	fIOWrite																															
#012H T8  AB:0FF DB:C3                  WR IORQ	2	4	fIOWrite			Y																												
#end																																		
																																		
#if pla[91] & pla[21] : ini/inir/ind/indr			"5,4,3,(5)"																															
#035H T1  AB:00A DB:--  M1	1	1	fMFetch															<	res			H	XOR					P						
#036H T2  AB:00A DB:B2  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#037H T3  AB:004 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#038H T4  AB:004 DB:--     RFSH MREQ	1	4	fMFetch	Y																														
#039H T5  AB:004 DB:--	1	5			ior																													
#040H T6  AB:000 DB:--	2	1	fIORead				BC			W																								
#041H T7  AB:000 DB:--               RD    IORQ	2	2	fIORead								B		>				alu	>s0		0	bus	L	ADD				*						NEG_OP2	
#042H T8  AB:000 DB:--               RD    IORQ	2	3	fIORead									B	<				alu	<	res			H	ADD		*	*				*			NEG_OP2	
#043H T9  AB:000 DB:--               RD    IORQ	2	4	fIORead		mw									d	<	R	alu	>s0			bus								S				NEG_OP2	
#044H T10 AB:000 DB:--	3	1	fMWrite				HL			W																								
#045H T11 AB:000 DB:B1          MREQ	3	2	fMWrite					HL	op3	R																								
#046H T12 AB:000 DB:B1          MREQ    WR	3	3	fMWrite		Y	BZ																												
#047H T13 AB:000 DB:--	4	1					PC			W																								
#048H T14 AB:000 DB:--	4	2						PC	-	R																								
#049H T15 AB:000 DB:--	4	3					PC			W																								
#050H T16 AB:000 DB:--	4	4						PC	-	R																								
#051H T17 AB:000 DB:--	4	5				Y																												
#end																																		
																																		
#if pla[91] & pla[20] : outi/outir/outd/outdr			"5,4,3,(5)"																															
#035H T1  AB:00A DB:--  M1	1	1	fMFetch														alu	<	res			H	XOR					P						
#036H T2  AB:00A DB:B3  M1      MREQ RD	1	2	fMFetch									F	<				<																	
#037H T3  AB:004 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#038H T4  AB:004 DB:--     RFSH MREQ	1	4	fMFetch	Y							B		>				alu	>s0		0	bus	L	ADD				*						NEG_OP2	
#039H T5  AB:004 DB:--	1	5			mr							B	<				alu	<	res			H	ADD		*	*							NEG_OP2	
#040H T6  AB:000 DB:--	2	1	fMRead				HL			W																								
#041H T7  AB:000 DB:21          MREQ RD	2	2	fMRead					HL	op3	R																								
#042H T8  AB:000 DB:21          MREQ RD	2	3	fMRead		iow						L		>l	d				>s0			bus													
#043H T9  AB:000 DB:--	3	1	fIOWrite				BC			W																								
#044H T10 AB:000 DB:21                  WR IORQ	3	2	fIOWrite											d	<	R	alu	>s0		bus		L	ADD				*		S					
#045H T11 AB:000 DB:21                  WR IORQ	3	3	fIOWrite														alu	<	res			H	ADD							*				
#046H T12 AB:000 DB:21                  WR IORQ	3	4	fIOWrite		Y	BZ																												
#047H T13 AB:000 DB:--	4	1					PC			W																								
#048H T14 AB:000 DB:--	4	2						PC	-	R																								
#049H T15 AB:000 DB:--	4	3					PC			W																								
#050H T16 AB:000 DB:--	4	4						PC	-	R																								
#051H T17 AB:000 DB:--	4	5				Y																												
#end																																		
																																		
// Jump Group																																		
																																		
#if pla[29] : jp nn			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C3  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead			Y	WZ			W		W	<h	d	<	R																	NOT_PC!	
#end																																		
																																		
"#if pla[43] : jp cc,nn"			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C2  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead			Y	WZ?			W		W?	<h	d	<	R																		Select WZ if condition is true
#end																																		
																																		
#if pla[47] : jr e			"4,3,5"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:18  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		Y																													
#008H T8  AB:001 DB:--	3	1												d	<	R	alu	>s0		bus					*									"Reads ""e"" from the data latch"
#009H T9  AB:001 DB:--	3	2									PCl		>l	d			alu	>s0			bus	L	ADD				*							
#010H T10 AB:001 DB:--	3	3										Z	<l	u			alu	<	res			H	ADD							*				
#011H T11 AB:001 DB:--	3	4									PCh		>				alu	>s0		0	bus	L	ADC				*						?SF_NEG	
#012H T12 AB:001 DB:--	3	5				Y	WZ			W		W	<h				alu	<	res			H	ADC										"?SF_NEG, NOT_PC!"	
#end																																		
																																		
"#if pla[48] : jr ss,e"			"4,3,(5)"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:20  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																												CondShort	M1/T4 evaluates a condition: force short
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		Y	SS																												
#008H T8  AB:001 DB:--	3	1												d	<	R	alu	>s0		bus					*									"Reads ""e"" from the data latch"
#009H T9  AB:001 DB:--	3	2									PCl		>l	d			alu	>s0			bus	L	ADD				*							
#010H T10 AB:001 DB:--	3	3										Z	<l	u			alu	<	res			H	ADD							*				
#011H T11 AB:001 DB:--	3	4									PCh		>				alu	>s0		0	bus	L	ADC				*						?SF_NEG	
#012H T12 AB:001 DB:--	3	5				Y	WZ			W		W	<h				alu	<	res			H	ADC										"?SF_NEG, NOT_PC!"	
#end																																		
																																		
#if pla[6] : jp hl			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:E9  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y	HL			W																							NOT_PC!	
#end																																		
																																		
#if pla[26] : djnz e			"5,3,(5)"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:10  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y							B		>h				alu	>s0		0	bus	L	ADD				*						NEG_OP2	B=B-1
#005H T5  AB:000 DB:--	1	5			mr							B	<				alu	<	res			H	ADD		*								NEG_OP2	
#006H T6  AB:001 DB:--	2	1	fMRead				PC			W																								
#007H T7  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#008H T8  AB:001 DB:01          MREQ RD	2	3	fMRead		Y	ZF																												
#009H T9  AB:001 DB:--	3	1												d	<	R	alu	>s0		bus					*									"Reads ""e"" from the data latch"
#010H T10 AB:001 DB:--	3	2									PCl		>l	d			alu	>s0			bus	L	ADD				*							
#011H T11 AB:001 DB:--	3	3										Z	<l	u			alu	<	res			H	ADD							*				
#012H T12 AB:001 DB:--	3	4									PCh		>h				alu	>s0		0	bus	L	ADC				*						?SF_NEG	
#013H T13 AB:001 DB:--	3	5				Y	WZ			W		W	<h				alu	<	res			H	ADC										"?SF_NEG, NOT_PC!"	
#end																																		
																																		
// Call and Return Group																																		
																																		
#if pla[24] : call nn			"4,3,4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:CD  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead									W	<h	d	<	R																		
#011H T11 AB:002 DB:--	3	4			mw		SP		-	W																								
#012H T12 AB:000 DB:--	4	1	fMWrite						-	P	PCh		>h	u	>	W																		
#013H T13 AB:000 DB:00          MREQ	4	2	fMWrite					SP	-	R																								
#014H T14 AB:000 DB:00          MREQ    WR	4	3	fMWrite		mw		SP		-	W																								
#015H T15 AB:0FF DB:--	5	1	fMWrite						-	P	PCl		>l		>	W																		
#016H T16 AB:0FF DB:03          MREQ	5	2	fMWrite					SP	-	R																								
#017H T17 AB:0FF DB:03          MREQ    WR	5	3	fMWrite			Y	WZ			W																							NOT_PC!	
#end																																		
																																		
"#if pla[42] : call cc,nn"			"4,3,3/(4,3,4,3,3)"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C4  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:001 DB:--	2	1	fMRead				PC			W																								
#006H T6  AB:001 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#007H T7  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:002 DB:--	3	1	fMRead				PC			W																								
#009H T9  AB:002 DB:02          MREQ RD	3	2	fMRead					PC	+	R																								
#010H T10 AB:002 DB:02          MREQ RD	3	3	fMRead		CC	CC						W?	<h	d	<	R																		Load W only if condition is true
#011H T11 AB:002 DB:--	3	4			mw		SP		-	W																								
#012H T12 AB:000 DB:--	4	1	fMWrite						-	P	PCh		>h	u	>	W																		
#013H T13 AB:000 DB:00          MREQ	4	2	fMWrite					SP	-	R																								
#014H T14 AB:000 DB:00          MREQ    WR	4	3	fMWrite		mw		SP		-	W																								
#015H T15 AB:0FF DB:--	5	1	fMWrite						-	P	PCl		>l		>	W																		
#016H T16 AB:0FF DB:03          MREQ	5	2	fMWrite					SP	-	R																								
#017H T17 AB:0FF DB:03          MREQ    WR	5	3	fMWrite			Y	WZ			W																							NOT_PC!	
#end																																		
																																		
#if pla[35] : ret			"4,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C9  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#005H T5  AB:0FF DB:--	2	1	fMRead				SP			W																								
#006H T6  AB:0FF DB:01          MREQ RD	2	2	fMRead					SP	+	R																								
#007H T7  AB:0FF DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#008H T8  AB:000 DB:--	3	1	fMRead				SP			W																								
#009H T9  AB:000 DB:C9          MREQ RD	3	2	fMRead					SP	+	R																								
#010H T10 AB:000 DB:C9          MREQ RD	3	3	fMRead			Y	WZ			W		W	<h	d	<	R																	NOT_PC!	
#end																																		
																																		
#if pla[45] : ret cc			"5/(5,3,3)"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C0  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*				
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y																														
#005H T5  AB:000 DB:--	1	5			mr	CC																												
#006H T6  AB:001 DB:--	2	1	fMRead				SP			W																								
#007H T7  AB:001 DB:01          MREQ RD	2	2	fMRead					SP	+	R																								
#008H T8  AB:001 DB:01          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#009H T9  AB:002 DB:--	3	1	fMRead				SP			W																								
#010H T10 AB:002 DB:02          MREQ RD	3	2	fMRead					SP	+	R																								
#011H T11 AB:002 DB:02          MREQ RD	3	3	fMRead			Y	WZ			W		W	<h	d	<	R																	NOT_PC!	
#end																																		
																																		
#if pla[46] : reti/retn			"4,3,3"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:45  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch																															
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																												RETN	IFF1<=IFF2
#009H T5  AB:001 DB:--	2	1	fMRead				SP			W																								
#010H T6  AB:001 DB:45          MREQ RD	2	2	fMRead					SP	+	R																								
#011H T7  AB:001 DB:45          MREQ RD	2	3	fMRead		mr							Z	<l	d	<	R																		
#012H T8  AB:002 DB:--	3	1	fMRead				SP			W																								
#013H T9  AB:002 DB:01          MREQ RD	3	2	fMRead					SP	+	R																								
#014H T10 AB:002 DB:01          MREQ RD	3	3	fMRead			Y	WZ			W		W	<h	d	<	R																	NOT_PC!	
#end																																		
																																		
#if pla[56] : rst p			"5,3,3"																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:C7  M1      MREQ RD	1	2	fMFetch																															
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch									WZ	<			R		<	op1		0												"MASK_543, RST_NMI, RST_INT"	RST instruction also executes on NMI and INT
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y																														
#005H T5  AB:000 DB:--	1	5			mw		SP		-	W				d	<	R		>s0			bus													Store im2 vector into the ALU op1
#006H T6  AB:000 DB:--	2	1	fMWrite						-	P	PCh		>h	u	>	W																		
#007H T7  AB:000 DB:00          MREQ	2	2	fMWrite					SP	-	R																								
#008H T8  AB:000 DB:00          MREQ    WR	2	3	fMWrite		mw		SP		-	W																								
#009H T9  AB:0FF DB:--	3	1	fMWrite						-	P	PCl		>l		>	W																		
#010H T10 AB:0FF DB:01          MREQ	3	2	fMWrite					SP	-	R																								
#011H T11 AB:0FF DB:01          MREQ    WR	3	3	fMWrite		INT	INT	WZ			W																							NOT_PC!	Value on the bus into ALU OP
// INTR IM2 continues here...																																		Extension for IM2 interrupt mode
#012H T12 AB:001 DB:--	4	1	fMRead				I*			W			<l	u				<	op1															
#013H T13 AB:001 DB:01          MREQ RD	4	2	fMRead					>	+	R			>l	d				>s0			bus													
#014H T14 AB:001 DB:01          MREQ RD	4	3	fMRead		mr							Z	<l	d	<	R																		
#015H T15 AB:002 DB:--	5	1	fMRead				I*			W			<l	u				<	op1															
#016H T16 AB:002 DB:02          MREQ RD	5	2	fMRead						+	R																								
#017H T17 AB:002 DB:02          MREQ RD	5	3	fMRead			Y	WZ			W		W	<h	d	<	R																	NOT_PC!	
#end																																		
																																		
// CB-Table opcodes																																		
																																		
#if pla[49] : Every CB with IX/IY			"4,3,5,+"																															
#005H T1  AB:001 DB:--  M1	1	1	fMFetch																															
#006H T2  AB:001 DB:CB  M1      MREQ RD	1	2	fMFetch																															
#007H T3  AB:001 DB:--     RFSH	1	3	fMFetch								AF		>				>	>s0		bus	bus				*	*	*	*	*	*			CB	
#008H T4  AB:001 DB:--     RFSH MREQ	1	4	fMFetch	Y	mr																													
#009H T5  AB:002 DB:--	2	1	fMRead				PC			W																								
#010H T6  AB:002 DB:01          MREQ RD	2	2	fMRead					PC	+	R																								
#011H T7  AB:002 DB:01          MREQ RD	2	3	fMRead		mr																													
#012H T8  AB:003 DB:--	3	1	fMRead				PC			W																							WZ=IX+d	
#013H T9  AB:003 DB:00          MREQ RD	3	2	fMRead					PC	+	R																							WZ=IX+d	
#014H T10 AB:003 DB:00          MREQ RD	3	3	fMRead																														WZ=IX+d	Loads the opcode byte in parallel
#015H T11 AB:003 DB:--	3	4																															WZ=IX+d	
#016H T12 AB:003 DB:--	3	5			mr																												WZ=IX+d	
#017H T13 AB:000 DB:--	4	1														R		>bs		bus	bus												OpcodeToIR	Loads instruction register; starts the execute cycle
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle																																		
#end																																		
																																		
// Special Purposes PLA Entries																																		
																																		
#if pla[3] : IX/IY			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:DD  M1      MREQ RD	1	2	fMFetch																														IX_IY	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																											NO_INTS	"At last M/T, inhibit interrupts"
#end																																		
																																		
#if pla[44] : CB prefix			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:CB  M1      MREQ RD	1	2	fMFetch																														CB	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																											NO_INTS	"At last M/T, inhibit interrupts"
"#end Only set CB ff and clear ED, XX ff"																																		
																																		
#if pla[51] : ED prefix			4																															
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																															
#002H T2  AB:000 DB:ED  M1      MREQ RD	1	2	fMFetch																														ED	
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch																															
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch	Y		Y																											NO_INTS	"At last M/T, inhibit interrupts"
"#end Only set ED ff and clear CB, XX ff"																																		
																																		
#if pla[76] : ALU CP																																		
#always																							CP						1					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch																									V						Update P/V once on a high nibble phase
#end																																		Does not store the result!
																																		
#if pla[78] : ALU SUB																																		
#always																							SUB						1					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		V						Update P/V and store result to A
#end																																		
																																		
#if pla[79] : ALU SBC																																		
#always																							SBC						1					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		V						Update P/V and store result to A
#end																																		
																																		
#if pla[80] : ALU ADC																																		
#always																							ADC						0					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		V						Update P/V and store result to A
#end																																		
																																		
#if pla[84] : ALU ADD																																		
#always																							ADD						0					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		V						Update P/V and store result to A
#end																																		
																																		
#if pla[85] : ALU AND																																		
#always																							AND						0					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		P						Update P/V and store result to A
#002H T2  AB:000 DB:A0  M1      MREQ RD	1	2	fMFetch																											0				AND clears CF
#end																																		
																																		
#if pla[86] : ALU OR																																		
#always																							OR						0					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		P						Update P/V and store result to A
#002H T2  AB:000 DB:B0  M1      MREQ RD	1	2	fMFetch																											0				OR clears CF
#end																																		
																																		
#if pla[88] : ALU XOR																																		
#always																							XOR						0					
#001H T1  AB:000 DB:--  M1	1	1	fMFetch									A	<													*		P						Update P/V and store result to A
#002H T2  AB:000 DB:A8  M1      MREQ RD	1	2	fMFetch																											0				XOR clears CF
#end																																		
																																		
// State machine to compute (IX+d)																																		
#if ixy_d : Compute WZ=IX+d																																		
#001H T1 any M-cycle	?	1												d	<	R	alu	>s0		bus					*									"Reads ""d"" from the data latch"
#002H T2	?	2									L		>l	d			alu	>s0			bus	L	ADD				*							
#003H T3	?	3										Z	<l	u			alu	<	res			H	ADC								W			
#004H T4	?	4									H		>				alu	>s0		0	bus	L	ADC				*				R		?SF_NEG	Stores result into WZ
#005H T5	?	5					WZ			W		W	<h				alu	<	res			H	ADC			*							"?SF_NEG, CLR_IX_IY"	and disables any further use of IX/IY
#end																																		
																																		
// Default instruction fetch (M1) state machine																																		
#if 1 :																																		
#001H T1  AB:000 DB:--  M1	1	1	fMFetch					PC	+	RL																								Fetch/execute overlap
#002H T2  AB:000 DB:CB  M1      MREQ RD	1	2	fMFetch				IR			W						R																	"CLR_IX_IY, CLR_CB_ED, OpcodeToIR, OverrideIR"	Prepares for the next execution cycle
#003H T3  AB:000 DB:--     RFSH	1	3	fMFetch					IR	+	RL																							Limit6	"Fetch opcode, evaluate flags"
#004H T4  AB:000 DB:--     RFSH MREQ	1	4	fMFetch																														EvalCond	
#end																																		
																																		
"// For all undecoded instructions, at M1/T4 advance a byte to the next opcode"																																		
#if ~validPLA : A catch-all case																																		
#001H	1	4				Y																												
#end																																		
																																		
// The last cycle of an instruction is also the first cycle of the next one																																		
#if setM1 :																																		
#always							PC			W																								Fetch/execute overlap
#end