// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

// DATE "03/30/2022 12:38:42"

// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module spectrum (
	CLOCK_50,
	LED);
input 	CLOCK_50;
output 	[7:0] LED;

// Design Ports Information
// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("spectrum_6_1200mv_85c_v_slow.sdo");
// synopsys translate_on

wire \LED[0]~output_o ;
wire \LED[1]~output_o ;
wire \LED[2]~output_o ;
wire \LED[3]~output_o ;
wire \LED[4]~output_o ;
wire \LED[5]~output_o ;
wire \LED[6]~output_o ;
wire \LED[7]~output_o ;
wire \CLOCK_50~input_o ;
wire \CLOCK_50~inputclkctrl_outclk ;
wire \Add0~0_combout ;
wire \Add0~1 ;
wire \Add0~2_combout ;
wire \Add0~3 ;
wire \Add0~4_combout ;
wire \Add0~5 ;
wire \Add0~6_combout ;
wire \Add0~7 ;
wire \Add0~8_combout ;
wire \Add0~9 ;
wire \Add0~10_combout ;
wire \Add0~11 ;
wire \Add0~12_combout ;
wire \Add0~13 ;
wire \Add0~14_combout ;
wire \Add0~15 ;
wire \Add0~16_combout ;
wire \Add0~17 ;
wire \Add0~18_combout ;
wire \Add0~19 ;
wire \Add0~20_combout ;
wire \Add0~21 ;
wire \Add0~22_combout ;
wire \Add0~23 ;
wire \Add0~24_combout ;
wire \Add0~25 ;
wire \Add0~26_combout ;
wire \Add0~27 ;
wire \Add0~28_combout ;
wire \Add0~29 ;
wire \Add0~30_combout ;
wire \Add0~31 ;
wire \Add0~32_combout ;
wire \Add0~33 ;
wire \Add0~34_combout ;
wire \Add0~35 ;
wire \Add0~36_combout ;
wire \Add0~37 ;
wire \Add0~38_combout ;
wire \Add0~39 ;
wire \Add0~40_combout ;
wire \Equal0~5_combout ;
wire \Equal0~1_combout ;
wire \Equal0~0_combout ;
wire \Equal0~2_combout ;
wire \Equal0~3_combout ;
wire \Equal0~4_combout ;
wire \address[0]~0_combout ;
wire \Equal0~6_combout ;
wire \Equal0~7_combout ;
wire \address[1]~1_combout ;
wire \address[1]~2_combout ;
wire \address[2]~3_combout ;
wire [20:0] counter;
wire [2:0] address;
wire [7:0] \rom|altsyncram_component|auto_generated|q_a ;

wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];

// Location: IOOBUF_X38_Y34_N16
cycloneive_io_obuf \LED[0]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[0]~output .bus_hold = "false";
defparam \LED[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N2
cycloneive_io_obuf \LED[1]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[1]~output .bus_hold = "false";
defparam \LED[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N9
cycloneive_io_obuf \LED[2]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[2]~output .bus_hold = "false";
defparam \LED[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y34_N2
cycloneive_io_obuf \LED[3]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[3]~output .bus_hold = "false";
defparam \LED[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y25_N9
cycloneive_io_obuf \LED[4]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[4]~output .bus_hold = "false";
defparam \LED[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y26_N16
cycloneive_io_obuf \LED[5]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[5]~output .bus_hold = "false";
defparam \LED[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y28_N9
cycloneive_io_obuf \LED[6]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[6]~output .bus_hold = "false";
defparam \LED[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y10_N23
cycloneive_io_obuf \LED[7]~output (
	.i(\rom|altsyncram_component|auto_generated|q_a [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[7]~output .bus_hold = "false";
defparam \LED[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X27_Y0_N22
cycloneive_io_ibuf \CLOCK_50~input (
	.i(CLOCK_50),
	.ibar(gnd),
	.o(\CLOCK_50~input_o ));
// synopsys translate_off
defparam \CLOCK_50~input .bus_hold = "false";
defparam \CLOCK_50~input .simulate_z_as = "z";
// synopsys translate_on

// Location: CLKCTRL_G18
cycloneive_clkctrl \CLOCK_50~inputclkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\CLOCK_50~inputclkctrl_outclk ));
// synopsys translate_off
defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: FF_X31_Y17_N21
dffeas \counter[20] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~40_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[20]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[20] .is_wysiwyg = "true";
defparam \counter[20] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N12
cycloneive_lcell_comb \Add0~0 (
// Equation(s):
// \Add0~0_combout  = counter[0] $ (VCC)
// \Add0~1  = CARRY(counter[0])

	.dataa(counter[0]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add0~0_combout ),
	.cout(\Add0~1 ));
// synopsys translate_off
defparam \Add0~0 .lut_mask = 16'h55AA;
defparam \Add0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X31_Y18_N13
dffeas \counter[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[0]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[0] .is_wysiwyg = "true";
defparam \counter[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N14
cycloneive_lcell_comb \Add0~2 (
// Equation(s):
// \Add0~2_combout  = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND)))
// \Add0~3  = CARRY((!\Add0~1 ) # (!counter[1]))

	.dataa(gnd),
	.datab(counter[1]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~1 ),
	.combout(\Add0~2_combout ),
	.cout(\Add0~3 ));
// synopsys translate_off
defparam \Add0~2 .lut_mask = 16'h3C3F;
defparam \Add0~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N15
dffeas \counter[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[1]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[1] .is_wysiwyg = "true";
defparam \counter[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N16
cycloneive_lcell_comb \Add0~4 (
// Equation(s):
// \Add0~4_combout  = (counter[2] & (\Add0~3  $ (GND))) # (!counter[2] & (!\Add0~3  & VCC))
// \Add0~5  = CARRY((counter[2] & !\Add0~3 ))

	.dataa(gnd),
	.datab(counter[2]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~3 ),
	.combout(\Add0~4_combout ),
	.cout(\Add0~5 ));
// synopsys translate_off
defparam \Add0~4 .lut_mask = 16'hC30C;
defparam \Add0~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N17
dffeas \counter[2] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~4_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[2]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[2] .is_wysiwyg = "true";
defparam \counter[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N18
cycloneive_lcell_comb \Add0~6 (
// Equation(s):
// \Add0~6_combout  = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND)))
// \Add0~7  = CARRY((!\Add0~5 ) # (!counter[3]))

	.dataa(gnd),
	.datab(counter[3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~5 ),
	.combout(\Add0~6_combout ),
	.cout(\Add0~7 ));
// synopsys translate_off
defparam \Add0~6 .lut_mask = 16'h3C3F;
defparam \Add0~6 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N19
dffeas \counter[3] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~6_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[3]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[3] .is_wysiwyg = "true";
defparam \counter[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N20
cycloneive_lcell_comb \Add0~8 (
// Equation(s):
// \Add0~8_combout  = (counter[4] & (\Add0~7  $ (GND))) # (!counter[4] & (!\Add0~7  & VCC))
// \Add0~9  = CARRY((counter[4] & !\Add0~7 ))

	.dataa(counter[4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~7 ),
	.combout(\Add0~8_combout ),
	.cout(\Add0~9 ));
// synopsys translate_off
defparam \Add0~8 .lut_mask = 16'hA50A;
defparam \Add0~8 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N21
dffeas \counter[4] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~8_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[4]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[4] .is_wysiwyg = "true";
defparam \counter[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N22
cycloneive_lcell_comb \Add0~10 (
// Equation(s):
// \Add0~10_combout  = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND)))
// \Add0~11  = CARRY((!\Add0~9 ) # (!counter[5]))

	.dataa(gnd),
	.datab(counter[5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~9 ),
	.combout(\Add0~10_combout ),
	.cout(\Add0~11 ));
// synopsys translate_off
defparam \Add0~10 .lut_mask = 16'h3C3F;
defparam \Add0~10 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N23
dffeas \counter[5] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~10_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[5]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[5] .is_wysiwyg = "true";
defparam \counter[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N24
cycloneive_lcell_comb \Add0~12 (
// Equation(s):
// \Add0~12_combout  = (counter[6] & (\Add0~11  $ (GND))) # (!counter[6] & (!\Add0~11  & VCC))
// \Add0~13  = CARRY((counter[6] & !\Add0~11 ))

	.dataa(counter[6]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~11 ),
	.combout(\Add0~12_combout ),
	.cout(\Add0~13 ));
// synopsys translate_off
defparam \Add0~12 .lut_mask = 16'hA50A;
defparam \Add0~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N25
dffeas \counter[6] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~12_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[6]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[6] .is_wysiwyg = "true";
defparam \counter[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N26
cycloneive_lcell_comb \Add0~14 (
// Equation(s):
// \Add0~14_combout  = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND)))
// \Add0~15  = CARRY((!\Add0~13 ) # (!counter[7]))

	.dataa(gnd),
	.datab(counter[7]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~13 ),
	.combout(\Add0~14_combout ),
	.cout(\Add0~15 ));
// synopsys translate_off
defparam \Add0~14 .lut_mask = 16'h3C3F;
defparam \Add0~14 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N27
dffeas \counter[7] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~14_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[7]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[7] .is_wysiwyg = "true";
defparam \counter[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N28
cycloneive_lcell_comb \Add0~16 (
// Equation(s):
// \Add0~16_combout  = (counter[8] & (\Add0~15  $ (GND))) # (!counter[8] & (!\Add0~15  & VCC))
// \Add0~17  = CARRY((counter[8] & !\Add0~15 ))

	.dataa(gnd),
	.datab(counter[8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~15 ),
	.combout(\Add0~16_combout ),
	.cout(\Add0~17 ));
// synopsys translate_off
defparam \Add0~16 .lut_mask = 16'hC30C;
defparam \Add0~16 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N29
dffeas \counter[8] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~16_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[8]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[8] .is_wysiwyg = "true";
defparam \counter[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N30
cycloneive_lcell_comb \Add0~18 (
// Equation(s):
// \Add0~18_combout  = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND)))
// \Add0~19  = CARRY((!\Add0~17 ) # (!counter[9]))

	.dataa(counter[9]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~17 ),
	.combout(\Add0~18_combout ),
	.cout(\Add0~19 ));
// synopsys translate_off
defparam \Add0~18 .lut_mask = 16'h5A5F;
defparam \Add0~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y18_N31
dffeas \counter[9] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~18_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[9]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[9] .is_wysiwyg = "true";
defparam \counter[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N0
cycloneive_lcell_comb \Add0~20 (
// Equation(s):
// \Add0~20_combout  = (counter[10] & (\Add0~19  $ (GND))) # (!counter[10] & (!\Add0~19  & VCC))
// \Add0~21  = CARRY((counter[10] & !\Add0~19 ))

	.dataa(gnd),
	.datab(counter[10]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~19 ),
	.combout(\Add0~20_combout ),
	.cout(\Add0~21 ));
// synopsys translate_off
defparam \Add0~20 .lut_mask = 16'hC30C;
defparam \Add0~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N1
dffeas \counter[10] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~20_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[10]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[10] .is_wysiwyg = "true";
defparam \counter[10] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N2
cycloneive_lcell_comb \Add0~22 (
// Equation(s):
// \Add0~22_combout  = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND)))
// \Add0~23  = CARRY((!\Add0~21 ) # (!counter[11]))

	.dataa(gnd),
	.datab(counter[11]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~21 ),
	.combout(\Add0~22_combout ),
	.cout(\Add0~23 ));
// synopsys translate_off
defparam \Add0~22 .lut_mask = 16'h3C3F;
defparam \Add0~22 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N3
dffeas \counter[11] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~22_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[11]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[11] .is_wysiwyg = "true";
defparam \counter[11] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N4
cycloneive_lcell_comb \Add0~24 (
// Equation(s):
// \Add0~24_combout  = (counter[12] & (\Add0~23  $ (GND))) # (!counter[12] & (!\Add0~23  & VCC))
// \Add0~25  = CARRY((counter[12] & !\Add0~23 ))

	.dataa(gnd),
	.datab(counter[12]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~23 ),
	.combout(\Add0~24_combout ),
	.cout(\Add0~25 ));
// synopsys translate_off
defparam \Add0~24 .lut_mask = 16'hC30C;
defparam \Add0~24 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N5
dffeas \counter[12] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~24_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[12]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[12] .is_wysiwyg = "true";
defparam \counter[12] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N6
cycloneive_lcell_comb \Add0~26 (
// Equation(s):
// \Add0~26_combout  = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND)))
// \Add0~27  = CARRY((!\Add0~25 ) # (!counter[13]))

	.dataa(gnd),
	.datab(counter[13]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~25 ),
	.combout(\Add0~26_combout ),
	.cout(\Add0~27 ));
// synopsys translate_off
defparam \Add0~26 .lut_mask = 16'h3C3F;
defparam \Add0~26 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N7
dffeas \counter[13] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~26_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[13]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[13] .is_wysiwyg = "true";
defparam \counter[13] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N8
cycloneive_lcell_comb \Add0~28 (
// Equation(s):
// \Add0~28_combout  = (counter[14] & (\Add0~27  $ (GND))) # (!counter[14] & (!\Add0~27  & VCC))
// \Add0~29  = CARRY((counter[14] & !\Add0~27 ))

	.dataa(counter[14]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~27 ),
	.combout(\Add0~28_combout ),
	.cout(\Add0~29 ));
// synopsys translate_off
defparam \Add0~28 .lut_mask = 16'hA50A;
defparam \Add0~28 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N9
dffeas \counter[14] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~28_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[14]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[14] .is_wysiwyg = "true";
defparam \counter[14] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N10
cycloneive_lcell_comb \Add0~30 (
// Equation(s):
// \Add0~30_combout  = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND)))
// \Add0~31  = CARRY((!\Add0~29 ) # (!counter[15]))

	.dataa(gnd),
	.datab(counter[15]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~29 ),
	.combout(\Add0~30_combout ),
	.cout(\Add0~31 ));
// synopsys translate_off
defparam \Add0~30 .lut_mask = 16'h3C3F;
defparam \Add0~30 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N11
dffeas \counter[15] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~30_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[15]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[15] .is_wysiwyg = "true";
defparam \counter[15] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N12
cycloneive_lcell_comb \Add0~32 (
// Equation(s):
// \Add0~32_combout  = (counter[16] & (\Add0~31  $ (GND))) # (!counter[16] & (!\Add0~31  & VCC))
// \Add0~33  = CARRY((counter[16] & !\Add0~31 ))

	.dataa(gnd),
	.datab(counter[16]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~31 ),
	.combout(\Add0~32_combout ),
	.cout(\Add0~33 ));
// synopsys translate_off
defparam \Add0~32 .lut_mask = 16'hC30C;
defparam \Add0~32 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N13
dffeas \counter[16] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~32_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[16]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[16] .is_wysiwyg = "true";
defparam \counter[16] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N14
cycloneive_lcell_comb \Add0~34 (
// Equation(s):
// \Add0~34_combout  = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND)))
// \Add0~35  = CARRY((!\Add0~33 ) # (!counter[17]))

	.dataa(counter[17]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~33 ),
	.combout(\Add0~34_combout ),
	.cout(\Add0~35 ));
// synopsys translate_off
defparam \Add0~34 .lut_mask = 16'h5A5F;
defparam \Add0~34 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N15
dffeas \counter[17] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~34_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[17]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[17] .is_wysiwyg = "true";
defparam \counter[17] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N16
cycloneive_lcell_comb \Add0~36 (
// Equation(s):
// \Add0~36_combout  = (counter[18] & (\Add0~35  $ (GND))) # (!counter[18] & (!\Add0~35  & VCC))
// \Add0~37  = CARRY((counter[18] & !\Add0~35 ))

	.dataa(counter[18]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~35 ),
	.combout(\Add0~36_combout ),
	.cout(\Add0~37 ));
// synopsys translate_off
defparam \Add0~36 .lut_mask = 16'hA50A;
defparam \Add0~36 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N17
dffeas \counter[18] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~36_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[18]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[18] .is_wysiwyg = "true";
defparam \counter[18] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N18
cycloneive_lcell_comb \Add0~38 (
// Equation(s):
// \Add0~38_combout  = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND)))
// \Add0~39  = CARRY((!\Add0~37 ) # (!counter[19]))

	.dataa(counter[19]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~37 ),
	.combout(\Add0~38_combout ),
	.cout(\Add0~39 ));
// synopsys translate_off
defparam \Add0~38 .lut_mask = 16'h5A5F;
defparam \Add0~38 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y17_N19
dffeas \counter[19] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\Add0~38_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[19]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[19] .is_wysiwyg = "true";
defparam \counter[19] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N20
cycloneive_lcell_comb \Add0~40 (
// Equation(s):
// \Add0~40_combout  = \Add0~39  $ (!counter[20])

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(counter[20]),
	.cin(\Add0~39 ),
	.combout(\Add0~40_combout ),
	.cout());
// synopsys translate_off
defparam \Add0~40 .lut_mask = 16'hF00F;
defparam \Add0~40 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N28
cycloneive_lcell_comb \Equal0~5 (
// Equation(s):
// \Equal0~5_combout  = (!\Add0~32_combout  & (!\Add0~36_combout  & (!\Add0~34_combout  & !\Add0~38_combout )))

	.dataa(\Add0~32_combout ),
	.datab(\Add0~36_combout ),
	.datac(\Add0~34_combout ),
	.datad(\Add0~38_combout ),
	.cin(gnd),
	.combout(\Equal0~5_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~5 .lut_mask = 16'h0001;
defparam \Equal0~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N6
cycloneive_lcell_comb \Equal0~1 (
// Equation(s):
// \Equal0~1_combout  = (!\Add0~10_combout  & (!\Add0~8_combout  & (!\Add0~14_combout  & !\Add0~12_combout )))

	.dataa(\Add0~10_combout ),
	.datab(\Add0~8_combout ),
	.datac(\Add0~14_combout ),
	.datad(\Add0~12_combout ),
	.cin(gnd),
	.combout(\Equal0~1_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~1 .lut_mask = 16'h0001;
defparam \Equal0~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N4
cycloneive_lcell_comb \Equal0~0 (
// Equation(s):
// \Equal0~0_combout  = (!\Add0~4_combout  & (!\Add0~0_combout  & (!\Add0~6_combout  & !\Add0~2_combout )))

	.dataa(\Add0~4_combout ),
	.datab(\Add0~0_combout ),
	.datac(\Add0~6_combout ),
	.datad(\Add0~2_combout ),
	.cin(gnd),
	.combout(\Equal0~0_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~0 .lut_mask = 16'h0001;
defparam \Equal0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N30
cycloneive_lcell_comb \Equal0~2 (
// Equation(s):
// \Equal0~2_combout  = (!\Add0~22_combout  & (!\Add0~16_combout  & (!\Add0~20_combout  & !\Add0~18_combout )))

	.dataa(\Add0~22_combout ),
	.datab(\Add0~16_combout ),
	.datac(\Add0~20_combout ),
	.datad(\Add0~18_combout ),
	.cin(gnd),
	.combout(\Equal0~2_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~2 .lut_mask = 16'h0001;
defparam \Equal0~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N30
cycloneive_lcell_comb \Equal0~3 (
// Equation(s):
// \Equal0~3_combout  = (!\Add0~26_combout  & (!\Add0~24_combout  & (!\Add0~28_combout  & !\Add0~30_combout )))

	.dataa(\Add0~26_combout ),
	.datab(\Add0~24_combout ),
	.datac(\Add0~28_combout ),
	.datad(\Add0~30_combout ),
	.cin(gnd),
	.combout(\Equal0~3_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~3 .lut_mask = 16'h0001;
defparam \Equal0~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N28
cycloneive_lcell_comb \Equal0~4 (
// Equation(s):
// \Equal0~4_combout  = (\Equal0~1_combout  & (\Equal0~0_combout  & (\Equal0~2_combout  & \Equal0~3_combout )))

	.dataa(\Equal0~1_combout ),
	.datab(\Equal0~0_combout ),
	.datac(\Equal0~2_combout ),
	.datad(\Equal0~3_combout ),
	.cin(gnd),
	.combout(\Equal0~4_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~4 .lut_mask = 16'h8000;
defparam \Equal0~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N20
cycloneive_lcell_comb \address[0]~0 (
// Equation(s):
// \address[0]~0_combout  = address[0] $ (((!\Add0~40_combout  & (\Equal0~5_combout  & \Equal0~4_combout ))))

	.dataa(\Add0~40_combout ),
	.datab(\Equal0~5_combout ),
	.datac(address[0]),
	.datad(\Equal0~4_combout ),
	.cin(gnd),
	.combout(\address[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \address[0]~0 .lut_mask = 16'hB4F0;
defparam \address[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X32_Y17_N21
dffeas \address[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\address[0]~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(address[0]),
	.prn(vcc));
// synopsys translate_off
defparam \address[0] .is_wysiwyg = "true";
defparam \address[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N26
cycloneive_lcell_comb \Equal0~6 (
// Equation(s):
// \Equal0~6_combout  = (!\Add0~34_combout  & !\Add0~32_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\Add0~34_combout ),
	.datad(\Add0~32_combout ),
	.cin(gnd),
	.combout(\Equal0~6_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~6 .lut_mask = 16'h000F;
defparam \Equal0~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y17_N24
cycloneive_lcell_comb \Equal0~7 (
// Equation(s):
// \Equal0~7_combout  = (!\Add0~40_combout  & (!\Add0~36_combout  & (\Equal0~6_combout  & !\Add0~38_combout )))

	.dataa(\Add0~40_combout ),
	.datab(\Add0~36_combout ),
	.datac(\Equal0~6_combout ),
	.datad(\Add0~38_combout ),
	.cin(gnd),
	.combout(\Equal0~7_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~7 .lut_mask = 16'h0010;
defparam \Equal0~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N10
cycloneive_lcell_comb \address[1]~1 (
// Equation(s):
// \address[1]~1_combout  = address[1] $ (((address[0] & (\Equal0~4_combout  & \Equal0~7_combout ))))

	.dataa(address[0]),
	.datab(\Equal0~4_combout ),
	.datac(address[1]),
	.datad(\Equal0~7_combout ),
	.cin(gnd),
	.combout(\address[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \address[1]~1 .lut_mask = 16'h78F0;
defparam \address[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X32_Y17_N11
dffeas \address[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\address[1]~1_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(address[1]),
	.prn(vcc));
// synopsys translate_off
defparam \address[1] .is_wysiwyg = "true";
defparam \address[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N2
cycloneive_lcell_comb \address[1]~2 (
// Equation(s):
// \address[1]~2_combout  = (address[0] & (\Equal0~5_combout  & (!\Add0~40_combout  & \Equal0~4_combout )))

	.dataa(address[0]),
	.datab(\Equal0~5_combout ),
	.datac(\Add0~40_combout ),
	.datad(\Equal0~4_combout ),
	.cin(gnd),
	.combout(\address[1]~2_combout ),
	.cout());
// synopsys translate_off
defparam \address[1]~2 .lut_mask = 16'h0800;
defparam \address[1]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N16
cycloneive_lcell_comb \address[2]~3 (
// Equation(s):
// \address[2]~3_combout  = address[2] $ (((address[1] & \address[1]~2_combout )))

	.dataa(gnd),
	.datab(address[1]),
	.datac(address[2]),
	.datad(\address[1]~2_combout ),
	.cin(gnd),
	.combout(\address[2]~3_combout ),
	.cout());
// synopsys translate_off
defparam \address[2]~3 .lut_mask = 16'h3CF0;
defparam \address[2]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X32_Y17_N17
dffeas \address[2] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\address[2]~3_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(address[2]),
	.prn(vcc));
// synopsys translate_off
defparam \address[2] .is_wysiwyg = "true";
defparam \address[2] .power_up = "low";
// synopsys translate_on

// Location: M9K_X33_Y26_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(18'b000000000000000000),
	.portaaddr({address[2],address[1],address[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(18'b000000000000000000),
	.portbaddr(3'b000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081;
// synopsys translate_on

assign LED[0] = \LED[0]~output_o ;

assign LED[1] = \LED[1]~output_o ;

assign LED[2] = \LED[2]~output_o ;

assign LED[3] = \LED[3]~output_o ;

assign LED[4] = \LED[4]~output_o ;

assign LED[5] = \LED[5]~output_o ;

assign LED[6] = \LED[6]~output_o ;

assign LED[7] = \LED[7]~output_o ;

endmodule