VERSION: WM1.0
MODULE: altsyncram
PRIVATE: ADDRESSSTALL_A NUMERIC "0"
PRIVATE: AclrAddr NUMERIC "0"
PRIVATE: AclrByte NUMERIC "0"
PRIVATE: AclrOutput NUMERIC "0"
PRIVATE: BYTE_ENABLE NUMERIC "0"
PRIVATE: BYTE_SIZE NUMERIC "8"
PRIVATE: BlankMemory NUMERIC "0"
PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
PRIVATE: Clken NUMERIC "0"
PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
PRIVATE: INIT_TO_SIM_X NUMERIC "0"
PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
PRIVATE: JTAG_ENABLED NUMERIC "0"
PRIVATE: JTAG_ID STRING "NONE"
PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
PRIVATE: MIFfilename STRING "led_patterns.mif"
PRIVATE: NUMWORDS_A NUMERIC "8"
PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
PRIVATE: RegAddr NUMERIC "1"
PRIVATE: RegOutput NUMERIC "1"
PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
PRIVATE: SingleClock NUMERIC "1"
PRIVATE: UseDQRAM NUMERIC "0"
PRIVATE: WidthAddr NUMERIC "3"
PRIVATE: WidthData NUMERIC "8"
PRIVATE: rden NUMERIC "0"
LIBRARY: altera_mf altera_mf.altera_mf_components.all
CONSTANT: ADDRESS_ACLR_A STRING "NONE"
CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
CONSTANT: INIT_FILE STRING "led_patterns.mif"
CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
CONSTANT: LPM_TYPE STRING "altsyncram"
CONSTANT: NUMWORDS_A NUMERIC "8"
CONSTANT: OPERATION_MODE STRING "ROM"
CONSTANT: OUTDATA_ACLR_A STRING "NONE"
CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
CONSTANT: WIDTHAD_A NUMERIC "3"
CONSTANT: WIDTH_A NUMERIC "8"
CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
CONNECT: @address_a 0 0 3 0 address 0 0 3 0
CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
CONNECT: q 0 0 8 0 @q_a 0 0 8 0
GEN_FILE: TYPE_NORMAL rom0.v TRUE
GEN_FILE: TYPE_NORMAL rom0.inc FALSE
GEN_FILE: TYPE_NORMAL rom0.cmp FALSE
GEN_FILE: TYPE_NORMAL rom0.bsf FALSE
GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE
GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE
LIB_FILE: altera_mf

LICENSE_ID: "DEVICE_FAMILY_Cyclone III"	30229803K6032210322T
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E"	30229803A6032210322A
LICENSE_ID: "DEVICE_FAMILY_Cyclone V"	30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX"	30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone III LS"	30229803A6032210322B
LICENSE_ID: "FEATURE_STRATIXGX_DPA"	30229803M6032210322T
LICENSE_ID: "FEATURE_STRATIXGX_BASIC"	30229803A6032210322B


SUPPORTED_DEVICE_FAMILY: "Cyclone III"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
SUPPORTED_DEVICE_FAMILY: "Cyclone V"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
SUPPORTED_DEVICE_FAMILY: "Cyclone III LS"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"

WIZARD_TITLE: "ROM: 1-PORT"
QUARTUS_VERSION: "Version 13.1"
QUARTUS_SVERSION: "13.1.0 Build 162 10/23/2013 SJ Web Edition:10/23/2013"
QUARTUS_BUILD_DATE: "10/23/2013"
ALTERA_COPYRIGHT: "Copyright (C) 1991-2013 Altera Corporation"
RESC_INFO: ON


HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIX_WEB_LINK$http://www.altera.com/literature/hb/stx/ch_3_vol_2.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIX_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix (GX)"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_IV_WEB_LINK$http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_IV_WEB_MENU_LABEL$Cyclone IV Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONEII_WEB_LINK$http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONEII_WEB_MENU_LABEL$Cyclone II Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_WEB_LINK$http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_WEB_MENU_LABEL$Memory Implementations Using Cyclone Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXII_WEB_LINK$http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXII_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix II"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXIII_WEB_LINK$http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXIII_WEB_MENU_LABEL$TriMatrix Embedded Memory Blocks in Stratix III"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$APEX_WEB_LINK$http://www.altera.com/literature/an/an179.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$APEX_WEB_MENU_LABEL$Designing with ESBs"
HELP_MENU_ITEM: FALSE "IUG$ROM Megafunction User Guide$http://www.altera.com/literature/ug/ug_memrom.pdf"