// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "spectrum")
  (DATE "03/30/2022 13:47:24")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 32-bit")
  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[0\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2240:2240:2240) (2288:2288:2288))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[1\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2683:2683:2683) (2776:2776:2776))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[2\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2672:2672:2672) (2728:2728:2728))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[3\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1887:1887:1887) (1922:1922:1922))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[4\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2419:2419:2419) (2498:2498:2498))
        (IOPATH i o (2582:2582:2582) (2502:2502:2502))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[5\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1958:1958:1958) (2059:2059:2059))
        (IOPATH i o (4477:4477:4477) (4127:4127:4127))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[6\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2348:2348:2348) (2361:2361:2361))
        (IOPATH i o (2455:2455:2455) (2378:2378:2378))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[7\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1275:1275:1275) (1275:1275:1275))
        (IOPATH i o (4477:4477:4477) (4127:4127:4127))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE CLOCK_50\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (479:479:479) (732:732:732))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE CLOCK_50\~inputclkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (154:154:154) (138:138:138))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[0\]\~63)
    (DELAY
      (ABSOLUTE
        (IOPATH datac combout (353:353:353) (369:369:369))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (253:253:253) (345:345:345))
        (PORT datab (251:251:251) (336:336:336))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[2\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT datab (251:251:251) (336:336:336))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[3\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT datab (250:250:250) (335:335:335))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[4\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (251:251:251) (337:337:337))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[5\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (250:250:250) (335:335:335))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[6\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT dataa (252:252:252) (342:342:342))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[7\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (344:344:344))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[8\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (264:264:264) (350:350:350))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[9\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (344:344:344))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[10\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (264:264:264) (350:350:350))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[11\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (261:261:261) (343:343:343))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[12\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (248:248:248) (333:333:333))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[13\]\~45)
    (DELAY
      (ABSOLUTE
        (PORT dataa (403:403:403) (479:479:479))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[14\]\~47)
    (DELAY
      (ABSOLUTE
        (PORT dataa (251:251:251) (342:342:342))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[15\]\~49)
    (DELAY
      (ABSOLUTE
        (PORT dataa (403:403:403) (479:479:479))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[16\]\~51)
    (DELAY
      (ABSOLUTE
        (PORT dataa (253:253:253) (343:343:343))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[17\]\~53)
    (DELAY
      (ABSOLUTE
        (PORT dataa (253:253:253) (345:345:345))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[18\]\~55)
    (DELAY
      (ABSOLUTE
        (PORT datab (252:252:252) (338:338:338))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[19\]\~57)
    (DELAY
      (ABSOLUTE
        (PORT datab (252:252:252) (338:338:338))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1543:1543:1543))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[20\]\~59)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[20\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1896:1896:1896) (1918:1918:1918))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[21\]\~61)
    (DELAY
      (ABSOLUTE
        (PORT datad (239:239:239) (309:309:309))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1896:1896:1896) (1918:1918:1918))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (252:252:252) (343:343:343))
        (PORT datab (251:251:251) (335:335:335))
        (PORT datac (223:223:223) (302:302:302))
        (PORT datad (225:225:225) (298:298:298))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (350:350:350) (368:368:368))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (252:252:252) (341:341:341))
        (PORT datab (249:249:249) (334:334:334))
        (PORT datac (223:223:223) (301:301:301))
        (PORT datad (224:224:224) (296:296:296))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (350:350:350) (368:368:368))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (345:345:345))
        (PORT datab (252:252:252) (338:338:338))
        (PORT datac (381:381:381) (442:442:442))
        (PORT datad (226:226:226) (299:299:299))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (350:350:350) (368:368:368))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (447:447:447) (515:515:515))
        (PORT datab (406:406:406) (480:480:480))
        (PORT datac (566:566:566) (611:611:611))
        (PORT datad (576:576:576) (620:620:620))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (350:350:350) (368:368:368))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (346:346:346))
        (PORT datab (265:265:265) (348:348:348))
        (PORT datac (238:238:238) (315:315:315))
        (PORT datad (228:228:228) (300:300:300))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (350:350:350) (368:368:368))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (388:388:388) (416:416:416))
        (PORT datab (345:345:345) (380:380:380))
        (PORT datac (171:171:171) (204:204:204))
        (PORT datad (640:640:640) (652:652:652))
        (IOPATH dataa combout (300:300:300) (307:307:307))
        (IOPATH datab combout (300:300:300) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (888:888:888) (955:955:955))
        (PORT datab (926:926:926) (973:973:973))
        (PORT datac (615:615:615) (635:635:635))
        (PORT datad (173:173:173) (198:198:198))
        (IOPATH dataa combout (301:301:301) (299:299:299))
        (IOPATH datab combout (300:300:300) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[0\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT datad (330:330:330) (344:344:344))
        (IOPATH datac combout (353:353:353) (369:369:369))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[1\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (449:449:449) (522:522:522))
        (PORT datab (618:618:618) (683:683:683))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[2\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT datab (261:261:261) (343:343:343))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[3\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (344:344:344))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[4\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (351:351:351))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[5\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (345:345:345))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[6\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (353:353:353))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[7\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (353:353:353))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[8\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (403:403:403) (480:480:480))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[9\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (284:284:284) (367:367:367))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[10\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[11\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[12\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (352:352:352))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[13\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datad (258:258:258) (327:327:327))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1897:1897:1897) (1919:1919:1919))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (816:816:816) (814:814:814))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1043:1043:1043) (1097:1097:1097))
        (PORT clk (1858:1858:1858) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1047:1047:1047) (1146:1146:1146))
        (PORT d[1] (1492:1492:1492) (1562:1562:1562))
        (PORT d[2] (954:954:954) (1036:1036:1036))
        (PORT d[3] (1018:1018:1018) (1075:1075:1075))
        (PORT d[4] (1018:1018:1018) (1075:1075:1075))
        (PORT d[5] (783:783:783) (838:838:838))
        (PORT d[6] (783:783:783) (838:838:838))
        (PORT d[7] (783:783:783) (838:838:838))
        (PORT d[8] (783:783:783) (838:838:838))
        (PORT d[9] (783:783:783) (838:838:838))
        (PORT d[10] (783:783:783) (838:838:838))
        (PORT d[11] (783:783:783) (838:838:838))
        (PORT d[12] (783:783:783) (838:838:838))
        (PORT clk (1855:1855:1855) (1880:1880:1880))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1884:1884:1884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1809:1809:1809))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1048:1048:1048) (1102:1102:1102))
        (PORT clk (1823:1823:1823) (1815:1815:1815))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1028:1028:1028) (1127:1127:1127))
        (PORT d[1] (1493:1493:1493) (1562:1562:1562))
        (PORT d[2] (979:979:979) (1058:1058:1058))
        (PORT d[3] (1250:1250:1250) (1312:1312:1312))
        (PORT d[4] (967:967:967) (1025:1025:1025))
        (PORT d[5] (1558:1558:1558) (1643:1643:1643))
        (PORT d[6] (1237:1237:1237) (1323:1323:1323))
        (PORT d[7] (1284:1284:1284) (1363:1363:1363))
        (PORT d[8] (1214:1214:1214) (1273:1273:1273))
        (PORT d[9] (1235:1235:1235) (1302:1302:1302))
        (PORT d[10] (1250:1250:1250) (1318:1318:1318))
        (PORT d[11] (1232:1232:1232) (1314:1314:1314))
        (PORT d[12] (1287:1287:1287) (1358:1358:1358))
        (PORT clk (1819:1819:1819) (1811:1811:1811))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1823:1823:1823) (1815:1815:1815))
        (PORT d[0] (903:903:903) (890:890:890))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1824:1824:1824) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1824:1824:1824) (1816:1816:1816))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1824:1824:1824) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1824:1824:1824) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1006:1006:1006) (1061:1061:1061))
        (PORT clk (1856:1856:1856) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1030:1030:1030) (1132:1132:1132))
        (PORT d[1] (1194:1194:1194) (1270:1270:1270))
        (PORT d[2] (957:957:957) (1039:1039:1039))
        (PORT d[3] (1025:1025:1025) (1086:1086:1086))
        (PORT d[4] (1025:1025:1025) (1086:1086:1086))
        (PORT d[5] (813:813:813) (881:881:881))
        (PORT d[6] (813:813:813) (881:881:881))
        (PORT d[7] (813:813:813) (881:881:881))
        (PORT d[8] (813:813:813) (881:881:881))
        (PORT d[9] (813:813:813) (881:881:881))
        (PORT d[10] (813:813:813) (881:881:881))
        (PORT d[11] (813:813:813) (881:881:881))
        (PORT d[12] (813:813:813) (881:881:881))
        (PORT clk (1853:1853:1853) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1856:1856:1856) (1883:1883:1883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1808:1808:1808))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1011:1011:1011) (1066:1066:1066))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1054:1054:1054) (1156:1156:1156))
        (PORT d[1] (960:960:960) (1039:1039:1039))
        (PORT d[2] (1276:1276:1276) (1350:1350:1350))
        (PORT d[3] (1249:1249:1249) (1279:1279:1279))
        (PORT d[4] (941:941:941) (1014:1014:1014))
        (PORT d[5] (1553:1553:1553) (1633:1633:1633))
        (PORT d[6] (1275:1275:1275) (1334:1334:1334))
        (PORT d[7] (1286:1286:1286) (1364:1364:1364))
        (PORT d[8] (1442:1442:1442) (1487:1487:1487))
        (PORT d[9] (1239:1239:1239) (1309:1309:1309))
        (PORT d[10] (1259:1259:1259) (1333:1333:1333))
        (PORT d[11] (1243:1243:1243) (1305:1305:1305))
        (PORT d[12] (1271:1271:1271) (1318:1318:1318))
        (PORT clk (1817:1817:1817) (1810:1810:1810))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (PORT d[0] (908:908:908) (894:894:894))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1352:1352:1352) (1400:1400:1400))
        (PORT clk (1859:1859:1859) (1886:1886:1886))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1071:1071:1071) (1146:1146:1146))
        (PORT d[1] (935:935:935) (1004:1004:1004))
        (PORT d[2] (1531:1531:1531) (1621:1621:1621))
        (PORT d[3] (1349:1349:1349) (1401:1401:1401))
        (PORT d[4] (1349:1349:1349) (1401:1401:1401))
        (PORT d[5] (773:773:773) (814:814:814))
        (PORT d[6] (773:773:773) (814:814:814))
        (PORT d[7] (773:773:773) (814:814:814))
        (PORT d[8] (773:773:773) (814:814:814))
        (PORT d[9] (773:773:773) (814:814:814))
        (PORT d[10] (773:773:773) (814:814:814))
        (PORT d[11] (773:773:773) (814:814:814))
        (PORT d[12] (773:773:773) (814:814:814))
        (PORT clk (1856:1856:1856) (1882:1882:1882))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1886:1886:1886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1811:1811:1811))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1357:1357:1357) (1405:1405:1405))
        (PORT clk (1824:1824:1824) (1817:1817:1817))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1049:1049:1049) (1122:1122:1122))
        (PORT d[1] (1503:1503:1503) (1591:1591:1591))
        (PORT d[2] (917:917:917) (979:979:979))
        (PORT d[3] (1464:1464:1464) (1521:1521:1521))
        (PORT d[4] (935:935:935) (996:996:996))
        (PORT d[5] (1058:1058:1058) (1128:1128:1128))
        (PORT d[6] (1250:1250:1250) (1319:1319:1319))
        (PORT d[7] (1047:1047:1047) (1105:1105:1105))
        (PORT d[8] (1486:1486:1486) (1542:1542:1542))
        (PORT d[9] (1254:1254:1254) (1312:1312:1312))
        (PORT d[10] (1242:1242:1242) (1297:1297:1297))
        (PORT d[11] (1250:1250:1250) (1319:1319:1319))
        (PORT d[12] (1251:1251:1251) (1299:1299:1299))
        (PORT clk (1820:1820:1820) (1813:1813:1813))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1824:1824:1824) (1817:1817:1817))
        (PORT d[0] (880:880:880) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1825:1825:1825) (1818:1818:1818))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1825:1825:1825) (1818:1818:1818))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1825:1825:1825) (1818:1818:1818))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1825:1825:1825) (1818:1818:1818))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1362:1362:1362) (1429:1429:1429))
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (762:762:762) (824:824:824))
        (PORT d[1] (644:644:644) (706:706:706))
        (PORT d[2] (1543:1543:1543) (1614:1614:1614))
        (PORT d[3] (664:664:664) (693:693:693))
        (PORT d[4] (664:664:664) (693:693:693))
        (PORT d[5] (484:484:484) (522:522:522))
        (PORT d[6] (484:484:484) (522:522:522))
        (PORT d[7] (484:484:484) (522:522:522))
        (PORT d[8] (484:484:484) (522:522:522))
        (PORT d[9] (484:484:484) (522:522:522))
        (PORT d[10] (484:484:484) (522:522:522))
        (PORT d[11] (484:484:484) (522:522:522))
        (PORT d[12] (484:484:484) (522:522:522))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1815:1815:1815) (1812:1812:1812))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1367:1367:1367) (1434:1434:1434))
        (PORT clk (1825:1825:1825) (1818:1818:1818))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (735:735:735) (812:812:812))
        (PORT d[1] (1534:1534:1534) (1599:1599:1599))
        (PORT d[2] (1545:1545:1545) (1615:1615:1615))
        (PORT d[3] (659:659:659) (709:709:709))
        (PORT d[4] (664:664:664) (725:725:725))
        (PORT d[5] (722:722:722) (794:794:794))
        (PORT d[6] (766:766:766) (839:839:839))
        (PORT d[7] (749:749:749) (827:827:827))
        (PORT d[8] (1517:1517:1517) (1590:1590:1590))
        (PORT d[9] (761:761:761) (822:822:822))
        (PORT d[10] (979:979:979) (1037:1037:1037))
        (PORT d[11] (734:734:734) (803:803:803))
        (PORT d[12] (940:940:940) (991:991:991))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1825:1825:1825) (1818:1818:1818))
        (PORT d[0] (628:628:628) (619:619:619))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1826:1826:1826) (1819:1819:1819))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1826:1826:1826) (1819:1819:1819))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1826:1826:1826) (1819:1819:1819))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1826:1826:1826) (1819:1819:1819))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1580:1580:1580) (1693:1693:1693))
        (PORT d[1] (1272:1272:1272) (1354:1354:1354))
        (PORT d[2] (1245:1245:1245) (1308:1308:1308))
        (PORT d[3] (1263:1263:1263) (1339:1339:1339))
        (PORT d[4] (1283:1283:1283) (1370:1370:1370))
        (PORT d[5] (1569:1569:1569) (1701:1701:1701))
        (PORT d[6] (1243:1243:1243) (1329:1329:1329))
        (PORT d[7] (1231:1231:1231) (1310:1310:1310))
        (PORT d[8] (1267:1267:1267) (1363:1363:1363))
        (PORT d[9] (1273:1273:1273) (1361:1361:1361))
        (PORT d[10] (1275:1275:1275) (1366:1366:1366))
        (PORT d[11] (1259:1259:1259) (1344:1344:1344))
        (PORT d[12] (1532:1532:1532) (1614:1614:1614))
        (PORT clk (1847:1847:1847) (1874:1874:1874))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1847:1847:1847) (1874:1874:1874))
        (PORT d[0] (1172:1172:1172) (1188:1188:1188))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1875:1875:1875))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1810:1810:1810) (1837:1837:1837))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (995:995:995) (1000:1000:1000))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (996:996:996) (1001:1001:1001))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (996:996:996) (1001:1001:1001))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (996:996:996) (1001:1001:1001))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1320:1320:1320) (1440:1440:1440))
        (PORT d[1] (1259:1259:1259) (1353:1353:1353))
        (PORT d[2] (1264:1264:1264) (1323:1323:1323))
        (PORT d[3] (1324:1324:1324) (1419:1419:1419))
        (PORT d[4] (1316:1316:1316) (1418:1418:1418))
        (PORT d[5] (1564:1564:1564) (1691:1691:1691))
        (PORT d[6] (1229:1229:1229) (1326:1326:1326))
        (PORT d[7] (1239:1239:1239) (1332:1332:1332))
        (PORT d[8] (1280:1280:1280) (1393:1393:1393))
        (PORT d[9] (1254:1254:1254) (1351:1351:1351))
        (PORT d[10] (1258:1258:1258) (1357:1357:1357))
        (PORT d[11] (1267:1267:1267) (1367:1367:1367))
        (PORT d[12] (1266:1266:1266) (1351:1351:1351))
        (PORT clk (1846:1846:1846) (1872:1872:1872))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1846:1846:1846) (1872:1872:1872))
        (PORT d[0] (1215:1215:1215) (1202:1202:1202))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1847:1847:1847) (1873:1873:1873))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1809:1809:1809) (1835:1835:1835))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (994:994:994) (998:998:998))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (995:995:995) (999:999:999))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (995:995:995) (999:999:999))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (995:995:995) (999:999:999))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datac (643:643:643) (706:706:706))
        (IOPATH datac combout (243:243:243) (242:242:242))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1545:1545:1545))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (219:219:219) (289:289:289))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1531:1531:1531) (1545:1545:1545))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (628:628:628) (637:637:637))
        (PORT datac (922:922:922) (922:922:922))
        (PORT datad (973:973:973) (1040:1040:1040))
        (IOPATH datab combout (306:306:306) (311:311:311))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1588:1588:1588) (1696:1696:1696))
        (PORT d[1] (980:980:980) (1067:1067:1067))
        (PORT d[2] (995:995:995) (1068:1068:1068))
        (PORT d[3] (1044:1044:1044) (1123:1123:1123))
        (PORT d[4] (975:975:975) (1061:1061:1061))
        (PORT d[5] (1570:1570:1570) (1702:1702:1702))
        (PORT d[6] (974:974:974) (1057:1057:1057))
        (PORT d[7] (950:950:950) (1029:1029:1029))
        (PORT d[8] (1007:1007:1007) (1107:1107:1107))
        (PORT d[9] (1511:1511:1511) (1583:1583:1583))
        (PORT d[10] (1476:1476:1476) (1552:1552:1552))
        (PORT d[11] (949:949:949) (1029:1029:1029))
        (PORT d[12] (993:993:993) (1056:1056:1056))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1875:1875:1875))
        (PORT d[0] (897:897:897) (921:921:921))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1849:1849:1849) (1876:1876:1876))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1838:1838:1838))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (996:996:996) (1001:1001:1001))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1251:1251:1251) (1346:1346:1346))
        (PORT d[1] (1263:1263:1263) (1359:1359:1359))
        (PORT d[2] (1230:1230:1230) (1312:1312:1312))
        (PORT d[3] (1305:1305:1305) (1378:1378:1378))
        (PORT d[4] (1268:1268:1268) (1374:1374:1374))
        (PORT d[5] (1558:1558:1558) (1661:1661:1661))
        (PORT d[6] (1255:1255:1255) (1359:1359:1359))
        (PORT d[7] (1243:1243:1243) (1338:1338:1338))
        (PORT d[8] (1284:1284:1284) (1400:1400:1400))
        (PORT d[9] (1257:1257:1257) (1358:1358:1358))
        (PORT d[10] (1261:1261:1261) (1362:1362:1362))
        (PORT d[11] (1244:1244:1244) (1341:1341:1341))
        (PORT d[12] (1513:1513:1513) (1597:1597:1597))
        (PORT clk (1844:1844:1844) (1871:1871:1871))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1844:1844:1844) (1871:1871:1871))
        (PORT d[0] (1181:1181:1181) (1146:1146:1146))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1845:1845:1845) (1872:1872:1872))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1807:1807:1807) (1834:1834:1834))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (992:992:992) (997:997:997))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (993:993:993) (998:998:998))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (993:993:993) (998:998:998))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (993:993:993) (998:998:998))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (627:627:627) (648:648:648))
        (PORT datab (722:722:722) (791:791:791))
        (PORT datac (902:902:902) (941:941:941))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datac combout (243:243:243) (242:242:242))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1869:1869:1869) (2011:2011:2011))
        (PORT d[1] (1219:1219:1219) (1293:1293:1293))
        (PORT d[2] (1262:1262:1262) (1328:1328:1328))
        (PORT d[3] (1315:1315:1315) (1385:1385:1385))
        (PORT d[4] (1268:1268:1268) (1345:1345:1345))
        (PORT d[5] (1878:1878:1878) (2013:2013:2013))
        (PORT d[6] (1241:1241:1241) (1311:1311:1311))
        (PORT d[7] (1353:1353:1353) (1455:1455:1455))
        (PORT d[8] (1215:1215:1215) (1306:1306:1306))
        (PORT d[9] (1254:1254:1254) (1335:1335:1335))
        (PORT d[10] (1270:1270:1270) (1354:1354:1354))
        (PORT d[11] (1212:1212:1212) (1279:1279:1279))
        (PORT d[12] (1262:1262:1262) (1346:1346:1346))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1875:1875:1875))
        (PORT d[0] (1161:1161:1161) (1144:1144:1144))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1849:1849:1849) (1876:1876:1876))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1838:1838:1838))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (996:996:996) (1001:1001:1001))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (997:997:997) (1002:1002:1002))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (767:767:767) (837:837:837))
        (PORT d[1] (644:644:644) (707:707:707))
        (PORT d[2] (1522:1522:1522) (1591:1591:1591))
        (PORT d[3] (1232:1232:1232) (1276:1276:1276))
        (PORT d[4] (948:948:948) (1009:1009:1009))
        (PORT d[5] (1053:1053:1053) (1132:1132:1132))
        (PORT d[6] (1198:1198:1198) (1268:1268:1268))
        (PORT d[7] (1251:1251:1251) (1321:1321:1321))
        (PORT d[8] (1492:1492:1492) (1563:1563:1563))
        (PORT d[9] (1256:1256:1256) (1307:1307:1307))
        (PORT d[10] (1239:1239:1239) (1292:1292:1292))
        (PORT d[11] (1213:1213:1213) (1275:1275:1275))
        (PORT d[12] (1242:1242:1242) (1308:1308:1308))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1883:1883:1883))
        (PORT d[0] (890:890:890) (887:887:887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1846:1846:1846))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1005:1005:1005) (1009:1009:1009))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1006:1006:1006) (1010:1010:1010))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1006:1006:1006) (1010:1010:1010))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1006:1006:1006) (1010:1010:1010))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (938:938:938) (1009:1009:1009))
        (PORT datac (597:597:597) (600:600:600))
        (PORT datad (1037:1037:1037) (1036:1036:1036))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1536:1536:1536) (1641:1641:1641))
        (PORT d[1] (1285:1285:1285) (1385:1385:1385))
        (PORT d[2] (1257:1257:1257) (1341:1341:1341))
        (PORT d[3] (1362:1362:1362) (1438:1438:1438))
        (PORT d[4] (1567:1567:1567) (1669:1669:1669))
        (PORT d[5] (1299:1299:1299) (1410:1410:1410))
        (PORT d[6] (1283:1283:1283) (1391:1391:1391))
        (PORT d[7] (1243:1243:1243) (1339:1339:1339))
        (PORT d[8] (1257:1257:1257) (1369:1369:1369))
        (PORT d[9] (1285:1285:1285) (1390:1390:1390))
        (PORT d[10] (1289:1289:1289) (1395:1395:1395))
        (PORT d[11] (1244:1244:1244) (1342:1342:1342))
        (PORT d[12] (1238:1238:1238) (1316:1316:1316))
        (PORT clk (1842:1842:1842) (1869:1869:1869))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1842:1842:1842) (1869:1869:1869))
        (PORT d[0] (1140:1140:1140) (1166:1166:1166))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1843:1843:1843) (1870:1870:1870))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1805:1805:1805) (1832:1832:1832))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (990:990:990) (995:995:995))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (991:991:991) (996:996:996))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (991:991:991) (996:996:996))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (991:991:991) (996:996:996))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1019:1019:1019) (1118:1118:1118))
        (PORT d[1] (928:928:928) (1013:1013:1013))
        (PORT d[2] (926:926:926) (1007:1007:1007))
        (PORT d[3] (1249:1249:1249) (1279:1279:1279))
        (PORT d[4] (1509:1509:1509) (1612:1612:1612))
        (PORT d[5] (1306:1306:1306) (1397:1397:1397))
        (PORT d[6] (1247:1247:1247) (1313:1313:1313))
        (PORT d[7] (1321:1321:1321) (1414:1414:1414))
        (PORT d[8] (1471:1471:1471) (1521:1521:1521))
        (PORT d[9] (1265:1265:1265) (1341:1341:1341))
        (PORT d[10] (1259:1259:1259) (1333:1333:1333))
        (PORT d[11] (1270:1270:1270) (1337:1337:1337))
        (PORT d[12] (1271:1271:1271) (1319:1319:1319))
        (PORT clk (1851:1851:1851) (1877:1877:1877))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1877:1877:1877))
        (PORT d[0] (909:909:909) (894:894:894))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1878:1878:1878))
        (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1840:1840:1840))
        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (51:51:51))
      (HOLD d (posedge clk) (159:159:159))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (999:999:999) (1003:1003:1003))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1000:1000:1000) (1004:1004:1004))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1000:1000:1000) (1004:1004:1004))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1000:1000:1000) (1004:1004:1004))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (992:992:992) (1066:1066:1066))
        (PORT datac (604:604:604) (608:608:608))
        (PORT datad (1039:1039:1039) (1055:1055:1055))
        (IOPATH datab combout (342:342:342) (342:342:342))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
)