// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "spectrum")
  (DATE "03/30/2022 13:47:24")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 32-bit")
  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[0\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2068:2068:2068) (2050:2050:2050))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[1\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2478:2478:2478) (2480:2480:2480))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[2\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2467:2467:2467) (2430:2430:2430))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[3\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1746:1746:1746) (1704:1704:1704))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[4\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2240:2240:2240) (2238:2238:2238))
        (IOPATH i o (2277:2277:2277) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[5\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1807:1807:1807) (1820:1820:1820))
        (IOPATH i o (3961:3961:3961) (3539:3539:3539))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[6\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2185:2185:2185) (2116:2116:2116))
        (IOPATH i o (2194:2194:2194) (2119:2119:2119))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE LED\[7\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1193:1193:1193) (1143:1143:1143))
        (IOPATH i o (3961:3961:3961) (3539:3539:3539))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE CLOCK_50\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (459:459:459) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE CLOCK_50\~inputclkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (133:133:133) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[0\]\~63)
    (DELAY
      (ABSOLUTE
        (IOPATH datac combout (312:312:312) (325:325:325))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (309:309:309))
        (PORT datab (227:227:227) (300:300:300))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[2\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT datab (228:228:228) (299:299:299))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[3\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT datab (228:228:228) (300:300:300))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[4\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (227:227:227) (301:301:301))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[5\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (228:228:228) (300:300:300))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[6\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[7\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (239:239:239) (308:308:308))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[8\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (240:240:240) (312:312:312))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[9\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (238:238:238) (307:307:307))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[10\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (240:240:240) (312:312:312))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1352:1352:1352) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[11\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (238:238:238) (306:306:306))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[12\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (226:226:226) (297:297:297))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[13\]\~45)
    (DELAY
      (ABSOLUTE
        (PORT dataa (379:379:379) (426:426:426))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[14\]\~47)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[15\]\~49)
    (DELAY
      (ABSOLUTE
        (PORT dataa (379:379:379) (426:426:426))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[16\]\~51)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[17\]\~53)
    (DELAY
      (ABSOLUTE
        (PORT dataa (231:231:231) (309:309:309))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[18\]\~55)
    (DELAY
      (ABSOLUTE
        (PORT datab (229:229:229) (301:301:301))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[19\]\~57)
    (DELAY
      (ABSOLUTE
        (PORT datab (229:229:229) (302:302:302))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[20\]\~59)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[20\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1680:1680:1680) (1699:1699:1699))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[21\]\~61)
    (DELAY
      (ABSOLUTE
        (PORT datad (218:218:218) (276:276:276))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1680:1680:1680) (1699:1699:1699))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (307:307:307))
        (PORT datab (227:227:227) (299:299:299))
        (PORT datac (201:201:201) (271:271:271))
        (PORT datad (205:205:205) (267:267:267))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (305:305:305))
        (PORT datab (226:226:226) (298:298:298))
        (PORT datac (200:200:200) (270:270:270))
        (PORT datad (203:203:203) (265:265:265))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (231:231:231) (309:309:309))
        (PORT datab (228:228:228) (302:302:302))
        (PORT datac (353:353:353) (392:392:392))
        (PORT datad (205:205:205) (267:267:267))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (419:419:419) (453:453:453))
        (PORT datab (379:379:379) (422:422:422))
        (PORT datac (533:533:533) (544:544:544))
        (PORT datad (537:537:537) (553:553:553))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (232:232:232) (310:310:310))
        (PORT datab (241:241:241) (311:311:311))
        (PORT datac (216:216:216) (283:283:283))
        (PORT datad (206:206:206) (268:268:268))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (365:365:365) (368:368:368))
        (PORT datab (323:323:323) (337:337:337))
        (PORT datac (156:156:156) (186:186:186))
        (PORT datad (586:586:586) (583:583:583))
        (IOPATH dataa combout (265:265:265) (269:269:269))
        (IOPATH datab combout (265:265:265) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (826:826:826) (842:842:842))
        (PORT datab (861:861:861) (867:867:867))
        (PORT datac (571:571:571) (562:562:562))
        (PORT datad (158:158:158) (179:179:179))
        (IOPATH dataa combout (267:267:267) (269:269:269))
        (IOPATH datab combout (267:267:267) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[0\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT datad (308:308:308) (313:313:313))
        (IOPATH datac combout (312:312:312) (325:325:325))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[1\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (413:413:413) (463:463:463))
        (PORT datab (575:575:575) (602:602:602))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[2\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT datab (238:238:238) (307:307:307))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[3\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (239:239:239) (307:307:307))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[4\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (313:313:313))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[5\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (308:308:308))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[6\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (315:315:315))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[7\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (315:315:315))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[8\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (373:373:373) (423:423:423))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[9\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (259:259:259) (329:329:329))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[10\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[11\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[12\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (314:314:314))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[13\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datad (235:235:235) (292:292:292))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1700:1700:1700))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (740:740:740) (743:743:743))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (965:965:965) (986:986:986))
        (PORT clk (1644:1644:1644) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (967:967:967) (1018:1018:1018))
        (PORT d[1] (1372:1372:1372) (1392:1392:1392))
        (PORT d[2] (884:884:884) (921:921:921))
        (PORT d[3] (941:941:941) (967:967:967))
        (PORT d[4] (941:941:941) (967:967:967))
        (PORT d[5] (720:720:720) (753:753:753))
        (PORT d[6] (720:720:720) (753:753:753))
        (PORT d[7] (720:720:720) (753:753:753))
        (PORT d[8] (720:720:720) (753:753:753))
        (PORT d[9] (720:720:720) (753:753:753))
        (PORT d[10] (720:720:720) (753:753:753))
        (PORT d[11] (720:720:720) (753:753:753))
        (PORT d[12] (720:720:720) (753:753:753))
        (PORT clk (1641:1641:1641) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1670:1670:1670))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (969:969:969) (990:990:990))
        (PORT clk (1611:1611:1611) (1607:1607:1607))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (949:949:949) (1000:1000:1000))
        (PORT d[1] (1373:1373:1373) (1393:1393:1393))
        (PORT d[2] (907:907:907) (939:939:939))
        (PORT d[3] (1154:1154:1154) (1170:1170:1170))
        (PORT d[4] (893:893:893) (932:932:932))
        (PORT d[5] (1441:1441:1441) (1466:1466:1466))
        (PORT d[6] (1147:1147:1147) (1174:1174:1174))
        (PORT d[7] (1183:1183:1183) (1221:1221:1221))
        (PORT d[8] (1128:1128:1128) (1149:1149:1149))
        (PORT d[9] (1143:1143:1143) (1180:1180:1180))
        (PORT d[10] (1158:1158:1158) (1183:1183:1183))
        (PORT d[11] (1143:1143:1143) (1170:1170:1170))
        (PORT d[12] (1190:1190:1190) (1223:1223:1223))
        (PORT clk (1608:1608:1608) (1604:1604:1604))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (PORT d[0] (817:817:817) (818:818:818))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1608:1608:1608))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (936:936:936) (951:951:951))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (952:952:952) (1005:1005:1005))
        (PORT d[1] (1106:1106:1106) (1134:1134:1134))
        (PORT d[2] (886:886:886) (926:926:926))
        (PORT d[3] (953:953:953) (973:973:973))
        (PORT d[4] (953:953:953) (973:973:973))
        (PORT d[5] (749:749:749) (791:791:791))
        (PORT d[6] (749:749:749) (791:791:791))
        (PORT d[7] (749:749:749) (791:791:791))
        (PORT d[8] (749:749:749) (791:791:791))
        (PORT d[9] (749:749:749) (791:791:791))
        (PORT d[10] (749:749:749) (791:791:791))
        (PORT d[11] (749:749:749) (791:791:791))
        (PORT d[12] (749:749:749) (791:791:791))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (940:940:940) (955:955:955))
        (PORT clk (1610:1610:1610) (1607:1607:1607))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (974:974:974) (1028:1028:1028))
        (PORT d[1] (886:886:886) (928:928:928))
        (PORT d[2] (1182:1182:1182) (1202:1202:1202))
        (PORT d[3] (1153:1153:1153) (1160:1160:1160))
        (PORT d[4] (870:870:870) (911:911:911))
        (PORT d[5] (1436:1436:1436) (1446:1446:1446))
        (PORT d[6] (1183:1183:1183) (1208:1208:1208))
        (PORT d[7] (1185:1185:1185) (1223:1223:1223))
        (PORT d[8] (1334:1334:1334) (1340:1340:1340))
        (PORT d[9] (1147:1147:1147) (1186:1186:1186))
        (PORT d[10] (1167:1167:1167) (1196:1196:1196))
        (PORT d[11] (1154:1154:1154) (1177:1177:1177))
        (PORT d[12] (1176:1176:1176) (1203:1203:1203))
        (PORT clk (1607:1607:1607) (1604:1604:1604))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1607:1607:1607))
        (PORT d[0] (823:823:823) (821:821:821))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1246:1246:1246) (1257:1257:1257))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (985:985:985) (1031:1031:1031))
        (PORT d[1] (862:862:862) (901:901:901))
        (PORT d[2] (1411:1411:1411) (1436:1436:1436))
        (PORT d[3] (1243:1243:1243) (1258:1258:1258))
        (PORT d[4] (1243:1243:1243) (1258:1258:1258))
        (PORT d[5] (710:710:710) (733:733:733))
        (PORT d[6] (710:710:710) (733:733:733))
        (PORT d[7] (710:710:710) (733:733:733))
        (PORT d[8] (710:710:710) (733:733:733))
        (PORT d[9] (710:710:710) (733:733:733))
        (PORT d[10] (710:710:710) (733:733:733))
        (PORT d[11] (710:710:710) (733:733:733))
        (PORT d[12] (710:710:710) (733:733:733))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1602:1602:1602))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1250:1250:1250) (1261:1261:1261))
        (PORT clk (1612:1612:1612) (1609:1609:1609))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (965:965:965) (1011:1011:1011))
        (PORT d[1] (1384:1384:1384) (1415:1415:1415))
        (PORT d[2] (851:851:851) (879:879:879))
        (PORT d[3] (1359:1359:1359) (1362:1362:1362))
        (PORT d[4] (865:865:865) (893:893:893))
        (PORT d[5] (979:979:979) (1019:1019:1019))
        (PORT d[6] (1158:1158:1158) (1174:1174:1174))
        (PORT d[7] (970:970:970) (994:994:994))
        (PORT d[8] (1375:1375:1375) (1392:1392:1392))
        (PORT d[9] (1161:1161:1161) (1191:1191:1191))
        (PORT d[10] (1150:1150:1150) (1166:1166:1166))
        (PORT d[11] (1157:1157:1157) (1177:1177:1177))
        (PORT d[12] (1155:1155:1155) (1174:1174:1174))
        (PORT clk (1609:1609:1609) (1606:1606:1606))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1609:1609:1609))
        (PORT d[0] (800:800:800) (809:809:809))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1610:1610:1610))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1610:1610:1610))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1610:1610:1610))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1610:1610:1610))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1257:1257:1257) (1262:1262:1262))
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (704:704:704) (733:733:733))
        (PORT d[1] (597:597:597) (634:634:634))
        (PORT d[2] (1424:1424:1424) (1449:1449:1449))
        (PORT d[3] (623:623:623) (627:627:627))
        (PORT d[4] (623:623:623) (627:627:627))
        (PORT d[5] (447:447:447) (472:472:472))
        (PORT d[6] (447:447:447) (472:472:472))
        (PORT d[7] (447:447:447) (472:472:472))
        (PORT d[8] (447:447:447) (472:472:472))
        (PORT d[9] (447:447:447) (472:472:472))
        (PORT d[10] (447:447:447) (472:472:472))
        (PORT d[11] (447:447:447) (472:472:472))
        (PORT d[12] (447:447:447) (472:472:472))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1605:1605:1605) (1603:1603:1603))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1261:1261:1261) (1266:1266:1266))
        (PORT clk (1613:1613:1613) (1610:1610:1610))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (679:679:679) (718:718:718))
        (PORT d[1] (1414:1414:1414) (1440:1440:1440))
        (PORT d[2] (1426:1426:1426) (1449:1449:1449))
        (PORT d[3] (613:613:613) (642:642:642))
        (PORT d[4] (616:616:616) (651:651:651))
        (PORT d[5] (671:671:671) (707:707:707))
        (PORT d[6] (713:713:713) (745:745:745))
        (PORT d[7] (696:696:696) (738:738:738))
        (PORT d[8] (1404:1404:1404) (1432:1432:1432))
        (PORT d[9] (709:709:709) (732:732:732))
        (PORT d[10] (910:910:910) (932:932:932))
        (PORT d[11] (684:684:684) (714:714:714))
        (PORT d[12] (872:872:872) (895:895:895))
        (PORT clk (1610:1610:1610) (1607:1607:1607))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1610:1610:1610))
        (PORT d[0] (557:557:557) (569:569:569))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1611:1611:1611))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1611:1611:1611))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1611:1611:1611))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1611:1611:1611))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1463:1463:1463) (1520:1520:1520))
        (PORT d[1] (1184:1184:1184) (1215:1215:1215))
        (PORT d[2] (1162:1162:1162) (1194:1194:1194))
        (PORT d[3] (1176:1176:1176) (1202:1202:1202))
        (PORT d[4] (1194:1194:1194) (1236:1236:1236))
        (PORT d[5] (1453:1453:1453) (1530:1530:1530))
        (PORT d[6] (1157:1157:1157) (1196:1196:1196))
        (PORT d[7] (1142:1142:1142) (1184:1184:1184))
        (PORT d[8] (1171:1171:1171) (1208:1208:1208))
        (PORT d[9] (1184:1184:1184) (1214:1214:1214))
        (PORT d[10] (1181:1181:1181) (1207:1207:1207))
        (PORT d[11] (1171:1171:1171) (1210:1210:1210))
        (PORT d[12] (1425:1425:1425) (1468:1468:1468))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1663:1663:1663))
        (PORT d[0] (1080:1080:1080) (1047:1047:1047))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1225:1225:1225) (1295:1295:1295))
        (PORT d[1] (1172:1172:1172) (1212:1212:1212))
        (PORT d[2] (1177:1177:1177) (1223:1223:1223))
        (PORT d[3] (1234:1234:1234) (1269:1269:1269))
        (PORT d[4] (1224:1224:1224) (1277:1277:1277))
        (PORT d[5] (1448:1448:1448) (1523:1523:1523))
        (PORT d[6] (1144:1144:1144) (1190:1190:1190))
        (PORT d[7] (1151:1151:1151) (1201:1201:1201))
        (PORT d[8] (1184:1184:1184) (1233:1233:1233))
        (PORT d[9] (1167:1167:1167) (1202:1202:1202))
        (PORT d[10] (1166:1166:1166) (1196:1196:1196))
        (PORT d[11] (1181:1181:1181) (1219:1219:1219))
        (PORT d[12] (1176:1176:1176) (1246:1246:1246))
        (PORT clk (1633:1633:1633) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1660:1660:1660))
        (PORT d[0] (1083:1083:1083) (1109:1109:1109))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datac (597:597:597) (621:621:621))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1353:1353:1353) (1370:1370:1370))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (200:200:200) (258:258:258))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1353:1353:1353) (1370:1370:1370))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (586:586:586) (570:570:570))
        (PORT datac (853:853:853) (841:841:841))
        (PORT datad (901:901:901) (939:939:939))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1471:1471:1471) (1536:1536:1536))
        (PORT d[1] (917:917:917) (958:958:958))
        (PORT d[2] (929:929:929) (984:984:984))
        (PORT d[3] (974:974:974) (991:991:991))
        (PORT d[4] (912:912:912) (955:955:955))
        (PORT d[5] (1454:1454:1454) (1531:1531:1531))
        (PORT d[6] (910:910:910) (947:947:947))
        (PORT d[7] (884:884:884) (927:927:927))
        (PORT d[8] (938:938:938) (983:983:983))
        (PORT d[9] (1410:1410:1410) (1416:1416:1416))
        (PORT d[10] (1372:1372:1372) (1359:1359:1359))
        (PORT d[11] (886:886:886) (923:923:923))
        (PORT d[12] (926:926:926) (969:969:969))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (PORT d[0] (829:829:829) (809:809:809))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1166:1166:1166) (1209:1209:1209))
        (PORT d[1] (1176:1176:1176) (1219:1219:1219))
        (PORT d[2] (1148:1148:1148) (1195:1195:1195))
        (PORT d[3] (1218:1218:1218) (1252:1252:1252))
        (PORT d[4] (1181:1181:1181) (1236:1236:1236))
        (PORT d[5] (1446:1446:1446) (1481:1481:1481))
        (PORT d[6] (1170:1170:1170) (1218:1218:1218))
        (PORT d[7] (1154:1154:1154) (1206:1206:1206))
        (PORT d[8] (1188:1188:1188) (1239:1239:1239))
        (PORT d[9] (1170:1170:1170) (1208:1208:1208))
        (PORT d[10] (1169:1169:1169) (1201:1201:1201))
        (PORT d[11] (1159:1159:1159) (1204:1204:1204))
        (PORT d[12] (1405:1405:1405) (1441:1441:1441))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1660:1660:1660))
        (PORT d[0] (1034:1034:1034) (1056:1056:1056))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (581:581:581) (581:581:581))
        (PORT datab (675:675:675) (722:722:722))
        (PORT datac (835:835:835) (825:825:825))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1730:1730:1730) (1788:1788:1788))
        (PORT d[1] (1138:1138:1138) (1162:1162:1162))
        (PORT d[2] (1178:1178:1178) (1212:1212:1212))
        (PORT d[3] (1221:1221:1221) (1226:1226:1226))
        (PORT d[4] (1174:1174:1174) (1190:1190:1190))
        (PORT d[5] (1739:1739:1739) (1812:1812:1812))
        (PORT d[6] (1161:1161:1161) (1174:1174:1174))
        (PORT d[7] (1257:1257:1257) (1318:1318:1318))
        (PORT d[8] (1125:1125:1125) (1155:1155:1155))
        (PORT d[9] (1167:1167:1167) (1188:1188:1188))
        (PORT d[10] (1178:1178:1178) (1194:1194:1194))
        (PORT d[11] (1131:1131:1131) (1145:1145:1145))
        (PORT d[12] (1172:1172:1172) (1230:1230:1230))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (PORT d[0] (1039:1039:1039) (1059:1059:1059))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (709:709:709) (744:744:744))
        (PORT d[1] (597:597:597) (635:635:635))
        (PORT d[2] (1405:1405:1405) (1428:1428:1428))
        (PORT d[3] (1136:1136:1136) (1139:1139:1139))
        (PORT d[4] (876:876:876) (905:905:905))
        (PORT d[5] (977:977:977) (1007:1007:1007))
        (PORT d[6] (1112:1112:1112) (1125:1125:1125))
        (PORT d[7] (1159:1159:1159) (1172:1172:1172))
        (PORT d[8] (1381:1381:1381) (1409:1409:1409))
        (PORT d[9] (1161:1161:1161) (1186:1186:1186))
        (PORT d[10] (1148:1148:1148) (1158:1158:1158))
        (PORT d[11] (1125:1125:1125) (1135:1135:1135))
        (PORT d[12] (1149:1149:1149) (1159:1159:1159))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (PORT d[0] (817:817:817) (799:799:799))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (876:876:876) (918:918:918))
        (PORT datac (557:557:557) (538:538:538))
        (PORT datad (966:966:966) (927:927:927))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1429:1429:1429) (1476:1476:1476))
        (PORT d[1] (1197:1197:1197) (1241:1241:1241))
        (PORT d[2] (1171:1171:1171) (1217:1217:1217))
        (PORT d[3] (1268:1268:1268) (1305:1305:1305))
        (PORT d[4] (1457:1457:1457) (1497:1497:1497))
        (PORT d[5] (1204:1204:1204) (1268:1268:1268))
        (PORT d[6] (1196:1196:1196) (1238:1238:1238))
        (PORT d[7] (1155:1155:1155) (1207:1207:1207))
        (PORT d[8] (1164:1164:1164) (1212:1212:1212))
        (PORT d[9] (1196:1196:1196) (1237:1237:1237))
        (PORT d[10] (1195:1195:1195) (1230:1230:1230))
        (PORT d[11] (1159:1159:1159) (1205:1205:1205))
        (PORT d[12] (1156:1156:1156) (1197:1197:1197))
        (PORT clk (1629:1629:1629) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1629:1629:1629) (1658:1658:1658))
        (PORT d[0] (1051:1051:1051) (1017:1017:1017))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1630:1630:1630) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1596:1596:1596) (1624:1624:1624))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (871:871:871))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (942:942:942) (994:994:994))
        (PORT d[1] (857:857:857) (902:902:902))
        (PORT d[2] (859:859:859) (895:895:895))
        (PORT d[3] (1152:1152:1152) (1160:1160:1160))
        (PORT d[4] (1403:1403:1403) (1451:1451:1451))
        (PORT d[5] (1209:1209:1209) (1238:1238:1238))
        (PORT d[6] (1157:1157:1157) (1180:1180:1180))
        (PORT d[7] (1218:1218:1218) (1253:1253:1253))
        (PORT d[8] (1362:1362:1362) (1381:1381:1381))
        (PORT d[9] (1172:1172:1172) (1214:1214:1214))
        (PORT d[10] (1167:1167:1167) (1196:1196:1196))
        (PORT d[11] (1179:1179:1179) (1206:1206:1206))
        (PORT d[12] (1176:1176:1176) (1203:1203:1203))
        (PORT clk (1637:1637:1637) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1666:1666:1666))
        (PORT d[0] (824:824:824) (822:822:822))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1632:1632:1632))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (875:875:875) (879:879:879))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (927:927:927) (979:979:979))
        (PORT datac (562:562:562) (545:545:545))
        (PORT datad (978:978:978) (932:932:932))
        (IOPATH datab combout (308:308:308) (300:300:300))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
)