// Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // VENDOR "Altera" // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" // DATE "03/30/2022 13:47:24" // // Device: Altera EP4CE22F17C6 Package FBGA256 // // // This Verilog file should be used for ModelSim-Altera (Verilog) only // `timescale 1 ps/ 1 ps module spectrum ( CLOCK_50, LED); input CLOCK_50; output [7:0] LED; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[1] => Location: PIN_A13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[2] => Location: PIN_B13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[3] => Location: PIN_A11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[4] => Location: PIN_D1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default wire gnd; wire vcc; wire unknown; assign gnd = 1'b0; assign vcc = 1'b1; assign unknown = 1'bx; tri1 devclrn; tri1 devpor; tri1 devoe; // synopsys translate_off initial $sdf_annotate("spectrum_6_1200mv_0c_v_slow.sdo"); // synopsys translate_on wire \LED[0]~output_o ; wire \LED[1]~output_o ; wire \LED[2]~output_o ; wire \LED[3]~output_o ; wire \LED[4]~output_o ; wire \LED[5]~output_o ; wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; wire \counter[0]~63_combout ; wire \counter[1]~21_combout ; wire \counter[1]~22 ; wire \counter[2]~23_combout ; wire \counter[2]~24 ; wire \counter[3]~25_combout ; wire \counter[3]~26 ; wire \counter[4]~27_combout ; wire \counter[4]~28 ; wire \counter[5]~29_combout ; wire \counter[5]~30 ; wire \counter[6]~31_combout ; wire \counter[6]~32 ; wire \counter[7]~33_combout ; wire \counter[7]~34 ; wire \counter[8]~35_combout ; wire \counter[8]~36 ; wire \counter[9]~37_combout ; wire \counter[9]~38 ; wire \counter[10]~39_combout ; wire \counter[10]~40 ; wire \counter[11]~41_combout ; wire \counter[11]~42 ; wire \counter[12]~43_combout ; wire \counter[12]~44 ; wire \counter[13]~45_combout ; wire \counter[13]~46 ; wire \counter[14]~47_combout ; wire \counter[14]~48 ; wire \counter[15]~49_combout ; wire \counter[15]~50 ; wire \counter[16]~51_combout ; wire \counter[16]~52 ; wire \counter[17]~53_combout ; wire \counter[17]~54 ; wire \counter[18]~55_combout ; wire \counter[18]~56 ; wire \counter[19]~57_combout ; wire \counter[19]~58 ; wire \counter[20]~59_combout ; wire \counter[20]~60 ; wire \counter[21]~61_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; wire \Equal0~6_combout ; wire \A[0]~39_combout ; wire \A[1]~13_combout ; wire \A[1]~14 ; wire \A[2]~15_combout ; wire \A[2]~16 ; wire \A[3]~17_combout ; wire \A[3]~18 ; wire \A[4]~19_combout ; wire \A[4]~20 ; wire \A[5]~21_combout ; wire \A[5]~22 ; wire \A[6]~23_combout ; wire \A[6]~24 ; wire \A[7]~25_combout ; wire \A[7]~26 ; wire \A[8]~27_combout ; wire \A[8]~28 ; wire \A[9]~29_combout ; wire \A[9]~30 ; wire \A[10]~31_combout ; wire \A[10]~32 ; wire \A[11]~33_combout ; wire \A[11]~34 ; wire \A[12]~35_combout ; wire \A[12]~36 ; wire \A[13]~37_combout ; wire \~GND~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; wire [21:0] counter; wire [15:0] A; wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[0]~output_o ), .obar()); // synopsys translate_off defparam \LED[0]~output .bus_hold = "false"; defparam \LED[0]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[1]~output_o ), .obar()); // synopsys translate_off defparam \LED[1]~output .bus_hold = "false"; defparam \LED[1]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[2]~output_o ), .obar()); // synopsys translate_off defparam \LED[2]~output .bus_hold = "false"; defparam \LED[2]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[3]~output_o ), .obar()); // synopsys translate_off defparam \LED[3]~output .bus_hold = "false"; defparam \LED[3]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[4]~output_o ), .obar()); // synopsys translate_off defparam \LED[4]~output .bus_hold = "false"; defparam \LED[4]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[5]~output_o ), .obar()); // synopsys translate_off defparam \LED[5]~output .bus_hold = "false"; defparam \LED[5]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[6]~output_o ), .obar()); // synopsys translate_off defparam \LED[6]~output .bus_hold = "false"; defparam \LED[6]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(\LED[7]~output_o ), .obar()); // synopsys translate_off defparam \LED[7]~output .bus_hold = "false"; defparam \LED[7]~output .open_drain_output = "false"; // synopsys translate_on // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), .ibar(gnd), .o(\CLOCK_50~input_o )); // synopsys translate_off defparam \CLOCK_50~input .bus_hold = "false"; defparam \CLOCK_50~input .simulate_z_as = "z"; // synopsys translate_on // Location: CLKCTRL_G18 cycloneive_clkctrl \CLOCK_50~inputclkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), .outclk(\CLOCK_50~inputclkctrl_outclk )); // synopsys translate_off defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] .dataa(gnd), .datab(gnd), .datac(counter[0]), .datad(gnd), .cin(gnd), .combout(\counter[0]~63_combout ), .cout()); // synopsys translate_off defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X30_Y14_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[0]), .prn(vcc)); // synopsys translate_off defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) // \counter[1]~22 = CARRY((counter[1] & counter[0])) .dataa(counter[1]), .datab(counter[0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\counter[1]~21_combout ), .cout(\counter[1]~22 )); // synopsys translate_off defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X30_Y14_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[1]), .prn(vcc)); // synopsys translate_off defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) // \counter[2]~24 = CARRY((!\counter[1]~22 ) # (!counter[2])) .dataa(gnd), .datab(counter[2]), .datac(gnd), .datad(vcc), .cin(\counter[1]~22 ), .combout(\counter[2]~23_combout ), .cout(\counter[2]~24 )); // synopsys translate_off defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[2]), .prn(vcc)); // synopsys translate_off defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) // \counter[3]~26 = CARRY((counter[3] & !\counter[2]~24 )) .dataa(gnd), .datab(counter[3]), .datac(gnd), .datad(vcc), .cin(\counter[2]~24 ), .combout(\counter[3]~25_combout ), .cout(\counter[3]~26 )); // synopsys translate_off defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[3]), .prn(vcc)); // synopsys translate_off defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) // \counter[4]~28 = CARRY((!\counter[3]~26 ) # (!counter[4])) .dataa(gnd), .datab(counter[4]), .datac(gnd), .datad(vcc), .cin(\counter[3]~26 ), .combout(\counter[4]~27_combout ), .cout(\counter[4]~28 )); // synopsys translate_off defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[4]), .prn(vcc)); // synopsys translate_off defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) // \counter[5]~30 = CARRY((counter[5] & !\counter[4]~28 )) .dataa(gnd), .datab(counter[5]), .datac(gnd), .datad(vcc), .cin(\counter[4]~28 ), .combout(\counter[5]~29_combout ), .cout(\counter[5]~30 )); // synopsys translate_off defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[5]), .prn(vcc)); // synopsys translate_off defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) // \counter[6]~32 = CARRY((!\counter[5]~30 ) # (!counter[6])) .dataa(counter[6]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[5]~30 ), .combout(\counter[6]~31_combout ), .cout(\counter[6]~32 )); // synopsys translate_off defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[6]), .prn(vcc)); // synopsys translate_off defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) // \counter[7]~34 = CARRY((counter[7] & !\counter[6]~32 )) .dataa(gnd), .datab(counter[7]), .datac(gnd), .datad(vcc), .cin(\counter[6]~32 ), .combout(\counter[7]~33_combout ), .cout(\counter[7]~34 )); // synopsys translate_off defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[7]), .prn(vcc)); // synopsys translate_off defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) // \counter[8]~36 = CARRY((!\counter[7]~34 ) # (!counter[8])) .dataa(counter[8]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[7]~34 ), .combout(\counter[8]~35_combout ), .cout(\counter[8]~36 )); // synopsys translate_off defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[8]), .prn(vcc)); // synopsys translate_off defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) // \counter[9]~38 = CARRY((counter[9] & !\counter[8]~36 )) .dataa(gnd), .datab(counter[9]), .datac(gnd), .datad(vcc), .cin(\counter[8]~36 ), .combout(\counter[9]~37_combout ), .cout(\counter[9]~38 )); // synopsys translate_off defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[9]), .prn(vcc)); // synopsys translate_off defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) // \counter[10]~40 = CARRY((!\counter[9]~38 ) # (!counter[10])) .dataa(counter[10]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[9]~38 ), .combout(\counter[10]~39_combout ), .cout(\counter[10]~40 )); // synopsys translate_off defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y14_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[10]), .prn(vcc)); // synopsys translate_off defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) // \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) .dataa(gnd), .datab(counter[11]), .datac(gnd), .datad(vcc), .cin(\counter[10]~40 ), .combout(\counter[11]~41_combout ), .cout(\counter[11]~42 )); // synopsys translate_off defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[11]~41_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[11]), .prn(vcc)); // synopsys translate_off defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) // \counter[12]~44 = CARRY((!\counter[11]~42 ) # (!counter[12])) .dataa(gnd), .datab(counter[12]), .datac(gnd), .datad(vcc), .cin(\counter[11]~42 ), .combout(\counter[12]~43_combout ), .cout(\counter[12]~44 )); // synopsys translate_off defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[12]), .prn(vcc)); // synopsys translate_off defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) // \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) .dataa(counter[13]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[12]~44 ), .combout(\counter[13]~45_combout ), .cout(\counter[13]~46 )); // synopsys translate_off defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[13]), .prn(vcc)); // synopsys translate_off defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) // \counter[14]~48 = CARRY((!\counter[13]~46 ) # (!counter[14])) .dataa(counter[14]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[13]~46 ), .combout(\counter[14]~47_combout ), .cout(\counter[14]~48 )); // synopsys translate_off defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[14]), .prn(vcc)); // synopsys translate_off defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) .dataa(counter[15]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off defparam \counter[15]~49 .lut_mask = 16'hA50A; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[15]), .prn(vcc)); // synopsys translate_off defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) // \counter[16]~52 = CARRY((!\counter[15]~50 ) # (!counter[16])) .dataa(counter[16]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[15]~50 ), .combout(\counter[16]~51_combout ), .cout(\counter[16]~52 )); // synopsys translate_off defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[16]), .prn(vcc)); // synopsys translate_off defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) // \counter[17]~54 = CARRY((counter[17] & !\counter[16]~52 )) .dataa(counter[17]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[16]~52 ), .combout(\counter[17]~53_combout ), .cout(\counter[17]~54 )); // synopsys translate_off defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[17]), .prn(vcc)); // synopsys translate_off defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) // \counter[18]~56 = CARRY((!\counter[17]~54 ) # (!counter[18])) .dataa(gnd), .datab(counter[18]), .datac(gnd), .datad(vcc), .cin(\counter[17]~54 ), .combout(\counter[18]~55_combout ), .cout(\counter[18]~56 )); // synopsys translate_off defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[18]), .prn(vcc)); // synopsys translate_off defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) // \counter[19]~58 = CARRY((counter[19] & !\counter[18]~56 )) .dataa(gnd), .datab(counter[19]), .datac(gnd), .datad(vcc), .cin(\counter[18]~56 ), .combout(\counter[19]~57_combout ), .cout(\counter[19]~58 )); // synopsys translate_off defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[19]), .prn(vcc)); // synopsys translate_off defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) // \counter[20]~60 = CARRY((!\counter[19]~58 ) # (!counter[20])) .dataa(gnd), .datab(counter[20]), .datac(gnd), .datad(vcc), .cin(\counter[19]~58 ), .combout(\counter[20]~59_combout ), .cout(\counter[20]~60 )); // synopsys translate_off defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[20]), .prn(vcc)); // synopsys translate_off defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) .dataa(gnd), .datab(gnd), .datac(gnd), .datad(counter[21]), .cin(\counter[20]~60 ), .combout(\counter[21]~61_combout ), .cout()); // synopsys translate_off defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X30_Y13_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(counter[21]), .prn(vcc)); // synopsys translate_off defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N24 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): // \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) .dataa(counter[17]), .datab(counter[19]), .datac(counter[18]), .datad(counter[16]), .cin(gnd), .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N4 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): // \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) .dataa(counter[1]), .datab(counter[0]), .datac(counter[2]), .datad(counter[3]), .cin(gnd), .combout(\Equal0~0_combout ), .cout()); // synopsys translate_off defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N10 cycloneive_lcell_comb \Equal0~1 ( // Equation(s): // \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) .dataa(counter[6]), .datab(counter[4]), .datac(counter[7]), .datad(counter[5]), .cin(gnd), .combout(\Equal0~1_combout ), .cout()); // synopsys translate_off defparam \Equal0~1 .lut_mask = 16'h0001; defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N26 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): // \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) .dataa(counter[10]), .datab(counter[9]), .datac(counter[8]), .datad(counter[11]), .cin(gnd), .combout(\Equal0~2_combout ), .cout()); // synopsys translate_off defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y13_N30 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): // \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) .dataa(counter[14]), .datab(counter[15]), .datac(counter[13]), .datad(counter[12]), .cin(gnd), .combout(\Equal0~3_combout ), .cout()); // synopsys translate_off defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): // \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) .dataa(\Equal0~0_combout ), .datab(\Equal0~1_combout ), .datac(\Equal0~2_combout ), .datad(\Equal0~3_combout ), .cin(gnd), .combout(\Equal0~4_combout ), .cout()); // synopsys translate_off defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N30 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): // \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) .dataa(counter[20]), .datab(counter[21]), .datac(\Equal0~5_combout ), .datad(\Equal0~4_combout ), .cin(gnd), .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N0 cycloneive_lcell_comb \A[0]~39 ( // Equation(s): // \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) .dataa(gnd), .datab(gnd), .datac(A[0]), .datad(\Equal0~6_combout ), .cin(gnd), .combout(\A[0]~39_combout ), .cout()); // synopsys translate_off defparam \A[0]~39 .lut_mask = 16'h0FF0; defparam \A[0]~39 .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X30_Y14_N1 dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(A[0]), .prn(vcc)); // synopsys translate_off defparam \A[0] .is_wysiwyg = "true"; defparam \A[0] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N0 cycloneive_lcell_comb \A[1]~13 ( // Equation(s): // \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) // \A[1]~14 = CARRY((A[1] & A[0])) .dataa(A[1]), .datab(A[0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\A[1]~13_combout ), .cout(\A[1]~14 )); // synopsys translate_off defparam \A[1]~13 .lut_mask = 16'h6688; defparam \A[1]~13 .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X29_Y14_N1 dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[1]), .prn(vcc)); // synopsys translate_off defparam \A[1] .is_wysiwyg = "true"; defparam \A[1] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N2 cycloneive_lcell_comb \A[2]~15 ( // Equation(s): // \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) // \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) .dataa(gnd), .datab(A[2]), .datac(gnd), .datad(vcc), .cin(\A[1]~14 ), .combout(\A[2]~15_combout ), .cout(\A[2]~16 )); // synopsys translate_off defparam \A[2]~15 .lut_mask = 16'h3C3F; defparam \A[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N3 dffeas \A[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[2]~15_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[2]), .prn(vcc)); // synopsys translate_off defparam \A[2] .is_wysiwyg = "true"; defparam \A[2] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N4 cycloneive_lcell_comb \A[3]~17 ( // Equation(s): // \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) // \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) .dataa(gnd), .datab(A[3]), .datac(gnd), .datad(vcc), .cin(\A[2]~16 ), .combout(\A[3]~17_combout ), .cout(\A[3]~18 )); // synopsys translate_off defparam \A[3]~17 .lut_mask = 16'hC30C; defparam \A[3]~17 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N5 dffeas \A[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[3]~17_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[3]), .prn(vcc)); // synopsys translate_off defparam \A[3] .is_wysiwyg = "true"; defparam \A[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N6 cycloneive_lcell_comb \A[4]~19 ( // Equation(s): // \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) // \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) .dataa(A[4]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\A[3]~18 ), .combout(\A[4]~19_combout ), .cout(\A[4]~20 )); // synopsys translate_off defparam \A[4]~19 .lut_mask = 16'h5A5F; defparam \A[4]~19 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N7 dffeas \A[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[4]~19_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[4]), .prn(vcc)); // synopsys translate_off defparam \A[4] .is_wysiwyg = "true"; defparam \A[4] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N8 cycloneive_lcell_comb \A[5]~21 ( // Equation(s): // \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) // \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) .dataa(gnd), .datab(A[5]), .datac(gnd), .datad(vcc), .cin(\A[4]~20 ), .combout(\A[5]~21_combout ), .cout(\A[5]~22 )); // synopsys translate_off defparam \A[5]~21 .lut_mask = 16'hC30C; defparam \A[5]~21 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N9 dffeas \A[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[5]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[5]), .prn(vcc)); // synopsys translate_off defparam \A[5] .is_wysiwyg = "true"; defparam \A[5] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N10 cycloneive_lcell_comb \A[6]~23 ( // Equation(s): // \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) // \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) .dataa(A[6]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\A[5]~22 ), .combout(\A[6]~23_combout ), .cout(\A[6]~24 )); // synopsys translate_off defparam \A[6]~23 .lut_mask = 16'h5A5F; defparam \A[6]~23 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N11 dffeas \A[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[6]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[6]), .prn(vcc)); // synopsys translate_off defparam \A[6] .is_wysiwyg = "true"; defparam \A[6] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N12 cycloneive_lcell_comb \A[7]~25 ( // Equation(s): // \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) // \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) .dataa(A[7]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\A[6]~24 ), .combout(\A[7]~25_combout ), .cout(\A[7]~26 )); // synopsys translate_off defparam \A[7]~25 .lut_mask = 16'hA50A; defparam \A[7]~25 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N13 dffeas \A[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[7]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[7]), .prn(vcc)); // synopsys translate_off defparam \A[7] .is_wysiwyg = "true"; defparam \A[7] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N14 cycloneive_lcell_comb \A[8]~27 ( // Equation(s): // \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) // \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) .dataa(A[8]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\A[7]~26 ), .combout(\A[8]~27_combout ), .cout(\A[8]~28 )); // synopsys translate_off defparam \A[8]~27 .lut_mask = 16'h5A5F; defparam \A[8]~27 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N15 dffeas \A[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[8]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[8]), .prn(vcc)); // synopsys translate_off defparam \A[8] .is_wysiwyg = "true"; defparam \A[8] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N16 cycloneive_lcell_comb \A[9]~29 ( // Equation(s): // \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) // \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) .dataa(gnd), .datab(A[9]), .datac(gnd), .datad(vcc), .cin(\A[8]~28 ), .combout(\A[9]~29_combout ), .cout(\A[9]~30 )); // synopsys translate_off defparam \A[9]~29 .lut_mask = 16'hC30C; defparam \A[9]~29 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N17 dffeas \A[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[9]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[9]), .prn(vcc)); // synopsys translate_off defparam \A[9] .is_wysiwyg = "true"; defparam \A[9] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N18 cycloneive_lcell_comb \A[10]~31 ( // Equation(s): // \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) // \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) .dataa(gnd), .datab(A[10]), .datac(gnd), .datad(vcc), .cin(\A[9]~30 ), .combout(\A[10]~31_combout ), .cout(\A[10]~32 )); // synopsys translate_off defparam \A[10]~31 .lut_mask = 16'h3C3F; defparam \A[10]~31 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N19 dffeas \A[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[10]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[10]), .prn(vcc)); // synopsys translate_off defparam \A[10] .is_wysiwyg = "true"; defparam \A[10] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N20 cycloneive_lcell_comb \A[11]~33 ( // Equation(s): // \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) // \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) .dataa(gnd), .datab(A[11]), .datac(gnd), .datad(vcc), .cin(\A[10]~32 ), .combout(\A[11]~33_combout ), .cout(\A[11]~34 )); // synopsys translate_off defparam \A[11]~33 .lut_mask = 16'hC30C; defparam \A[11]~33 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N21 dffeas \A[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[11]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[11]), .prn(vcc)); // synopsys translate_off defparam \A[11] .is_wysiwyg = "true"; defparam \A[11] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N22 cycloneive_lcell_comb \A[12]~35 ( // Equation(s): // \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) // \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) .dataa(A[12]), .datab(gnd), .datac(gnd), .datad(vcc), .cin(\A[11]~34 ), .combout(\A[12]~35_combout ), .cout(\A[12]~36 )); // synopsys translate_off defparam \A[12]~35 .lut_mask = 16'h5A5F; defparam \A[12]~35 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N23 dffeas \A[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[12]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[12]), .prn(vcc)); // synopsys translate_off defparam \A[12] .is_wysiwyg = "true"; defparam \A[12] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X29_Y14_N24 cycloneive_lcell_comb \A[13]~37 ( // Equation(s): // \A[13]~37_combout = \A[12]~36 $ (!A[13]) .dataa(gnd), .datab(gnd), .datac(gnd), .datad(A[13]), .cin(\A[12]~36 ), .combout(\A[13]~37_combout ), .cout()); // synopsys translate_off defparam \A[13]~37 .lut_mask = 16'hF00F; defparam \A[13]~37 .sum_lutc_input = "cin"; // synopsys translate_on // Location: FF_X29_Y14_N25 dffeas \A[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\A[13]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(A[13]), .prn(vcc)); // synopsys translate_off defparam \A[13] .is_wysiwyg = "true"; defparam \A[13] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X34_Y14_N4 cycloneive_lcell_comb \~GND ( // Equation(s): // \~GND~combout = GND .dataa(gnd), .datab(gnd), .datac(gnd), .datad(gnd), .cin(gnd), .combout(\~GND~combout ), .cout()); // synopsys translate_off defparam \~GND .lut_mask = 16'h0000; defparam \~GND .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X33_Y12_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), .ena0(vcc), .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain({\~GND~combout }), .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on // Location: M9K_X33_Y11_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), .ena0(vcc), .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain({\~GND~combout }), .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on // Location: M9K_X33_Y13_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), .ena0(vcc), .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain({\~GND~combout }), .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on // Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), .ena0(vcc), .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain({\~GND~combout }), .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on // Location: M9K_X22_Y13_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on // Location: M9K_X22_Y12_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on // Location: LCCOMB_X27_Y14_N2 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( // Equation(s): // \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] .dataa(gnd), .datab(gnd), .datac(A[13]), .datad(gnd), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X27_Y14_N3 dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), .prn(vcc)); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X27_Y14_N16 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( // Equation(s): // \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] .dataa(gnd), .datab(gnd), .datac(gnd), .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on // Location: FF_X27_Y14_N17 dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .prn(vcc)); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X23_Y13_N4 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( // Equation(s): // \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) .dataa(gnd), .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on // Location: M9K_X22_Y11_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on // Location: LCCOMB_X23_Y14_N4 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( // Equation(s): // \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(gnd), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X22_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on // Location: M9K_X33_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on // Location: LCCOMB_X23_Y15_N0 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( // Equation(s): // \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) .dataa(gnd), .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X22_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; // synopsys translate_on // Location: M9K_X33_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; // synopsys translate_on // Location: LCCOMB_X23_Y10_N0 cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( // Equation(s): // \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) .dataa(gnd), .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .cout()); // synopsys translate_off defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; assign LED[1] = \LED[1]~output_o ; assign LED[2] = \LED[2]~output_o ; assign LED[3] = \LED[3]~output_o ; assign LED[4] = \LED[4]~output_o ; assign LED[5] = \LED[5]~output_o ; assign LED[6] = \LED[6]~output_o ; assign LED[7] = \LED[7]~output_o ; endmodule