TimeQuest Timing Analyzer report for spectrum Wed Mar 30 13:47:22 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. Clocks 5. Slow 1200mV 85C Model Fmax Summary 6. Timing Closure Recommendations 7. Slow 1200mV 85C Model Setup Summary 8. Slow 1200mV 85C Model Hold Summary 9. Slow 1200mV 85C Model Recovery Summary 10. Slow 1200mV 85C Model Removal Summary 11. Slow 1200mV 85C Model Minimum Pulse Width Summary 12. Slow 1200mV 85C Model Setup: 'CLOCK_50' 13. Slow 1200mV 85C Model Hold: 'CLOCK_50' 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' 15. Clock to Output Times 16. Minimum Clock to Output Times 17. Slow 1200mV 85C Model Metastability Report 18. Slow 1200mV 0C Model Fmax Summary 19. Slow 1200mV 0C Model Setup Summary 20. Slow 1200mV 0C Model Hold Summary 21. Slow 1200mV 0C Model Recovery Summary 22. Slow 1200mV 0C Model Removal Summary 23. Slow 1200mV 0C Model Minimum Pulse Width Summary 24. Slow 1200mV 0C Model Setup: 'CLOCK_50' 25. Slow 1200mV 0C Model Hold: 'CLOCK_50' 26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' 27. Clock to Output Times 28. Minimum Clock to Output Times 29. Slow 1200mV 0C Model Metastability Report 30. Fast 1200mV 0C Model Setup Summary 31. Fast 1200mV 0C Model Hold Summary 32. Fast 1200mV 0C Model Recovery Summary 33. Fast 1200mV 0C Model Removal Summary 34. Fast 1200mV 0C Model Minimum Pulse Width Summary 35. Fast 1200mV 0C Model Setup: 'CLOCK_50' 36. Fast 1200mV 0C Model Hold: 'CLOCK_50' 37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' 38. Clock to Output Times 39. Minimum Clock to Output Times 40. Fast 1200mV 0C Model Metastability Report 41. Multicorner Timing Analysis Summary 42. Clock to Output Times 43. Minimum Clock to Output Times 44. Board Trace Model Assignments 45. Input Transition Times 46. Signal Integrity Metrics (Slow 1200mv 0c Model) 47. Signal Integrity Metrics (Slow 1200mv 85c Model) 48. Signal Integrity Metrics (Fast 1200mv 0c Model) 49. Setup Transfers 50. Hold Transfers 51. Report TCCS 52. Report RSKM 53. Unconstrained Paths 54. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +--------------------+----------------------------------------------------+ ; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Device Family ; Cyclone IV E ; ; Device Name ; EP4CE22F17C6 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +--------------------+----------------------------------------------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 12 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +--------------------------------------------------------------------------------+ ; Clocks ; +--------------------------------------------------------------------------------+ Clock Name : CLOCK_50 Type : Base Period : 1.000 Frequency : 1000.0 MHz Rise : 0.000 Fall : 0.500 Duty Cycle : Divide by : Multiply by : Phase : Offset : Edge List : Edge Shift : Inverted : Master : Source : Targets : { CLOCK_50 } +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ Fmax : 355.62 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) +--------------------------------------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. ---------------------------------- ; Timing Closure Recommendations ; ---------------------------------- HTML report is unavailable in plain text report export. +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -1.812 End Point TNS : -85.179 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : 0.343 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ------------------------------------------ ; Slow 1200mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Slow 1200mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 End Point TNS : -119.480 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -1.812 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.125 Data Delay : 2.616 Slack : -1.811 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.124 Data Delay : 2.616 Slack : -1.811 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.124 Data Delay : 2.616 Slack : -1.811 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.124 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.756 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 Slack : -1.506 From Node : counter[2] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.438 Slack : -1.501 From Node : counter[15] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.501 From Node : counter[15] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.786 Slack : -1.499 From Node : counter[14] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.499 From Node : counter[14] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.290 Data Delay : 2.784 Slack : -1.455 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.139 Data Delay : 2.344 Slack : -1.436 From Node : A[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.077 Data Delay : 2.354 Slack : -1.428 From Node : counter[1] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.360 Slack : -1.424 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.138 Data Delay : 2.314 Slack : -1.423 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.141 Data Delay : 2.310 Slack : -1.423 From Node : counter[0] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.355 Slack : -1.418 From Node : A[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.077 Data Delay : 2.336 Slack : -1.406 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.142 Data Delay : 2.292 Slack : -1.401 From Node : counter[1] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.401 From Node : counter[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.685 Slack : -1.399 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.137 Data Delay : 2.290 Slack : -1.394 From Node : counter[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.394 From Node : counter[0] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.678 Slack : -1.391 From Node : counter[4] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.323 Slack : -1.390 From Node : counter[2] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.322 Slack : -1.385 From Node : counter[0] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.317 Slack : -1.384 From Node : counter[2] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.316 Slack : -1.382 From Node : counter[1] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 Data Delay : 2.314 Slack : -1.369 From Node : counter[21] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.369 From Node : counter[21] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 2.288 Slack : -1.367 From Node : counter[6] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 Slack : -1.367 From Node : counter[6] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.289 Data Delay : 2.651 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : 0.343 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.577 Slack : 0.360 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.580 Slack : 0.375 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.594 Slack : 0.376 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.610 Slack : 0.394 From Node : A[13] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.628 Slack : 0.484 From Node : counter[19] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.069 Slack : 0.486 From Node : counter[19] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.071 Slack : 0.554 From Node : A[4] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.788 Slack : 0.555 From Node : A[12] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.789 Slack : 0.555 From Node : A[6] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.789 Slack : 0.555 From Node : A[2] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.789 Slack : 0.556 From Node : A[7] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.790 Slack : 0.556 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.775 Slack : 0.556 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.776 Slack : 0.557 From Node : A[10] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.791 Slack : 0.557 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.776 Slack : 0.558 From Node : A[3] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.792 Slack : 0.558 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.777 Slack : 0.558 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.792 Slack : 0.559 From Node : A[5] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.793 Slack : 0.559 From Node : counter[17] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.778 Slack : 0.559 From Node : counter[4] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.779 Slack : 0.559 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.779 Slack : 0.560 From Node : A[11] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.794 Slack : 0.560 From Node : counter[5] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.780 Slack : 0.560 From Node : counter[3] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.780 Slack : 0.561 From Node : counter[18] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.780 Slack : 0.563 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.782 Slack : 0.567 From Node : counter[10] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.787 Slack : 0.567 From Node : counter[8] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.787 Slack : 0.570 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.790 Slack : 0.571 From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.791 Slack : 0.571 From Node : counter[1] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.791 Slack : 0.572 From Node : counter[11] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.791 Slack : 0.572 From Node : counter[7] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.792 Slack : 0.579 From Node : A[9] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.813 Slack : 0.579 From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.164 Slack : 0.581 From Node : counter[18] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.166 Slack : 0.593 From Node : counter[17] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.178 Slack : 0.595 From Node : counter[17] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.180 Slack : 0.603 From Node : A[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.026 Data Delay : 0.816 Slack : 0.604 From Node : A[1] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.026 Data Delay : 0.817 Slack : 0.681 From Node : A[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.831 Slack : 0.685 From Node : A[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.835 Slack : 0.687 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.921 Slack : 0.689 From Node : counter[16] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.274 Slack : 0.691 From Node : counter[16] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.276 Slack : 0.703 From Node : counter[15] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.922 Slack : 0.703 From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.922 Slack : 0.717 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.026 Data Delay : 0.930 Slack : 0.721 From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.026 Data Delay : 0.934 Slack : 0.742 From Node : A[5] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.892 Slack : 0.746 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.980 Slack : 0.753 From Node : A[11] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.903 Slack : 0.754 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.904 Slack : 0.767 From Node : A[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.917 Slack : 0.779 From Node : A[9] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.929 Slack : 0.784 From Node : A[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.037 Data Delay : 0.934 Slack : 0.799 From Node : counter[14] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.384 Slack : 0.801 From Node : counter[14] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.386 Slack : 0.829 From Node : A[2] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.063 Slack : 0.829 From Node : A[4] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.063 Slack : 0.830 From Node : A[12] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.064 Slack : 0.830 From Node : A[6] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.064 Slack : 0.831 From Node : A[10] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.065 Slack : 0.831 From Node : counter[6] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.051 Slack : 0.831 From Node : counter[14] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.050 Slack : 0.831 From Node : counter[12] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.050 Slack : 0.832 From Node : counter[20] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.066 Slack : 0.833 From Node : counter[16] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.052 Slack : 0.833 From Node : counter[4] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.053 Slack : 0.833 From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.053 Slack : 0.835 From Node : counter[18] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.054 Slack : 0.842 From Node : counter[8] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.062 Slack : 0.843 From Node : counter[10] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.062 Slack : 0.844 From Node : A[7] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.078 Slack : 0.845 From Node : A[3] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.079 Slack : 0.845 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.065 Slack : 0.846 From Node : A[5] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.080 Slack : 0.846 From Node : A[7] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.080 Slack : 0.847 From Node : A[11] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.081 Slack : 0.847 From Node : counter[5] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.067 Slack : 0.847 From Node : counter[3] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.067 Slack : 0.847 From Node : counter[17] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.066 Slack : 0.847 From Node : A[3] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.081 Slack : 0.847 From Node : counter[1] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.067 Slack : 0.848 From Node : A[5] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.082 Slack : 0.848 From Node : counter[0] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.068 Slack : 0.849 From Node : counter[15] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.434 Slack : 0.849 From Node : A[11] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 Data Delay : 1.083 Slack : 0.849 From Node : counter[5] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.069 Slack : 0.849 From Node : counter[3] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.069 Slack : 0.849 From Node : counter[17] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.068 Slack : 0.850 From Node : counter[0] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.070 Slack : 0.851 From Node : counter[15] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.436 Slack : 0.858 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.078 Slack : 0.859 From Node : counter[11] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.078 Slack : 0.859 From Node : counter[7] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.079 Slack : 0.861 From Node : counter[11] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 Data Delay : 1.080 Slack : 0.861 From Node : counter[7] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 Data Delay : 1.081 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -3.000 Actual Width : 1.000 Required Width : 4.000 Type : Port Rate Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[14] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[15] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[16] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[17] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[18] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[19] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[21] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : 0.000 Actual Width : 0.230 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 10.303 Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 7.474 Fall : 7.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 7.915 Fall : 7.923 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 7.907 Fall : 7.878 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 7.123 Fall : 7.073 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 8.891 Fall : 8.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 10.303 Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 8.706 Fall : 8.626 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 9.651 Fall : 9.302 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 6.895 Fall : 6.842 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 7.233 Fall : 7.193 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 7.656 Fall : 7.659 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 7.648 Fall : 7.616 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 6.895 Fall : 6.842 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 8.165 Fall : 8.150 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 9.531 Fall : 9.293 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 8.085 Fall : 8.027 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 9.079 Fall : 8.736 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ ---------------------------------------------- ; Slow 1200mV 85C Model Metastability Report ; ---------------------------------------------- No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ Fmax : 395.1 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) +--------------------------------------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -1.531 End Point TNS : -69.352 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : 0.299 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ----------------------------------------- ; Slow 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Slow 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 End Point TNS : -119.478 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -1.531 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.116 Data Delay : 2.353 Slack : -1.531 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.116 Data Delay : 2.353 Slack : -1.531 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.116 Data Delay : 2.353 Slack : -1.531 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.116 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.484 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 Slack : -1.265 From Node : counter[15] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.265 From Node : counter[15] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.522 Slack : -1.264 From Node : counter[14] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.264 From Node : counter[14] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.262 Data Delay : 2.521 Slack : -1.221 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.132 Data Delay : 2.109 Slack : -1.200 From Node : counter[2] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.056 Data Delay : 2.139 Slack : -1.177 From Node : counter[1] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.177 From Node : counter[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.433 Slack : -1.170 From Node : counter[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.170 From Node : counter[0] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.426 Slack : -1.169 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.130 Data Delay : 2.059 Slack : -1.169 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.133 Data Delay : 2.056 Slack : -1.168 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.131 Data Delay : 2.057 Slack : -1.157 From Node : A[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.068 Data Delay : 2.084 Slack : -1.145 From Node : A[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.068 Data Delay : 2.072 Slack : -1.144 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.136 Data Delay : 2.028 Slack : -1.144 From Node : counter[6] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.144 From Node : counter[6] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.400 Slack : -1.139 From Node : counter[1] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.056 Data Delay : 2.078 Slack : -1.137 From Node : counter[4] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.137 From Node : counter[4] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.261 Data Delay : 2.393 Slack : -1.131 From Node : counter[21] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.067 Data Delay : 2.059 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : 0.299 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.511 Slack : 0.320 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.519 Slack : 0.334 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.547 Slack : 0.340 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.539 Slack : 0.352 From Node : A[13] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.564 Slack : 0.425 From Node : counter[19] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 0.953 Slack : 0.432 From Node : counter[19] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 0.960 Slack : 0.498 From Node : A[4] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.710 Slack : 0.499 From Node : A[12] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.711 Slack : 0.499 From Node : A[6] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.711 Slack : 0.499 From Node : A[2] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.711 Slack : 0.500 From Node : A[7] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.712 Slack : 0.500 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.699 Slack : 0.500 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.699 Slack : 0.501 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.700 Slack : 0.501 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.700 Slack : 0.501 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.714 Slack : 0.502 From Node : A[10] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.714 Slack : 0.502 From Node : A[3] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.714 Slack : 0.502 From Node : counter[4] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.701 Slack : 0.503 From Node : A[5] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.715 Slack : 0.503 From Node : counter[17] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.702 Slack : 0.503 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.702 Slack : 0.504 From Node : A[11] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.716 Slack : 0.504 From Node : counter[18] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.703 Slack : 0.505 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 Slack : 0.505 From Node : counter[5] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 Slack : 0.505 From Node : counter[3] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 Slack : 0.509 From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.037 Slack : 0.510 From Node : counter[10] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.709 Slack : 0.510 From Node : counter[8] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.709 Slack : 0.514 From Node : counter[11] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.713 Slack : 0.514 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.713 Slack : 0.515 From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.714 Slack : 0.515 From Node : counter[7] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.714 Slack : 0.516 From Node : counter[18] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.044 Slack : 0.516 From Node : counter[1] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.715 Slack : 0.519 From Node : counter[17] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.047 Slack : 0.521 From Node : A[9] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.733 Slack : 0.526 From Node : counter[17] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.054 Slack : 0.562 From Node : A[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 Data Delay : 0.752 Slack : 0.563 From Node : A[1] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 Data Delay : 0.753 Slack : 0.601 From Node : counter[16] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.129 Slack : 0.608 From Node : counter[16] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.136 Slack : 0.625 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.837 Slack : 0.639 From Node : A[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.769 Slack : 0.642 From Node : A[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.772 Slack : 0.644 From Node : counter[15] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.843 Slack : 0.645 From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.844 Slack : 0.666 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 Data Delay : 0.856 Slack : 0.670 From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.021 Data Delay : 0.860 Slack : 0.678 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.890 Slack : 0.695 From Node : A[5] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.825 Slack : 0.696 From Node : counter[14] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.224 Slack : 0.702 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.832 Slack : 0.703 From Node : counter[14] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.231 Slack : 0.707 From Node : A[11] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.837 Slack : 0.718 From Node : A[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.848 Slack : 0.731 From Node : A[9] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.861 Slack : 0.735 From Node : A[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.039 Data Delay : 0.865 Slack : 0.742 From Node : A[4] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.954 Slack : 0.743 From Node : A[12] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.955 Slack : 0.743 From Node : A[6] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.955 Slack : 0.744 From Node : A[2] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.956 Slack : 0.744 From Node : counter[6] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.943 Slack : 0.744 From Node : counter[14] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.943 Slack : 0.745 From Node : counter[16] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.944 Slack : 0.746 From Node : counter[20] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.959 Slack : 0.746 From Node : counter[12] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.945 Slack : 0.747 From Node : A[10] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.959 Slack : 0.747 From Node : counter[4] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.946 Slack : 0.748 From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.947 Slack : 0.749 From Node : counter[18] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.948 Slack : 0.749 From Node : A[7] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.961 Slack : 0.751 From Node : A[3] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.963 Slack : 0.751 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.950 Slack : 0.752 From Node : A[5] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.964 Slack : 0.752 From Node : counter[17] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.951 Slack : 0.753 From Node : A[11] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.965 Slack : 0.753 From Node : counter[0] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.952 Slack : 0.754 From Node : counter[8] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.953 Slack : 0.754 From Node : counter[5] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.953 Slack : 0.754 From Node : counter[3] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.953 Slack : 0.755 From Node : counter[10] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.953 Slack : 0.756 From Node : A[7] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.968 Slack : 0.756 From Node : counter[15] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.284 Slack : 0.758 From Node : A[3] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.970 Slack : 0.758 From Node : counter[1] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.957 Slack : 0.759 From Node : A[5] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.971 Slack : 0.759 From Node : counter[17] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.958 Slack : 0.760 From Node : A[11] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.972 Slack : 0.760 From Node : counter[0] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.959 Slack : 0.761 From Node : counter[5] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.960 Slack : 0.761 From Node : counter[3] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.960 Slack : 0.763 From Node : counter[11] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.962 Slack : 0.763 From Node : counter[15] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.291 Slack : 0.764 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.963 Slack : 0.764 From Node : counter[7] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.963 Slack : 0.770 From Node : A[9] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.982 Slack : 0.770 From Node : counter[11] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.969 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -3.000 Actual Width : 1.000 Required Width : 4.000 Type : Port Rate Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[14] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[15] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[16] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[17] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[18] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[19] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[21] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -0.008 Actual Width : 0.222 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -0.008 Actual Width : 0.222 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.007 Actual Width : 0.223 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -0.002 Actual Width : 0.228 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 9.271 Fall : 8.853 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 6.755 Fall : 6.657 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 7.164 Fall : 7.086 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 7.155 Fall : 7.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 6.435 Fall : 6.313 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 8.039 Fall : 7.928 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 9.271 Fall : 8.853 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 7.923 Fall : 7.721 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 8.704 Fall : 8.167 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 6.217 Fall : 6.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 6.524 Fall : 6.427 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 6.917 Fall : 6.838 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 6.908 Fall : 6.793 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 6.217 Fall : 6.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 7.382 Fall : 7.269 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 8.568 Fall : 8.173 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 7.330 Fall : 7.173 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 8.145 Fall : 7.660 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ --------------------------------------------- ; Slow 1200mV 0C Model Metastability Report ; --------------------------------------------- No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -0.444 End Point TNS : -17.149 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : 0.178 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ----------------------------------------- ; Fast 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Fast 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 End Point TNS : -99.404 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -0.444 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.077 Data Delay : 1.376 Slack : -0.424 From Node : counter[2] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.374 Slack : -0.423 From Node : A[5] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.075 Data Delay : 1.357 Slack : -0.411 From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.075 Data Delay : 1.345 Slack : -0.411 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.076 Data Delay : 1.344 Slack : -0.407 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.079 Data Delay : 1.337 Slack : -0.401 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.081 Data Delay : 1.329 Slack : -0.394 From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.075 Data Delay : 1.328 Slack : -0.385 From Node : A[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.045 Data Delay : 1.327 Slack : -0.380 From Node : counter[15] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.380 From Node : counter[15] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.521 Slack : -0.377 From Node : counter[0] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.327 Slack : -0.375 From Node : counter[1] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.325 Slack : -0.374 From Node : counter[14] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.374 From Node : counter[14] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.154 Data Delay : 1.515 Slack : -0.360 From Node : counter[2] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.310 Slack : -0.356 From Node : counter[2] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.306 Slack : -0.356 From Node : counter[4] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.306 Slack : -0.355 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.078 Data Delay : 1.232 Slack : -0.355 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.078 Data Delay : 1.232 Slack : -0.355 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.078 Data Delay : 1.232 Slack : -0.354 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.077 Data Delay : 1.232 Slack : -0.350 From Node : counter[21] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.350 From Node : counter[21] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.293 Slack : -0.345 From Node : counter[1] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.295 Slack : -0.345 From Node : counter[0] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 Data Delay : 1.295 Slack : -0.336 From Node : counter[20] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.336 From Node : counter[20] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.044 Data Delay : 1.279 Slack : -0.334 From Node : A[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.045 Data Delay : 1.276 Slack : -0.326 From Node : counter[1] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.326 From Node : counter[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.466 Slack : -0.325 From Node : counter[0] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.325 From Node : counter[0] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : 0.153 Data Delay : 1.465 Slack : -0.324 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.047 Data Delay : 1.232 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : 0.178 From Node : A[0] To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.307 Slack : 0.193 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 Slack : 0.195 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.315 Slack : 0.196 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.325 Slack : 0.208 From Node : A[13] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.337 Slack : 0.261 From Node : counter[19] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.579 Slack : 0.264 From Node : counter[19] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.582 Slack : 0.296 From Node : A[12] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 Slack : 0.296 From Node : A[6] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 Slack : 0.296 From Node : A[4] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 Slack : 0.296 From Node : A[2] To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.425 Slack : 0.297 From Node : A[7] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.426 Slack : 0.297 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.417 Slack : 0.297 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.418 Slack : 0.298 From Node : A[10] To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.298 From Node : A[5] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.298 From Node : A[3] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.298 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.418 Slack : 0.298 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.418 Slack : 0.298 From Node : counter[4] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 Slack : 0.298 From Node : counter[3] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 Slack : 0.298 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 Slack : 0.298 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.427 Slack : 0.299 From Node : A[11] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.428 Slack : 0.299 From Node : counter[5] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.420 Slack : 0.300 From Node : counter[18] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.420 Slack : 0.300 From Node : counter[17] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.420 Slack : 0.301 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.421 Slack : 0.303 From Node : counter[10] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.424 Slack : 0.303 From Node : counter[8] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.424 Slack : 0.304 From Node : counter[1] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.425 Slack : 0.305 From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.426 Slack : 0.305 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.426 Slack : 0.306 From Node : counter[11] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.426 Slack : 0.306 From Node : counter[7] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.427 Slack : 0.308 From Node : A[1] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.030 Data Delay : 0.442 Slack : 0.309 From Node : A[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.029 Data Delay : 0.442 Slack : 0.310 From Node : A[9] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.439 Slack : 0.314 From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.632 Slack : 0.317 From Node : counter[18] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.635 Slack : 0.326 From Node : counter[17] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.644 Slack : 0.329 From Node : counter[17] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.647 Slack : 0.359 From Node : A[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.451 Slack : 0.361 From Node : A[8] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.490 Slack : 0.362 From Node : A[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.454 Slack : 0.372 From Node : counter[15] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.492 Slack : 0.372 From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.492 Slack : 0.373 From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.030 Data Delay : 0.507 Slack : 0.376 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.029 Data Delay : 0.509 Slack : 0.378 From Node : counter[16] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.696 Slack : 0.381 From Node : counter[16] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.699 Slack : 0.390 From Node : A[1] To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.519 Slack : 0.395 From Node : A[5] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.487 Slack : 0.404 From Node : A[11] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.496 Slack : 0.405 From Node : A[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.497 Slack : 0.413 From Node : A[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.505 Slack : 0.414 From Node : A[9] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.506 Slack : 0.419 From Node : A[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : -0.012 Data Delay : 0.511 Slack : 0.444 From Node : counter[14] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.762 Slack : 0.445 From Node : A[12] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.574 Slack : 0.445 From Node : A[6] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.574 Slack : 0.445 From Node : A[4] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.574 Slack : 0.445 From Node : A[2] To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.574 Slack : 0.446 From Node : counter[6] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.567 Slack : 0.446 From Node : counter[12] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.566 Slack : 0.447 From Node : counter[20] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.576 Slack : 0.447 From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.568 Slack : 0.447 From Node : A[10] To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.576 Slack : 0.447 From Node : counter[4] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.568 Slack : 0.447 From Node : counter[16] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.567 Slack : 0.447 From Node : counter[14] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.567 Slack : 0.447 From Node : counter[14] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.765 Slack : 0.449 From Node : counter[18] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.569 Slack : 0.452 From Node : counter[8] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.573 Slack : 0.453 From Node : counter[10] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.573 Slack : 0.455 From Node : A[7] To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.584 Slack : 0.456 From Node : A[5] To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.585 Slack : 0.456 From Node : A[3] To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.585 Slack : 0.456 From Node : counter[3] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.577 Slack : 0.456 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.577 Slack : 0.457 From Node : A[11] To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.586 Slack : 0.457 From Node : counter[5] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.578 Slack : 0.458 From Node : counter[17] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.578 Slack : 0.458 From Node : A[7] To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.587 Slack : 0.458 From Node : counter[0] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.579 Slack : 0.459 From Node : A[5] To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.588 Slack : 0.459 From Node : A[3] To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.588 Slack : 0.459 From Node : counter[1] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.580 Slack : 0.459 From Node : counter[3] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.580 Slack : 0.460 From Node : A[11] To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.589 Slack : 0.460 From Node : counter[5] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.581 Slack : 0.461 From Node : counter[17] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.581 Slack : 0.461 From Node : counter[0] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.582 Slack : 0.463 From Node : A[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.029 Data Delay : 0.596 Slack : 0.463 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.584 Slack : 0.464 From Node : counter[11] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.584 Slack : 0.464 From Node : counter[7] To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.585 Slack : 0.464 From Node : counter[15] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.782 Slack : 0.465 From Node : A[11] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.034 Data Delay : 0.603 Slack : 0.467 From Node : A[7] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.034 Data Delay : 0.605 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ Slack : -3.000 Actual Width : 1.000 Required Width : 4.000 Type : Port Rate Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : A[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[10] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[11] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[12] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[13] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[14] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[15] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[16] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[17] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[18] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[19] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[21] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[2] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[3] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[4] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[5] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[6] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[7] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[8] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -0.292 Actual Width : -0.062 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -0.292 Actual Width : -0.062 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -0.289 Actual Width : -0.059 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -0.289 Actual Width : -0.059 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : -0.289 Actual Width : -0.059 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.288 Actual Width : -0.058 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -0.287 Actual Width : -0.057 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 6.337 Fall : 6.302 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 4.384 Fall : 4.484 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 4.664 Fall : 4.798 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 4.639 Fall : 4.768 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 4.160 Fall : 4.243 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 5.127 Fall : 5.334 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 6.337 Fall : 6.302 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 5.006 Fall : 5.199 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 5.916 Fall : 5.799 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 4.024 Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 4.238 Fall : 4.332 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 4.506 Fall : 4.633 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 4.483 Fall : 4.604 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 4.024 Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 4.709 Fall : 4.829 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 5.876 Fall : 5.767 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 4.659 Fall : 4.810 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 5.589 Fall : 5.444 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ --------------------------------------------- ; Fast 1200mV 0C Model Metastability Report ; --------------------------------------------- No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack Setup : -1.812 Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : CLOCK_50 Setup : -1.812 Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : Design-wide TNS Setup : -85.179 Hold : 0.0 Recovery : 0.0 Removal : 0.0 Minimum Pulse Width : -119.48 Clock : CLOCK_50 Setup : -85.179 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : -119.480 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 10.303 Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 7.474 Fall : 7.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 7.915 Fall : 7.923 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 7.907 Fall : 7.878 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 7.123 Fall : 7.073 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 8.891 Fall : 8.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 10.303 Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 8.706 Fall : 8.626 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 9.651 Fall : 9.302 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 Rise : 4.024 Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 Rise : 4.238 Fall : 4.332 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 Rise : 4.506 Fall : 4.633 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 Rise : 4.483 Fall : 4.604 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 Rise : 4.024 Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 Rise : 4.709 Fall : 4.829 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 Rise : 5.876 Fall : 5.767 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 Rise : 4.659 Fall : 4.810 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 Rise : 5.589 Fall : 5.444 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +--------------------------------------------------------------------------------+ Pin : LED[0] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[1] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[2] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[3] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[4] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[5] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[6] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : LED[7] I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a Pin : ~ALTERA_nCEO~ I/O Standard : 2.5 V Near Tline Length : 0 in Near Tline L per Length : 0 H/in Near Tline C per Length : 0 F/in Near Series R : short Near Differential R : - Near Pull-up R : open Near Pull-down R : open Near C : open Far Tline Length : 0 in Far Tline L per Length : 0 H/in Far Tline C per Length : 0 F/in Far Series R : short Far Pull-up R : open Far Pull-down R : open Far C : open Termination Voltage : 0 V Far Differential R : - EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Input Transition Times ; +--------------------------------------------------------------------------------+ Pin : CLOCK_50 I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps Pin : ~ALTERA_ASDO_DATA1~ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps Pin : ~ALTERA_FLASH_nCE_nCSO~ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps Pin : ~ALTERA_DATA0~ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +--------------------------------------------------------------------------------+ Pin : LED[0] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.24e-08 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.115 V Ringback Voltage on Rise at FPGA Pin : 0.31 V Ringback Voltage on Fall at FPGA Pin : 0.241 V 10-90 Rise Time at FPGA Pin : 5.06e-10 s 90-10 Fall Time at FPGA Pin : 4.37e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.24e-08 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.115 V Ringback Voltage on Rise at Far-end : 0.31 V Ringback Voltage on Fall at Far-end : 0.241 V 10-90 Rise Time at Far-end : 5.06e-10 s 90-10 Fall Time at Far-end : 4.37e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[1] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.24e-08 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.115 V Ringback Voltage on Rise at FPGA Pin : 0.31 V Ringback Voltage on Fall at FPGA Pin : 0.241 V 10-90 Rise Time at FPGA Pin : 5.06e-10 s 90-10 Fall Time at FPGA Pin : 4.37e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.24e-08 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.115 V Ringback Voltage on Rise at Far-end : 0.31 V Ringback Voltage on Fall at Far-end : 0.241 V 10-90 Rise Time at Far-end : 5.06e-10 s 90-10 Fall Time at Far-end : 4.37e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[2] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.24e-08 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.115 V Ringback Voltage on Rise at FPGA Pin : 0.31 V Ringback Voltage on Fall at FPGA Pin : 0.241 V 10-90 Rise Time at FPGA Pin : 5.06e-10 s 90-10 Fall Time at FPGA Pin : 4.37e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.24e-08 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.115 V Ringback Voltage on Rise at Far-end : 0.31 V Ringback Voltage on Fall at Far-end : 0.241 V 10-90 Rise Time at Far-end : 5.06e-10 s 90-10 Fall Time at Far-end : 4.37e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[3] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.24e-08 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.115 V Ringback Voltage on Rise at FPGA Pin : 0.31 V Ringback Voltage on Fall at FPGA Pin : 0.241 V 10-90 Rise Time at FPGA Pin : 5.06e-10 s 90-10 Fall Time at FPGA Pin : 4.37e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.24e-08 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.115 V Ringback Voltage on Rise at Far-end : 0.31 V Ringback Voltage on Fall at Far-end : 0.241 V 10-90 Rise Time at Far-end : 5.06e-10 s 90-10 Fall Time at Far-end : 4.37e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[4] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 1.54e-08 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.074 V Ringback Voltage on Rise at FPGA Pin : 0.343 V Ringback Voltage on Fall at FPGA Pin : 0.194 V 10-90 Rise Time at FPGA Pin : 7.35e-10 s 90-10 Fall Time at FPGA Pin : 6.36e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 1.54e-08 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.074 V Ringback Voltage on Rise at Far-end : 0.343 V Ringback Voltage on Fall at Far-end : 0.194 V 10-90 Rise Time at Far-end : 7.35e-10 s 90-10 Fall Time at Far-end : 6.36e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[5] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 1.54e-08 V Voh Max at FPGA Pin : 3.09 V Vol Min at FPGA Pin : -0.0119 V Ringback Voltage on Rise at FPGA Pin : 0.277 V Ringback Voltage on Fall at FPGA Pin : 0.297 V 10-90 Rise Time at FPGA Pin : 4.54e-09 s 90-10 Fall Time at FPGA Pin : 3.32e-09 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 1.54e-08 V Voh Max at Far-end : 3.09 V Vol Min at Far-end : -0.0119 V Ringback Voltage on Rise at Far-end : 0.277 V Ringback Voltage on Fall at Far-end : 0.297 V 10-90 Rise Time at Far-end : 4.54e-09 s 90-10 Fall Time at Far-end : 3.32e-09 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[6] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 1.54e-08 V Voh Max at FPGA Pin : 3.16 V Vol Min at FPGA Pin : -0.11 V Ringback Voltage on Rise at FPGA Pin : 0.302 V Ringback Voltage on Fall at FPGA Pin : 0.22 V 10-90 Rise Time at FPGA Pin : 4.82e-10 s 90-10 Fall Time at FPGA Pin : 4.27e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 1.54e-08 V Voh Max at Far-end : 3.16 V Vol Min at Far-end : -0.11 V Ringback Voltage on Rise at Far-end : 0.302 V Ringback Voltage on Fall at Far-end : 0.22 V 10-90 Rise Time at Far-end : 4.82e-10 s 90-10 Fall Time at Far-end : 4.27e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[7] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 1.54e-08 V Voh Max at FPGA Pin : 3.09 V Vol Min at FPGA Pin : -0.0119 V Ringback Voltage on Rise at FPGA Pin : 0.277 V Ringback Voltage on Fall at FPGA Pin : 0.297 V 10-90 Rise Time at FPGA Pin : 4.54e-09 s 90-10 Fall Time at FPGA Pin : 3.32e-09 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 1.54e-08 V Voh Max at Far-end : 3.09 V Vol Min at Far-end : -0.0119 V Ringback Voltage on Rise at Far-end : 0.277 V Ringback Voltage on Fall at Far-end : 0.297 V 10-90 Rise Time at Far-end : 4.54e-09 s 90-10 Fall Time at Far-end : 3.32e-09 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 8.05e-09 V Voh Max at FPGA Pin : 3.21 V Vol Min at FPGA Pin : -0.181 V Ringback Voltage on Rise at FPGA Pin : 0.16 V Ringback Voltage on Fall at FPGA Pin : 0.253 V 10-90 Rise Time at FPGA Pin : 2.77e-10 s 90-10 Fall Time at FPGA Pin : 2.32e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : Yes Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 8.05e-09 V Voh Max at Far-end : 3.21 V Vol Min at Far-end : -0.181 V Ringback Voltage on Rise at Far-end : 0.16 V Ringback Voltage on Fall at Far-end : 0.253 V 10-90 Rise Time at Far-end : 2.77e-10 s 90-10 Fall Time at Far-end : 2.32e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : Yes Pin : ~ALTERA_nCEO~ I/O Standard : 2.5 V Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 2.32 V Steady State Vol at FPGA Pin : 5.61e-09 V Voh Max at FPGA Pin : 2.38 V Vol Min at FPGA Pin : -0.00274 V Ringback Voltage on Rise at FPGA Pin : 0.141 V Ringback Voltage on Fall at FPGA Pin : 0.006 V 10-90 Rise Time at FPGA Pin : 4.7e-10 s 90-10 Fall Time at FPGA Pin : 6.02e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : Yes Steady State Voh at Far-end : 2.32 V Steady State Vol at Far-end : 5.61e-09 V Voh Max at Far-end : 2.38 V Vol Min at Far-end : -0.00274 V Ringback Voltage on Rise at Far-end : 0.141 V Ringback Voltage on Fall at Far-end : 0.006 V 10-90 Rise Time at Far-end : 4.7e-10 s 90-10 Fall Time at Far-end : 6.02e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +--------------------------------------------------------------------------------+ Pin : LED[0] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.99e-06 V Voh Max at FPGA Pin : 3.11 V Vol Min at FPGA Pin : -0.0717 V Ringback Voltage on Rise at FPGA Pin : 0.209 V Ringback Voltage on Fall at FPGA Pin : 0.168 V 10-90 Rise Time at FPGA Pin : 6.66e-10 s 90-10 Fall Time at FPGA Pin : 6.19e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.99e-06 V Voh Max at Far-end : 3.11 V Vol Min at Far-end : -0.0717 V Ringback Voltage on Rise at Far-end : 0.209 V Ringback Voltage on Fall at Far-end : 0.168 V 10-90 Rise Time at Far-end : 6.66e-10 s 90-10 Fall Time at Far-end : 6.19e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[1] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.99e-06 V Voh Max at FPGA Pin : 3.11 V Vol Min at FPGA Pin : -0.0717 V Ringback Voltage on Rise at FPGA Pin : 0.209 V Ringback Voltage on Fall at FPGA Pin : 0.168 V 10-90 Rise Time at FPGA Pin : 6.66e-10 s 90-10 Fall Time at FPGA Pin : 6.19e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.99e-06 V Voh Max at Far-end : 3.11 V Vol Min at Far-end : -0.0717 V Ringback Voltage on Rise at Far-end : 0.209 V Ringback Voltage on Fall at Far-end : 0.168 V 10-90 Rise Time at Far-end : 6.66e-10 s 90-10 Fall Time at Far-end : 6.19e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[2] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.99e-06 V Voh Max at FPGA Pin : 3.11 V Vol Min at FPGA Pin : -0.0717 V Ringback Voltage on Rise at FPGA Pin : 0.209 V Ringback Voltage on Fall at FPGA Pin : 0.168 V 10-90 Rise Time at FPGA Pin : 6.66e-10 s 90-10 Fall Time at FPGA Pin : 6.19e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.99e-06 V Voh Max at Far-end : 3.11 V Vol Min at Far-end : -0.0717 V Ringback Voltage on Rise at Far-end : 0.209 V Ringback Voltage on Fall at Far-end : 0.168 V 10-90 Rise Time at Far-end : 6.66e-10 s 90-10 Fall Time at Far-end : 6.19e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[3] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2.99e-06 V Voh Max at FPGA Pin : 3.11 V Vol Min at FPGA Pin : -0.0717 V Ringback Voltage on Rise at FPGA Pin : 0.209 V Ringback Voltage on Fall at FPGA Pin : 0.168 V 10-90 Rise Time at FPGA Pin : 6.66e-10 s 90-10 Fall Time at FPGA Pin : 6.19e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2.99e-06 V Voh Max at Far-end : 3.11 V Vol Min at Far-end : -0.0717 V Ringback Voltage on Rise at Far-end : 0.209 V Ringback Voltage on Fall at Far-end : 0.168 V 10-90 Rise Time at Far-end : 6.66e-10 s 90-10 Fall Time at Far-end : 6.19e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[4] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2e-06 V Voh Max at FPGA Pin : 3.12 V Vol Min at FPGA Pin : -0.0547 V Ringback Voltage on Rise at FPGA Pin : 0.276 V Ringback Voltage on Fall at FPGA Pin : 0.181 V 10-90 Rise Time at FPGA Pin : 9.17e-10 s 90-10 Fall Time at FPGA Pin : 8.31e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2e-06 V Voh Max at Far-end : 3.12 V Vol Min at Far-end : -0.0547 V Ringback Voltage on Rise at Far-end : 0.276 V Ringback Voltage on Fall at Far-end : 0.181 V 10-90 Rise Time at Far-end : 9.17e-10 s 90-10 Fall Time at Far-end : 8.31e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[5] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2e-06 V Voh Max at FPGA Pin : 3.08 V Vol Min at FPGA Pin : -0.00666 V Ringback Voltage on Rise at FPGA Pin : 0.298 V Ringback Voltage on Fall at FPGA Pin : 0.277 V 10-90 Rise Time at FPGA Pin : 5.29e-09 s 90-10 Fall Time at FPGA Pin : 4.2e-09 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2e-06 V Voh Max at Far-end : 3.08 V Vol Min at Far-end : -0.00666 V Ringback Voltage on Rise at Far-end : 0.298 V Ringback Voltage on Fall at Far-end : 0.277 V 10-90 Rise Time at Far-end : 5.29e-09 s 90-10 Fall Time at Far-end : 4.2e-09 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : LED[6] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2e-06 V Voh Max at FPGA Pin : 3.13 V Vol Min at FPGA Pin : -0.0781 V Ringback Voltage on Rise at FPGA Pin : 0.202 V Ringback Voltage on Fall at FPGA Pin : 0.359 V 10-90 Rise Time at FPGA Pin : 6.54e-10 s 90-10 Fall Time at FPGA Pin : 5e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2e-06 V Voh Max at Far-end : 3.13 V Vol Min at Far-end : -0.0781 V Ringback Voltage on Rise at Far-end : 0.202 V Ringback Voltage on Fall at Far-end : 0.359 V 10-90 Rise Time at Far-end : 6.54e-10 s 90-10 Fall Time at Far-end : 5e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[7] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 2e-06 V Voh Max at FPGA Pin : 3.08 V Vol Min at FPGA Pin : -0.00666 V Ringback Voltage on Rise at FPGA Pin : 0.298 V Ringback Voltage on Fall at FPGA Pin : 0.277 V 10-90 Rise Time at FPGA Pin : 5.29e-09 s 90-10 Fall Time at FPGA Pin : 4.2e-09 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 2e-06 V Voh Max at Far-end : 3.08 V Vol Min at Far-end : -0.00666 V Ringback Voltage on Rise at Far-end : 0.298 V Ringback Voltage on Fall at Far-end : 0.277 V 10-90 Rise Time at Far-end : 5.29e-09 s 90-10 Fall Time at Far-end : 4.2e-09 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.08 V Steady State Vol at FPGA Pin : 1.02e-06 V Voh Max at FPGA Pin : 3.14 V Vol Min at FPGA Pin : -0.124 V Ringback Voltage on Rise at FPGA Pin : 0.134 V Ringback Voltage on Fall at FPGA Pin : 0.323 V 10-90 Rise Time at FPGA Pin : 3.02e-10 s 90-10 Fall Time at FPGA Pin : 2.85e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.08 V Steady State Vol at Far-end : 1.02e-06 V Voh Max at Far-end : 3.14 V Vol Min at Far-end : -0.124 V Ringback Voltage on Rise at Far-end : 0.134 V Ringback Voltage on Fall at Far-end : 0.323 V 10-90 Rise Time at Far-end : 3.02e-10 s 90-10 Fall Time at Far-end : 2.85e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No Pin : ~ALTERA_nCEO~ I/O Standard : 2.5 V Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 2.32 V Steady State Vol at FPGA Pin : 9.45e-07 V Voh Max at FPGA Pin : 2.35 V Vol Min at FPGA Pin : -0.00643 V Ringback Voltage on Rise at FPGA Pin : 0.081 V Ringback Voltage on Fall at FPGA Pin : 0.031 V 10-90 Rise Time at FPGA Pin : 5.31e-10 s 90-10 Fall Time at FPGA Pin : 7.59e-10 s Monotonic Rise at FPGA Pin : Yes Monotonic Fall at FPGA Pin : Yes Steady State Voh at Far-end : 2.32 V Steady State Vol at Far-end : 9.45e-07 V Voh Max at Far-end : 2.35 V Vol Min at Far-end : -0.00643 V Ringback Voltage on Rise at Far-end : 0.081 V Ringback Voltage on Fall at Far-end : 0.031 V 10-90 Rise Time at Far-end : 5.31e-10 s 90-10 Fall Time at Far-end : 7.59e-10 s Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +--------------------------------------------------------------------------------+ Pin : LED[0] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.85e-07 V Voh Max at FPGA Pin : 3.57 V Vol Min at FPGA Pin : -0.141 V Ringback Voltage on Rise at FPGA Pin : 0.301 V Ringback Voltage on Fall at FPGA Pin : 0.239 V 10-90 Rise Time at FPGA Pin : 4.61e-10 s 90-10 Fall Time at FPGA Pin : 4.2e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.85e-07 V Voh Max at Far-end : 3.57 V Vol Min at Far-end : -0.141 V Ringback Voltage on Rise at Far-end : 0.301 V Ringback Voltage on Fall at Far-end : 0.239 V 10-90 Rise Time at Far-end : 4.61e-10 s 90-10 Fall Time at Far-end : 4.2e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[1] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.85e-07 V Voh Max at FPGA Pin : 3.57 V Vol Min at FPGA Pin : -0.141 V Ringback Voltage on Rise at FPGA Pin : 0.301 V Ringback Voltage on Fall at FPGA Pin : 0.239 V 10-90 Rise Time at FPGA Pin : 4.61e-10 s 90-10 Fall Time at FPGA Pin : 4.2e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.85e-07 V Voh Max at Far-end : 3.57 V Vol Min at Far-end : -0.141 V Ringback Voltage on Rise at Far-end : 0.301 V Ringback Voltage on Fall at Far-end : 0.239 V 10-90 Rise Time at Far-end : 4.61e-10 s 90-10 Fall Time at Far-end : 4.2e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[2] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.85e-07 V Voh Max at FPGA Pin : 3.57 V Vol Min at FPGA Pin : -0.141 V Ringback Voltage on Rise at FPGA Pin : 0.301 V Ringback Voltage on Fall at FPGA Pin : 0.239 V 10-90 Rise Time at FPGA Pin : 4.61e-10 s 90-10 Fall Time at FPGA Pin : 4.2e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.85e-07 V Voh Max at Far-end : 3.57 V Vol Min at Far-end : -0.141 V Ringback Voltage on Rise at Far-end : 0.301 V Ringback Voltage on Fall at Far-end : 0.239 V 10-90 Rise Time at Far-end : 4.61e-10 s 90-10 Fall Time at Far-end : 4.2e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[3] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.85e-07 V Voh Max at FPGA Pin : 3.57 V Vol Min at FPGA Pin : -0.141 V Ringback Voltage on Rise at FPGA Pin : 0.301 V Ringback Voltage on Fall at FPGA Pin : 0.239 V 10-90 Rise Time at FPGA Pin : 4.61e-10 s 90-10 Fall Time at FPGA Pin : 4.2e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.85e-07 V Voh Max at Far-end : 3.57 V Vol Min at Far-end : -0.141 V Ringback Voltage on Rise at Far-end : 0.301 V Ringback Voltage on Fall at Far-end : 0.239 V 10-90 Rise Time at Far-end : 4.61e-10 s 90-10 Fall Time at Far-end : 4.2e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[4] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.25e-07 V Voh Max at FPGA Pin : 3.57 V Vol Min at FPGA Pin : -0.0855 V Ringback Voltage on Rise at FPGA Pin : 0.315 V Ringback Voltage on Fall at FPGA Pin : 0.175 V 10-90 Rise Time at FPGA Pin : 6.79e-10 s 90-10 Fall Time at FPGA Pin : 6.15e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.25e-07 V Voh Max at Far-end : 3.57 V Vol Min at Far-end : -0.0855 V Ringback Voltage on Rise at Far-end : 0.315 V Ringback Voltage on Fall at Far-end : 0.175 V 10-90 Rise Time at Far-end : 6.79e-10 s 90-10 Fall Time at Far-end : 6.15e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[5] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.25e-07 V Voh Max at FPGA Pin : 3.48 V Vol Min at FPGA Pin : -0.0162 V Ringback Voltage on Rise at FPGA Pin : 0.354 V Ringback Voltage on Fall at FPGA Pin : 0.317 V 10-90 Rise Time at FPGA Pin : 3.88e-09 s 90-10 Fall Time at FPGA Pin : 3.06e-09 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.25e-07 V Voh Max at Far-end : 3.48 V Vol Min at Far-end : -0.0162 V Ringback Voltage on Rise at Far-end : 0.354 V Ringback Voltage on Fall at Far-end : 0.317 V 10-90 Rise Time at Far-end : 3.88e-09 s 90-10 Fall Time at Far-end : 3.06e-09 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[6] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.25e-07 V Voh Max at FPGA Pin : 3.6 V Vol Min at FPGA Pin : -0.127 V Ringback Voltage on Rise at FPGA Pin : 0.302 V Ringback Voltage on Fall at FPGA Pin : 0.21 V 10-90 Rise Time at FPGA Pin : 4.55e-10 s 90-10 Fall Time at FPGA Pin : 4.11e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.25e-07 V Voh Max at Far-end : 3.6 V Vol Min at Far-end : -0.127 V Ringback Voltage on Rise at Far-end : 0.302 V Ringback Voltage on Fall at Far-end : 0.21 V 10-90 Rise Time at Far-end : 4.55e-10 s 90-10 Fall Time at Far-end : 4.11e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : LED[7] I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 1.25e-07 V Voh Max at FPGA Pin : 3.48 V Vol Min at FPGA Pin : -0.0162 V Ringback Voltage on Rise at FPGA Pin : 0.354 V Ringback Voltage on Fall at FPGA Pin : 0.317 V 10-90 Rise Time at FPGA Pin : 3.88e-09 s 90-10 Fall Time at FPGA Pin : 3.06e-09 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : No Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 1.25e-07 V Voh Max at Far-end : 3.48 V Vol Min at Far-end : -0.0162 V Ringback Voltage on Rise at Far-end : 0.354 V Ringback Voltage on Fall at Far-end : 0.317 V 10-90 Rise Time at Far-end : 3.88e-09 s 90-10 Fall Time at Far-end : 3.06e-09 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 3.46 V Steady State Vol at FPGA Pin : 6.54e-08 V Voh Max at FPGA Pin : 3.66 V Vol Min at FPGA Pin : -0.258 V Ringback Voltage on Rise at FPGA Pin : 0.41 V Ringback Voltage on Fall at FPGA Pin : 0.318 V 10-90 Rise Time at FPGA Pin : 1.57e-10 s 90-10 Fall Time at FPGA Pin : 2.15e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : Yes Steady State Voh at Far-end : 3.46 V Steady State Vol at Far-end : 6.54e-08 V Voh Max at Far-end : 3.66 V Vol Min at Far-end : -0.258 V Ringback Voltage on Rise at Far-end : 0.41 V Ringback Voltage on Fall at Far-end : 0.318 V 10-90 Rise Time at Far-end : 1.57e-10 s 90-10 Fall Time at Far-end : 2.15e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : Yes Pin : ~ALTERA_nCEO~ I/O Standard : 2.5 V Board Delay on Rise : 0 s Board Delay on Fall : 0 s Steady State Voh at FPGA Pin : 2.62 V Steady State Vol at FPGA Pin : 3.54e-08 V Voh Max at FPGA Pin : 2.7 V Vol Min at FPGA Pin : -0.00943 V Ringback Voltage on Rise at FPGA Pin : 0.276 V Ringback Voltage on Fall at FPGA Pin : 0.035 V 10-90 Rise Time at FPGA Pin : 3.19e-10 s 90-10 Fall Time at FPGA Pin : 4.99e-10 s Monotonic Rise at FPGA Pin : No Monotonic Fall at FPGA Pin : Yes Steady State Voh at Far-end : 2.62 V Steady State Vol at Far-end : 3.54e-08 V Voh Max at Far-end : 2.7 V Vol Min at Far-end : -0.00943 V Ringback Voltage on Rise at Far-end : 0.276 V Ringback Voltage on Fall at Far-end : 0.035 V 10-90 Rise Time at Far-end : 3.19e-10 s 90-10 Fall Time at Far-end : 4.99e-10 s Monotonic Rise at Far-end : No Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Setup Transfers ; +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 RR Paths : 864 FR Paths : 0 RF Paths : 0 FF Paths : 0 +--------------------------------------------------------------------------------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +--------------------------------------------------------------------------------+ ; Hold Transfers ; +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 RR Paths : 864 FR Paths : 0 RF Paths : 0 FF Paths : 0 +--------------------------------------------------------------------------------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +--------------------------------------------------------------------------------+ ; Unconstrained Paths ; +--------------------------------------------------------------------------------+ Property : Illegal Clocks Setup : 0 Hold : 0 Property : Unconstrained Clocks Setup : 0 Hold : 0 Property : Unconstrained Input Ports Setup : 0 Hold : 0 Property : Unconstrained Input Port Paths Setup : 0 Hold : 0 Property : Unconstrained Output Ports Setup : 8 Hold : 8 Property : Unconstrained Output Port Paths Setup : 16 Hold : 16 +--------------------------------------------------------------------------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Processing started: Wed Mar 30 13:47:20 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled Info (21077): Core supply voltage is 1.2V Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1.812 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.812 -85.179 CLOCK_50 Info (332146): Worst-case hold slack is 0.343 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.343 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -119.480 CLOCK_50 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1.531 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.531 -69.352 CLOCK_50 Info (332146): Worst-case hold slack is 0.299 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.299 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -119.478 CLOCK_50 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -0.444 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.444 -17.149 CLOCK_50 Info (332146): Worst-case hold slack is 0.178 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.178 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -99.404 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings Info: Peak virtual memory: 419 megabytes Info: Processing ended: Wed Mar 30 13:47:22 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02