|spectrum CLOCK_50 => CLOCK_50.IN1 LED[0] <= rom0:rom.q LED[1] <= rom0:rom.q LED[2] <= rom0:rom.q LED[3] <= rom0:rom.q LED[4] <= rom0:rom.q LED[5] <= rom0:rom.q LED[6] <= rom0:rom.q LED[7] <= rom0:rom.q |spectrum|rom0:rom address[0] => address[0].IN1 address[1] => address[1].IN1 address[2] => address[2].IN1 address[3] => address[3].IN1 address[4] => address[4].IN1 address[5] => address[5].IN1 address[6] => address[6].IN1 address[7] => address[7].IN1 address[8] => address[8].IN1 address[9] => address[9].IN1 address[10] => address[10].IN1 address[11] => address[11].IN1 address[12] => address[12].IN1 address[13] => address[13].IN1 clock => clock.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a q[2] <= altsyncram:altsyncram_component.q_a q[3] <= altsyncram:altsyncram_component.q_a q[4] <= altsyncram:altsyncram_component.q_a q[5] <= altsyncram:altsyncram_component.q_a q[6] <= altsyncram:altsyncram_component.q_a q[7] <= altsyncram:altsyncram_component.q_a |spectrum|rom0:rom|altsyncram:altsyncram_component wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => ~NO_FANOUT~ data_a[1] => ~NO_FANOUT~ data_a[2] => ~NO_FANOUT~ data_a[3] => ~NO_FANOUT~ data_a[4] => ~NO_FANOUT~ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_qh91:auto_generated.address_a[0] address_a[1] => altsyncram_qh91:auto_generated.address_a[1] address_a[2] => altsyncram_qh91:auto_generated.address_a[2] address_a[3] => altsyncram_qh91:auto_generated.address_a[3] address_a[4] => altsyncram_qh91:auto_generated.address_a[4] address_a[5] => altsyncram_qh91:auto_generated.address_a[5] address_a[6] => altsyncram_qh91:auto_generated.address_a[6] address_a[7] => altsyncram_qh91:auto_generated.address_a[7] address_a[8] => altsyncram_qh91:auto_generated.address_a[8] address_a[9] => altsyncram_qh91:auto_generated.address_a[9] address_a[10] => altsyncram_qh91:auto_generated.address_a[10] address_a[11] => altsyncram_qh91:auto_generated.address_a[11] address_a[12] => altsyncram_qh91:auto_generated.address_a[12] address_a[13] => altsyncram_qh91:auto_generated.address_a[13] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_qh91:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_qh91:auto_generated.q_a[0] q_a[1] <= altsyncram_qh91:auto_generated.q_a[1] q_a[2] <= altsyncram_qh91:auto_generated.q_a[2] q_a[3] <= altsyncram_qh91:auto_generated.q_a[3] q_a[4] <= altsyncram_qh91:auto_generated.q_a[4] q_a[5] <= altsyncram_qh91:auto_generated.q_a[5] q_a[6] <= altsyncram_qh91:auto_generated.q_a[6] q_a[7] <= altsyncram_qh91:auto_generated.q_a[7] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_a[8] => ram_block1a15.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[9] => ram_block1a8.PORTAADDR9 address_a[9] => ram_block1a9.PORTAADDR9 address_a[9] => ram_block1a10.PORTAADDR9 address_a[9] => ram_block1a11.PORTAADDR9 address_a[9] => ram_block1a12.PORTAADDR9 address_a[9] => ram_block1a13.PORTAADDR9 address_a[9] => ram_block1a14.PORTAADDR9 address_a[9] => ram_block1a15.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 address_a[10] => ram_block1a8.PORTAADDR10 address_a[10] => ram_block1a9.PORTAADDR10 address_a[10] => ram_block1a10.PORTAADDR10 address_a[10] => ram_block1a11.PORTAADDR10 address_a[10] => ram_block1a12.PORTAADDR10 address_a[10] => ram_block1a13.PORTAADDR10 address_a[10] => ram_block1a14.PORTAADDR10 address_a[10] => ram_block1a15.PORTAADDR10 address_a[11] => ram_block1a0.PORTAADDR11 address_a[11] => ram_block1a1.PORTAADDR11 address_a[11] => ram_block1a2.PORTAADDR11 address_a[11] => ram_block1a3.PORTAADDR11 address_a[11] => ram_block1a4.PORTAADDR11 address_a[11] => ram_block1a5.PORTAADDR11 address_a[11] => ram_block1a6.PORTAADDR11 address_a[11] => ram_block1a7.PORTAADDR11 address_a[11] => ram_block1a8.PORTAADDR11 address_a[11] => ram_block1a9.PORTAADDR11 address_a[11] => ram_block1a10.PORTAADDR11 address_a[11] => ram_block1a11.PORTAADDR11 address_a[11] => ram_block1a12.PORTAADDR11 address_a[11] => ram_block1a13.PORTAADDR11 address_a[11] => ram_block1a14.PORTAADDR11 address_a[11] => ram_block1a15.PORTAADDR11 address_a[12] => ram_block1a0.PORTAADDR12 address_a[12] => ram_block1a1.PORTAADDR12 address_a[12] => ram_block1a2.PORTAADDR12 address_a[12] => ram_block1a3.PORTAADDR12 address_a[12] => ram_block1a4.PORTAADDR12 address_a[12] => ram_block1a5.PORTAADDR12 address_a[12] => ram_block1a6.PORTAADDR12 address_a[12] => ram_block1a7.PORTAADDR12 address_a[12] => ram_block1a8.PORTAADDR12 address_a[12] => ram_block1a9.PORTAADDR12 address_a[12] => ram_block1a10.PORTAADDR12 address_a[12] => ram_block1a11.PORTAADDR12 address_a[12] => ram_block1a12.PORTAADDR12 address_a[12] => ram_block1a13.PORTAADDR12 address_a[12] => ram_block1a14.PORTAADDR12 address_a[12] => ram_block1a15.PORTAADDR12 address_a[13] => address_reg_a[0].DATAIN address_a[13] => decode_c8a:rden_decode.data[0] clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => address_reg_a[0].CLK clock0 => out_address_reg_a[0].CLK q_a[0] <= mux_3nb:mux2.result[0] q_a[1] <= mux_3nb:mux2.result[1] q_a[2] <= mux_3nb:mux2.result[2] q_a[3] <= mux_3nb:mux2.result[3] q_a[4] <= mux_3nb:mux2.result[4] q_a[5] <= mux_3nb:mux2.result[5] q_a[6] <= mux_3nb:mux2.result[6] q_a[7] <= mux_3nb:mux2.result[7] |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 data[0] => result_node[0].IN1 data[1] => result_node[1].IN1 data[2] => result_node[2].IN1 data[3] => result_node[3].IN1 data[4] => result_node[4].IN1 data[5] => result_node[5].IN1 data[6] => result_node[6].IN1 data[7] => result_node[7].IN1 data[8] => result_node[0].IN1 data[9] => result_node[1].IN1 data[10] => result_node[2].IN1 data[11] => result_node[3].IN1 data[12] => result_node[4].IN1 data[13] => result_node[5].IN1 data[14] => result_node[6].IN1 data[15] => result_node[7].IN1 result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE sel[0] => result_node[7].IN0 sel[0] => _.IN0 sel[0] => result_node[6].IN0 sel[0] => _.IN0 sel[0] => result_node[5].IN0 sel[0] => _.IN0 sel[0] => result_node[4].IN0 sel[0] => _.IN0 sel[0] => result_node[3].IN0 sel[0] => _.IN0 sel[0] => result_node[2].IN0 sel[0] => _.IN0 sel[0] => result_node[1].IN0 sel[0] => _.IN0 sel[0] => result_node[0].IN0 sel[0] => _.IN0