// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

// DATE "03/30/2022 14:56:19"

// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module spectrum (
	CLOCK_50,
	LED,
	GPIO_0);
input 	CLOCK_50;
output 	[7:0] LED;
output 	[33:0] GPIO_0;

// Design Ports Information
// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[0]	=>  Location: PIN_D3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[1]	=>  Location: PIN_C3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[2]	=>  Location: PIN_A2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[3]	=>  Location: PIN_A3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[4]	=>  Location: PIN_B3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[5]	=>  Location: PIN_B4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[6]	=>  Location: PIN_A4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[7]	=>  Location: PIN_B5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[8]	=>  Location: PIN_A5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[9]	=>  Location: PIN_D5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[10]	=>  Location: PIN_B6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[11]	=>  Location: PIN_A6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[12]	=>  Location: PIN_B7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[13]	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[14]	=>  Location: PIN_A7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[15]	=>  Location: PIN_C6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[16]	=>  Location: PIN_C8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[17]	=>  Location: PIN_E6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[18]	=>  Location: PIN_E7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[19]	=>  Location: PIN_D8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[20]	=>  Location: PIN_E8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[21]	=>  Location: PIN_F8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[22]	=>  Location: PIN_F9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[23]	=>  Location: PIN_E9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[24]	=>  Location: PIN_C9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[25]	=>  Location: PIN_D9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[26]	=>  Location: PIN_E11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[27]	=>  Location: PIN_E10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[28]	=>  Location: PIN_C11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[29]	=>  Location: PIN_B11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[30]	=>  Location: PIN_A12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[31]	=>  Location: PIN_D11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[32]	=>  Location: PIN_D12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0[33]	=>  Location: PIN_B12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("spectrum_v.sdo");
// synopsys translate_on

wire \LED[0]~output_o ;
wire \LED[1]~output_o ;
wire \LED[2]~output_o ;
wire \LED[3]~output_o ;
wire \LED[4]~output_o ;
wire \LED[5]~output_o ;
wire \LED[6]~output_o ;
wire \LED[7]~output_o ;
wire \GPIO_0[0]~output_o ;
wire \GPIO_0[1]~output_o ;
wire \GPIO_0[2]~output_o ;
wire \GPIO_0[3]~output_o ;
wire \GPIO_0[4]~output_o ;
wire \GPIO_0[5]~output_o ;
wire \GPIO_0[6]~output_o ;
wire \GPIO_0[7]~output_o ;
wire \GPIO_0[8]~output_o ;
wire \GPIO_0[9]~output_o ;
wire \GPIO_0[10]~output_o ;
wire \GPIO_0[11]~output_o ;
wire \GPIO_0[12]~output_o ;
wire \GPIO_0[13]~output_o ;
wire \GPIO_0[14]~output_o ;
wire \GPIO_0[15]~output_o ;
wire \GPIO_0[16]~output_o ;
wire \GPIO_0[17]~output_o ;
wire \GPIO_0[18]~output_o ;
wire \GPIO_0[19]~output_o ;
wire \GPIO_0[20]~output_o ;
wire \GPIO_0[21]~output_o ;
wire \GPIO_0[22]~output_o ;
wire \GPIO_0[23]~output_o ;
wire \GPIO_0[24]~output_o ;
wire \GPIO_0[25]~output_o ;
wire \GPIO_0[26]~output_o ;
wire \GPIO_0[27]~output_o ;
wire \GPIO_0[28]~output_o ;
wire \GPIO_0[29]~output_o ;
wire \GPIO_0[30]~output_o ;
wire \GPIO_0[31]~output_o ;
wire \GPIO_0[32]~output_o ;
wire \GPIO_0[33]~output_o ;
wire \CLOCK_50~input_o ;
wire \CLOCK_50~inputclkctrl_outclk ;
wire \counter[0]~63_combout ;
wire \counter[1]~21_combout ;
wire \counter[1]~22 ;
wire \counter[2]~23_combout ;
wire \counter[2]~24 ;
wire \counter[3]~25_combout ;
wire \counter[3]~26 ;
wire \counter[4]~27_combout ;
wire \counter[4]~28 ;
wire \counter[5]~29_combout ;
wire \counter[5]~30 ;
wire \counter[6]~31_combout ;
wire \counter[6]~32 ;
wire \counter[7]~33_combout ;
wire \counter[7]~34 ;
wire \counter[8]~35_combout ;
wire \counter[8]~36 ;
wire \counter[9]~37_combout ;
wire \counter[9]~38 ;
wire \counter[10]~39_combout ;
wire \counter[10]~40 ;
wire \counter[11]~41_combout ;
wire \counter[11]~42 ;
wire \counter[12]~43_combout ;
wire \counter[12]~44 ;
wire \counter[13]~45_combout ;
wire \counter[13]~46 ;
wire \counter[14]~47_combout ;
wire \counter[14]~48 ;
wire \counter[15]~49_combout ;
wire \counter[15]~50 ;
wire \counter[16]~51_combout ;
wire \counter[16]~52 ;
wire \counter[17]~53_combout ;
wire \counter[17]~54 ;
wire \counter[18]~55_combout ;
wire \counter[18]~56 ;
wire \counter[19]~57_combout ;
wire \counter[19]~58 ;
wire \counter[20]~59_combout ;
wire \counter[20]~60 ;
wire \counter[21]~61_combout ;
wire \Equal0~7_combout ;
wire \Equal0~5_combout ;
wire \Equal0~0_combout ;
wire \Equal0~1_combout ;
wire \Equal0~2_combout ;
wire \Equal0~3_combout ;
wire \Equal0~4_combout ;
wire \A[0]~40_combout ;
wire \A[1]~14_combout ;
wire \Equal0~6_combout ;
wire \A[1]~15 ;
wire \A[2]~16_combout ;
wire \A[2]~17 ;
wire \A[3]~18_combout ;
wire \A[3]~19 ;
wire \A[4]~20_combout ;
wire \A[4]~21 ;
wire \A[5]~22_combout ;
wire \A[5]~23 ;
wire \A[6]~24_combout ;
wire \A[6]~25 ;
wire \A[7]~26_combout ;
wire \A[7]~27 ;
wire \A[8]~28_combout ;
wire \A[8]~29 ;
wire \A[9]~30_combout ;
wire \A[9]~31 ;
wire \A[10]~32_combout ;
wire \A[10]~33 ;
wire \A[11]~34_combout ;
wire \A[11]~35 ;
wire \A[12]~36_combout ;
wire \A[12]~37 ;
wire \A[13]~38_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ;
wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ;
wire \~GND~combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
wire \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ;
wire \A[13]~39 ;
wire \A[14]~41_combout ;
wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ;
wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
wire \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ;
wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ;
wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ;
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ;
wire \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ;
wire [21:0] counter;
wire [15:0] A;
wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ;
wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ;
wire [2:0] \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w ;

wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ;

assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];

assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout  = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout  = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];

assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0  = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];

assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout  = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0];

// Location: IOOBUF_X38_Y34_N16
cycloneive_io_obuf \LED[0]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[0]~output .bus_hold = "false";
defparam \LED[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N2
cycloneive_io_obuf \LED[1]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[1]~output .bus_hold = "false";
defparam \LED[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N9
cycloneive_io_obuf \LED[2]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[2]~output .bus_hold = "false";
defparam \LED[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y34_N2
cycloneive_io_obuf \LED[3]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[3]~output .bus_hold = "false";
defparam \LED[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y25_N9
cycloneive_io_obuf \LED[4]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[4]~output .bus_hold = "false";
defparam \LED[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y26_N16
cycloneive_io_obuf \LED[5]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[5]~output .bus_hold = "false";
defparam \LED[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y28_N9
cycloneive_io_obuf \LED[6]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[6]~output .bus_hold = "false";
defparam \LED[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y10_N23
cycloneive_io_obuf \LED[7]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\LED[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \LED[7]~output .bus_hold = "false";
defparam \LED[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y34_N9
cycloneive_io_obuf \GPIO_0[0]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[0]~output .bus_hold = "false";
defparam \GPIO_0[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y34_N2
cycloneive_io_obuf \GPIO_0[1]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[1]~output .bus_hold = "false";
defparam \GPIO_0[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N9
cycloneive_io_obuf \GPIO_0[2]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[2]~output .bus_hold = "false";
defparam \GPIO_0[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N16
cycloneive_io_obuf \GPIO_0[3]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[3]~output .bus_hold = "false";
defparam \GPIO_0[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X3_Y34_N2
cycloneive_io_obuf \GPIO_0[4]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[4]~output .bus_hold = "false";
defparam \GPIO_0[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N2
cycloneive_io_obuf \GPIO_0[5]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[5]~output .bus_hold = "false";
defparam \GPIO_0[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y34_N23
cycloneive_io_obuf \GPIO_0[6]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[6]~output .bus_hold = "false";
defparam \GPIO_0[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y34_N2
cycloneive_io_obuf \GPIO_0[7]~output (
	.i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[7]~output .bus_hold = "false";
defparam \GPIO_0[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y34_N23
cycloneive_io_obuf \GPIO_0[8]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[8]~output .bus_hold = "false";
defparam \GPIO_0[8]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y34_N16
cycloneive_io_obuf \GPIO_0[9]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[9]~output .bus_hold = "false";
defparam \GPIO_0[9]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N9
cycloneive_io_obuf \GPIO_0[10]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[10]~output .bus_hold = "false";
defparam \GPIO_0[10]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N2
cycloneive_io_obuf \GPIO_0[11]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[11]~output .bus_hold = "false";
defparam \GPIO_0[11]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X18_Y34_N2
cycloneive_io_obuf \GPIO_0[12]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[12]~output .bus_hold = "false";
defparam \GPIO_0[12]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y34_N9
cycloneive_io_obuf \GPIO_0[13]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[13]~output .bus_hold = "false";
defparam \GPIO_0[13]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N23
cycloneive_io_obuf \GPIO_0[14]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[14]~output .bus_hold = "false";
defparam \GPIO_0[14]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X18_Y34_N23
cycloneive_io_obuf \GPIO_0[15]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[15]~output .bus_hold = "false";
defparam \GPIO_0[15]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y34_N16
cycloneive_io_obuf \GPIO_0[16]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[16]~output .bus_hold = "false";
defparam \GPIO_0[16]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y34_N16
cycloneive_io_obuf \GPIO_0[17]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[17]~output .bus_hold = "false";
defparam \GPIO_0[17]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N16
cycloneive_io_obuf \GPIO_0[18]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[18]~output .bus_hold = "false";
defparam \GPIO_0[18]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y34_N23
cycloneive_io_obuf \GPIO_0[19]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[19]~output .bus_hold = "false";
defparam \GPIO_0[19]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N9
cycloneive_io_obuf \GPIO_0[20]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[20]~output .bus_hold = "false";
defparam \GPIO_0[20]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N16
cycloneive_io_obuf \GPIO_0[21]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[21]~output .bus_hold = "false";
defparam \GPIO_0[21]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X34_Y34_N2
cycloneive_io_obuf \GPIO_0[22]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[22]~output .bus_hold = "false";
defparam \GPIO_0[22]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X29_Y34_N16
cycloneive_io_obuf \GPIO_0[23]~output (
	.i(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[23]~output .bus_hold = "false";
defparam \GPIO_0[23]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X31_Y34_N2
cycloneive_io_obuf \GPIO_0[24]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[24]~output .bus_hold = "false";
defparam \GPIO_0[24]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X31_Y34_N9
cycloneive_io_obuf \GPIO_0[25]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[25]~output .bus_hold = "false";
defparam \GPIO_0[25]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X45_Y34_N9
cycloneive_io_obuf \GPIO_0[26]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[26]~output .bus_hold = "false";
defparam \GPIO_0[26]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X45_Y34_N16
cycloneive_io_obuf \GPIO_0[27]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[27]~output .bus_hold = "false";
defparam \GPIO_0[27]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X38_Y34_N2
cycloneive_io_obuf \GPIO_0[28]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[28]~output .bus_hold = "false";
defparam \GPIO_0[28]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y34_N9
cycloneive_io_obuf \GPIO_0[29]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[29]~output .bus_hold = "false";
defparam \GPIO_0[29]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X43_Y34_N16
cycloneive_io_obuf \GPIO_0[30]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[30]~output .bus_hold = "false";
defparam \GPIO_0[30]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X51_Y34_N16
cycloneive_io_obuf \GPIO_0[31]~output (
	.i(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[31]~output .bus_hold = "false";
defparam \GPIO_0[31]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X51_Y34_N23
cycloneive_io_obuf \GPIO_0[32]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[32]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[32]~output .bus_hold = "false";
defparam \GPIO_0[32]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X43_Y34_N23
cycloneive_io_obuf \GPIO_0[33]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\GPIO_0[33]~output_o ),
	.obar());
// synopsys translate_off
defparam \GPIO_0[33]~output .bus_hold = "false";
defparam \GPIO_0[33]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X27_Y0_N22
cycloneive_io_ibuf \CLOCK_50~input (
	.i(CLOCK_50),
	.ibar(gnd),
	.o(\CLOCK_50~input_o ));
// synopsys translate_off
defparam \CLOCK_50~input .bus_hold = "false";
defparam \CLOCK_50~input .simulate_z_as = "z";
// synopsys translate_on

// Location: CLKCTRL_G18
cycloneive_clkctrl \CLOCK_50~inputclkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\CLOCK_50~inputclkctrl_outclk ));
// synopsys translate_off
defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N2
cycloneive_lcell_comb \counter[0]~63 (
// Equation(s):
// \counter[0]~63_combout  = !counter[0]

	.dataa(gnd),
	.datab(gnd),
	.datac(counter[0]),
	.datad(gnd),
	.cin(gnd),
	.combout(\counter[0]~63_combout ),
	.cout());
// synopsys translate_off
defparam \counter[0]~63 .lut_mask = 16'h0F0F;
defparam \counter[0]~63 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X31_Y7_N3
dffeas \counter[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[0]~63_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[0]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[0] .is_wysiwyg = "true";
defparam \counter[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N12
cycloneive_lcell_comb \counter[1]~21 (
// Equation(s):
// \counter[1]~21_combout  = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC))
// \counter[1]~22  = CARRY((counter[1] & counter[0]))

	.dataa(counter[1]),
	.datab(counter[0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\counter[1]~21_combout ),
	.cout(\counter[1]~22 ));
// synopsys translate_off
defparam \counter[1]~21 .lut_mask = 16'h6688;
defparam \counter[1]~21 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X31_Y7_N13
dffeas \counter[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[1]~21_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[1]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[1] .is_wysiwyg = "true";
defparam \counter[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N14
cycloneive_lcell_comb \counter[2]~23 (
// Equation(s):
// \counter[2]~23_combout  = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND)))
// \counter[2]~24  = CARRY((!\counter[1]~22 ) # (!counter[2]))

	.dataa(gnd),
	.datab(counter[2]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[1]~22 ),
	.combout(\counter[2]~23_combout ),
	.cout(\counter[2]~24 ));
// synopsys translate_off
defparam \counter[2]~23 .lut_mask = 16'h3C3F;
defparam \counter[2]~23 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N15
dffeas \counter[2] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[2]~23_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[2]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[2] .is_wysiwyg = "true";
defparam \counter[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N16
cycloneive_lcell_comb \counter[3]~25 (
// Equation(s):
// \counter[3]~25_combout  = (counter[3] & (\counter[2]~24  $ (GND))) # (!counter[3] & (!\counter[2]~24  & VCC))
// \counter[3]~26  = CARRY((counter[3] & !\counter[2]~24 ))

	.dataa(gnd),
	.datab(counter[3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[2]~24 ),
	.combout(\counter[3]~25_combout ),
	.cout(\counter[3]~26 ));
// synopsys translate_off
defparam \counter[3]~25 .lut_mask = 16'hC30C;
defparam \counter[3]~25 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N17
dffeas \counter[3] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[3]~25_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[3]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[3] .is_wysiwyg = "true";
defparam \counter[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N18
cycloneive_lcell_comb \counter[4]~27 (
// Equation(s):
// \counter[4]~27_combout  = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND)))
// \counter[4]~28  = CARRY((!\counter[3]~26 ) # (!counter[4]))

	.dataa(gnd),
	.datab(counter[4]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[3]~26 ),
	.combout(\counter[4]~27_combout ),
	.cout(\counter[4]~28 ));
// synopsys translate_off
defparam \counter[4]~27 .lut_mask = 16'h3C3F;
defparam \counter[4]~27 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N19
dffeas \counter[4] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[4]~27_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[4]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[4] .is_wysiwyg = "true";
defparam \counter[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N20
cycloneive_lcell_comb \counter[5]~29 (
// Equation(s):
// \counter[5]~29_combout  = (counter[5] & (\counter[4]~28  $ (GND))) # (!counter[5] & (!\counter[4]~28  & VCC))
// \counter[5]~30  = CARRY((counter[5] & !\counter[4]~28 ))

	.dataa(gnd),
	.datab(counter[5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[4]~28 ),
	.combout(\counter[5]~29_combout ),
	.cout(\counter[5]~30 ));
// synopsys translate_off
defparam \counter[5]~29 .lut_mask = 16'hC30C;
defparam \counter[5]~29 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N21
dffeas \counter[5] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[5]~29_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[5]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[5] .is_wysiwyg = "true";
defparam \counter[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N22
cycloneive_lcell_comb \counter[6]~31 (
// Equation(s):
// \counter[6]~31_combout  = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND)))
// \counter[6]~32  = CARRY((!\counter[5]~30 ) # (!counter[6]))

	.dataa(counter[6]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[5]~30 ),
	.combout(\counter[6]~31_combout ),
	.cout(\counter[6]~32 ));
// synopsys translate_off
defparam \counter[6]~31 .lut_mask = 16'h5A5F;
defparam \counter[6]~31 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N23
dffeas \counter[6] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[6]~31_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[6]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[6] .is_wysiwyg = "true";
defparam \counter[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N24
cycloneive_lcell_comb \counter[7]~33 (
// Equation(s):
// \counter[7]~33_combout  = (counter[7] & (\counter[6]~32  $ (GND))) # (!counter[7] & (!\counter[6]~32  & VCC))
// \counter[7]~34  = CARRY((counter[7] & !\counter[6]~32 ))

	.dataa(gnd),
	.datab(counter[7]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[6]~32 ),
	.combout(\counter[7]~33_combout ),
	.cout(\counter[7]~34 ));
// synopsys translate_off
defparam \counter[7]~33 .lut_mask = 16'hC30C;
defparam \counter[7]~33 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N25
dffeas \counter[7] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[7]~33_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[7]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[7] .is_wysiwyg = "true";
defparam \counter[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N26
cycloneive_lcell_comb \counter[8]~35 (
// Equation(s):
// \counter[8]~35_combout  = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND)))
// \counter[8]~36  = CARRY((!\counter[7]~34 ) # (!counter[8]))

	.dataa(counter[8]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[7]~34 ),
	.combout(\counter[8]~35_combout ),
	.cout(\counter[8]~36 ));
// synopsys translate_off
defparam \counter[8]~35 .lut_mask = 16'h5A5F;
defparam \counter[8]~35 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N27
dffeas \counter[8] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[8]~35_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[8]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[8] .is_wysiwyg = "true";
defparam \counter[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N28
cycloneive_lcell_comb \counter[9]~37 (
// Equation(s):
// \counter[9]~37_combout  = (counter[9] & (\counter[8]~36  $ (GND))) # (!counter[9] & (!\counter[8]~36  & VCC))
// \counter[9]~38  = CARRY((counter[9] & !\counter[8]~36 ))

	.dataa(gnd),
	.datab(counter[9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[8]~36 ),
	.combout(\counter[9]~37_combout ),
	.cout(\counter[9]~38 ));
// synopsys translate_off
defparam \counter[9]~37 .lut_mask = 16'hC30C;
defparam \counter[9]~37 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N29
dffeas \counter[9] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[9]~37_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[9]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[9] .is_wysiwyg = "true";
defparam \counter[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N30
cycloneive_lcell_comb \counter[10]~39 (
// Equation(s):
// \counter[10]~39_combout  = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND)))
// \counter[10]~40  = CARRY((!\counter[9]~38 ) # (!counter[10]))

	.dataa(counter[10]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[9]~38 ),
	.combout(\counter[10]~39_combout ),
	.cout(\counter[10]~40 ));
// synopsys translate_off
defparam \counter[10]~39 .lut_mask = 16'h5A5F;
defparam \counter[10]~39 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y7_N31
dffeas \counter[10] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[10]~39_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[10]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[10] .is_wysiwyg = "true";
defparam \counter[10] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N0
cycloneive_lcell_comb \counter[11]~41 (
// Equation(s):
// \counter[11]~41_combout  = (counter[11] & (\counter[10]~40  $ (GND))) # (!counter[11] & (!\counter[10]~40  & VCC))
// \counter[11]~42  = CARRY((counter[11] & !\counter[10]~40 ))

	.dataa(gnd),
	.datab(counter[11]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[10]~40 ),
	.combout(\counter[11]~41_combout ),
	.cout(\counter[11]~42 ));
// synopsys translate_off
defparam \counter[11]~41 .lut_mask = 16'hC30C;
defparam \counter[11]~41 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N1
dffeas \counter[11] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[11]~41_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[11]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[11] .is_wysiwyg = "true";
defparam \counter[11] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N2
cycloneive_lcell_comb \counter[12]~43 (
// Equation(s):
// \counter[12]~43_combout  = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND)))
// \counter[12]~44  = CARRY((!\counter[11]~42 ) # (!counter[12]))

	.dataa(gnd),
	.datab(counter[12]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[11]~42 ),
	.combout(\counter[12]~43_combout ),
	.cout(\counter[12]~44 ));
// synopsys translate_off
defparam \counter[12]~43 .lut_mask = 16'h3C3F;
defparam \counter[12]~43 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N3
dffeas \counter[12] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[12]~43_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[12]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[12] .is_wysiwyg = "true";
defparam \counter[12] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N4
cycloneive_lcell_comb \counter[13]~45 (
// Equation(s):
// \counter[13]~45_combout  = (counter[13] & (\counter[12]~44  $ (GND))) # (!counter[13] & (!\counter[12]~44  & VCC))
// \counter[13]~46  = CARRY((counter[13] & !\counter[12]~44 ))

	.dataa(counter[13]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[12]~44 ),
	.combout(\counter[13]~45_combout ),
	.cout(\counter[13]~46 ));
// synopsys translate_off
defparam \counter[13]~45 .lut_mask = 16'hA50A;
defparam \counter[13]~45 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N5
dffeas \counter[13] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[13]~45_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[13]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[13] .is_wysiwyg = "true";
defparam \counter[13] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N6
cycloneive_lcell_comb \counter[14]~47 (
// Equation(s):
// \counter[14]~47_combout  = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND)))
// \counter[14]~48  = CARRY((!\counter[13]~46 ) # (!counter[14]))

	.dataa(counter[14]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[13]~46 ),
	.combout(\counter[14]~47_combout ),
	.cout(\counter[14]~48 ));
// synopsys translate_off
defparam \counter[14]~47 .lut_mask = 16'h5A5F;
defparam \counter[14]~47 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N7
dffeas \counter[14] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[14]~47_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[14]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[14] .is_wysiwyg = "true";
defparam \counter[14] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N8
cycloneive_lcell_comb \counter[15]~49 (
// Equation(s):
// \counter[15]~49_combout  = (counter[15] & (\counter[14]~48  $ (GND))) # (!counter[15] & (!\counter[14]~48  & VCC))
// \counter[15]~50  = CARRY((counter[15] & !\counter[14]~48 ))

	.dataa(gnd),
	.datab(counter[15]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[14]~48 ),
	.combout(\counter[15]~49_combout ),
	.cout(\counter[15]~50 ));
// synopsys translate_off
defparam \counter[15]~49 .lut_mask = 16'hC30C;
defparam \counter[15]~49 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N9
dffeas \counter[15] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[15]~49_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[15]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[15] .is_wysiwyg = "true";
defparam \counter[15] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N10
cycloneive_lcell_comb \counter[16]~51 (
// Equation(s):
// \counter[16]~51_combout  = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND)))
// \counter[16]~52  = CARRY((!\counter[15]~50 ) # (!counter[16]))

	.dataa(counter[16]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[15]~50 ),
	.combout(\counter[16]~51_combout ),
	.cout(\counter[16]~52 ));
// synopsys translate_off
defparam \counter[16]~51 .lut_mask = 16'h5A5F;
defparam \counter[16]~51 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N11
dffeas \counter[16] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[16]~51_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[16]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[16] .is_wysiwyg = "true";
defparam \counter[16] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N12
cycloneive_lcell_comb \counter[17]~53 (
// Equation(s):
// \counter[17]~53_combout  = (counter[17] & (\counter[16]~52  $ (GND))) # (!counter[17] & (!\counter[16]~52  & VCC))
// \counter[17]~54  = CARRY((counter[17] & !\counter[16]~52 ))

	.dataa(counter[17]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[16]~52 ),
	.combout(\counter[17]~53_combout ),
	.cout(\counter[17]~54 ));
// synopsys translate_off
defparam \counter[17]~53 .lut_mask = 16'hA50A;
defparam \counter[17]~53 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N13
dffeas \counter[17] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[17]~53_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[17]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[17] .is_wysiwyg = "true";
defparam \counter[17] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N14
cycloneive_lcell_comb \counter[18]~55 (
// Equation(s):
// \counter[18]~55_combout  = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND)))
// \counter[18]~56  = CARRY((!\counter[17]~54 ) # (!counter[18]))

	.dataa(gnd),
	.datab(counter[18]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[17]~54 ),
	.combout(\counter[18]~55_combout ),
	.cout(\counter[18]~56 ));
// synopsys translate_off
defparam \counter[18]~55 .lut_mask = 16'h3C3F;
defparam \counter[18]~55 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N15
dffeas \counter[18] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[18]~55_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[18]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[18] .is_wysiwyg = "true";
defparam \counter[18] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N16
cycloneive_lcell_comb \counter[19]~57 (
// Equation(s):
// \counter[19]~57_combout  = (counter[19] & (\counter[18]~56  $ (GND))) # (!counter[19] & (!\counter[18]~56  & VCC))
// \counter[19]~58  = CARRY((counter[19] & !\counter[18]~56 ))

	.dataa(gnd),
	.datab(counter[19]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[18]~56 ),
	.combout(\counter[19]~57_combout ),
	.cout(\counter[19]~58 ));
// synopsys translate_off
defparam \counter[19]~57 .lut_mask = 16'hC30C;
defparam \counter[19]~57 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N17
dffeas \counter[19] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[19]~57_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[19]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[19] .is_wysiwyg = "true";
defparam \counter[19] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N18
cycloneive_lcell_comb \counter[20]~59 (
// Equation(s):
// \counter[20]~59_combout  = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND)))
// \counter[20]~60  = CARRY((!\counter[19]~58 ) # (!counter[20]))

	.dataa(gnd),
	.datab(counter[20]),
	.datac(gnd),
	.datad(vcc),
	.cin(\counter[19]~58 ),
	.combout(\counter[20]~59_combout ),
	.cout(\counter[20]~60 ));
// synopsys translate_off
defparam \counter[20]~59 .lut_mask = 16'h3C3F;
defparam \counter[20]~59 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N19
dffeas \counter[20] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[20]~59_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[20]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[20] .is_wysiwyg = "true";
defparam \counter[20] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N20
cycloneive_lcell_comb \counter[21]~61 (
// Equation(s):
// \counter[21]~61_combout  = \counter[20]~60  $ (!counter[21])

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(counter[21]),
	.cin(\counter[20]~60 ),
	.combout(\counter[21]~61_combout ),
	.cout());
// synopsys translate_off
defparam \counter[21]~61 .lut_mask = 16'hF00F;
defparam \counter[21]~61 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X31_Y6_N21
dffeas \counter[21] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\counter[21]~61_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(counter[21]),
	.prn(vcc));
// synopsys translate_off
defparam \counter[21] .is_wysiwyg = "true";
defparam \counter[21] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N6
cycloneive_lcell_comb \Equal0~7 (
// Equation(s):
// \Equal0~7_combout  = (!counter[20] & !counter[21])

	.dataa(counter[20]),
	.datab(gnd),
	.datac(counter[21]),
	.datad(gnd),
	.cin(gnd),
	.combout(\Equal0~7_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~7 .lut_mask = 16'h0505;
defparam \Equal0~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N24
cycloneive_lcell_comb \Equal0~5 (
// Equation(s):
// \Equal0~5_combout  = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16])))

	.dataa(counter[17]),
	.datab(counter[19]),
	.datac(counter[18]),
	.datad(counter[16]),
	.cin(gnd),
	.combout(\Equal0~5_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~5 .lut_mask = 16'h0001;
defparam \Equal0~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N4
cycloneive_lcell_comb \Equal0~0 (
// Equation(s):
// \Equal0~0_combout  = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3])))

	.dataa(counter[1]),
	.datab(counter[0]),
	.datac(counter[2]),
	.datad(counter[3]),
	.cin(gnd),
	.combout(\Equal0~0_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~0 .lut_mask = 16'h0001;
defparam \Equal0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N10
cycloneive_lcell_comb \Equal0~1 (
// Equation(s):
// \Equal0~1_combout  = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4])))

	.dataa(counter[6]),
	.datab(counter[7]),
	.datac(counter[5]),
	.datad(counter[4]),
	.cin(gnd),
	.combout(\Equal0~1_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~1 .lut_mask = 16'h0001;
defparam \Equal0~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N8
cycloneive_lcell_comb \Equal0~2 (
// Equation(s):
// \Equal0~2_combout  = (!counter[8] & (!counter[9] & (!counter[10] & !counter[11])))

	.dataa(counter[8]),
	.datab(counter[9]),
	.datac(counter[10]),
	.datad(counter[11]),
	.cin(gnd),
	.combout(\Equal0~2_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~2 .lut_mask = 16'h0001;
defparam \Equal0~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y6_N30
cycloneive_lcell_comb \Equal0~3 (
// Equation(s):
// \Equal0~3_combout  = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12])))

	.dataa(counter[14]),
	.datab(counter[15]),
	.datac(counter[13]),
	.datad(counter[12]),
	.cin(gnd),
	.combout(\Equal0~3_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~3 .lut_mask = 16'h0001;
defparam \Equal0~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N28
cycloneive_lcell_comb \Equal0~4 (
// Equation(s):
// \Equal0~4_combout  = (\Equal0~0_combout  & (\Equal0~1_combout  & (\Equal0~2_combout  & \Equal0~3_combout )))

	.dataa(\Equal0~0_combout ),
	.datab(\Equal0~1_combout ),
	.datac(\Equal0~2_combout ),
	.datad(\Equal0~3_combout ),
	.cin(gnd),
	.combout(\Equal0~4_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~4 .lut_mask = 16'h8000;
defparam \Equal0~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y7_N0
cycloneive_lcell_comb \A[0]~40 (
// Equation(s):
// \A[0]~40_combout  = A[0] $ (((\Equal0~7_combout  & (\Equal0~5_combout  & \Equal0~4_combout ))))

	.dataa(\Equal0~7_combout ),
	.datab(\Equal0~5_combout ),
	.datac(A[0]),
	.datad(\Equal0~4_combout ),
	.cin(gnd),
	.combout(\A[0]~40_combout ),
	.cout());
// synopsys translate_off
defparam \A[0]~40 .lut_mask = 16'h78F0;
defparam \A[0]~40 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X31_Y7_N1
dffeas \A[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[0]~40_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[0]),
	.prn(vcc));
// synopsys translate_off
defparam \A[0] .is_wysiwyg = "true";
defparam \A[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N0
cycloneive_lcell_comb \A[1]~14 (
// Equation(s):
// \A[1]~14_combout  = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC))
// \A[1]~15  = CARRY((A[1] & A[0]))

	.dataa(A[1]),
	.datab(A[0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\A[1]~14_combout ),
	.cout(\A[1]~15 ));
// synopsys translate_off
defparam \A[1]~14 .lut_mask = 16'h6688;
defparam \A[1]~14 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N30
cycloneive_lcell_comb \Equal0~6 (
// Equation(s):
// \Equal0~6_combout  = (!counter[21] & (!counter[20] & (\Equal0~5_combout  & \Equal0~4_combout )))

	.dataa(counter[21]),
	.datab(counter[20]),
	.datac(\Equal0~5_combout ),
	.datad(\Equal0~4_combout ),
	.cin(gnd),
	.combout(\Equal0~6_combout ),
	.cout());
// synopsys translate_off
defparam \Equal0~6 .lut_mask = 16'h1000;
defparam \Equal0~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X30_Y7_N1
dffeas \A[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[1]~14_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[1]),
	.prn(vcc));
// synopsys translate_off
defparam \A[1] .is_wysiwyg = "true";
defparam \A[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N2
cycloneive_lcell_comb \A[2]~16 (
// Equation(s):
// \A[2]~16_combout  = (A[2] & (!\A[1]~15 )) # (!A[2] & ((\A[1]~15 ) # (GND)))
// \A[2]~17  = CARRY((!\A[1]~15 ) # (!A[2]))

	.dataa(gnd),
	.datab(A[2]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[1]~15 ),
	.combout(\A[2]~16_combout ),
	.cout(\A[2]~17 ));
// synopsys translate_off
defparam \A[2]~16 .lut_mask = 16'h3C3F;
defparam \A[2]~16 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N3
dffeas \A[2] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[2]~16_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[2]),
	.prn(vcc));
// synopsys translate_off
defparam \A[2] .is_wysiwyg = "true";
defparam \A[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N4
cycloneive_lcell_comb \A[3]~18 (
// Equation(s):
// \A[3]~18_combout  = (A[3] & (\A[2]~17  $ (GND))) # (!A[3] & (!\A[2]~17  & VCC))
// \A[3]~19  = CARRY((A[3] & !\A[2]~17 ))

	.dataa(gnd),
	.datab(A[3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[2]~17 ),
	.combout(\A[3]~18_combout ),
	.cout(\A[3]~19 ));
// synopsys translate_off
defparam \A[3]~18 .lut_mask = 16'hC30C;
defparam \A[3]~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N5
dffeas \A[3] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[3]~18_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[3]),
	.prn(vcc));
// synopsys translate_off
defparam \A[3] .is_wysiwyg = "true";
defparam \A[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N6
cycloneive_lcell_comb \A[4]~20 (
// Equation(s):
// \A[4]~20_combout  = (A[4] & (!\A[3]~19 )) # (!A[4] & ((\A[3]~19 ) # (GND)))
// \A[4]~21  = CARRY((!\A[3]~19 ) # (!A[4]))

	.dataa(A[4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[3]~19 ),
	.combout(\A[4]~20_combout ),
	.cout(\A[4]~21 ));
// synopsys translate_off
defparam \A[4]~20 .lut_mask = 16'h5A5F;
defparam \A[4]~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N7
dffeas \A[4] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[4]~20_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[4]),
	.prn(vcc));
// synopsys translate_off
defparam \A[4] .is_wysiwyg = "true";
defparam \A[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N8
cycloneive_lcell_comb \A[5]~22 (
// Equation(s):
// \A[5]~22_combout  = (A[5] & (\A[4]~21  $ (GND))) # (!A[5] & (!\A[4]~21  & VCC))
// \A[5]~23  = CARRY((A[5] & !\A[4]~21 ))

	.dataa(gnd),
	.datab(A[5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[4]~21 ),
	.combout(\A[5]~22_combout ),
	.cout(\A[5]~23 ));
// synopsys translate_off
defparam \A[5]~22 .lut_mask = 16'hC30C;
defparam \A[5]~22 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N9
dffeas \A[5] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[5]~22_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[5]),
	.prn(vcc));
// synopsys translate_off
defparam \A[5] .is_wysiwyg = "true";
defparam \A[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N10
cycloneive_lcell_comb \A[6]~24 (
// Equation(s):
// \A[6]~24_combout  = (A[6] & (!\A[5]~23 )) # (!A[6] & ((\A[5]~23 ) # (GND)))
// \A[6]~25  = CARRY((!\A[5]~23 ) # (!A[6]))

	.dataa(A[6]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[5]~23 ),
	.combout(\A[6]~24_combout ),
	.cout(\A[6]~25 ));
// synopsys translate_off
defparam \A[6]~24 .lut_mask = 16'h5A5F;
defparam \A[6]~24 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N11
dffeas \A[6] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[6]~24_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[6]),
	.prn(vcc));
// synopsys translate_off
defparam \A[6] .is_wysiwyg = "true";
defparam \A[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N12
cycloneive_lcell_comb \A[7]~26 (
// Equation(s):
// \A[7]~26_combout  = (A[7] & (\A[6]~25  $ (GND))) # (!A[7] & (!\A[6]~25  & VCC))
// \A[7]~27  = CARRY((A[7] & !\A[6]~25 ))

	.dataa(A[7]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[6]~25 ),
	.combout(\A[7]~26_combout ),
	.cout(\A[7]~27 ));
// synopsys translate_off
defparam \A[7]~26 .lut_mask = 16'hA50A;
defparam \A[7]~26 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N13
dffeas \A[7] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[7]~26_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[7]),
	.prn(vcc));
// synopsys translate_off
defparam \A[7] .is_wysiwyg = "true";
defparam \A[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N14
cycloneive_lcell_comb \A[8]~28 (
// Equation(s):
// \A[8]~28_combout  = (A[8] & (!\A[7]~27 )) # (!A[8] & ((\A[7]~27 ) # (GND)))
// \A[8]~29  = CARRY((!\A[7]~27 ) # (!A[8]))

	.dataa(gnd),
	.datab(A[8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[7]~27 ),
	.combout(\A[8]~28_combout ),
	.cout(\A[8]~29 ));
// synopsys translate_off
defparam \A[8]~28 .lut_mask = 16'h3C3F;
defparam \A[8]~28 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N15
dffeas \A[8] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[8]~28_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[8]),
	.prn(vcc));
// synopsys translate_off
defparam \A[8] .is_wysiwyg = "true";
defparam \A[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N16
cycloneive_lcell_comb \A[9]~30 (
// Equation(s):
// \A[9]~30_combout  = (A[9] & (\A[8]~29  $ (GND))) # (!A[9] & (!\A[8]~29  & VCC))
// \A[9]~31  = CARRY((A[9] & !\A[8]~29 ))

	.dataa(gnd),
	.datab(A[9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[8]~29 ),
	.combout(\A[9]~30_combout ),
	.cout(\A[9]~31 ));
// synopsys translate_off
defparam \A[9]~30 .lut_mask = 16'hC30C;
defparam \A[9]~30 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N17
dffeas \A[9] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[9]~30_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[9]),
	.prn(vcc));
// synopsys translate_off
defparam \A[9] .is_wysiwyg = "true";
defparam \A[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N18
cycloneive_lcell_comb \A[10]~32 (
// Equation(s):
// \A[10]~32_combout  = (A[10] & (!\A[9]~31 )) # (!A[10] & ((\A[9]~31 ) # (GND)))
// \A[10]~33  = CARRY((!\A[9]~31 ) # (!A[10]))

	.dataa(gnd),
	.datab(A[10]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[9]~31 ),
	.combout(\A[10]~32_combout ),
	.cout(\A[10]~33 ));
// synopsys translate_off
defparam \A[10]~32 .lut_mask = 16'h3C3F;
defparam \A[10]~32 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N19
dffeas \A[10] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[10]~32_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[10]),
	.prn(vcc));
// synopsys translate_off
defparam \A[10] .is_wysiwyg = "true";
defparam \A[10] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N20
cycloneive_lcell_comb \A[11]~34 (
// Equation(s):
// \A[11]~34_combout  = (A[11] & (\A[10]~33  $ (GND))) # (!A[11] & (!\A[10]~33  & VCC))
// \A[11]~35  = CARRY((A[11] & !\A[10]~33 ))

	.dataa(gnd),
	.datab(A[11]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[10]~33 ),
	.combout(\A[11]~34_combout ),
	.cout(\A[11]~35 ));
// synopsys translate_off
defparam \A[11]~34 .lut_mask = 16'hC30C;
defparam \A[11]~34 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N21
dffeas \A[11] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[11]~34_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[11]),
	.prn(vcc));
// synopsys translate_off
defparam \A[11] .is_wysiwyg = "true";
defparam \A[11] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N22
cycloneive_lcell_comb \A[12]~36 (
// Equation(s):
// \A[12]~36_combout  = (A[12] & (!\A[11]~35 )) # (!A[12] & ((\A[11]~35 ) # (GND)))
// \A[12]~37  = CARRY((!\A[11]~35 ) # (!A[12]))

	.dataa(A[12]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[11]~35 ),
	.combout(\A[12]~36_combout ),
	.cout(\A[12]~37 ));
// synopsys translate_off
defparam \A[12]~36 .lut_mask = 16'h5A5F;
defparam \A[12]~36 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N23
dffeas \A[12] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[12]~36_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[12]),
	.prn(vcc));
// synopsys translate_off
defparam \A[12] .is_wysiwyg = "true";
defparam \A[12] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N24
cycloneive_lcell_comb \A[13]~38 (
// Equation(s):
// \A[13]~38_combout  = (A[13] & (\A[12]~37  $ (GND))) # (!A[13] & (!\A[12]~37  & VCC))
// \A[13]~39  = CARRY((A[13] & !\A[12]~37 ))

	.dataa(gnd),
	.datab(A[13]),
	.datac(gnd),
	.datad(vcc),
	.cin(\A[12]~37 ),
	.combout(\A[13]~38_combout ),
	.cout(\A[13]~39 ));
// synopsys translate_off
defparam \A[13]~38 .lut_mask = 16'hC30C;
defparam \A[13]~38 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N25
dffeas \A[13] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[13]~38_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[13]),
	.prn(vcc));
// synopsys translate_off
defparam \A[13] .is_wysiwyg = "true";
defparam \A[13] .power_up = "low";
// synopsys translate_on

// Location: M9K_X22_Y29_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF;
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7;
// synopsys translate_on

// Location: LCCOMB_X32_Y26_N2
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout  = A[13]

	.dataa(gnd),
	.datab(gnd),
	.datac(A[13]),
	.datad(gnd),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0;
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X32_Y26_N3
dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]),
	.prn(vcc));
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true";
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X32_Y26_N4
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout  = \ram1|altsyncram_component|auto_generated|address_reg_a [0]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00;
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X32_Y26_N5
dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.prn(vcc));
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true";
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low";
// synopsys translate_on

// Location: M9K_X22_Y26_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56;
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF;
// synopsys translate_on

// Location: LCCOMB_X23_Y28_N28
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hB8B8;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y22_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB;
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B;
// synopsys translate_on

// Location: M9K_X22_Y20_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6;
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60;
// synopsys translate_on

// Location: LCCOMB_X21_Y27_N0
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))

	.dataa(gnd),
	.datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
	.datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0CC;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y23_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F;
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A;
// synopsys translate_on

// Location: M9K_X22_Y31_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E;
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB;
// synopsys translate_on

// Location: LCCOMB_X21_Y31_N16
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFA0A;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y16_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF;
// synopsys translate_on

// Location: M9K_X22_Y19_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7;
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A;
// synopsys translate_on

// Location: LCCOMB_X21_Y19_N16
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y15_N28
cycloneive_lcell_comb \~GND (
// Equation(s):
// \~GND~combout  = GND

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\~GND~combout ),
	.cout());
// synopsys translate_off
defparam \~GND .lut_mask = 16'h0000;
defparam \~GND .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y28_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
// synopsys translate_on

// Location: M9K_X33_Y27_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X24_Y28_N12
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(gnd),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .lut_mask = 16'hFA50;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[4]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y28_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
// synopsys translate_on

// Location: M9K_X33_Y26_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X32_Y26_N18
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[5]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y17_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
// synopsys translate_on

// Location: M9K_X33_Y19_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X32_Y24_N24
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))

	.dataa(gnd),
	.datab(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .lut_mask = 16'hFC0C;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[6]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y23_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
// synopsys translate_on

// Location: M9K_X33_Y24_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X32_Y24_N26
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[7]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y17_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB;
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D;
// synopsys translate_on

// Location: M9K_X22_Y25_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160;
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C;
// synopsys translate_on

// Location: LCCOMB_X21_Y25_N4
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hFA0A;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y24_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E;
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604;
// synopsys translate_on

// Location: M9K_X22_Y21_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003;
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B;
// synopsys translate_on

// Location: LCCOMB_X21_Y28_N20
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
	.datab(gnd),
	.datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hAAF0;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y14_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E;
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679;
// synopsys translate_on

// Location: M9K_X22_Y12_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E;
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6;
// synopsys translate_on

// Location: LCCOMB_X21_Y17_N0
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))

	.dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hFA0A;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y27_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966;
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B;
// synopsys translate_on

// Location: M9K_X22_Y30_N0
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(1'b0),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E;
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2;
// synopsys translate_on

// Location: LCCOMB_X21_Y27_N30
cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 (
// Equation(s):
// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
	.datad(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
	.cin(gnd),
	.combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ),
	.cout());
// synopsys translate_off
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hFC30;
defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y22_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
// synopsys translate_on

// Location: M9K_X33_Y21_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X32_Y26_N12
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[0]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y30_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y31_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N28
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))

	.dataa(gnd),
	.datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .lut_mask = 16'hCFC0;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[1]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y32_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y25_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
// synopsys translate_on

// Location: LCCOMB_X23_Y29_N4
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(gnd),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .lut_mask = 16'hF5A0;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[2]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y29_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y32_N0
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(!A[13]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain({\~GND~combout }),
	.portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
	.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock0";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
// synopsys translate_on

// Location: LCCOMB_X32_Y29_N24
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))

	.dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .lut_mask = 16'hAFA0;
defparam \ram0|altsyncram_component|auto_generated|mux4|result_node[3]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y7_N26
cycloneive_lcell_comb \A[14]~41 (
// Equation(s):
// \A[14]~41_combout  = A[14] $ (\A[13]~39 )

	.dataa(A[14]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\A[13]~39 ),
	.combout(\A[14]~41_combout ),
	.cout());
// synopsys translate_off
defparam \A[14]~41 .lut_mask = 16'h5A5A;
defparam \A[14]~41 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y7_N27
dffeas \A[14] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\A[14]~41_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal0~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(A[14]),
	.prn(vcc));
// synopsys translate_off
defparam \A[14] .is_wysiwyg = "true";
defparam \A[14] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N18
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout  = (A[14] & !A[13])

	.dataa(gnd),
	.datab(gnd),
	.datac(A[14]),
	.datad(A[13]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00F0;
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y1_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N14
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout  = (A[14] & A[13])

	.dataa(gnd),
	.datab(gnd),
	.datac(A[14]),
	.datad(A[13]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .lut_mask = 16'hF000;
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y16_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N16
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2] = (!A[14] & !A[13])

	.dataa(gnd),
	.datab(gnd),
	.datac(A[14]),
	.datad(A[13]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .lut_mask = 16'h000F;
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w[2] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y6_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N30
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout  = (!A[14] & A[13])

	.dataa(gnd),
	.datab(gnd),
	.datac(A[14]),
	.datad(A[13]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .lut_mask = 16'h0F00;
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y3_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N0
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout  = A[14]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(A[14]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .lut_mask = 16'hFF00;
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X29_Y7_N1
dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\ram1|altsyncram_component|auto_generated|address_reg_a[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]),
	.prn(vcc));
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true";
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N20
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout  = \ram1|altsyncram_component|auto_generated|address_reg_a [1]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\ram1|altsyncram_component|auto_generated|address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .lut_mask = 16'hFF00;
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X29_Y7_N21
dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] (
	.clk(\CLOCK_50~inputclkctrl_outclk ),
	.d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.prn(vcc));
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true";
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N26
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # 
// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout  & 
// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hAAE4;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N28
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout  = (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout  & (((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout  & 
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .lut_mask = 16'hCAF0;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y1_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X22_Y2_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y6_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N28
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # 
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout  & 
// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .lut_mask = 16'hAAD8;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y15_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N10
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout  = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout  & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout  & 
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~2_combout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .lut_mask = 16'hE2CC;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y4_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X22_Y5_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
// synopsys translate_on

// Location: M9K_X22_Y3_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N22
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .lut_mask = 16'hF2C2;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y8_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N24
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout  & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~4_combout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .lut_mask = 16'hF838;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y18_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
// synopsys translate_on

// Location: M9K_X33_Y12_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N12
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & 
// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y7_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y9_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N26
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout  = (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout  & (((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout  & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hE6A2;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y4_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X22_Y11_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y14_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N20
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hB9A8;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y18_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N14
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout  = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout  & (((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout  & 
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hE2CC;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y11_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X22_Y10_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
// synopsys translate_on

// Location: M9K_X33_Y10_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N4
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y13_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X26_Y11_N22
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout  & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hF838;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y9_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X22_Y8_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
// synopsys translate_on

// Location: LCCOMB_X27_Y9_N0
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout )))))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hEE50;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y13_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y7_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X27_Y9_N18
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout  & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout  & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ))

	.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hEC64;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y5_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~1_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y20_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode261w [2]),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N6
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout )))))

	.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hE3E0;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y15_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~2_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: M9K_X33_Y2_N0
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 (
	.portawe(gnd),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLOCK_50~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND~combout }),
	.portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr(13'b0000000000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K";
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// Location: LCCOMB_X29_Y7_N12
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 (
// Equation(s):
// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout  = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout  & (((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout  & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & 
// ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ))))

	.dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
	.datac(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ),
	.datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ),
	.cin(gnd),
	.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ),
	.cout());
// synopsys translate_off
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hE6A2;
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y22_N16
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 )))

	.dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~PORTBDATAOUT0 ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .lut_mask = 16'hAFA0;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N10
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N0
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ))

	.dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(gnd),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .lut_mask = 16'hEE22;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N14
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[3]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N24
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a12~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .lut_mask = 16'hFC30;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[4]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N30
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 )))

	.dataa(gnd),
	.datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~PORTBDATAOUT0 ),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .lut_mask = 16'hCFC0;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y17_N0
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 )) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 )))

	.dataa(gnd),
	.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~PORTBDATAOUT0 ),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .lut_mask = 16'hF3C0;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y30_N4
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 (
// Equation(s):
// \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout  = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ))) # 
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ))

	.dataa(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ),
	.datab(gnd),
	.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
	.datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~PORTBDATAOUT0 ),
	.cin(gnd),
	.combout(\ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7_combout ),
	.cout());
// synopsys translate_off
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .lut_mask = 16'hFA0A;
defparam \ram0|altsyncram_component|auto_generated|mux5|result_node[7]~7 .sum_lutc_input = "datac";
// synopsys translate_on

assign LED[0] = \LED[0]~output_o ;

assign LED[1] = \LED[1]~output_o ;

assign LED[2] = \LED[2]~output_o ;

assign LED[3] = \LED[3]~output_o ;

assign LED[4] = \LED[4]~output_o ;

assign LED[5] = \LED[5]~output_o ;

assign LED[6] = \LED[6]~output_o ;

assign LED[7] = \LED[7]~output_o ;

assign GPIO_0[0] = \GPIO_0[0]~output_o ;

assign GPIO_0[1] = \GPIO_0[1]~output_o ;

assign GPIO_0[2] = \GPIO_0[2]~output_o ;

assign GPIO_0[3] = \GPIO_0[3]~output_o ;

assign GPIO_0[4] = \GPIO_0[4]~output_o ;

assign GPIO_0[5] = \GPIO_0[5]~output_o ;

assign GPIO_0[6] = \GPIO_0[6]~output_o ;

assign GPIO_0[7] = \GPIO_0[7]~output_o ;

assign GPIO_0[8] = \GPIO_0[8]~output_o ;

assign GPIO_0[9] = \GPIO_0[9]~output_o ;

assign GPIO_0[10] = \GPIO_0[10]~output_o ;

assign GPIO_0[11] = \GPIO_0[11]~output_o ;

assign GPIO_0[12] = \GPIO_0[12]~output_o ;

assign GPIO_0[13] = \GPIO_0[13]~output_o ;

assign GPIO_0[14] = \GPIO_0[14]~output_o ;

assign GPIO_0[15] = \GPIO_0[15]~output_o ;

assign GPIO_0[16] = \GPIO_0[16]~output_o ;

assign GPIO_0[17] = \GPIO_0[17]~output_o ;

assign GPIO_0[18] = \GPIO_0[18]~output_o ;

assign GPIO_0[19] = \GPIO_0[19]~output_o ;

assign GPIO_0[20] = \GPIO_0[20]~output_o ;

assign GPIO_0[21] = \GPIO_0[21]~output_o ;

assign GPIO_0[22] = \GPIO_0[22]~output_o ;

assign GPIO_0[23] = \GPIO_0[23]~output_o ;

assign GPIO_0[24] = \GPIO_0[24]~output_o ;

assign GPIO_0[25] = \GPIO_0[25]~output_o ;

assign GPIO_0[26] = \GPIO_0[26]~output_o ;

assign GPIO_0[27] = \GPIO_0[27]~output_o ;

assign GPIO_0[28] = \GPIO_0[28]~output_o ;

assign GPIO_0[29] = \GPIO_0[29]~output_o ;

assign GPIO_0[30] = \GPIO_0[30]~output_o ;

assign GPIO_0[31] = \GPIO_0[31]~output_o ;

assign GPIO_0[32] = \GPIO_0[32]~output_o ;

assign GPIO_0[33] = \GPIO_0[33]~output_o ;

endmodule