|spectrum CLOCK_50 => CLOCK_50.IN3 LED[0] <= rom0:rom.q LED[1] <= rom0:rom.q LED[2] <= rom0:rom.q LED[3] <= rom0:rom.q LED[4] <= ram16:ram0.q_a LED[5] <= ram16:ram0.q_a LED[6] <= ram16:ram0.q_a LED[7] <= ram16:ram0.q_a GPIO_0[0] <= rom0:rom.q GPIO_0[1] <= rom0:rom.q GPIO_0[2] <= rom0:rom.q GPIO_0[3] <= rom0:rom.q GPIO_0[4] <= rom0:rom.q GPIO_0[5] <= rom0:rom.q GPIO_0[6] <= rom0:rom.q GPIO_0[7] <= rom0:rom.q GPIO_0[8] <= ram16:ram0.q_a GPIO_0[9] <= ram16:ram0.q_a GPIO_0[10] <= ram16:ram0.q_a GPIO_0[11] <= ram16:ram0.q_a GPIO_0[12] <= ram16:ram0.q_a GPIO_0[13] <= ram16:ram0.q_a GPIO_0[14] <= ram16:ram0.q_a GPIO_0[15] <= ram16:ram0.q_a GPIO_0[16] <= ram32:ram1.q GPIO_0[17] <= ram32:ram1.q GPIO_0[18] <= ram32:ram1.q GPIO_0[19] <= ram32:ram1.q GPIO_0[20] <= ram32:ram1.q GPIO_0[21] <= ram32:ram1.q GPIO_0[22] <= ram32:ram1.q GPIO_0[23] <= ram32:ram1.q GPIO_0[24] <= ram16:ram0.q_b GPIO_0[25] <= ram16:ram0.q_b GPIO_0[26] <= ram16:ram0.q_b GPIO_0[27] <= ram16:ram0.q_b GPIO_0[28] <= ram16:ram0.q_b GPIO_0[29] <= ram16:ram0.q_b GPIO_0[30] <= ram16:ram0.q_b GPIO_0[31] <= ram16:ram0.q_b GPIO_0[32] <= GPIO_0[33] <= |spectrum|rom0:rom address[0] => address[0].IN1 address[1] => address[1].IN1 address[2] => address[2].IN1 address[3] => address[3].IN1 address[4] => address[4].IN1 address[5] => address[5].IN1 address[6] => address[6].IN1 address[7] => address[7].IN1 address[8] => address[8].IN1 address[9] => address[9].IN1 address[10] => address[10].IN1 address[11] => address[11].IN1 address[12] => address[12].IN1 address[13] => address[13].IN1 clock => clock.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a q[2] <= altsyncram:altsyncram_component.q_a q[3] <= altsyncram:altsyncram_component.q_a q[4] <= altsyncram:altsyncram_component.q_a q[5] <= altsyncram:altsyncram_component.q_a q[6] <= altsyncram:altsyncram_component.q_a q[7] <= altsyncram:altsyncram_component.q_a |spectrum|rom0:rom|altsyncram:altsyncram_component wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => ~NO_FANOUT~ data_a[1] => ~NO_FANOUT~ data_a[2] => ~NO_FANOUT~ data_a[3] => ~NO_FANOUT~ data_a[4] => ~NO_FANOUT~ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_qh91:auto_generated.address_a[0] address_a[1] => altsyncram_qh91:auto_generated.address_a[1] address_a[2] => altsyncram_qh91:auto_generated.address_a[2] address_a[3] => altsyncram_qh91:auto_generated.address_a[3] address_a[4] => altsyncram_qh91:auto_generated.address_a[4] address_a[5] => altsyncram_qh91:auto_generated.address_a[5] address_a[6] => altsyncram_qh91:auto_generated.address_a[6] address_a[7] => altsyncram_qh91:auto_generated.address_a[7] address_a[8] => altsyncram_qh91:auto_generated.address_a[8] address_a[9] => altsyncram_qh91:auto_generated.address_a[9] address_a[10] => altsyncram_qh91:auto_generated.address_a[10] address_a[11] => altsyncram_qh91:auto_generated.address_a[11] address_a[12] => altsyncram_qh91:auto_generated.address_a[12] address_a[13] => altsyncram_qh91:auto_generated.address_a[13] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_qh91:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_qh91:auto_generated.q_a[0] q_a[1] <= altsyncram_qh91:auto_generated.q_a[1] q_a[2] <= altsyncram_qh91:auto_generated.q_a[2] q_a[3] <= altsyncram_qh91:auto_generated.q_a[3] q_a[4] <= altsyncram_qh91:auto_generated.q_a[4] q_a[5] <= altsyncram_qh91:auto_generated.q_a[5] q_a[6] <= altsyncram_qh91:auto_generated.q_a[6] q_a[7] <= altsyncram_qh91:auto_generated.q_a[7] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_a[8] => ram_block1a15.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[9] => ram_block1a8.PORTAADDR9 address_a[9] => ram_block1a9.PORTAADDR9 address_a[9] => ram_block1a10.PORTAADDR9 address_a[9] => ram_block1a11.PORTAADDR9 address_a[9] => ram_block1a12.PORTAADDR9 address_a[9] => ram_block1a13.PORTAADDR9 address_a[9] => ram_block1a14.PORTAADDR9 address_a[9] => ram_block1a15.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 address_a[10] => ram_block1a8.PORTAADDR10 address_a[10] => ram_block1a9.PORTAADDR10 address_a[10] => ram_block1a10.PORTAADDR10 address_a[10] => ram_block1a11.PORTAADDR10 address_a[10] => ram_block1a12.PORTAADDR10 address_a[10] => ram_block1a13.PORTAADDR10 address_a[10] => ram_block1a14.PORTAADDR10 address_a[10] => ram_block1a15.PORTAADDR10 address_a[11] => ram_block1a0.PORTAADDR11 address_a[11] => ram_block1a1.PORTAADDR11 address_a[11] => ram_block1a2.PORTAADDR11 address_a[11] => ram_block1a3.PORTAADDR11 address_a[11] => ram_block1a4.PORTAADDR11 address_a[11] => ram_block1a5.PORTAADDR11 address_a[11] => ram_block1a6.PORTAADDR11 address_a[11] => ram_block1a7.PORTAADDR11 address_a[11] => ram_block1a8.PORTAADDR11 address_a[11] => ram_block1a9.PORTAADDR11 address_a[11] => ram_block1a10.PORTAADDR11 address_a[11] => ram_block1a11.PORTAADDR11 address_a[11] => ram_block1a12.PORTAADDR11 address_a[11] => ram_block1a13.PORTAADDR11 address_a[11] => ram_block1a14.PORTAADDR11 address_a[11] => ram_block1a15.PORTAADDR11 address_a[12] => ram_block1a0.PORTAADDR12 address_a[12] => ram_block1a1.PORTAADDR12 address_a[12] => ram_block1a2.PORTAADDR12 address_a[12] => ram_block1a3.PORTAADDR12 address_a[12] => ram_block1a4.PORTAADDR12 address_a[12] => ram_block1a5.PORTAADDR12 address_a[12] => ram_block1a6.PORTAADDR12 address_a[12] => ram_block1a7.PORTAADDR12 address_a[12] => ram_block1a8.PORTAADDR12 address_a[12] => ram_block1a9.PORTAADDR12 address_a[12] => ram_block1a10.PORTAADDR12 address_a[12] => ram_block1a11.PORTAADDR12 address_a[12] => ram_block1a12.PORTAADDR12 address_a[12] => ram_block1a13.PORTAADDR12 address_a[12] => ram_block1a14.PORTAADDR12 address_a[12] => ram_block1a15.PORTAADDR12 address_a[13] => address_reg_a[0].DATAIN address_a[13] => decode_c8a:rden_decode.data[0] clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => address_reg_a[0].CLK clock0 => out_address_reg_a[0].CLK q_a[0] <= mux_3nb:mux2.result[0] q_a[1] <= mux_3nb:mux2.result[1] q_a[2] <= mux_3nb:mux2.result[2] q_a[3] <= mux_3nb:mux2.result[3] q_a[4] <= mux_3nb:mux2.result[4] q_a[5] <= mux_3nb:mux2.result[5] q_a[6] <= mux_3nb:mux2.result[6] q_a[7] <= mux_3nb:mux2.result[7] |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 data[0] => result_node[0].IN1 data[1] => result_node[1].IN1 data[2] => result_node[2].IN1 data[3] => result_node[3].IN1 data[4] => result_node[4].IN1 data[5] => result_node[5].IN1 data[6] => result_node[6].IN1 data[7] => result_node[7].IN1 data[8] => result_node[0].IN1 data[9] => result_node[1].IN1 data[10] => result_node[2].IN1 data[11] => result_node[3].IN1 data[12] => result_node[4].IN1 data[13] => result_node[5].IN1 data[14] => result_node[6].IN1 data[15] => result_node[7].IN1 result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE sel[0] => result_node[7].IN0 sel[0] => _.IN0 sel[0] => result_node[6].IN0 sel[0] => _.IN0 sel[0] => result_node[5].IN0 sel[0] => _.IN0 sel[0] => result_node[4].IN0 sel[0] => _.IN0 sel[0] => result_node[3].IN0 sel[0] => _.IN0 sel[0] => result_node[2].IN0 sel[0] => _.IN0 sel[0] => result_node[1].IN0 sel[0] => _.IN0 sel[0] => result_node[0].IN0 sel[0] => _.IN0 |spectrum|ram16:ram0 address_a[0] => address_a[0].IN1 address_a[1] => address_a[1].IN1 address_a[2] => address_a[2].IN1 address_a[3] => address_a[3].IN1 address_a[4] => address_a[4].IN1 address_a[5] => address_a[5].IN1 address_a[6] => address_a[6].IN1 address_a[7] => address_a[7].IN1 address_a[8] => address_a[8].IN1 address_a[9] => address_a[9].IN1 address_a[10] => address_a[10].IN1 address_a[11] => address_a[11].IN1 address_a[12] => address_a[12].IN1 address_a[13] => address_a[13].IN1 address_b[0] => address_b[0].IN1 address_b[1] => address_b[1].IN1 address_b[2] => address_b[2].IN1 address_b[3] => address_b[3].IN1 address_b[4] => address_b[4].IN1 address_b[5] => address_b[5].IN1 address_b[6] => address_b[6].IN1 address_b[7] => address_b[7].IN1 address_b[8] => address_b[8].IN1 address_b[9] => address_b[9].IN1 address_b[10] => address_b[10].IN1 address_b[11] => address_b[11].IN1 address_b[12] => address_b[12].IN1 address_b[13] => address_b[13].IN1 clock => clock.IN1 data_a[0] => data_a[0].IN1 data_a[1] => data_a[1].IN1 data_a[2] => data_a[2].IN1 data_a[3] => data_a[3].IN1 data_a[4] => data_a[4].IN1 data_a[5] => data_a[5].IN1 data_a[6] => data_a[6].IN1 data_a[7] => data_a[7].IN1 data_b[0] => data_b[0].IN1 data_b[1] => data_b[1].IN1 data_b[2] => data_b[2].IN1 data_b[3] => data_b[3].IN1 data_b[4] => data_b[4].IN1 data_b[5] => data_b[5].IN1 data_b[6] => data_b[6].IN1 data_b[7] => data_b[7].IN1 wren_a => wren_a.IN1 wren_b => wren_b.IN1 q_a[0] <= altsyncram:altsyncram_component.q_a q_a[1] <= altsyncram:altsyncram_component.q_a q_a[2] <= altsyncram:altsyncram_component.q_a q_a[3] <= altsyncram:altsyncram_component.q_a q_a[4] <= altsyncram:altsyncram_component.q_a q_a[5] <= altsyncram:altsyncram_component.q_a q_a[6] <= altsyncram:altsyncram_component.q_a q_a[7] <= altsyncram:altsyncram_component.q_a q_b[0] <= altsyncram:altsyncram_component.q_b q_b[1] <= altsyncram:altsyncram_component.q_b q_b[2] <= altsyncram:altsyncram_component.q_b q_b[3] <= altsyncram:altsyncram_component.q_b q_b[4] <= altsyncram:altsyncram_component.q_b q_b[5] <= altsyncram:altsyncram_component.q_b q_b[6] <= altsyncram:altsyncram_component.q_b q_b[7] <= altsyncram:altsyncram_component.q_b |spectrum|ram16:ram0|altsyncram:altsyncram_component wren_a => altsyncram_bui2:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => altsyncram_bui2:auto_generated.wren_b rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_bui2:auto_generated.data_a[0] data_a[1] => altsyncram_bui2:auto_generated.data_a[1] data_a[2] => altsyncram_bui2:auto_generated.data_a[2] data_a[3] => altsyncram_bui2:auto_generated.data_a[3] data_a[4] => altsyncram_bui2:auto_generated.data_a[4] data_a[5] => altsyncram_bui2:auto_generated.data_a[5] data_a[6] => altsyncram_bui2:auto_generated.data_a[6] data_a[7] => altsyncram_bui2:auto_generated.data_a[7] data_b[0] => altsyncram_bui2:auto_generated.data_b[0] data_b[1] => altsyncram_bui2:auto_generated.data_b[1] data_b[2] => altsyncram_bui2:auto_generated.data_b[2] data_b[3] => altsyncram_bui2:auto_generated.data_b[3] data_b[4] => altsyncram_bui2:auto_generated.data_b[4] data_b[5] => altsyncram_bui2:auto_generated.data_b[5] data_b[6] => altsyncram_bui2:auto_generated.data_b[6] data_b[7] => altsyncram_bui2:auto_generated.data_b[7] address_a[0] => altsyncram_bui2:auto_generated.address_a[0] address_a[1] => altsyncram_bui2:auto_generated.address_a[1] address_a[2] => altsyncram_bui2:auto_generated.address_a[2] address_a[3] => altsyncram_bui2:auto_generated.address_a[3] address_a[4] => altsyncram_bui2:auto_generated.address_a[4] address_a[5] => altsyncram_bui2:auto_generated.address_a[5] address_a[6] => altsyncram_bui2:auto_generated.address_a[6] address_a[7] => altsyncram_bui2:auto_generated.address_a[7] address_a[8] => altsyncram_bui2:auto_generated.address_a[8] address_a[9] => altsyncram_bui2:auto_generated.address_a[9] address_a[10] => altsyncram_bui2:auto_generated.address_a[10] address_a[11] => altsyncram_bui2:auto_generated.address_a[11] address_a[12] => altsyncram_bui2:auto_generated.address_a[12] address_a[13] => altsyncram_bui2:auto_generated.address_a[13] address_b[0] => altsyncram_bui2:auto_generated.address_b[0] address_b[1] => altsyncram_bui2:auto_generated.address_b[1] address_b[2] => altsyncram_bui2:auto_generated.address_b[2] address_b[3] => altsyncram_bui2:auto_generated.address_b[3] address_b[4] => altsyncram_bui2:auto_generated.address_b[4] address_b[5] => altsyncram_bui2:auto_generated.address_b[5] address_b[6] => altsyncram_bui2:auto_generated.address_b[6] address_b[7] => altsyncram_bui2:auto_generated.address_b[7] address_b[8] => altsyncram_bui2:auto_generated.address_b[8] address_b[9] => altsyncram_bui2:auto_generated.address_b[9] address_b[10] => altsyncram_bui2:auto_generated.address_b[10] address_b[11] => altsyncram_bui2:auto_generated.address_b[11] address_b[12] => altsyncram_bui2:auto_generated.address_b[12] address_b[13] => altsyncram_bui2:auto_generated.address_b[13] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_bui2:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_bui2:auto_generated.q_a[0] q_a[1] <= altsyncram_bui2:auto_generated.q_a[1] q_a[2] <= altsyncram_bui2:auto_generated.q_a[2] q_a[3] <= altsyncram_bui2:auto_generated.q_a[3] q_a[4] <= altsyncram_bui2:auto_generated.q_a[4] q_a[5] <= altsyncram_bui2:auto_generated.q_a[5] q_a[6] <= altsyncram_bui2:auto_generated.q_a[6] q_a[7] <= altsyncram_bui2:auto_generated.q_a[7] q_b[0] <= altsyncram_bui2:auto_generated.q_b[0] q_b[1] <= altsyncram_bui2:auto_generated.q_b[1] q_b[2] <= altsyncram_bui2:auto_generated.q_b[2] q_b[3] <= altsyncram_bui2:auto_generated.q_b[3] q_b[4] <= altsyncram_bui2:auto_generated.q_b[4] q_b[5] <= altsyncram_bui2:auto_generated.q_b[5] q_b[6] <= altsyncram_bui2:auto_generated.q_b[6] q_b[7] <= altsyncram_bui2:auto_generated.q_b[7] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_a[8] => ram_block1a15.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[9] => ram_block1a8.PORTAADDR9 address_a[9] => ram_block1a9.PORTAADDR9 address_a[9] => ram_block1a10.PORTAADDR9 address_a[9] => ram_block1a11.PORTAADDR9 address_a[9] => ram_block1a12.PORTAADDR9 address_a[9] => ram_block1a13.PORTAADDR9 address_a[9] => ram_block1a14.PORTAADDR9 address_a[9] => ram_block1a15.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 address_a[10] => ram_block1a8.PORTAADDR10 address_a[10] => ram_block1a9.PORTAADDR10 address_a[10] => ram_block1a10.PORTAADDR10 address_a[10] => ram_block1a11.PORTAADDR10 address_a[10] => ram_block1a12.PORTAADDR10 address_a[10] => ram_block1a13.PORTAADDR10 address_a[10] => ram_block1a14.PORTAADDR10 address_a[10] => ram_block1a15.PORTAADDR10 address_a[11] => ram_block1a0.PORTAADDR11 address_a[11] => ram_block1a1.PORTAADDR11 address_a[11] => ram_block1a2.PORTAADDR11 address_a[11] => ram_block1a3.PORTAADDR11 address_a[11] => ram_block1a4.PORTAADDR11 address_a[11] => ram_block1a5.PORTAADDR11 address_a[11] => ram_block1a6.PORTAADDR11 address_a[11] => ram_block1a7.PORTAADDR11 address_a[11] => ram_block1a8.PORTAADDR11 address_a[11] => ram_block1a9.PORTAADDR11 address_a[11] => ram_block1a10.PORTAADDR11 address_a[11] => ram_block1a11.PORTAADDR11 address_a[11] => ram_block1a12.PORTAADDR11 address_a[11] => ram_block1a13.PORTAADDR11 address_a[11] => ram_block1a14.PORTAADDR11 address_a[11] => ram_block1a15.PORTAADDR11 address_a[12] => ram_block1a0.PORTAADDR12 address_a[12] => ram_block1a1.PORTAADDR12 address_a[12] => ram_block1a2.PORTAADDR12 address_a[12] => ram_block1a3.PORTAADDR12 address_a[12] => ram_block1a4.PORTAADDR12 address_a[12] => ram_block1a5.PORTAADDR12 address_a[12] => ram_block1a6.PORTAADDR12 address_a[12] => ram_block1a7.PORTAADDR12 address_a[12] => ram_block1a8.PORTAADDR12 address_a[12] => ram_block1a9.PORTAADDR12 address_a[12] => ram_block1a10.PORTAADDR12 address_a[12] => ram_block1a11.PORTAADDR12 address_a[12] => ram_block1a12.PORTAADDR12 address_a[12] => ram_block1a13.PORTAADDR12 address_a[12] => ram_block1a14.PORTAADDR12 address_a[12] => ram_block1a15.PORTAADDR12 address_a[13] => address_reg_a[0].DATAIN address_a[13] => decode_jsa:decode2.data[0] address_a[13] => decode_c8a:rden_decode_a.data[0] address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[5] => ram_block1a15.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[6] => ram_block1a15.PORTBADDR6 address_b[7] => ram_block1a0.PORTBADDR7 address_b[7] => ram_block1a1.PORTBADDR7 address_b[7] => ram_block1a2.PORTBADDR7 address_b[7] => ram_block1a3.PORTBADDR7 address_b[7] => ram_block1a4.PORTBADDR7 address_b[7] => ram_block1a5.PORTBADDR7 address_b[7] => ram_block1a6.PORTBADDR7 address_b[7] => ram_block1a7.PORTBADDR7 address_b[7] => ram_block1a8.PORTBADDR7 address_b[7] => ram_block1a9.PORTBADDR7 address_b[7] => ram_block1a10.PORTBADDR7 address_b[7] => ram_block1a11.PORTBADDR7 address_b[7] => ram_block1a12.PORTBADDR7 address_b[7] => ram_block1a13.PORTBADDR7 address_b[7] => ram_block1a14.PORTBADDR7 address_b[7] => ram_block1a15.PORTBADDR7 address_b[8] => ram_block1a0.PORTBADDR8 address_b[8] => ram_block1a1.PORTBADDR8 address_b[8] => ram_block1a2.PORTBADDR8 address_b[8] => ram_block1a3.PORTBADDR8 address_b[8] => ram_block1a4.PORTBADDR8 address_b[8] => ram_block1a5.PORTBADDR8 address_b[8] => ram_block1a6.PORTBADDR8 address_b[8] => ram_block1a7.PORTBADDR8 address_b[8] => ram_block1a8.PORTBADDR8 address_b[8] => ram_block1a9.PORTBADDR8 address_b[8] => ram_block1a10.PORTBADDR8 address_b[8] => ram_block1a11.PORTBADDR8 address_b[8] => ram_block1a12.PORTBADDR8 address_b[8] => ram_block1a13.PORTBADDR8 address_b[8] => ram_block1a14.PORTBADDR8 address_b[8] => ram_block1a15.PORTBADDR8 address_b[9] => ram_block1a0.PORTBADDR9 address_b[9] => ram_block1a1.PORTBADDR9 address_b[9] => ram_block1a2.PORTBADDR9 address_b[9] => ram_block1a3.PORTBADDR9 address_b[9] => ram_block1a4.PORTBADDR9 address_b[9] => ram_block1a5.PORTBADDR9 address_b[9] => ram_block1a6.PORTBADDR9 address_b[9] => ram_block1a7.PORTBADDR9 address_b[9] => ram_block1a8.PORTBADDR9 address_b[9] => ram_block1a9.PORTBADDR9 address_b[9] => ram_block1a10.PORTBADDR9 address_b[9] => ram_block1a11.PORTBADDR9 address_b[9] => ram_block1a12.PORTBADDR9 address_b[9] => ram_block1a13.PORTBADDR9 address_b[9] => ram_block1a14.PORTBADDR9 address_b[9] => ram_block1a15.PORTBADDR9 address_b[10] => ram_block1a0.PORTBADDR10 address_b[10] => ram_block1a1.PORTBADDR10 address_b[10] => ram_block1a2.PORTBADDR10 address_b[10] => ram_block1a3.PORTBADDR10 address_b[10] => ram_block1a4.PORTBADDR10 address_b[10] => ram_block1a5.PORTBADDR10 address_b[10] => ram_block1a6.PORTBADDR10 address_b[10] => ram_block1a7.PORTBADDR10 address_b[10] => ram_block1a8.PORTBADDR10 address_b[10] => ram_block1a9.PORTBADDR10 address_b[10] => ram_block1a10.PORTBADDR10 address_b[10] => ram_block1a11.PORTBADDR10 address_b[10] => ram_block1a12.PORTBADDR10 address_b[10] => ram_block1a13.PORTBADDR10 address_b[10] => ram_block1a14.PORTBADDR10 address_b[10] => ram_block1a15.PORTBADDR10 address_b[11] => ram_block1a0.PORTBADDR11 address_b[11] => ram_block1a1.PORTBADDR11 address_b[11] => ram_block1a2.PORTBADDR11 address_b[11] => ram_block1a3.PORTBADDR11 address_b[11] => ram_block1a4.PORTBADDR11 address_b[11] => ram_block1a5.PORTBADDR11 address_b[11] => ram_block1a6.PORTBADDR11 address_b[11] => ram_block1a7.PORTBADDR11 address_b[11] => ram_block1a8.PORTBADDR11 address_b[11] => ram_block1a9.PORTBADDR11 address_b[11] => ram_block1a10.PORTBADDR11 address_b[11] => ram_block1a11.PORTBADDR11 address_b[11] => ram_block1a12.PORTBADDR11 address_b[11] => ram_block1a13.PORTBADDR11 address_b[11] => ram_block1a14.PORTBADDR11 address_b[11] => ram_block1a15.PORTBADDR11 address_b[12] => ram_block1a0.PORTBADDR12 address_b[12] => ram_block1a1.PORTBADDR12 address_b[12] => ram_block1a2.PORTBADDR12 address_b[12] => ram_block1a3.PORTBADDR12 address_b[12] => ram_block1a4.PORTBADDR12 address_b[12] => ram_block1a5.PORTBADDR12 address_b[12] => ram_block1a6.PORTBADDR12 address_b[12] => ram_block1a7.PORTBADDR12 address_b[12] => ram_block1a8.PORTBADDR12 address_b[12] => ram_block1a9.PORTBADDR12 address_b[12] => ram_block1a10.PORTBADDR12 address_b[12] => ram_block1a11.PORTBADDR12 address_b[12] => ram_block1a12.PORTBADDR12 address_b[12] => ram_block1a13.PORTBADDR12 address_b[12] => ram_block1a14.PORTBADDR12 address_b[12] => ram_block1a15.PORTBADDR12 address_b[13] => address_reg_b[0].DATAIN address_b[13] => decode_jsa:decode3.data[0] address_b[13] => decode_c8a:rden_decode_b.data[0] clock0 => ram_block1a0.CLK0 clock0 => ram_block1a0.CLK1 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a1.CLK1 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a2.CLK1 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a3.CLK1 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a4.CLK1 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a5.CLK1 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a6.CLK1 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a7.CLK1 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a8.CLK1 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a9.CLK1 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a10.CLK1 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a11.CLK1 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a12.CLK1 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a13.CLK1 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a14.CLK1 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a15.CLK1 clock0 => address_reg_a[0].CLK clock0 => address_reg_b[0].CLK clock0 => out_address_reg_a[0].CLK clock0 => out_address_reg_b[0].CLK data_a[0] => ram_block1a0.PORTADATAIN data_a[0] => ram_block1a8.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[1] => ram_block1a9.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[2] => ram_block1a10.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[3] => ram_block1a11.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[4] => ram_block1a12.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[5] => ram_block1a13.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[6] => ram_block1a14.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[7] => ram_block1a15.PORTADATAIN data_b[0] => ram_block1a0.PORTBDATAIN data_b[0] => ram_block1a8.PORTBDATAIN data_b[1] => ram_block1a1.PORTBDATAIN data_b[1] => ram_block1a9.PORTBDATAIN data_b[2] => ram_block1a2.PORTBDATAIN data_b[2] => ram_block1a10.PORTBDATAIN data_b[3] => ram_block1a3.PORTBDATAIN data_b[3] => ram_block1a11.PORTBDATAIN data_b[4] => ram_block1a4.PORTBDATAIN data_b[4] => ram_block1a12.PORTBDATAIN data_b[5] => ram_block1a5.PORTBDATAIN data_b[5] => ram_block1a13.PORTBDATAIN data_b[6] => ram_block1a6.PORTBDATAIN data_b[6] => ram_block1a14.PORTBDATAIN data_b[7] => ram_block1a7.PORTBDATAIN data_b[7] => ram_block1a15.PORTBDATAIN q_a[0] <= mux_3nb:mux4.result[0] q_a[1] <= mux_3nb:mux4.result[1] q_a[2] <= mux_3nb:mux4.result[2] q_a[3] <= mux_3nb:mux4.result[3] q_a[4] <= mux_3nb:mux4.result[4] q_a[5] <= mux_3nb:mux4.result[5] q_a[6] <= mux_3nb:mux4.result[6] q_a[7] <= mux_3nb:mux4.result[7] q_b[0] <= mux_3nb:mux5.result[0] q_b[1] <= mux_3nb:mux5.result[1] q_b[2] <= mux_3nb:mux5.result[2] q_b[3] <= mux_3nb:mux5.result[3] q_b[4] <= mux_3nb:mux5.result[4] q_b[5] <= mux_3nb:mux5.result[5] q_b[6] <= mux_3nb:mux5.result[6] q_b[7] <= mux_3nb:mux5.result[7] wren_a => decode_jsa:decode2.enable wren_b => decode_jsa:decode3.enable |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2 data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 enable => eq_node[1].IN1 enable => eq_node[0].IN1 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode3 data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 enable => eq_node[1].IN1 enable => eq_node[0].IN1 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_a data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_b data[0] => eq_node[1].IN0 data[0] => eq_node[0].IN0 eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4 data[0] => result_node[0].IN1 data[1] => result_node[1].IN1 data[2] => result_node[2].IN1 data[3] => result_node[3].IN1 data[4] => result_node[4].IN1 data[5] => result_node[5].IN1 data[6] => result_node[6].IN1 data[7] => result_node[7].IN1 data[8] => result_node[0].IN1 data[9] => result_node[1].IN1 data[10] => result_node[2].IN1 data[11] => result_node[3].IN1 data[12] => result_node[4].IN1 data[13] => result_node[5].IN1 data[14] => result_node[6].IN1 data[15] => result_node[7].IN1 result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE sel[0] => result_node[7].IN0 sel[0] => _.IN0 sel[0] => result_node[6].IN0 sel[0] => _.IN0 sel[0] => result_node[5].IN0 sel[0] => _.IN0 sel[0] => result_node[4].IN0 sel[0] => _.IN0 sel[0] => result_node[3].IN0 sel[0] => _.IN0 sel[0] => result_node[2].IN0 sel[0] => _.IN0 sel[0] => result_node[1].IN0 sel[0] => _.IN0 sel[0] => result_node[0].IN0 sel[0] => _.IN0 |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5 data[0] => result_node[0].IN1 data[1] => result_node[1].IN1 data[2] => result_node[2].IN1 data[3] => result_node[3].IN1 data[4] => result_node[4].IN1 data[5] => result_node[5].IN1 data[6] => result_node[6].IN1 data[7] => result_node[7].IN1 data[8] => result_node[0].IN1 data[9] => result_node[1].IN1 data[10] => result_node[2].IN1 data[11] => result_node[3].IN1 data[12] => result_node[4].IN1 data[13] => result_node[5].IN1 data[14] => result_node[6].IN1 data[15] => result_node[7].IN1 result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE sel[0] => result_node[7].IN0 sel[0] => _.IN0 sel[0] => result_node[6].IN0 sel[0] => _.IN0 sel[0] => result_node[5].IN0 sel[0] => _.IN0 sel[0] => result_node[4].IN0 sel[0] => _.IN0 sel[0] => result_node[3].IN0 sel[0] => _.IN0 sel[0] => result_node[2].IN0 sel[0] => _.IN0 sel[0] => result_node[1].IN0 sel[0] => _.IN0 sel[0] => result_node[0].IN0 sel[0] => _.IN0 |spectrum|ram32:ram1 address[0] => address[0].IN1 address[1] => address[1].IN1 address[2] => address[2].IN1 address[3] => address[3].IN1 address[4] => address[4].IN1 address[5] => address[5].IN1 address[6] => address[6].IN1 address[7] => address[7].IN1 address[8] => address[8].IN1 address[9] => address[9].IN1 address[10] => address[10].IN1 address[11] => address[11].IN1 address[12] => address[12].IN1 address[13] => address[13].IN1 address[14] => address[14].IN1 clock => clock.IN1 data[0] => data[0].IN1 data[1] => data[1].IN1 data[2] => data[2].IN1 data[3] => data[3].IN1 data[4] => data[4].IN1 data[5] => data[5].IN1 data[6] => data[6].IN1 data[7] => data[7].IN1 wren => wren.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a q[2] <= altsyncram:altsyncram_component.q_a q[3] <= altsyncram:altsyncram_component.q_a q[4] <= altsyncram:altsyncram_component.q_a q[5] <= altsyncram:altsyncram_component.q_a q[6] <= altsyncram:altsyncram_component.q_a q[7] <= altsyncram:altsyncram_component.q_a |spectrum|ram32:ram1|altsyncram:altsyncram_component wren_a => altsyncram_g9i1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_g9i1:auto_generated.data_a[0] data_a[1] => altsyncram_g9i1:auto_generated.data_a[1] data_a[2] => altsyncram_g9i1:auto_generated.data_a[2] data_a[3] => altsyncram_g9i1:auto_generated.data_a[3] data_a[4] => altsyncram_g9i1:auto_generated.data_a[4] data_a[5] => altsyncram_g9i1:auto_generated.data_a[5] data_a[6] => altsyncram_g9i1:auto_generated.data_a[6] data_a[7] => altsyncram_g9i1:auto_generated.data_a[7] data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_g9i1:auto_generated.address_a[0] address_a[1] => altsyncram_g9i1:auto_generated.address_a[1] address_a[2] => altsyncram_g9i1:auto_generated.address_a[2] address_a[3] => altsyncram_g9i1:auto_generated.address_a[3] address_a[4] => altsyncram_g9i1:auto_generated.address_a[4] address_a[5] => altsyncram_g9i1:auto_generated.address_a[5] address_a[6] => altsyncram_g9i1:auto_generated.address_a[6] address_a[7] => altsyncram_g9i1:auto_generated.address_a[7] address_a[8] => altsyncram_g9i1:auto_generated.address_a[8] address_a[9] => altsyncram_g9i1:auto_generated.address_a[9] address_a[10] => altsyncram_g9i1:auto_generated.address_a[10] address_a[11] => altsyncram_g9i1:auto_generated.address_a[11] address_a[12] => altsyncram_g9i1:auto_generated.address_a[12] address_a[13] => altsyncram_g9i1:auto_generated.address_a[13] address_a[14] => altsyncram_g9i1:auto_generated.address_a[14] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_g9i1:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_g9i1:auto_generated.q_a[0] q_a[1] <= altsyncram_g9i1:auto_generated.q_a[1] q_a[2] <= altsyncram_g9i1:auto_generated.q_a[2] q_a[3] <= altsyncram_g9i1:auto_generated.q_a[3] q_a[4] <= altsyncram_g9i1:auto_generated.q_a[4] q_a[5] <= altsyncram_g9i1:auto_generated.q_a[5] q_a[6] <= altsyncram_g9i1:auto_generated.q_a[6] q_a[7] <= altsyncram_g9i1:auto_generated.q_a[7] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 address_a[5] => ram_block1a24.PORTAADDR5 address_a[5] => ram_block1a25.PORTAADDR5 address_a[5] => ram_block1a26.PORTAADDR5 address_a[5] => ram_block1a27.PORTAADDR5 address_a[5] => ram_block1a28.PORTAADDR5 address_a[5] => ram_block1a29.PORTAADDR5 address_a[5] => ram_block1a30.PORTAADDR5 address_a[5] => ram_block1a31.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_a[6] => ram_block1a20.PORTAADDR6 address_a[6] => ram_block1a21.PORTAADDR6 address_a[6] => ram_block1a22.PORTAADDR6 address_a[6] => ram_block1a23.PORTAADDR6 address_a[6] => ram_block1a24.PORTAADDR6 address_a[6] => ram_block1a25.PORTAADDR6 address_a[6] => ram_block1a26.PORTAADDR6 address_a[6] => ram_block1a27.PORTAADDR6 address_a[6] => ram_block1a28.PORTAADDR6 address_a[6] => ram_block1a29.PORTAADDR6 address_a[6] => ram_block1a30.PORTAADDR6 address_a[6] => ram_block1a31.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[7] => ram_block1a16.PORTAADDR7 address_a[7] => ram_block1a17.PORTAADDR7 address_a[7] => ram_block1a18.PORTAADDR7 address_a[7] => ram_block1a19.PORTAADDR7 address_a[7] => ram_block1a20.PORTAADDR7 address_a[7] => ram_block1a21.PORTAADDR7 address_a[7] => ram_block1a22.PORTAADDR7 address_a[7] => ram_block1a23.PORTAADDR7 address_a[7] => ram_block1a24.PORTAADDR7 address_a[7] => ram_block1a25.PORTAADDR7 address_a[7] => ram_block1a26.PORTAADDR7 address_a[7] => ram_block1a27.PORTAADDR7 address_a[7] => ram_block1a28.PORTAADDR7 address_a[7] => ram_block1a29.PORTAADDR7 address_a[7] => ram_block1a30.PORTAADDR7 address_a[7] => ram_block1a31.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_a[8] => ram_block1a15.PORTAADDR8 address_a[8] => ram_block1a16.PORTAADDR8 address_a[8] => ram_block1a17.PORTAADDR8 address_a[8] => ram_block1a18.PORTAADDR8 address_a[8] => ram_block1a19.PORTAADDR8 address_a[8] => ram_block1a20.PORTAADDR8 address_a[8] => ram_block1a21.PORTAADDR8 address_a[8] => ram_block1a22.PORTAADDR8 address_a[8] => ram_block1a23.PORTAADDR8 address_a[8] => ram_block1a24.PORTAADDR8 address_a[8] => ram_block1a25.PORTAADDR8 address_a[8] => ram_block1a26.PORTAADDR8 address_a[8] => ram_block1a27.PORTAADDR8 address_a[8] => ram_block1a28.PORTAADDR8 address_a[8] => ram_block1a29.PORTAADDR8 address_a[8] => ram_block1a30.PORTAADDR8 address_a[8] => ram_block1a31.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[9] => ram_block1a8.PORTAADDR9 address_a[9] => ram_block1a9.PORTAADDR9 address_a[9] => ram_block1a10.PORTAADDR9 address_a[9] => ram_block1a11.PORTAADDR9 address_a[9] => ram_block1a12.PORTAADDR9 address_a[9] => ram_block1a13.PORTAADDR9 address_a[9] => ram_block1a14.PORTAADDR9 address_a[9] => ram_block1a15.PORTAADDR9 address_a[9] => ram_block1a16.PORTAADDR9 address_a[9] => ram_block1a17.PORTAADDR9 address_a[9] => ram_block1a18.PORTAADDR9 address_a[9] => ram_block1a19.PORTAADDR9 address_a[9] => ram_block1a20.PORTAADDR9 address_a[9] => ram_block1a21.PORTAADDR9 address_a[9] => ram_block1a22.PORTAADDR9 address_a[9] => ram_block1a23.PORTAADDR9 address_a[9] => ram_block1a24.PORTAADDR9 address_a[9] => ram_block1a25.PORTAADDR9 address_a[9] => ram_block1a26.PORTAADDR9 address_a[9] => ram_block1a27.PORTAADDR9 address_a[9] => ram_block1a28.PORTAADDR9 address_a[9] => ram_block1a29.PORTAADDR9 address_a[9] => ram_block1a30.PORTAADDR9 address_a[9] => ram_block1a31.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 address_a[10] => ram_block1a8.PORTAADDR10 address_a[10] => ram_block1a9.PORTAADDR10 address_a[10] => ram_block1a10.PORTAADDR10 address_a[10] => ram_block1a11.PORTAADDR10 address_a[10] => ram_block1a12.PORTAADDR10 address_a[10] => ram_block1a13.PORTAADDR10 address_a[10] => ram_block1a14.PORTAADDR10 address_a[10] => ram_block1a15.PORTAADDR10 address_a[10] => ram_block1a16.PORTAADDR10 address_a[10] => ram_block1a17.PORTAADDR10 address_a[10] => ram_block1a18.PORTAADDR10 address_a[10] => ram_block1a19.PORTAADDR10 address_a[10] => ram_block1a20.PORTAADDR10 address_a[10] => ram_block1a21.PORTAADDR10 address_a[10] => ram_block1a22.PORTAADDR10 address_a[10] => ram_block1a23.PORTAADDR10 address_a[10] => ram_block1a24.PORTAADDR10 address_a[10] => ram_block1a25.PORTAADDR10 address_a[10] => ram_block1a26.PORTAADDR10 address_a[10] => ram_block1a27.PORTAADDR10 address_a[10] => ram_block1a28.PORTAADDR10 address_a[10] => ram_block1a29.PORTAADDR10 address_a[10] => ram_block1a30.PORTAADDR10 address_a[10] => ram_block1a31.PORTAADDR10 address_a[11] => ram_block1a0.PORTAADDR11 address_a[11] => ram_block1a1.PORTAADDR11 address_a[11] => ram_block1a2.PORTAADDR11 address_a[11] => ram_block1a3.PORTAADDR11 address_a[11] => ram_block1a4.PORTAADDR11 address_a[11] => ram_block1a5.PORTAADDR11 address_a[11] => ram_block1a6.PORTAADDR11 address_a[11] => ram_block1a7.PORTAADDR11 address_a[11] => ram_block1a8.PORTAADDR11 address_a[11] => ram_block1a9.PORTAADDR11 address_a[11] => ram_block1a10.PORTAADDR11 address_a[11] => ram_block1a11.PORTAADDR11 address_a[11] => ram_block1a12.PORTAADDR11 address_a[11] => ram_block1a13.PORTAADDR11 address_a[11] => ram_block1a14.PORTAADDR11 address_a[11] => ram_block1a15.PORTAADDR11 address_a[11] => ram_block1a16.PORTAADDR11 address_a[11] => ram_block1a17.PORTAADDR11 address_a[11] => ram_block1a18.PORTAADDR11 address_a[11] => ram_block1a19.PORTAADDR11 address_a[11] => ram_block1a20.PORTAADDR11 address_a[11] => ram_block1a21.PORTAADDR11 address_a[11] => ram_block1a22.PORTAADDR11 address_a[11] => ram_block1a23.PORTAADDR11 address_a[11] => ram_block1a24.PORTAADDR11 address_a[11] => ram_block1a25.PORTAADDR11 address_a[11] => ram_block1a26.PORTAADDR11 address_a[11] => ram_block1a27.PORTAADDR11 address_a[11] => ram_block1a28.PORTAADDR11 address_a[11] => ram_block1a29.PORTAADDR11 address_a[11] => ram_block1a30.PORTAADDR11 address_a[11] => ram_block1a31.PORTAADDR11 address_a[12] => ram_block1a0.PORTAADDR12 address_a[12] => ram_block1a1.PORTAADDR12 address_a[12] => ram_block1a2.PORTAADDR12 address_a[12] => ram_block1a3.PORTAADDR12 address_a[12] => ram_block1a4.PORTAADDR12 address_a[12] => ram_block1a5.PORTAADDR12 address_a[12] => ram_block1a6.PORTAADDR12 address_a[12] => ram_block1a7.PORTAADDR12 address_a[12] => ram_block1a8.PORTAADDR12 address_a[12] => ram_block1a9.PORTAADDR12 address_a[12] => ram_block1a10.PORTAADDR12 address_a[12] => ram_block1a11.PORTAADDR12 address_a[12] => ram_block1a12.PORTAADDR12 address_a[12] => ram_block1a13.PORTAADDR12 address_a[12] => ram_block1a14.PORTAADDR12 address_a[12] => ram_block1a15.PORTAADDR12 address_a[12] => ram_block1a16.PORTAADDR12 address_a[12] => ram_block1a17.PORTAADDR12 address_a[12] => ram_block1a18.PORTAADDR12 address_a[12] => ram_block1a19.PORTAADDR12 address_a[12] => ram_block1a20.PORTAADDR12 address_a[12] => ram_block1a21.PORTAADDR12 address_a[12] => ram_block1a22.PORTAADDR12 address_a[12] => ram_block1a23.PORTAADDR12 address_a[12] => ram_block1a24.PORTAADDR12 address_a[12] => ram_block1a25.PORTAADDR12 address_a[12] => ram_block1a26.PORTAADDR12 address_a[12] => ram_block1a27.PORTAADDR12 address_a[12] => ram_block1a28.PORTAADDR12 address_a[12] => ram_block1a29.PORTAADDR12 address_a[12] => ram_block1a30.PORTAADDR12 address_a[12] => ram_block1a31.PORTAADDR12 address_a[13] => address_reg_a[0].DATAIN address_a[13] => decode_msa:decode3.data[0] address_a[13] => decode_f8a:rden_decode.data[0] address_a[14] => address_reg_a[1].DATAIN address_a[14] => decode_msa:decode3.data[1] address_a[14] => decode_f8a:rden_decode.data[1] clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock0 => address_reg_a[1].CLK clock0 => address_reg_a[0].CLK clock0 => out_address_reg_a[1].CLK clock0 => out_address_reg_a[0].CLK data_a[0] => ram_block1a0.PORTADATAIN data_a[0] => ram_block1a8.PORTADATAIN data_a[0] => ram_block1a16.PORTADATAIN data_a[0] => ram_block1a24.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[1] => ram_block1a9.PORTADATAIN data_a[1] => ram_block1a17.PORTADATAIN data_a[1] => ram_block1a25.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[2] => ram_block1a10.PORTADATAIN data_a[2] => ram_block1a18.PORTADATAIN data_a[2] => ram_block1a26.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[3] => ram_block1a11.PORTADATAIN data_a[3] => ram_block1a19.PORTADATAIN data_a[3] => ram_block1a27.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[4] => ram_block1a12.PORTADATAIN data_a[4] => ram_block1a20.PORTADATAIN data_a[4] => ram_block1a28.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[5] => ram_block1a13.PORTADATAIN data_a[5] => ram_block1a21.PORTADATAIN data_a[5] => ram_block1a29.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[6] => ram_block1a14.PORTADATAIN data_a[6] => ram_block1a22.PORTADATAIN data_a[6] => ram_block1a30.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[7] => ram_block1a15.PORTADATAIN data_a[7] => ram_block1a23.PORTADATAIN data_a[7] => ram_block1a31.PORTADATAIN q_a[0] <= mux_6nb:mux2.result[0] q_a[1] <= mux_6nb:mux2.result[1] q_a[2] <= mux_6nb:mux2.result[2] q_a[3] <= mux_6nb:mux2.result[3] q_a[4] <= mux_6nb:mux2.result[4] q_a[5] <= mux_6nb:mux2.result[5] q_a[6] <= mux_6nb:mux2.result[6] q_a[7] <= mux_6nb:mux2.result[7] wren_a => decode_msa:decode3.enable |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3 data[0] => w_anode223w[1].IN0 data[0] => w_anode236w[1].IN1 data[0] => w_anode244w[1].IN0 data[0] => w_anode252w[1].IN1 data[1] => w_anode223w[2].IN0 data[1] => w_anode236w[2].IN0 data[1] => w_anode244w[2].IN1 data[1] => w_anode252w[2].IN1 enable => w_anode223w[1].IN0 enable => w_anode236w[1].IN0 enable => w_anode244w[1].IN0 enable => w_anode252w[1].IN0 eq[0] <= w_anode223w[2].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= w_anode236w[2].DB_MAX_OUTPUT_PORT_TYPE eq[2] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE eq[3] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode data[0] => w_anode261w[1].IN0 data[0] => w_anode275w[1].IN1 data[0] => w_anode284w[1].IN0 data[0] => w_anode293w[1].IN1 data[1] => w_anode261w[2].IN0 data[1] => w_anode275w[2].IN0 data[1] => w_anode284w[2].IN1 data[1] => w_anode293w[2].IN1 eq[0] <= w_anode261w[2].DB_MAX_OUTPUT_PORT_TYPE eq[1] <= w_anode275w[2].DB_MAX_OUTPUT_PORT_TYPE eq[2] <= w_anode284w[2].DB_MAX_OUTPUT_PORT_TYPE eq[3] <= w_anode293w[2].DB_MAX_OUTPUT_PORT_TYPE |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 data[0] => _.IN0 data[0] => _.IN0 data[1] => _.IN0 data[1] => _.IN0 data[2] => _.IN0 data[2] => _.IN0 data[3] => _.IN0 data[3] => _.IN0 data[4] => _.IN0 data[4] => _.IN0 data[5] => _.IN0 data[5] => _.IN0 data[6] => _.IN0 data[6] => _.IN0 data[7] => _.IN0 data[7] => _.IN0 data[8] => _.IN0 data[9] => _.IN0 data[10] => _.IN0 data[11] => _.IN0 data[12] => _.IN0 data[13] => _.IN0 data[14] => _.IN0 data[15] => _.IN0 data[16] => _.IN1 data[16] => _.IN1 data[17] => _.IN1 data[17] => _.IN1 data[18] => _.IN1 data[18] => _.IN1 data[19] => _.IN1 data[19] => _.IN1 data[20] => _.IN1 data[20] => _.IN1 data[21] => _.IN1 data[21] => _.IN1 data[22] => _.IN1 data[22] => _.IN1 data[23] => _.IN1 data[23] => _.IN1 data[24] => _.IN0 data[25] => _.IN0 data[26] => _.IN0 data[27] => _.IN0 data[28] => _.IN0 data[29] => _.IN0 data[30] => _.IN0 data[31] => _.IN0 result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN1 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[0] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0 sel[1] => _.IN0